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b5f1220d SN |
1 | /* |
2 | * Samsung S5P/EXYNOS4 SoC series MIPI-CSI receiver driver | |
3 | * | |
4 | * Copyright (C) 2011 Samsung Electronics Co., Ltd. | |
5 | * Contact: Sylwester Nawrocki, <s.nawrocki@samsung.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/clk.h> | |
13 | #include <linux/delay.h> | |
14 | #include <linux/device.h> | |
15 | #include <linux/errno.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/irq.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/memory.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/pm_runtime.h> | |
24 | #include <linux/regulator/consumer.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/spinlock.h> | |
27 | #include <linux/videodev2.h> | |
28 | #include <media/v4l2-subdev.h> | |
29 | #include <plat/mipi_csis.h> | |
30 | #include "mipi-csis.h" | |
31 | ||
32 | static int debug; | |
33 | module_param(debug, int, 0644); | |
34 | MODULE_PARM_DESC(debug, "Debug level (0-1)"); | |
35 | ||
36 | /* Register map definition */ | |
37 | ||
38 | /* CSIS global control */ | |
39 | #define S5PCSIS_CTRL 0x00 | |
40 | #define S5PCSIS_CTRL_DPDN_DEFAULT (0 << 31) | |
41 | #define S5PCSIS_CTRL_DPDN_SWAP (1 << 31) | |
42 | #define S5PCSIS_CTRL_ALIGN_32BIT (1 << 20) | |
43 | #define S5PCSIS_CTRL_UPDATE_SHADOW (1 << 16) | |
44 | #define S5PCSIS_CTRL_WCLK_EXTCLK (1 << 8) | |
45 | #define S5PCSIS_CTRL_RESET (1 << 4) | |
46 | #define S5PCSIS_CTRL_ENABLE (1 << 0) | |
47 | ||
48 | /* D-PHY control */ | |
49 | #define S5PCSIS_DPHYCTRL 0x04 | |
50 | #define S5PCSIS_DPHYCTRL_HSS_MASK (0x1f << 27) | |
51 | #define S5PCSIS_DPHYCTRL_ENABLE (0x1f << 0) | |
52 | ||
53 | #define S5PCSIS_CONFIG 0x08 | |
54 | #define S5PCSIS_CFG_FMT_YCBCR422_8BIT (0x1e << 2) | |
55 | #define S5PCSIS_CFG_FMT_RAW8 (0x2a << 2) | |
56 | #define S5PCSIS_CFG_FMT_RAW10 (0x2b << 2) | |
57 | #define S5PCSIS_CFG_FMT_RAW12 (0x2c << 2) | |
58 | /* User defined formats, x = 1...4 */ | |
59 | #define S5PCSIS_CFG_FMT_USER(x) ((0x30 + x - 1) << 2) | |
60 | #define S5PCSIS_CFG_FMT_MASK (0x3f << 2) | |
61 | #define S5PCSIS_CFG_NR_LANE_MASK 3 | |
62 | ||
63 | /* Interrupt mask. */ | |
64 | #define S5PCSIS_INTMSK 0x10 | |
65 | #define S5PCSIS_INTMSK_EN_ALL 0xf000003f | |
66 | #define S5PCSIS_INTSRC 0x14 | |
67 | ||
68 | /* Pixel resolution */ | |
69 | #define S5PCSIS_RESOL 0x2c | |
70 | #define CSIS_MAX_PIX_WIDTH 0xffff | |
71 | #define CSIS_MAX_PIX_HEIGHT 0xffff | |
72 | ||
73 | enum { | |
74 | CSIS_CLK_MUX, | |
75 | CSIS_CLK_GATE, | |
76 | }; | |
77 | ||
78 | static char *csi_clock_name[] = { | |
79 | [CSIS_CLK_MUX] = "sclk_csis", | |
80 | [CSIS_CLK_GATE] = "csis", | |
81 | }; | |
82 | #define NUM_CSIS_CLOCKS ARRAY_SIZE(csi_clock_name) | |
83 | ||
438df3eb SN |
84 | static const char * const csis_supply_name[] = { |
85 | "vdd11", /* 1.1V or 1.2V (s5pc100) MIPI CSI suppply */ | |
86 | "vdd18", /* VDD 1.8V and MIPI CSI PLL supply */ | |
87 | }; | |
88 | #define CSIS_NUM_SUPPLIES ARRAY_SIZE(csis_supply_name) | |
89 | ||
b5f1220d SN |
90 | enum { |
91 | ST_POWERED = 1, | |
92 | ST_STREAMING = 2, | |
93 | ST_SUSPENDED = 4, | |
94 | }; | |
95 | ||
96 | /** | |
97 | * struct csis_state - the driver's internal state data structure | |
98 | * @lock: mutex serializing the subdev and power management operations, | |
99 | * protecting @format and @flags members | |
100 | * @pads: CSIS pads array | |
101 | * @sd: v4l2_subdev associated with CSIS device instance | |
102 | * @pdev: CSIS platform device | |
103 | * @regs_res: requested I/O register memory resource | |
104 | * @regs: mmaped I/O registers memory | |
105 | * @clock: CSIS clocks | |
106 | * @irq: requested s5p-mipi-csis irq number | |
107 | * @flags: the state variable for power and streaming control | |
108 | * @csis_fmt: current CSIS pixel format | |
109 | * @format: common media bus format for the source and sink pad | |
110 | */ | |
111 | struct csis_state { | |
112 | struct mutex lock; | |
113 | struct media_pad pads[CSIS_PADS_NUM]; | |
114 | struct v4l2_subdev sd; | |
115 | struct platform_device *pdev; | |
116 | struct resource *regs_res; | |
117 | void __iomem *regs; | |
438df3eb | 118 | struct regulator_bulk_data supplies[CSIS_NUM_SUPPLIES]; |
b5f1220d SN |
119 | struct clk *clock[NUM_CSIS_CLOCKS]; |
120 | int irq; | |
b5f1220d SN |
121 | u32 flags; |
122 | const struct csis_pix_format *csis_fmt; | |
123 | struct v4l2_mbus_framefmt format; | |
124 | }; | |
125 | ||
126 | /** | |
127 | * struct csis_pix_format - CSIS pixel format description | |
128 | * @pix_width_alignment: horizontal pixel alignment, width will be | |
129 | * multiple of 2^pix_width_alignment | |
130 | * @code: corresponding media bus code | |
131 | * @fmt_reg: S5PCSIS_CONFIG register value | |
132 | */ | |
133 | struct csis_pix_format { | |
134 | unsigned int pix_width_alignment; | |
135 | enum v4l2_mbus_pixelcode code; | |
136 | u32 fmt_reg; | |
137 | }; | |
138 | ||
139 | static const struct csis_pix_format s5pcsis_formats[] = { | |
140 | { | |
141 | .code = V4L2_MBUS_FMT_VYUY8_2X8, | |
142 | .fmt_reg = S5PCSIS_CFG_FMT_YCBCR422_8BIT, | |
143 | }, { | |
144 | .code = V4L2_MBUS_FMT_JPEG_1X8, | |
145 | .fmt_reg = S5PCSIS_CFG_FMT_USER(1), | |
146 | }, | |
147 | }; | |
148 | ||
149 | #define s5pcsis_write(__csis, __r, __v) writel(__v, __csis->regs + __r) | |
150 | #define s5pcsis_read(__csis, __r) readl(__csis->regs + __r) | |
151 | ||
152 | static struct csis_state *sd_to_csis_state(struct v4l2_subdev *sdev) | |
153 | { | |
154 | return container_of(sdev, struct csis_state, sd); | |
155 | } | |
156 | ||
157 | static const struct csis_pix_format *find_csis_format( | |
158 | struct v4l2_mbus_framefmt *mf) | |
159 | { | |
160 | int i; | |
161 | ||
162 | for (i = 0; i < ARRAY_SIZE(s5pcsis_formats); i++) | |
163 | if (mf->code == s5pcsis_formats[i].code) | |
164 | return &s5pcsis_formats[i]; | |
165 | return NULL; | |
166 | } | |
167 | ||
168 | static void s5pcsis_enable_interrupts(struct csis_state *state, bool on) | |
169 | { | |
170 | u32 val = s5pcsis_read(state, S5PCSIS_INTMSK); | |
171 | ||
172 | val = on ? val | S5PCSIS_INTMSK_EN_ALL : | |
173 | val & ~S5PCSIS_INTMSK_EN_ALL; | |
174 | s5pcsis_write(state, S5PCSIS_INTMSK, val); | |
175 | } | |
176 | ||
177 | static void s5pcsis_reset(struct csis_state *state) | |
178 | { | |
179 | u32 val = s5pcsis_read(state, S5PCSIS_CTRL); | |
180 | ||
181 | s5pcsis_write(state, S5PCSIS_CTRL, val | S5PCSIS_CTRL_RESET); | |
182 | udelay(10); | |
183 | } | |
184 | ||
185 | static void s5pcsis_system_enable(struct csis_state *state, int on) | |
186 | { | |
187 | u32 val; | |
188 | ||
189 | val = s5pcsis_read(state, S5PCSIS_CTRL); | |
190 | if (on) | |
191 | val |= S5PCSIS_CTRL_ENABLE; | |
192 | else | |
193 | val &= ~S5PCSIS_CTRL_ENABLE; | |
194 | s5pcsis_write(state, S5PCSIS_CTRL, val); | |
195 | ||
196 | val = s5pcsis_read(state, S5PCSIS_DPHYCTRL); | |
197 | if (on) | |
198 | val |= S5PCSIS_DPHYCTRL_ENABLE; | |
199 | else | |
200 | val &= ~S5PCSIS_DPHYCTRL_ENABLE; | |
201 | s5pcsis_write(state, S5PCSIS_DPHYCTRL, val); | |
202 | } | |
203 | ||
204 | /* Called with the state.lock mutex held */ | |
205 | static void __s5pcsis_set_format(struct csis_state *state) | |
206 | { | |
207 | struct v4l2_mbus_framefmt *mf = &state->format; | |
208 | u32 val; | |
209 | ||
210 | v4l2_dbg(1, debug, &state->sd, "fmt: %d, %d x %d\n", | |
211 | mf->code, mf->width, mf->height); | |
212 | ||
213 | /* Color format */ | |
214 | val = s5pcsis_read(state, S5PCSIS_CONFIG); | |
215 | val = (val & ~S5PCSIS_CFG_FMT_MASK) | state->csis_fmt->fmt_reg; | |
216 | s5pcsis_write(state, S5PCSIS_CONFIG, val); | |
217 | ||
218 | /* Pixel resolution */ | |
219 | val = (mf->width << 16) | mf->height; | |
220 | s5pcsis_write(state, S5PCSIS_RESOL, val); | |
221 | } | |
222 | ||
223 | static void s5pcsis_set_hsync_settle(struct csis_state *state, int settle) | |
224 | { | |
225 | u32 val = s5pcsis_read(state, S5PCSIS_DPHYCTRL); | |
226 | ||
227 | val = (val & ~S5PCSIS_DPHYCTRL_HSS_MASK) | (settle << 27); | |
228 | s5pcsis_write(state, S5PCSIS_DPHYCTRL, val); | |
229 | } | |
230 | ||
231 | static void s5pcsis_set_params(struct csis_state *state) | |
232 | { | |
233 | struct s5p_platform_mipi_csis *pdata = state->pdev->dev.platform_data; | |
234 | u32 val; | |
235 | ||
236 | val = s5pcsis_read(state, S5PCSIS_CONFIG); | |
237 | val = (val & ~S5PCSIS_CFG_NR_LANE_MASK) | (pdata->lanes - 1); | |
238 | s5pcsis_write(state, S5PCSIS_CONFIG, val); | |
239 | ||
240 | __s5pcsis_set_format(state); | |
241 | s5pcsis_set_hsync_settle(state, pdata->hs_settle); | |
242 | ||
243 | val = s5pcsis_read(state, S5PCSIS_CTRL); | |
244 | if (pdata->alignment == 32) | |
245 | val |= S5PCSIS_CTRL_ALIGN_32BIT; | |
246 | else /* 24-bits */ | |
247 | val &= ~S5PCSIS_CTRL_ALIGN_32BIT; | |
248 | /* Not using external clock. */ | |
249 | val &= ~S5PCSIS_CTRL_WCLK_EXTCLK; | |
250 | s5pcsis_write(state, S5PCSIS_CTRL, val); | |
251 | ||
252 | /* Update the shadow register. */ | |
253 | val = s5pcsis_read(state, S5PCSIS_CTRL); | |
254 | s5pcsis_write(state, S5PCSIS_CTRL, val | S5PCSIS_CTRL_UPDATE_SHADOW); | |
255 | } | |
256 | ||
257 | static void s5pcsis_clk_put(struct csis_state *state) | |
258 | { | |
259 | int i; | |
260 | ||
bd7d8888 SN |
261 | for (i = 0; i < NUM_CSIS_CLOCKS; i++) { |
262 | if (IS_ERR_OR_NULL(state->clock[i])) | |
263 | continue; | |
264 | clk_unprepare(state->clock[i]); | |
265 | clk_put(state->clock[i]); | |
266 | state->clock[i] = NULL; | |
267 | } | |
b5f1220d SN |
268 | } |
269 | ||
270 | static int s5pcsis_clk_get(struct csis_state *state) | |
271 | { | |
272 | struct device *dev = &state->pdev->dev; | |
bd7d8888 | 273 | int i, ret; |
b5f1220d SN |
274 | |
275 | for (i = 0; i < NUM_CSIS_CLOCKS; i++) { | |
276 | state->clock[i] = clk_get(dev, csi_clock_name[i]); | |
bd7d8888 SN |
277 | if (IS_ERR(state->clock[i])) |
278 | goto err; | |
279 | ret = clk_prepare(state->clock[i]); | |
280 | if (ret < 0) { | |
281 | clk_put(state->clock[i]); | |
282 | state->clock[i] = NULL; | |
283 | goto err; | |
b5f1220d SN |
284 | } |
285 | } | |
286 | return 0; | |
bd7d8888 SN |
287 | err: |
288 | s5pcsis_clk_put(state); | |
289 | dev_err(dev, "failed to get clock: %s\n", csi_clock_name[i]); | |
290 | return -ENXIO; | |
b5f1220d SN |
291 | } |
292 | ||
293 | static int s5pcsis_s_power(struct v4l2_subdev *sd, int on) | |
294 | { | |
295 | struct csis_state *state = sd_to_csis_state(sd); | |
296 | struct device *dev = &state->pdev->dev; | |
297 | ||
298 | if (on) | |
299 | return pm_runtime_get_sync(dev); | |
300 | ||
301 | return pm_runtime_put_sync(dev); | |
302 | } | |
303 | ||
304 | static void s5pcsis_start_stream(struct csis_state *state) | |
305 | { | |
306 | s5pcsis_reset(state); | |
307 | s5pcsis_set_params(state); | |
308 | s5pcsis_system_enable(state, true); | |
309 | s5pcsis_enable_interrupts(state, true); | |
310 | } | |
311 | ||
312 | static void s5pcsis_stop_stream(struct csis_state *state) | |
313 | { | |
314 | s5pcsis_enable_interrupts(state, false); | |
315 | s5pcsis_system_enable(state, false); | |
316 | } | |
317 | ||
318 | /* v4l2_subdev operations */ | |
319 | static int s5pcsis_s_stream(struct v4l2_subdev *sd, int enable) | |
320 | { | |
321 | struct csis_state *state = sd_to_csis_state(sd); | |
322 | int ret = 0; | |
323 | ||
324 | v4l2_dbg(1, debug, sd, "%s: %d, state: 0x%x\n", | |
325 | __func__, enable, state->flags); | |
326 | ||
327 | if (enable) { | |
328 | ret = pm_runtime_get_sync(&state->pdev->dev); | |
329 | if (ret && ret != 1) | |
330 | return ret; | |
331 | } | |
332 | mutex_lock(&state->lock); | |
333 | if (enable) { | |
334 | if (state->flags & ST_SUSPENDED) { | |
335 | ret = -EBUSY; | |
336 | goto unlock; | |
337 | } | |
338 | s5pcsis_start_stream(state); | |
339 | state->flags |= ST_STREAMING; | |
340 | } else { | |
341 | s5pcsis_stop_stream(state); | |
342 | state->flags &= ~ST_STREAMING; | |
343 | } | |
344 | unlock: | |
345 | mutex_unlock(&state->lock); | |
346 | if (!enable) | |
347 | pm_runtime_put(&state->pdev->dev); | |
348 | ||
349 | return ret == 1 ? 0 : ret; | |
350 | } | |
351 | ||
352 | static int s5pcsis_enum_mbus_code(struct v4l2_subdev *sd, | |
353 | struct v4l2_subdev_fh *fh, | |
354 | struct v4l2_subdev_mbus_code_enum *code) | |
355 | { | |
356 | if (code->index >= ARRAY_SIZE(s5pcsis_formats)) | |
357 | return -EINVAL; | |
358 | ||
359 | code->code = s5pcsis_formats[code->index].code; | |
360 | return 0; | |
361 | } | |
362 | ||
363 | static struct csis_pix_format const *s5pcsis_try_format( | |
364 | struct v4l2_mbus_framefmt *mf) | |
365 | { | |
366 | struct csis_pix_format const *csis_fmt; | |
367 | ||
368 | csis_fmt = find_csis_format(mf); | |
369 | if (csis_fmt == NULL) | |
370 | csis_fmt = &s5pcsis_formats[0]; | |
371 | ||
372 | mf->code = csis_fmt->code; | |
373 | v4l_bound_align_image(&mf->width, 1, CSIS_MAX_PIX_WIDTH, | |
374 | csis_fmt->pix_width_alignment, | |
375 | &mf->height, 1, CSIS_MAX_PIX_HEIGHT, 1, | |
376 | 0); | |
377 | return csis_fmt; | |
378 | } | |
379 | ||
380 | static struct v4l2_mbus_framefmt *__s5pcsis_get_format( | |
381 | struct csis_state *state, struct v4l2_subdev_fh *fh, | |
382 | u32 pad, enum v4l2_subdev_format_whence which) | |
383 | { | |
384 | if (which == V4L2_SUBDEV_FORMAT_TRY) | |
385 | return fh ? v4l2_subdev_get_try_format(fh, pad) : NULL; | |
386 | ||
387 | return &state->format; | |
388 | } | |
389 | ||
390 | static int s5pcsis_set_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh, | |
391 | struct v4l2_subdev_format *fmt) | |
392 | { | |
393 | struct csis_state *state = sd_to_csis_state(sd); | |
394 | struct csis_pix_format const *csis_fmt; | |
395 | struct v4l2_mbus_framefmt *mf; | |
396 | ||
397 | if (fmt->pad != CSIS_PAD_SOURCE && fmt->pad != CSIS_PAD_SINK) | |
398 | return -EINVAL; | |
399 | ||
400 | mf = __s5pcsis_get_format(state, fh, fmt->pad, fmt->which); | |
401 | ||
402 | if (fmt->pad == CSIS_PAD_SOURCE) { | |
403 | if (mf) { | |
404 | mutex_lock(&state->lock); | |
405 | fmt->format = *mf; | |
406 | mutex_unlock(&state->lock); | |
407 | } | |
408 | return 0; | |
409 | } | |
410 | csis_fmt = s5pcsis_try_format(&fmt->format); | |
411 | if (mf) { | |
412 | mutex_lock(&state->lock); | |
413 | *mf = fmt->format; | |
414 | if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) | |
415 | state->csis_fmt = csis_fmt; | |
416 | mutex_unlock(&state->lock); | |
417 | } | |
418 | return 0; | |
419 | } | |
420 | ||
421 | static int s5pcsis_get_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh, | |
422 | struct v4l2_subdev_format *fmt) | |
423 | { | |
424 | struct csis_state *state = sd_to_csis_state(sd); | |
425 | struct v4l2_mbus_framefmt *mf; | |
426 | ||
427 | if (fmt->pad != CSIS_PAD_SOURCE && fmt->pad != CSIS_PAD_SINK) | |
428 | return -EINVAL; | |
429 | ||
430 | mf = __s5pcsis_get_format(state, fh, fmt->pad, fmt->which); | |
431 | if (!mf) | |
432 | return -EINVAL; | |
433 | ||
434 | mutex_lock(&state->lock); | |
435 | fmt->format = *mf; | |
436 | mutex_unlock(&state->lock); | |
437 | return 0; | |
438 | } | |
439 | ||
6cf1056f SN |
440 | static int s5pcsis_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) |
441 | { | |
442 | struct v4l2_mbus_framefmt *format = v4l2_subdev_get_try_format(fh, 0); | |
443 | ||
444 | format->colorspace = V4L2_COLORSPACE_JPEG; | |
445 | format->code = s5pcsis_formats[0].code; | |
446 | format->width = S5PCSIS_DEF_PIX_WIDTH; | |
447 | format->height = S5PCSIS_DEF_PIX_HEIGHT; | |
448 | format->field = V4L2_FIELD_NONE; | |
449 | ||
450 | return 0; | |
451 | } | |
452 | ||
453 | static const struct v4l2_subdev_internal_ops s5pcsis_sd_internal_ops = { | |
454 | .open = s5pcsis_open, | |
455 | }; | |
456 | ||
b5f1220d SN |
457 | static struct v4l2_subdev_core_ops s5pcsis_core_ops = { |
458 | .s_power = s5pcsis_s_power, | |
459 | }; | |
460 | ||
461 | static struct v4l2_subdev_pad_ops s5pcsis_pad_ops = { | |
462 | .enum_mbus_code = s5pcsis_enum_mbus_code, | |
463 | .get_fmt = s5pcsis_get_fmt, | |
464 | .set_fmt = s5pcsis_set_fmt, | |
465 | }; | |
466 | ||
467 | static struct v4l2_subdev_video_ops s5pcsis_video_ops = { | |
468 | .s_stream = s5pcsis_s_stream, | |
469 | }; | |
470 | ||
471 | static struct v4l2_subdev_ops s5pcsis_subdev_ops = { | |
472 | .core = &s5pcsis_core_ops, | |
473 | .pad = &s5pcsis_pad_ops, | |
474 | .video = &s5pcsis_video_ops, | |
475 | }; | |
476 | ||
477 | static irqreturn_t s5pcsis_irq_handler(int irq, void *dev_id) | |
478 | { | |
479 | struct csis_state *state = dev_id; | |
480 | u32 val; | |
481 | ||
482 | /* Just clear the interrupt pending bits. */ | |
483 | val = s5pcsis_read(state, S5PCSIS_INTSRC); | |
484 | s5pcsis_write(state, S5PCSIS_INTSRC, val); | |
485 | ||
486 | return IRQ_HANDLED; | |
487 | } | |
488 | ||
489 | static int __devinit s5pcsis_probe(struct platform_device *pdev) | |
490 | { | |
491 | struct s5p_platform_mipi_csis *pdata; | |
492 | struct resource *mem_res; | |
493 | struct resource *regs_res; | |
494 | struct csis_state *state; | |
495 | int ret = -ENOMEM; | |
438df3eb | 496 | int i; |
b5f1220d SN |
497 | |
498 | state = kzalloc(sizeof(*state), GFP_KERNEL); | |
499 | if (!state) | |
500 | return -ENOMEM; | |
501 | ||
502 | mutex_init(&state->lock); | |
503 | state->pdev = pdev; | |
504 | ||
505 | pdata = pdev->dev.platform_data; | |
506 | if (pdata == NULL || pdata->phy_enable == NULL) { | |
507 | dev_err(&pdev->dev, "Platform data not fully specified\n"); | |
508 | goto e_free; | |
509 | } | |
510 | ||
511 | if ((pdev->id == 1 && pdata->lanes > CSIS1_MAX_LANES) || | |
512 | pdata->lanes > CSIS0_MAX_LANES) { | |
513 | ret = -EINVAL; | |
514 | dev_err(&pdev->dev, "Unsupported number of data lanes: %d\n", | |
515 | pdata->lanes); | |
516 | goto e_free; | |
517 | } | |
518 | ||
519 | mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
520 | if (!mem_res) { | |
521 | dev_err(&pdev->dev, "Failed to get IO memory region\n"); | |
522 | goto e_free; | |
523 | } | |
524 | ||
525 | regs_res = request_mem_region(mem_res->start, resource_size(mem_res), | |
526 | pdev->name); | |
527 | if (!regs_res) { | |
528 | dev_err(&pdev->dev, "Failed to request IO memory region\n"); | |
529 | goto e_free; | |
530 | } | |
531 | state->regs_res = regs_res; | |
532 | ||
533 | state->regs = ioremap(mem_res->start, resource_size(mem_res)); | |
534 | if (!state->regs) { | |
535 | dev_err(&pdev->dev, "Failed to remap IO region\n"); | |
536 | goto e_reqmem; | |
537 | } | |
538 | ||
539 | ret = s5pcsis_clk_get(state); | |
540 | if (ret) | |
541 | goto e_unmap; | |
542 | ||
543 | clk_enable(state->clock[CSIS_CLK_MUX]); | |
544 | if (pdata->clk_rate) | |
545 | clk_set_rate(state->clock[CSIS_CLK_MUX], pdata->clk_rate); | |
546 | else | |
547 | dev_WARN(&pdev->dev, "No clock frequency specified!\n"); | |
548 | ||
549 | state->irq = platform_get_irq(pdev, 0); | |
550 | if (state->irq < 0) { | |
551 | ret = state->irq; | |
552 | dev_err(&pdev->dev, "Failed to get irq\n"); | |
553 | goto e_clkput; | |
554 | } | |
555 | ||
438df3eb SN |
556 | for (i = 0; i < CSIS_NUM_SUPPLIES; i++) |
557 | state->supplies[i].supply = csis_supply_name[i]; | |
558 | ||
559 | ret = regulator_bulk_get(&pdev->dev, CSIS_NUM_SUPPLIES, | |
560 | state->supplies); | |
561 | if (ret) | |
562 | goto e_clkput; | |
b5f1220d SN |
563 | |
564 | ret = request_irq(state->irq, s5pcsis_irq_handler, 0, | |
565 | dev_name(&pdev->dev), state); | |
566 | if (ret) { | |
567 | dev_err(&pdev->dev, "request_irq failed\n"); | |
568 | goto e_regput; | |
569 | } | |
570 | ||
571 | v4l2_subdev_init(&state->sd, &s5pcsis_subdev_ops); | |
572 | state->sd.owner = THIS_MODULE; | |
573 | strlcpy(state->sd.name, dev_name(&pdev->dev), sizeof(state->sd.name)); | |
6cf1056f | 574 | state->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; |
b5f1220d SN |
575 | state->csis_fmt = &s5pcsis_formats[0]; |
576 | ||
6cf1056f SN |
577 | state->format.code = s5pcsis_formats[0].code; |
578 | state->format.width = S5PCSIS_DEF_PIX_WIDTH; | |
579 | state->format.height = S5PCSIS_DEF_PIX_HEIGHT; | |
580 | ||
b5f1220d SN |
581 | state->pads[CSIS_PAD_SINK].flags = MEDIA_PAD_FL_SINK; |
582 | state->pads[CSIS_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE; | |
583 | ret = media_entity_init(&state->sd.entity, | |
584 | CSIS_PADS_NUM, state->pads, 0); | |
585 | if (ret < 0) | |
586 | goto e_irqfree; | |
587 | ||
588 | /* This allows to retrieve the platform device id by the host driver */ | |
589 | v4l2_set_subdevdata(&state->sd, pdev); | |
590 | ||
591 | /* .. and a pointer to the subdev. */ | |
592 | platform_set_drvdata(pdev, &state->sd); | |
593 | ||
b5f1220d SN |
594 | pm_runtime_enable(&pdev->dev); |
595 | ||
596 | return 0; | |
597 | ||
598 | e_irqfree: | |
599 | free_irq(state->irq, state); | |
600 | e_regput: | |
438df3eb | 601 | regulator_bulk_free(CSIS_NUM_SUPPLIES, state->supplies); |
b5f1220d SN |
602 | e_clkput: |
603 | clk_disable(state->clock[CSIS_CLK_MUX]); | |
604 | s5pcsis_clk_put(state); | |
605 | e_unmap: | |
606 | iounmap(state->regs); | |
607 | e_reqmem: | |
608 | release_mem_region(regs_res->start, resource_size(regs_res)); | |
609 | e_free: | |
610 | kfree(state); | |
611 | return ret; | |
612 | } | |
613 | ||
d4d4e3c9 | 614 | static int s5pcsis_pm_suspend(struct device *dev, bool runtime) |
b5f1220d SN |
615 | { |
616 | struct s5p_platform_mipi_csis *pdata = dev->platform_data; | |
617 | struct platform_device *pdev = to_platform_device(dev); | |
618 | struct v4l2_subdev *sd = platform_get_drvdata(pdev); | |
619 | struct csis_state *state = sd_to_csis_state(sd); | |
c68956c1 | 620 | int ret = 0; |
b5f1220d SN |
621 | |
622 | v4l2_dbg(1, debug, sd, "%s: flags: 0x%x\n", | |
623 | __func__, state->flags); | |
624 | ||
625 | mutex_lock(&state->lock); | |
626 | if (state->flags & ST_POWERED) { | |
627 | s5pcsis_stop_stream(state); | |
628 | ret = pdata->phy_enable(state->pdev, false); | |
629 | if (ret) | |
630 | goto unlock; | |
438df3eb SN |
631 | ret = regulator_bulk_disable(CSIS_NUM_SUPPLIES, |
632 | state->supplies); | |
633 | if (ret) | |
634 | goto unlock; | |
b5f1220d SN |
635 | clk_disable(state->clock[CSIS_CLK_GATE]); |
636 | state->flags &= ~ST_POWERED; | |
d4d4e3c9 SN |
637 | if (!runtime) |
638 | state->flags |= ST_SUSPENDED; | |
b5f1220d | 639 | } |
b5f1220d SN |
640 | unlock: |
641 | mutex_unlock(&state->lock); | |
642 | return ret ? -EAGAIN : 0; | |
643 | } | |
644 | ||
d4d4e3c9 | 645 | static int s5pcsis_pm_resume(struct device *dev, bool runtime) |
b5f1220d SN |
646 | { |
647 | struct s5p_platform_mipi_csis *pdata = dev->platform_data; | |
648 | struct platform_device *pdev = to_platform_device(dev); | |
649 | struct v4l2_subdev *sd = platform_get_drvdata(pdev); | |
650 | struct csis_state *state = sd_to_csis_state(sd); | |
651 | int ret = 0; | |
652 | ||
653 | v4l2_dbg(1, debug, sd, "%s: flags: 0x%x\n", | |
654 | __func__, state->flags); | |
655 | ||
656 | mutex_lock(&state->lock); | |
d4d4e3c9 | 657 | if (!runtime && !(state->flags & ST_SUSPENDED)) |
b5f1220d SN |
658 | goto unlock; |
659 | ||
660 | if (!(state->flags & ST_POWERED)) { | |
438df3eb SN |
661 | ret = regulator_bulk_enable(CSIS_NUM_SUPPLIES, |
662 | state->supplies); | |
b5f1220d SN |
663 | if (ret) |
664 | goto unlock; | |
b5f1220d SN |
665 | ret = pdata->phy_enable(state->pdev, true); |
666 | if (!ret) { | |
667 | state->flags |= ST_POWERED; | |
438df3eb SN |
668 | } else { |
669 | regulator_bulk_disable(CSIS_NUM_SUPPLIES, | |
670 | state->supplies); | |
b5f1220d SN |
671 | goto unlock; |
672 | } | |
673 | clk_enable(state->clock[CSIS_CLK_GATE]); | |
674 | } | |
675 | if (state->flags & ST_STREAMING) | |
676 | s5pcsis_start_stream(state); | |
677 | ||
678 | state->flags &= ~ST_SUSPENDED; | |
679 | unlock: | |
680 | mutex_unlock(&state->lock); | |
681 | return ret ? -EAGAIN : 0; | |
682 | } | |
683 | ||
684 | #ifdef CONFIG_PM_SLEEP | |
d4d4e3c9 | 685 | static int s5pcsis_suspend(struct device *dev) |
b5f1220d | 686 | { |
d4d4e3c9 | 687 | return s5pcsis_pm_suspend(dev, false); |
b5f1220d SN |
688 | } |
689 | ||
d4d4e3c9 | 690 | static int s5pcsis_resume(struct device *dev) |
b5f1220d | 691 | { |
d4d4e3c9 SN |
692 | return s5pcsis_pm_resume(dev, false); |
693 | } | |
694 | #endif | |
b5f1220d | 695 | |
d4d4e3c9 SN |
696 | #ifdef CONFIG_PM_RUNTIME |
697 | static int s5pcsis_runtime_suspend(struct device *dev) | |
698 | { | |
699 | return s5pcsis_pm_suspend(dev, true); | |
700 | } | |
b5f1220d | 701 | |
d4d4e3c9 SN |
702 | static int s5pcsis_runtime_resume(struct device *dev) |
703 | { | |
704 | return s5pcsis_pm_resume(dev, true); | |
b5f1220d SN |
705 | } |
706 | #endif | |
707 | ||
708 | static int __devexit s5pcsis_remove(struct platform_device *pdev) | |
709 | { | |
710 | struct v4l2_subdev *sd = platform_get_drvdata(pdev); | |
711 | struct csis_state *state = sd_to_csis_state(sd); | |
712 | struct resource *res = state->regs_res; | |
713 | ||
714 | pm_runtime_disable(&pdev->dev); | |
715 | s5pcsis_suspend(&pdev->dev); | |
716 | clk_disable(state->clock[CSIS_CLK_MUX]); | |
717 | pm_runtime_set_suspended(&pdev->dev); | |
718 | ||
719 | s5pcsis_clk_put(state); | |
438df3eb | 720 | regulator_bulk_free(CSIS_NUM_SUPPLIES, state->supplies); |
b5f1220d SN |
721 | |
722 | media_entity_cleanup(&state->sd.entity); | |
723 | free_irq(state->irq, state); | |
724 | iounmap(state->regs); | |
725 | release_mem_region(res->start, resource_size(res)); | |
726 | kfree(state); | |
727 | ||
728 | return 0; | |
729 | } | |
730 | ||
731 | static const struct dev_pm_ops s5pcsis_pm_ops = { | |
d4d4e3c9 SN |
732 | SET_RUNTIME_PM_OPS(s5pcsis_runtime_suspend, s5pcsis_runtime_resume, |
733 | NULL) | |
734 | SET_SYSTEM_SLEEP_PM_OPS(s5pcsis_suspend, s5pcsis_resume) | |
b5f1220d SN |
735 | }; |
736 | ||
737 | static struct platform_driver s5pcsis_driver = { | |
738 | .probe = s5pcsis_probe, | |
739 | .remove = __devexit_p(s5pcsis_remove), | |
740 | .driver = { | |
741 | .name = CSIS_DRIVER_NAME, | |
742 | .owner = THIS_MODULE, | |
743 | .pm = &s5pcsis_pm_ops, | |
744 | }, | |
745 | }; | |
746 | ||
747 | static int __init s5pcsis_init(void) | |
748 | { | |
749 | return platform_driver_probe(&s5pcsis_driver, s5pcsis_probe); | |
750 | } | |
751 | ||
752 | static void __exit s5pcsis_exit(void) | |
753 | { | |
754 | platform_driver_unregister(&s5pcsis_driver); | |
755 | } | |
756 | ||
757 | module_init(s5pcsis_init); | |
758 | module_exit(s5pcsis_exit); | |
759 | ||
760 | MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>"); | |
761 | MODULE_DESCRIPTION("S5P/EXYNOS4 MIPI CSI receiver driver"); | |
762 | MODULE_LICENSE("GPL"); |