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[media] s5p-fimc: Configure scaler registers depending on FIMC version
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / media / video / s5p-fimc / fimc-reg.c
CommitLineData
5fd8f738
SN		 1/*
2 * Register interface file for Samsung Camera Interface (FIMC) driver
3 *
4 * Copyright (c) 2010 Samsung Electronics
5 *
6 * Sylwester Nawrocki, s.nawrocki@samsung.com
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/io.h>
14#include <linux/delay.h>
15#include <mach/map.h>
df7e09a3 16#include <media/s5p_fimc.h>
5fd8f738
SN		 17
18#include "fimc-core.h"
19
20
21void fimc_hw_reset(struct fimc_dev *dev)
22{
23 u32 cfg;
24
25 cfg = readl(dev->regs + S5P_CISRCFMT);
26 cfg |= S5P_CISRCFMT_ITU601_8BIT;
27 writel(cfg, dev->regs + S5P_CISRCFMT);
28
29 /* Software reset. */
30 cfg = readl(dev->regs + S5P_CIGCTRL);
31 cfg |= (S5P_CIGCTRL_SWRST | S5P_CIGCTRL_IRQ_LEVEL);
32 writel(cfg, dev->regs + S5P_CIGCTRL);
548aafcd 33 udelay(1000);
5fd8f738
SN		 34
35 cfg = readl(dev->regs + S5P_CIGCTRL);
36 cfg &= ~S5P_CIGCTRL_SWRST;
37 writel(cfg, dev->regs + S5P_CIGCTRL);
5fd8f738
SN		 38}
39
ac75934c 40static u32 fimc_hw_get_in_flip(struct fimc_ctx *ctx)
5fd8f738
SN		 41{
42 u32 flip = S5P_MSCTRL_FLIP_NORMAL;
43
ac75934c 44 switch (ctx->flip) {
5fd8f738
SN		 45 case FLIP_X_AXIS:
46 flip = S5P_MSCTRL_FLIP_X_MIRROR;
47 break;
48 case FLIP_Y_AXIS:
49 flip = S5P_MSCTRL_FLIP_Y_MIRROR;
50 break;
51 case FLIP_XY_AXIS:
52 flip = S5P_MSCTRL_FLIP_180;
53 break;
ac75934c
SN		 54 default:
55 break;
5fd8f738 56 }
ac75934c
SN		 57 if (ctx->rotation <= 90)
58 return flip;
5fd8f738 59
ac75934c 60 return (flip ^ S5P_MSCTRL_FLIP_180) & S5P_MSCTRL_FLIP_180;
5fd8f738
SN		 61}
62
ac75934c 63static u32 fimc_hw_get_target_flip(struct fimc_ctx *ctx)
5fd8f738
SN		 64{
65 u32 flip = S5P_CITRGFMT_FLIP_NORMAL;
66
ac75934c 67 switch (ctx->flip) {
5fd8f738
SN		 68 case FLIP_X_AXIS:
69 flip = S5P_CITRGFMT_FLIP_X_MIRROR;
70 break;
71 case FLIP_Y_AXIS:
72 flip = S5P_CITRGFMT_FLIP_Y_MIRROR;
73 break;
74 case FLIP_XY_AXIS:
75 flip = S5P_CITRGFMT_FLIP_180;
76 break;
ac75934c 77 default:
5fd8f738 78 break;
5fd8f738 79 }
ac75934c
SN		 80 if (ctx->rotation <= 90)
81 return flip;
82
83 return (flip ^ S5P_CITRGFMT_FLIP_180) & S5P_CITRGFMT_FLIP_180;
5fd8f738
SN		 84}
85
47654df8
SN		 86void fimc_hw_set_rotation(struct fimc_ctx *ctx)
87{
88 u32 cfg, flip;
89 struct fimc_dev *dev = ctx->fimc_dev;
90
91 cfg = readl(dev->regs + S5P_CITRGFMT);
92 cfg &= ~(S5P_CITRGFMT_INROT90 | S5P_CITRGFMT_OUTROT90 |
ac75934c 93 S5P_CITRGFMT_FLIP_180);
47654df8
SN		 94
95 /*
96 * The input and output rotator cannot work simultaneously.
97 * Use the output rotator in output DMA mode or the input rotator
98 * in direct fifo output mode.
99 */
100 if (ctx->rotation == 90 || ctx->rotation == 270) {
47654df8 101 if (ctx->out_path == FIMC_LCDFIFO)
ac75934c 102 cfg |= S5P_CITRGFMT_INROT90;
47654df8 103 else
ac75934c 104 cfg |= S5P_CITRGFMT_OUTROT90;
47654df8 105 }
47654df8 106
ac75934c
SN		 107 if (ctx->out_path == FIMC_DMA) {
108 cfg |= fimc_hw_get_target_flip(ctx);
109 writel(cfg, dev->regs + S5P_CITRGFMT);
110 } else {
111 /* LCD FIFO path */
112 flip = readl(dev->regs + S5P_MSCTRL);
113 flip &= ~S5P_MSCTRL_FLIP_MASK;
114 flip |= fimc_hw_get_in_flip(ctx);
115 writel(flip, dev->regs + S5P_MSCTRL);
116 }
47654df8
SN		 117}
118
5fd8f738
SN		 119void fimc_hw_set_target_format(struct fimc_ctx *ctx)
120{
121 u32 cfg;
122 struct fimc_dev *dev = ctx->fimc_dev;
123 struct fimc_frame *frame = &ctx->d_frame;
124
125 dbg("w= %d, h= %d color: %d", frame->width,
126 frame->height, frame->fmt->color);
127
128 cfg = readl(dev->regs + S5P_CITRGFMT);
129 cfg &= ~(S5P_CITRGFMT_FMT_MASK | S5P_CITRGFMT_HSIZE_MASK |
130 S5P_CITRGFMT_VSIZE_MASK);
131
132 switch (frame->fmt->color) {
ac75934c 133 case S5P_FIMC_RGB565...S5P_FIMC_RGB888:
5fd8f738
SN		 134 cfg |= S5P_CITRGFMT_RGB;
135 break;
136 case S5P_FIMC_YCBCR420:
137 cfg |= S5P_CITRGFMT_YCBCR420;
138 break;
ac75934c 139 case S5P_FIMC_YCBYCR422...S5P_FIMC_CRYCBY422:
ef7af59b 140 if (frame->fmt->colplanes == 1)
5fd8f738
SN		 141 cfg |= S5P_CITRGFMT_YCBCR422_1P;
142 else
143 cfg |= S5P_CITRGFMT_YCBCR422;
144 break;
145 default:
146 break;
147 }
148
47654df8
SN		 149 if (ctx->rotation == 90 || ctx->rotation == 270) {
150 cfg |= S5P_CITRGFMT_HSIZE(frame->height);
151 cfg |= S5P_CITRGFMT_VSIZE(frame->width);
152 } else {
5fd8f738 153
47654df8
SN		 154 cfg |= S5P_CITRGFMT_HSIZE(frame->width);
155 cfg |= S5P_CITRGFMT_VSIZE(frame->height);
5fd8f738 156 }
47654df8 157
5fd8f738
SN		 158 writel(cfg, dev->regs + S5P_CITRGFMT);
159
160 cfg = readl(dev->regs + S5P_CITAREA) & ~S5P_CITAREA_MASK;
161 cfg |= (frame->width * frame->height);
162 writel(cfg, dev->regs + S5P_CITAREA);
163}
164
165static void fimc_hw_set_out_dma_size(struct fimc_ctx *ctx)
166{
167 struct fimc_dev *dev = ctx->fimc_dev;
168 struct fimc_frame *frame = &ctx->d_frame;
47654df8 169 u32 cfg;
5fd8f738 170
47654df8
SN		 171 cfg = S5P_ORIG_SIZE_HOR(frame->f_width);
172 cfg |= S5P_ORIG_SIZE_VER(frame->f_height);
5fd8f738 173 writel(cfg, dev->regs + S5P_ORGOSIZE);
5f3cc447
SN		 174
175 /* Select color space conversion equation (HD/SD size).*/
176 cfg = readl(dev->regs + S5P_CIGCTRL);
177 if (frame->f_width >= 1280) /* HD */
178 cfg |= S5P_CIGCTRL_CSC_ITU601_709;
179 else /* SD */
180 cfg &= ~S5P_CIGCTRL_CSC_ITU601_709;
181 writel(cfg, dev->regs + S5P_CIGCTRL);
182
5fd8f738
SN		 183}
184
185void fimc_hw_set_out_dma(struct fimc_ctx *ctx)
186{
187 u32 cfg;
188 struct fimc_dev *dev = ctx->fimc_dev;
189 struct fimc_frame *frame = &ctx->d_frame;
190 struct fimc_dma_offset *offset = &frame->dma_offset;
191
192 /* Set the input dma offsets. */
193 cfg = 0;
194 cfg |= S5P_CIO_OFFS_HOR(offset->y_h);
195 cfg |= S5P_CIO_OFFS_VER(offset->y_v);
196 writel(cfg, dev->regs + S5P_CIOYOFF);
197
198 cfg = 0;
199 cfg |= S5P_CIO_OFFS_HOR(offset->cb_h);
200 cfg |= S5P_CIO_OFFS_VER(offset->cb_v);
201 writel(cfg, dev->regs + S5P_CIOCBOFF);
202
203 cfg = 0;
204 cfg |= S5P_CIO_OFFS_HOR(offset->cr_h);
205 cfg |= S5P_CIO_OFFS_VER(offset->cr_v);
206 writel(cfg, dev->regs + S5P_CIOCROFF);
207
208 fimc_hw_set_out_dma_size(ctx);
209
210 /* Configure chroma components order. */
211 cfg = readl(dev->regs + S5P_CIOCTRL);
212
213 cfg &= ~(S5P_CIOCTRL_ORDER2P_MASK | S5P_CIOCTRL_ORDER422_MASK |
214 S5P_CIOCTRL_YCBCR_PLANE_MASK);
215
ef7af59b 216 if (frame->fmt->colplanes == 1)
5fd8f738 217 cfg |= ctx->out_order_1p;
ef7af59b 218 else if (frame->fmt->colplanes == 2)
5fd8f738 219 cfg |= ctx->out_order_2p | S5P_CIOCTRL_YCBCR_2PLANE;
ef7af59b 220 else if (frame->fmt->colplanes == 3)
5fd8f738
SN		 221 cfg |= S5P_CIOCTRL_YCBCR_3PLANE;
222
223 writel(cfg, dev->regs + S5P_CIOCTRL);
224}
225
226static void fimc_hw_en_autoload(struct fimc_dev *dev, int enable)
227{
228 u32 cfg = readl(dev->regs + S5P_ORGISIZE);
229 if (enable)
230 cfg |= S5P_CIREAL_ISIZE_AUTOLOAD_EN;
231 else
232 cfg &= ~S5P_CIREAL_ISIZE_AUTOLOAD_EN;
233 writel(cfg, dev->regs + S5P_ORGISIZE);
234}
235
236void fimc_hw_en_lastirq(struct fimc_dev *dev, int enable)
237{
5f3cc447 238 u32 cfg = readl(dev->regs + S5P_CIOCTRL);
5fd8f738
SN		 239 if (enable)
240 cfg |= S5P_CIOCTRL_LASTIRQ_ENABLE;
241 else
242 cfg &= ~S5P_CIOCTRL_LASTIRQ_ENABLE;
243 writel(cfg, dev->regs + S5P_CIOCTRL);
5fd8f738
SN		 244}
245
b241c6d6 246void fimc_hw_set_prescaler(struct fimc_ctx *ctx)
5fd8f738
SN		 247{
248 struct fimc_dev *dev = ctx->fimc_dev;
249 struct fimc_scaler *sc = &ctx->scaler;
548aafcd 250 u32 cfg, shfactor;
5fd8f738
SN		 251
252 shfactor = 10 - (sc->hfactor + sc->vfactor);
253
548aafcd 254 cfg = S5P_CISCPRERATIO_SHFACTOR(shfactor);
5fd8f738
SN		 255 cfg |= S5P_CISCPRERATIO_HOR(sc->pre_hratio);
256 cfg |= S5P_CISCPRERATIO_VER(sc->pre_vratio);
257 writel(cfg, dev->regs + S5P_CISCPRERATIO);
258
548aafcd 259 cfg = S5P_CISCPREDST_WIDTH(sc->pre_dst_width);
5fd8f738
SN		 260 cfg |= S5P_CISCPREDST_HEIGHT(sc->pre_dst_height);
261 writel(cfg, dev->regs + S5P_CISCPREDST);
262}
263
b241c6d6 264static void fimc_hw_set_scaler(struct fimc_ctx *ctx)
5fd8f738
SN		 265{
266 struct fimc_dev *dev = ctx->fimc_dev;
267 struct fimc_scaler *sc = &ctx->scaler;
268 struct fimc_frame *src_frame = &ctx->s_frame;
269 struct fimc_frame *dst_frame = &ctx->d_frame;
270 u32 cfg = 0;
271
272 if (!(ctx->flags & FIMC_COLOR_RANGE_NARROW))
273 cfg |= (S5P_CISCCTRL_CSCR2Y_WIDE | S5P_CISCCTRL_CSCY2R_WIDE);
274
275 if (!sc->enabled)
276 cfg |= S5P_CISCCTRL_SCALERBYPASS;
277
278 if (sc->scaleup_h)
279 cfg |= S5P_CISCCTRL_SCALEUP_H;
280
281 if (sc->scaleup_v)
282 cfg |= S5P_CISCCTRL_SCALEUP_V;
283
284 if (sc->copy_mode)
285 cfg |= S5P_CISCCTRL_ONE2ONE;
286
287
288 if (ctx->in_path == FIMC_DMA) {
289 if (src_frame->fmt->color == S5P_FIMC_RGB565)
290 cfg |= S5P_CISCCTRL_INRGB_FMT_RGB565;
291 else if (src_frame->fmt->color == S5P_FIMC_RGB666)
292 cfg |= S5P_CISCCTRL_INRGB_FMT_RGB666;
293 else if (src_frame->fmt->color == S5P_FIMC_RGB888)
294 cfg |= S5P_CISCCTRL_INRGB_FMT_RGB888;
295 }
296
297 if (ctx->out_path == FIMC_DMA) {
298 if (dst_frame->fmt->color == S5P_FIMC_RGB565)
299 cfg |= S5P_CISCCTRL_OUTRGB_FMT_RGB565;
300 else if (dst_frame->fmt->color == S5P_FIMC_RGB666)
301 cfg |= S5P_CISCCTRL_OUTRGB_FMT_RGB666;
302 else if (dst_frame->fmt->color == S5P_FIMC_RGB888)
303 cfg |= S5P_CISCCTRL_OUTRGB_FMT_RGB888;
304 } else {
305 cfg |= S5P_CISCCTRL_OUTRGB_FMT_RGB888;
306
307 if (ctx->flags & FIMC_SCAN_MODE_INTERLACED)
308 cfg |= S5P_CISCCTRL_INTERLACE;
309 }
310
b241c6d6
HK		 311 writel(cfg, dev->regs + S5P_CISCCTRL);
312}
313
314void fimc_hw_set_mainscaler(struct fimc_ctx *ctx)
315{
316 struct fimc_dev *dev = ctx->fimc_dev;
317 struct fimc_scaler *sc = &ctx->scaler;
318 u32 cfg;
319
320 dbg("main_hratio= 0x%X main_vratio= 0x%X",
321 sc->main_hratio, sc->main_vratio);
322
323 fimc_hw_set_scaler(ctx);
324
325 cfg = readl(dev->regs + S5P_CISCCTRL);
326 cfg &= ~S5P_CISCCTRL_MHRATIO_MASK;
327 cfg &= ~S5P_CISCCTRL_MVRATIO_MASK;
328 cfg |= S5P_CISCCTRL_MHRATIO(sc->main_hratio);
329 cfg |= S5P_CISCCTRL_MVRATIO(sc->main_vratio);
330
331 writel(cfg, dev->regs + S5P_CISCCTRL);
332}
333
334void fimc_hw_set_mainscaler_ext(struct fimc_ctx *ctx)
335{
336 struct fimc_dev *dev = ctx->fimc_dev;
337 struct fimc_scaler *sc = &ctx->scaler;
338 u32 cfg, cfg_ext;
339
5fd8f738
SN		 340 dbg("main_hratio= 0x%X main_vratio= 0x%X",
341 sc->main_hratio, sc->main_vratio);
342
b241c6d6
HK		 343 fimc_hw_set_scaler(ctx);
344
345 cfg = readl(dev->regs + S5P_CISCCTRL);
346 cfg &= ~S5P_CISCCTRL_MHRATIO_MASK;
347 cfg &= ~S5P_CISCCTRL_MVRATIO_MASK;
348 cfg |= S5P_CISCCTRL_MHRATIO_EXT(sc->main_hratio);
349 cfg |= S5P_CISCCTRL_MVRATIO_EXT(sc->main_vratio);
5fd8f738
SN		 350
351 writel(cfg, dev->regs + S5P_CISCCTRL);
b241c6d6
HK		 352
353 cfg_ext = readl(dev->regs + S5P_CIEXTEN);
354 cfg_ext &= ~S5P_CIEXTEN_MHRATIO_EXT_MASK;
355 cfg_ext &= ~S5P_CIEXTEN_MVRATIO_EXT_MASK;
356 cfg_ext |= S5P_CIEXTEN_MHRATIO_EXT(sc->main_hratio);
357 cfg_ext |= S5P_CIEXTEN_MVRATIO_EXT(sc->main_vratio);
358
359 writel(cfg_ext, dev->regs + S5P_CIEXTEN);
5fd8f738
SN		 360}
361
362void fimc_hw_en_capture(struct fimc_ctx *ctx)
363{
364 struct fimc_dev *dev = ctx->fimc_dev;
5fd8f738 365
5f3cc447
SN		 366 u32 cfg = readl(dev->regs + S5P_CIIMGCPT);
367
368 if (ctx->out_path == FIMC_DMA) {
369 /* one shot mode */
370 cfg |= S5P_CIIMGCPT_CPT_FREN_ENABLE | S5P_CIIMGCPT_IMGCPTEN;
371 } else {
372 /* Continous frame capture mode (freerun). */
373 cfg &= ~(S5P_CIIMGCPT_CPT_FREN_ENABLE |
374 S5P_CIIMGCPT_CPT_FRMOD_CNT);
375 cfg |= S5P_CIIMGCPT_IMGCPTEN;
376 }
5fd8f738
SN		 377
378 if (ctx->scaler.enabled)
379 cfg |= S5P_CIIMGCPT_IMGCPTEN_SC;
380
381 writel(cfg | S5P_CIIMGCPT_IMGCPTEN, dev->regs + S5P_CIIMGCPT);
382}
383
384void fimc_hw_set_effect(struct fimc_ctx *ctx)
385{
386 struct fimc_dev *dev = ctx->fimc_dev;
387 struct fimc_effect *effect = &ctx->effect;
388 u32 cfg = (S5P_CIIMGEFF_IE_ENABLE | S5P_CIIMGEFF_IE_SC_AFTER);
389
390 cfg |= effect->type;
391
392 if (effect->type == S5P_FIMC_EFFECT_ARBITRARY) {
393 cfg |= S5P_CIIMGEFF_PAT_CB(effect->pat_cb);
394 cfg |= S5P_CIIMGEFF_PAT_CR(effect->pat_cr);
395 }
396
397 writel(cfg, dev->regs + S5P_CIIMGEFF);
398}
399
400static void fimc_hw_set_in_dma_size(struct fimc_ctx *ctx)
401{
402 struct fimc_dev *dev = ctx->fimc_dev;
403 struct fimc_frame *frame = &ctx->s_frame;
404 u32 cfg_o = 0;
405 u32 cfg_r = 0;
406
407 if (FIMC_LCDFIFO == ctx->out_path)
548aafcd 408 cfg_r |= S5P_CIREAL_ISIZE_AUTOLOAD_EN;
5fd8f738
SN		 409
410 cfg_o |= S5P_ORIG_SIZE_HOR(frame->f_width);
411 cfg_o |= S5P_ORIG_SIZE_VER(frame->f_height);
412 cfg_r |= S5P_CIREAL_ISIZE_WIDTH(frame->width);
413 cfg_r |= S5P_CIREAL_ISIZE_HEIGHT(frame->height);
414
415 writel(cfg_o, dev->regs + S5P_ORGISIZE);
416 writel(cfg_r, dev->regs + S5P_CIREAL_ISIZE);
417}
418
419void fimc_hw_set_in_dma(struct fimc_ctx *ctx)
420{
421 struct fimc_dev *dev = ctx->fimc_dev;
422 struct fimc_frame *frame = &ctx->s_frame;
423 struct fimc_dma_offset *offset = &frame->dma_offset;
548aafcd 424 u32 cfg;
5fd8f738
SN		 425
426 /* Set the pixel offsets. */
548aafcd 427 cfg = S5P_CIO_OFFS_HOR(offset->y_h);
5fd8f738
SN		 428 cfg |= S5P_CIO_OFFS_VER(offset->y_v);
429 writel(cfg, dev->regs + S5P_CIIYOFF);
430
548aafcd 431 cfg = S5P_CIO_OFFS_HOR(offset->cb_h);
5fd8f738
SN		 432 cfg |= S5P_CIO_OFFS_VER(offset->cb_v);
433 writel(cfg, dev->regs + S5P_CIICBOFF);
434
548aafcd 435 cfg = S5P_CIO_OFFS_HOR(offset->cr_h);
5fd8f738
SN		 436 cfg |= S5P_CIO_OFFS_VER(offset->cr_v);
437 writel(cfg, dev->regs + S5P_CIICROFF);
438
439 /* Input original and real size. */
440 fimc_hw_set_in_dma_size(ctx);
441
548aafcd 442 /* Use DMA autoload only in FIFO mode. */
5fd8f738
SN		 443 fimc_hw_en_autoload(dev, ctx->out_path == FIMC_LCDFIFO);
444
445 /* Set the input DMA to process single frame only. */
446 cfg = readl(dev->regs + S5P_MSCTRL);
ac75934c 447 cfg &= ~(S5P_MSCTRL_INFORMAT_MASK
5fd8f738
SN		 448 | S5P_MSCTRL_IN_BURST_COUNT_MASK
449 | S5P_MSCTRL_INPUT_MASK
450 | S5P_MSCTRL_C_INT_IN_MASK
451 | S5P_MSCTRL_2P_IN_ORDER_MASK);
452
d9160afd 453 cfg |= S5P_MSCTRL_IN_BURST_COUNT(4) | S5P_MSCTRL_INPUT_MEMORY;
5fd8f738
SN		 454
455 switch (frame->fmt->color) {
d9160afd 456 case S5P_FIMC_RGB565...S5P_FIMC_RGB888:
5fd8f738
SN		 457 cfg |= S5P_MSCTRL_INFORMAT_RGB;
458 break;
459 case S5P_FIMC_YCBCR420:
460 cfg |= S5P_MSCTRL_INFORMAT_YCBCR420;
461
ef7af59b 462 if (frame->fmt->colplanes == 2)
5fd8f738
SN		 463 cfg |= ctx->in_order_2p | S5P_MSCTRL_C_INT_IN_2PLANE;
464 else
465 cfg |= S5P_MSCTRL_C_INT_IN_3PLANE;
466
467 break;
d9160afd 468 case S5P_FIMC_YCBYCR422...S5P_FIMC_CRYCBY422:
ef7af59b 469 if (frame->fmt->colplanes == 1) {
5fd8f738
SN		 470 cfg |= ctx->in_order_1p
471 | S5P_MSCTRL_INFORMAT_YCBCR422_1P;
472 } else {
473 cfg |= S5P_MSCTRL_INFORMAT_YCBCR422;
474
ef7af59b 475 if (frame->fmt->colplanes == 2)
5fd8f738
SN		 476 cfg |= ctx->in_order_2p
477 | S5P_MSCTRL_C_INT_IN_2PLANE;
478 else
479 cfg |= S5P_MSCTRL_C_INT_IN_3PLANE;
480 }
481 break;
482 default:
483 break;
484 }
485
5fd8f738
SN		 486 writel(cfg, dev->regs + S5P_MSCTRL);
487
488 /* Input/output DMA linear/tiled mode. */
489 cfg = readl(dev->regs + S5P_CIDMAPARAM);
490 cfg &= ~S5P_CIDMAPARAM_TILE_MASK;
491
492 if (tiled_fmt(ctx->s_frame.fmt))
493 cfg |= S5P_CIDMAPARAM_R_64X32;
494
495 if (tiled_fmt(ctx->d_frame.fmt))
496 cfg |= S5P_CIDMAPARAM_W_64X32;
497
498 writel(cfg, dev->regs + S5P_CIDMAPARAM);
499}
500
501
502void fimc_hw_set_input_path(struct fimc_ctx *ctx)
503{
504 struct fimc_dev *dev = ctx->fimc_dev;
505
506 u32 cfg = readl(dev->regs + S5P_MSCTRL);
507 cfg &= ~S5P_MSCTRL_INPUT_MASK;
508
509 if (ctx->in_path == FIMC_DMA)
510 cfg |= S5P_MSCTRL_INPUT_MEMORY;
511 else
512 cfg |= S5P_MSCTRL_INPUT_EXTCAM;
513
514 writel(cfg, dev->regs + S5P_MSCTRL);
515}
516
517void fimc_hw_set_output_path(struct fimc_ctx *ctx)
518{
519 struct fimc_dev *dev = ctx->fimc_dev;
520
521 u32 cfg = readl(dev->regs + S5P_CISCCTRL);
522 cfg &= ~S5P_CISCCTRL_LCDPATHEN_FIFO;
523 if (ctx->out_path == FIMC_LCDFIFO)
524 cfg |= S5P_CISCCTRL_LCDPATHEN_FIFO;
525 writel(cfg, dev->regs + S5P_CISCCTRL);
526}
527
528void fimc_hw_set_input_addr(struct fimc_dev *dev, struct fimc_addr *paddr)
529{
548aafcd 530 u32 cfg = readl(dev->regs + S5P_CIREAL_ISIZE);
5fd8f738
SN		 531 cfg |= S5P_CIREAL_ISIZE_ADDR_CH_DIS;
532 writel(cfg, dev->regs + S5P_CIREAL_ISIZE);
533
77e62082
SN		 534 writel(paddr->y, dev->regs + S5P_CIIYSA(0));
535 writel(paddr->cb, dev->regs + S5P_CIICBSA(0));
536 writel(paddr->cr, dev->regs + S5P_CIICRSA(0));
5fd8f738
SN		 537
538 cfg &= ~S5P_CIREAL_ISIZE_ADDR_CH_DIS;
539 writel(cfg, dev->regs + S5P_CIREAL_ISIZE);
540}
541
548aafcd
SN		 542void fimc_hw_set_output_addr(struct fimc_dev *dev,
543 struct fimc_addr *paddr, int index)
5fd8f738 544{
548aafcd
SN		 545 int i = (index == -1) ? 0 : index;
546 do {
5fd8f738
SN		 547 writel(paddr->y, dev->regs + S5P_CIOYSA(i));
548 writel(paddr->cb, dev->regs + S5P_CIOCBSA(i));
549 writel(paddr->cr, dev->regs + S5P_CIOCRSA(i));
548aafcd
SN		 550 dbg("dst_buf[%d]: 0x%X, cb: 0x%X, cr: 0x%X",
551 i, paddr->y, paddr->cb, paddr->cr);
552 } while (index == -1 && ++i < FIMC_MAX_OUT_BUFS);
5fd8f738 553}
5f3cc447
SN		 554
555int fimc_hw_set_camera_polarity(struct fimc_dev *fimc,
df7e09a3 556 struct s5p_fimc_isp_info *cam)
5f3cc447
SN		 557{
558 u32 cfg = readl(fimc->regs + S5P_CIGCTRL);
559
560 cfg &= ~(S5P_CIGCTRL_INVPOLPCLK | S5P_CIGCTRL_INVPOLVSYNC |
561 S5P_CIGCTRL_INVPOLHREF | S5P_CIGCTRL_INVPOLHSYNC);
562
563 if (cam->flags & FIMC_CLK_INV_PCLK)
564 cfg |= S5P_CIGCTRL_INVPOLPCLK;
565
566 if (cam->flags & FIMC_CLK_INV_VSYNC)
567 cfg |= S5P_CIGCTRL_INVPOLVSYNC;
568
569 if (cam->flags & FIMC_CLK_INV_HREF)
570 cfg |= S5P_CIGCTRL_INVPOLHREF;
571
572 if (cam->flags & FIMC_CLK_INV_HSYNC)
573 cfg |= S5P_CIGCTRL_INVPOLHSYNC;
574
575 writel(cfg, fimc->regs + S5P_CIGCTRL);
576
577 return 0;
578}
579
580int fimc_hw_set_camera_source(struct fimc_dev *fimc,
df7e09a3 581 struct s5p_fimc_isp_info *cam)
5f3cc447
SN		 582{
583 struct fimc_frame *f = &fimc->vid_cap.ctx->s_frame;
584 u32 cfg = 0;
3d0ce7ed
SN		 585 u32 bus_width;
586 int i;
587
588 static const struct {
589 u32 pixelcode;
590 u32 cisrcfmt;
591 u16 bus_width;
592 } pix_desc[] = {
593 { V4L2_MBUS_FMT_YUYV8_2X8, S5P_CISRCFMT_ORDER422_YCBYCR, 8 },
594 { V4L2_MBUS_FMT_YVYU8_2X8, S5P_CISRCFMT_ORDER422_YCRYCB, 8 },
595 { V4L2_MBUS_FMT_VYUY8_2X8, S5P_CISRCFMT_ORDER422_CRYCBY, 8 },
596 { V4L2_MBUS_FMT_UYVY8_2X8, S5P_CISRCFMT_ORDER422_CBYCRY, 8 },
597 /* TODO: Add pixel codes for 16-bit bus width */
598 };
5f3cc447
SN		 599
600 if (cam->bus_type == FIMC_ITU_601 || cam->bus_type == FIMC_ITU_656) {
3d0ce7ed
SN		 601 for (i = 0; i < ARRAY_SIZE(pix_desc); i++) {
602 if (fimc->vid_cap.fmt.code == pix_desc[i].pixelcode) {
603 cfg = pix_desc[i].cisrcfmt;
604 bus_width = pix_desc[i].bus_width;
605 break;
606 }
607 }
5f3cc447 608
3d0ce7ed
SN		 609 if (i == ARRAY_SIZE(pix_desc)) {
610 v4l2_err(&fimc->vid_cap.v4l2_dev,
611 "Camera color format not supported: %d\n",
612 fimc->vid_cap.fmt.code);
5f3cc447
SN		 613 return -EINVAL;
614 }
615
616 if (cam->bus_type == FIMC_ITU_601) {
3d0ce7ed 617 if (bus_width == 8)
5f3cc447 618 cfg |= S5P_CISRCFMT_ITU601_8BIT;
3d0ce7ed 619 else if (bus_width == 16)
5f3cc447 620 cfg |= S5P_CISRCFMT_ITU601_16BIT;
5f3cc447
SN		 621 } /* else defaults to ITU-R BT.656 8-bit */
622 }
623
624 cfg |= S5P_CISRCFMT_HSIZE(f->o_width) | S5P_CISRCFMT_VSIZE(f->o_height);
625 writel(cfg, fimc->regs + S5P_CISRCFMT);
626 return 0;
627}
628
629
630int fimc_hw_set_camera_offset(struct fimc_dev *fimc, struct fimc_frame *f)
631{
632 u32 hoff2, voff2;
633
634 u32 cfg = readl(fimc->regs + S5P_CIWDOFST);
635
636 cfg &= ~(S5P_CIWDOFST_HOROFF_MASK | S5P_CIWDOFST_VEROFF_MASK);
637 cfg |= S5P_CIWDOFST_OFF_EN |
638 S5P_CIWDOFST_HOROFF(f->offs_h) |
639 S5P_CIWDOFST_VEROFF(f->offs_v);
640
641 writel(cfg, fimc->regs + S5P_CIWDOFST);
642
643 /* See CIWDOFSTn register description in the datasheet for details. */
644 hoff2 = f->o_width - f->width - f->offs_h;
645 voff2 = f->o_height - f->height - f->offs_v;
646 cfg = S5P_CIWDOFST2_HOROFF(hoff2) | S5P_CIWDOFST2_VEROFF(voff2);
647
648 writel(cfg, fimc->regs + S5P_CIWDOFST2);
649 return 0;
650}
651
652int fimc_hw_set_camera_type(struct fimc_dev *fimc,
df7e09a3 653 struct s5p_fimc_isp_info *cam)
5f3cc447
SN		 654{
655 u32 cfg, tmp;
656 struct fimc_vid_cap *vid_cap = &fimc->vid_cap;
657
658 cfg = readl(fimc->regs + S5P_CIGCTRL);
659
660 /* Select ITU B interface, disable Writeback path and test pattern. */
661 cfg &= ~(S5P_CIGCTRL_TESTPAT_MASK | S5P_CIGCTRL_SELCAM_ITU_A |
662 S5P_CIGCTRL_SELCAM_MIPI | S5P_CIGCTRL_CAMIF_SELWB |
663 S5P_CIGCTRL_SELCAM_MIPI_A);
664
665 if (cam->bus_type == FIMC_MIPI_CSI2) {
666 cfg |= S5P_CIGCTRL_SELCAM_MIPI;
667
668 if (cam->mux_id == 0)
669 cfg |= S5P_CIGCTRL_SELCAM_MIPI_A;
670
671 /* TODO: add remaining supported formats. */
672 if (vid_cap->fmt.code == V4L2_MBUS_FMT_VYUY8_2X8) {
673 tmp = S5P_CSIIMGFMT_YCBCR422_8BIT;
674 } else {
675 err("camera image format not supported: %d",
676 vid_cap->fmt.code);
677 return -EINVAL;
678 }
679 writel(tmp | (0x1 << 8), fimc->regs + S5P_CSIIMGFMT);
680
681 } else if (cam->bus_type == FIMC_ITU_601 ||
682 cam->bus_type == FIMC_ITU_656) {
683 if (cam->mux_id == 0) /* ITU-A, ITU-B: 0, 1 */
684 cfg |= S5P_CIGCTRL_SELCAM_ITU_A;
685 } else if (cam->bus_type == FIMC_LCD_WB) {
686 cfg |= S5P_CIGCTRL_CAMIF_SELWB;
687 } else {
688 err("invalid camera bus type selected\n");
689 return -EINVAL;
690 }
691 writel(cfg, fimc->regs + S5P_CIGCTRL);
692
693 return 0;
694}
kernel source for telekom puls (alcatel/mediatek)