Commit | Line | Data |
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5fd8f738 SN |
1 | /* |
2 | * Copyright (c) 2010 Samsung Electronics | |
3 | * | |
4 | * Sylwester Nawrocki, <s.nawrocki@samsung.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #ifndef FIMC_CORE_H_ | |
12 | #define FIMC_CORE_H_ | |
13 | ||
5f3cc447 SN |
14 | /*#define DEBUG*/ |
15 | ||
aee7126c | 16 | #include <linux/sched.h> |
5fd8f738 | 17 | #include <linux/types.h> |
aee7126c | 18 | #include <linux/videodev2.h> |
2dab38e2 SN |
19 | #include <linux/io.h> |
20 | #include <media/videobuf2-core.h> | |
5fd8f738 SN |
21 | #include <media/v4l2-device.h> |
22 | #include <media/v4l2-mem2mem.h> | |
5f3cc447 | 23 | #include <media/v4l2-mediabus.h> |
df7e09a3 | 24 | #include <media/s5p_fimc.h> |
aee7126c | 25 | |
5fd8f738 SN |
26 | #include "regs-fimc.h" |
27 | ||
28 | #define err(fmt, args...) \ | |
29 | printk(KERN_ERR "%s:%d: " fmt "\n", __func__, __LINE__, ##args) | |
30 | ||
31 | #ifdef DEBUG | |
32 | #define dbg(fmt, args...) \ | |
33 | printk(KERN_DEBUG "%s:%d: " fmt "\n", __func__, __LINE__, ##args) | |
34 | #else | |
35 | #define dbg(fmt, args...) | |
36 | #endif | |
37 | ||
5f3cc447 SN |
38 | /* Time to wait for next frame VSYNC interrupt while stopping operation. */ |
39 | #define FIMC_SHUTDOWN_TIMEOUT ((100*HZ)/1000) | |
a25be18d | 40 | #define MAX_FIMC_CLOCKS 3 |
5fd8f738 | 41 | #define MODULE_NAME "s5p-fimc" |
a7d5bbcf | 42 | #define FIMC_MAX_DEVS 4 |
5fd8f738 SN |
43 | #define FIMC_MAX_OUT_BUFS 4 |
44 | #define SCALER_MAX_HRATIO 64 | |
45 | #define SCALER_MAX_VRATIO 64 | |
548aafcd | 46 | #define DMA_MIN_SIZE 8 |
5fd8f738 | 47 | |
a25be18d SN |
48 | /* indices to the clocks array */ |
49 | enum { | |
50 | CLK_BUS, | |
51 | CLK_GATE, | |
52 | CLK_CAM, | |
53 | }; | |
54 | ||
5f3cc447 SN |
55 | enum fimc_dev_flags { |
56 | /* for m2m node */ | |
5fd8f738 SN |
57 | ST_IDLE, |
58 | ST_OUTDMA_RUN, | |
59 | ST_M2M_PEND, | |
5f3cc447 SN |
60 | /* for capture node */ |
61 | ST_CAPT_PEND, | |
62 | ST_CAPT_RUN, | |
63 | ST_CAPT_STREAM, | |
64 | ST_CAPT_SHUT, | |
5fd8f738 SN |
65 | }; |
66 | ||
67 | #define fimc_m2m_active(dev) test_bit(ST_OUTDMA_RUN, &(dev)->state) | |
68 | #define fimc_m2m_pending(dev) test_bit(ST_M2M_PEND, &(dev)->state) | |
69 | ||
5f3cc447 SN |
70 | #define fimc_capture_running(dev) test_bit(ST_CAPT_RUN, &(dev)->state) |
71 | #define fimc_capture_pending(dev) test_bit(ST_CAPT_PEND, &(dev)->state) | |
72 | ||
73 | #define fimc_capture_active(dev) \ | |
74 | (test_bit(ST_CAPT_RUN, &(dev)->state) || \ | |
75 | test_bit(ST_CAPT_PEND, &(dev)->state)) | |
76 | ||
77 | #define fimc_capture_streaming(dev) \ | |
78 | test_bit(ST_CAPT_STREAM, &(dev)->state) | |
79 | ||
5fd8f738 | 80 | enum fimc_datapath { |
5f3cc447 | 81 | FIMC_CAMERA, |
5fd8f738 SN |
82 | FIMC_DMA, |
83 | FIMC_LCDFIFO, | |
84 | FIMC_WRITEBACK | |
85 | }; | |
86 | ||
87 | enum fimc_color_fmt { | |
548aafcd | 88 | S5P_FIMC_RGB565 = 0x10, |
5fd8f738 SN |
89 | S5P_FIMC_RGB666, |
90 | S5P_FIMC_RGB888, | |
548aafcd SN |
91 | S5P_FIMC_RGB30_LOCAL, |
92 | S5P_FIMC_YCBCR420 = 0x20, | |
5fd8f738 SN |
93 | S5P_FIMC_YCBYCR422, |
94 | S5P_FIMC_YCRYCB422, | |
95 | S5P_FIMC_CBYCRY422, | |
96 | S5P_FIMC_CRYCBY422, | |
5fd8f738 | 97 | S5P_FIMC_YCBCR444_LOCAL, |
5fd8f738 SN |
98 | }; |
99 | ||
548aafcd SN |
100 | #define fimc_fmt_is_rgb(x) ((x) & 0x10) |
101 | ||
5fd8f738 SN |
102 | /* Cb/Cr chrominance components order for 2 plane Y/CbCr 4:2:2 formats. */ |
103 | #define S5P_FIMC_LSB_CRCB S5P_CIOCTRL_ORDER422_2P_LSB_CRCB | |
104 | ||
105 | /* The embedded image effect selection */ | |
106 | #define S5P_FIMC_EFFECT_ORIGINAL S5P_CIIMGEFF_FIN_BYPASS | |
107 | #define S5P_FIMC_EFFECT_ARBITRARY S5P_CIIMGEFF_FIN_ARBITRARY | |
108 | #define S5P_FIMC_EFFECT_NEGATIVE S5P_CIIMGEFF_FIN_NEGATIVE | |
109 | #define S5P_FIMC_EFFECT_ARTFREEZE S5P_CIIMGEFF_FIN_ARTFREEZE | |
110 | #define S5P_FIMC_EFFECT_EMBOSSING S5P_CIIMGEFF_FIN_EMBOSSING | |
111 | #define S5P_FIMC_EFFECT_SIKHOUETTE S5P_CIIMGEFF_FIN_SILHOUETTE | |
112 | ||
113 | /* The hardware context state. */ | |
548aafcd SN |
114 | #define FIMC_PARAMS (1 << 0) |
115 | #define FIMC_SRC_ADDR (1 << 1) | |
116 | #define FIMC_DST_ADDR (1 << 2) | |
117 | #define FIMC_SRC_FMT (1 << 3) | |
118 | #define FIMC_DST_FMT (1 << 4) | |
119 | #define FIMC_CTX_M2M (1 << 5) | |
120 | #define FIMC_CTX_CAP (1 << 6) | |
5fd8f738 SN |
121 | |
122 | /* Image conversion flags */ | |
123 | #define FIMC_IN_DMA_ACCESS_TILED (1 << 0) | |
124 | #define FIMC_IN_DMA_ACCESS_LINEAR (0 << 0) | |
125 | #define FIMC_OUT_DMA_ACCESS_TILED (1 << 1) | |
126 | #define FIMC_OUT_DMA_ACCESS_LINEAR (0 << 1) | |
127 | #define FIMC_SCAN_MODE_PROGRESSIVE (0 << 2) | |
128 | #define FIMC_SCAN_MODE_INTERLACED (1 << 2) | |
548aafcd SN |
129 | /* |
130 | * YCbCr data dynamic range for RGB-YUV color conversion. | |
131 | * Y/Cb/Cr: (0 ~ 255) */ | |
5fd8f738 SN |
132 | #define FIMC_COLOR_RANGE_WIDE (0 << 3) |
133 | /* Y (16 ~ 235), Cb/Cr (16 ~ 240) */ | |
134 | #define FIMC_COLOR_RANGE_NARROW (1 << 3) | |
135 | ||
136 | #define FLIP_NONE 0 | |
137 | #define FLIP_X_AXIS 1 | |
138 | #define FLIP_Y_AXIS 2 | |
139 | #define FLIP_XY_AXIS (FLIP_X_AXIS | FLIP_Y_AXIS) | |
140 | ||
141 | /** | |
142 | * struct fimc_fmt - the driver's internal color format data | |
5f3cc447 | 143 | * @mbus_code: Media Bus pixel code, -1 if not applicable |
5fd8f738 | 144 | * @name: format description |
5f3cc447 | 145 | * @fourcc: the fourcc code for this format, 0 if not applicable |
5fd8f738 | 146 | * @color: the corresponding fimc_color_fmt |
ef7af59b SN |
147 | * @depth: per plane driver's private 'number of bits per pixel' |
148 | * @memplanes: number of physically non-contiguous data planes | |
149 | * @colplanes: number of physically contiguous data planes | |
5fd8f738 SN |
150 | */ |
151 | struct fimc_fmt { | |
5f3cc447 | 152 | enum v4l2_mbus_pixelcode mbus_code; |
5fd8f738 SN |
153 | char *name; |
154 | u32 fourcc; | |
155 | u32 color; | |
ef7af59b SN |
156 | u16 memplanes; |
157 | u16 colplanes; | |
158 | u8 depth[VIDEO_MAX_PLANES]; | |
5f3cc447 SN |
159 | u16 flags; |
160 | #define FMT_FLAGS_CAM (1 << 0) | |
161 | #define FMT_FLAGS_M2M (1 << 1) | |
5fd8f738 SN |
162 | }; |
163 | ||
164 | /** | |
165 | * struct fimc_dma_offset - pixel offset information for DMA | |
166 | * @y_h: y value horizontal offset | |
167 | * @y_v: y value vertical offset | |
168 | * @cb_h: cb value horizontal offset | |
169 | * @cb_v: cb value vertical offset | |
170 | * @cr_h: cr value horizontal offset | |
171 | * @cr_v: cr value vertical offset | |
172 | */ | |
173 | struct fimc_dma_offset { | |
174 | int y_h; | |
175 | int y_v; | |
176 | int cb_h; | |
177 | int cb_v; | |
178 | int cr_h; | |
179 | int cr_v; | |
180 | }; | |
181 | ||
182 | /** | |
183 | * struct fimc_effect - the configuration data for the "Arbitrary" image effect | |
184 | * @type: effect type | |
185 | * @pat_cb: cr value when type is "arbitrary" | |
186 | * @pat_cr: cr value when type is "arbitrary" | |
187 | */ | |
188 | struct fimc_effect { | |
189 | u32 type; | |
190 | u8 pat_cb; | |
191 | u8 pat_cr; | |
192 | }; | |
193 | ||
194 | /** | |
195 | * struct fimc_scaler - the configuration data for FIMC inetrnal scaler | |
196 | * | |
548aafcd SN |
197 | * @scaleup_h: flag indicating scaling up horizontally |
198 | * @scaleup_v: flag indicating scaling up vertically | |
199 | * @copy_mode: flag indicating transparent DMA transfer (no scaling | |
200 | * and color format conversion) | |
201 | * @enabled: flag indicating if the scaler is used | |
5fd8f738 SN |
202 | * @hfactor: horizontal shift factor |
203 | * @vfactor: vertical shift factor | |
204 | * @pre_hratio: horizontal ratio of the prescaler | |
205 | * @pre_vratio: vertical ratio of the prescaler | |
206 | * @pre_dst_width: the prescaler's destination width | |
207 | * @pre_dst_height: the prescaler's destination height | |
5fd8f738 SN |
208 | * @main_hratio: the main scaler's horizontal ratio |
209 | * @main_vratio: the main scaler's vertical ratio | |
548aafcd SN |
210 | * @real_width: source pixel (width - offset) |
211 | * @real_height: source pixel (height - offset) | |
5fd8f738 SN |
212 | */ |
213 | struct fimc_scaler { | |
dda7ae78 SN |
214 | unsigned int scaleup_h:1; |
215 | unsigned int scaleup_v:1; | |
216 | unsigned int copy_mode:1; | |
217 | unsigned int enabled:1; | |
5fd8f738 SN |
218 | u32 hfactor; |
219 | u32 vfactor; | |
220 | u32 pre_hratio; | |
221 | u32 pre_vratio; | |
222 | u32 pre_dst_width; | |
223 | u32 pre_dst_height; | |
5fd8f738 SN |
224 | u32 main_hratio; |
225 | u32 main_vratio; | |
226 | u32 real_width; | |
227 | u32 real_height; | |
5fd8f738 SN |
228 | }; |
229 | ||
230 | /** | |
231 | * struct fimc_addr - the FIMC physical address set for DMA | |
232 | * | |
233 | * @y: luminance plane physical address | |
234 | * @cb: Cb plane physical address | |
235 | * @cr: Cr plane physical address | |
236 | */ | |
237 | struct fimc_addr { | |
238 | u32 y; | |
239 | u32 cb; | |
240 | u32 cr; | |
241 | }; | |
242 | ||
243 | /** | |
244 | * struct fimc_vid_buffer - the driver's video buffer | |
5f3cc447 SN |
245 | * @vb: v4l videobuf buffer |
246 | * @paddr: precalculated physical address set | |
247 | * @index: buffer index for the output DMA engine | |
5fd8f738 SN |
248 | */ |
249 | struct fimc_vid_buffer { | |
2dab38e2 SN |
250 | struct vb2_buffer vb; |
251 | struct list_head list; | |
5f3cc447 SN |
252 | struct fimc_addr paddr; |
253 | int index; | |
5fd8f738 SN |
254 | }; |
255 | ||
256 | /** | |
548aafcd | 257 | * struct fimc_frame - source/target frame properties |
5fd8f738 SN |
258 | * @f_width: image full width (virtual screen size) |
259 | * @f_height: image full height (virtual screen size) | |
260 | * @o_width: original image width as set by S_FMT | |
261 | * @o_height: original image height as set by S_FMT | |
262 | * @offs_h: image horizontal pixel offset | |
263 | * @offs_v: image vertical pixel offset | |
264 | * @width: image pixel width | |
265 | * @height: image pixel weight | |
266 | * @paddr: image frame buffer physical addresses | |
267 | * @buf_cnt: number of buffers depending on a color format | |
ef7af59b | 268 | * @payload: image size in bytes (w x h x bpp) |
5fd8f738 SN |
269 | * @color: color format |
270 | * @dma_offset: DMA offset in bytes | |
271 | */ | |
272 | struct fimc_frame { | |
273 | u32 f_width; | |
274 | u32 f_height; | |
275 | u32 o_width; | |
276 | u32 o_height; | |
277 | u32 offs_h; | |
278 | u32 offs_v; | |
279 | u32 width; | |
280 | u32 height; | |
ef7af59b | 281 | unsigned long payload[VIDEO_MAX_PLANES]; |
5fd8f738 SN |
282 | struct fimc_addr paddr; |
283 | struct fimc_dma_offset dma_offset; | |
284 | struct fimc_fmt *fmt; | |
285 | }; | |
286 | ||
287 | /** | |
288 | * struct fimc_m2m_device - v4l2 memory-to-memory device data | |
289 | * @vfd: the video device node for v4l2 m2m mode | |
290 | * @v4l2_dev: v4l2 device for m2m mode | |
291 | * @m2m_dev: v4l2 memory-to-memory device data | |
292 | * @ctx: hardware context data | |
293 | * @refcnt: the reference counter | |
294 | */ | |
295 | struct fimc_m2m_device { | |
296 | struct video_device *vfd; | |
297 | struct v4l2_device v4l2_dev; | |
298 | struct v4l2_m2m_dev *m2m_dev; | |
299 | struct fimc_ctx *ctx; | |
300 | int refcnt; | |
301 | }; | |
302 | ||
5f3cc447 SN |
303 | /** |
304 | * struct fimc_vid_cap - camera capture device information | |
305 | * @ctx: hardware context data | |
306 | * @vfd: video device node for camera capture mode | |
307 | * @v4l2_dev: v4l2_device struct to manage subdevs | |
308 | * @sd: pointer to camera sensor subdevice currently in use | |
309 | * @fmt: Media Bus format configured at selected image sensor | |
310 | * @pending_buf_q: the pending buffer queue head | |
311 | * @active_buf_q: the queue head of buffers scheduled in hardware | |
312 | * @vbq: the capture am video buffer queue | |
313 | * @active_buf_cnt: number of video buffers scheduled in hardware | |
314 | * @buf_index: index for managing the output DMA buffers | |
315 | * @frame_count: the frame counter for statistics | |
316 | * @reqbufs_count: the number of buffers requested in REQBUFS ioctl | |
317 | * @input_index: input (camera sensor) index | |
318 | * @refcnt: driver's private reference counter | |
319 | */ | |
320 | struct fimc_vid_cap { | |
321 | struct fimc_ctx *ctx; | |
2dab38e2 | 322 | struct vb2_alloc_ctx *alloc_ctx; |
5f3cc447 SN |
323 | struct video_device *vfd; |
324 | struct v4l2_device v4l2_dev; | |
2dab38e2 | 325 | struct v4l2_subdev *sd;; |
5f3cc447 SN |
326 | struct v4l2_mbus_framefmt fmt; |
327 | struct list_head pending_buf_q; | |
328 | struct list_head active_buf_q; | |
2dab38e2 | 329 | struct vb2_queue vbq; |
5f3cc447 SN |
330 | int active_buf_cnt; |
331 | int buf_index; | |
332 | unsigned int frame_count; | |
333 | unsigned int reqbufs_count; | |
334 | int input_index; | |
335 | int refcnt; | |
336 | }; | |
337 | ||
a7d5bbcf SN |
338 | /** |
339 | * struct fimc_pix_limit - image pixel size limits in various IP configurations | |
340 | * | |
341 | * @scaler_en_w: max input pixel width when the scaler is enabled | |
342 | * @scaler_dis_w: max input pixel width when the scaler is disabled | |
343 | * @in_rot_en_h: max input width with the input rotator is on | |
344 | * @in_rot_dis_w: max input width with the input rotator is off | |
345 | * @out_rot_en_w: max output width with the output rotator on | |
346 | * @out_rot_dis_w: max output width with the output rotator off | |
347 | */ | |
348 | struct fimc_pix_limit { | |
349 | u16 scaler_en_w; | |
350 | u16 scaler_dis_w; | |
351 | u16 in_rot_en_h; | |
352 | u16 in_rot_dis_w; | |
353 | u16 out_rot_en_w; | |
354 | u16 out_rot_dis_w; | |
355 | }; | |
356 | ||
5fd8f738 SN |
357 | /** |
358 | * struct samsung_fimc_variant - camera interface variant information | |
359 | * | |
360 | * @pix_hoff: indicate whether horizontal offset is in pixels or in bytes | |
361 | * @has_inp_rot: set if has input rotator | |
362 | * @has_out_rot: set if has output rotator | |
798174ab | 363 | * @has_cistatus2: 1 if CISTATUS2 register is present in this IP revision |
b241c6d6 HK |
364 | * @has_mainscaler_ext: 1 if extended mainscaler ratios in CIEXTEN register |
365 | * are present in this IP revision | |
a7d5bbcf | 366 | * @pix_limit: pixel size constraints for the scaler |
5fd8f738 SN |
367 | * @min_inp_pixsize: minimum input pixel size |
368 | * @min_out_pixsize: minimum output pixel size | |
a7d5bbcf SN |
369 | * @hor_offs_align: horizontal pixel offset aligment |
370 | * @out_buf_count: the number of buffers in output DMA sequence | |
5fd8f738 SN |
371 | */ |
372 | struct samsung_fimc_variant { | |
373 | unsigned int pix_hoff:1; | |
374 | unsigned int has_inp_rot:1; | |
375 | unsigned int has_out_rot:1; | |
798174ab | 376 | unsigned int has_cistatus2:1; |
b241c6d6 | 377 | unsigned int has_mainscaler_ext:1; |
a7d5bbcf | 378 | struct fimc_pix_limit *pix_limit; |
5fd8f738 SN |
379 | u16 min_inp_pixsize; |
380 | u16 min_out_pixsize; | |
a7d5bbcf SN |
381 | u16 hor_offs_align; |
382 | u16 out_buf_count; | |
5fd8f738 SN |
383 | }; |
384 | ||
385 | /** | |
548aafcd | 386 | * struct samsung_fimc_driverdata - per device type driver data for init time. |
5fd8f738 SN |
387 | * |
388 | * @variant: the variant information for this driver. | |
389 | * @dev_cnt: number of fimc sub-devices available in SoC | |
5f3cc447 | 390 | * @lclk_frequency: fimc bus clock frequency |
5fd8f738 SN |
391 | */ |
392 | struct samsung_fimc_driverdata { | |
393 | struct samsung_fimc_variant *variant[FIMC_MAX_DEVS]; | |
5f3cc447 | 394 | unsigned long lclk_frequency; |
a7d5bbcf | 395 | int num_entities; |
5fd8f738 SN |
396 | }; |
397 | ||
398 | struct fimc_ctx; | |
399 | ||
400 | /** | |
548aafcd | 401 | * struct fimc_dev - abstraction for FIMC entity |
5fd8f738 SN |
402 | * |
403 | * @slock: the spinlock protecting this data structure | |
404 | * @lock: the mutex protecting this data structure | |
405 | * @pdev: pointer to the FIMC platform device | |
5f3cc447 | 406 | * @pdata: pointer to the device platform data |
a25be18d SN |
407 | * @id: FIMC device index (0..FIMC_MAX_DEVS) |
408 | * @num_clocks: the number of clocks managed by this device instance | |
5fd8f738 SN |
409 | * @clock[]: the clocks required for FIMC operation |
410 | * @regs: the mapped hardware registers | |
411 | * @regs_res: the resource claimed for IO registers | |
412 | * @irq: interrupt number of the FIMC subdevice | |
5f3cc447 | 413 | * @irq_queue: |
5fd8f738 | 414 | * @m2m: memory-to-memory V4L2 device information |
5f3cc447 SN |
415 | * @vid_cap: camera capture device information |
416 | * @state: flags used to synchronize m2m and capture mode operation | |
5fd8f738 SN |
417 | */ |
418 | struct fimc_dev { | |
419 | spinlock_t slock; | |
420 | struct mutex lock; | |
421 | struct platform_device *pdev; | |
df7e09a3 | 422 | struct s5p_platform_fimc *pdata; |
5fd8f738 | 423 | struct samsung_fimc_variant *variant; |
a25be18d SN |
424 | u16 id; |
425 | u16 num_clocks; | |
426 | struct clk *clock[MAX_FIMC_CLOCKS]; | |
5fd8f738 SN |
427 | void __iomem *regs; |
428 | struct resource *regs_res; | |
429 | int irq; | |
5f3cc447 | 430 | wait_queue_head_t irq_queue; |
5fd8f738 | 431 | struct fimc_m2m_device m2m; |
5f3cc447 | 432 | struct fimc_vid_cap vid_cap; |
5fd8f738 | 433 | unsigned long state; |
2dab38e2 | 434 | struct vb2_alloc_ctx *alloc_ctx; |
5fd8f738 SN |
435 | }; |
436 | ||
437 | /** | |
438 | * fimc_ctx - the device context data | |
439 | * | |
440 | * @lock: mutex protecting this data structure | |
441 | * @s_frame: source frame properties | |
442 | * @d_frame: destination frame properties | |
443 | * @out_order_1p: output 1-plane YCBCR order | |
444 | * @out_order_2p: output 2-plane YCBCR order | |
445 | * @in_order_1p input 1-plane YCBCR order | |
446 | * @in_order_2p: input 2-plane YCBCR order | |
447 | * @in_path: input mode (DMA or camera) | |
448 | * @out_path: output mode (DMA or FIFO) | |
449 | * @scaler: image scaler properties | |
450 | * @effect: image effect | |
451 | * @rotation: image clockwise rotation in degrees | |
452 | * @flip: image flip mode | |
548aafcd | 453 | * @flags: additional flags for image conversion |
5fd8f738 SN |
454 | * @state: flags to keep track of user configuration |
455 | * @fimc_dev: the FIMC device this context applies to | |
456 | * @m2m_ctx: memory-to-memory device context | |
457 | */ | |
458 | struct fimc_ctx { | |
459 | spinlock_t slock; | |
460 | struct fimc_frame s_frame; | |
461 | struct fimc_frame d_frame; | |
462 | u32 out_order_1p; | |
463 | u32 out_order_2p; | |
464 | u32 in_order_1p; | |
465 | u32 in_order_2p; | |
466 | enum fimc_datapath in_path; | |
467 | enum fimc_datapath out_path; | |
468 | struct fimc_scaler scaler; | |
469 | struct fimc_effect effect; | |
470 | int rotation; | |
471 | u32 flip; | |
472 | u32 flags; | |
473 | u32 state; | |
474 | struct fimc_dev *fimc_dev; | |
475 | struct v4l2_m2m_ctx *m2m_ctx; | |
476 | }; | |
477 | ||
5fd8f738 SN |
478 | static inline int tiled_fmt(struct fimc_fmt *fmt) |
479 | { | |
ef7af59b | 480 | return fmt->fourcc == V4L2_PIX_FMT_NV12MT; |
5fd8f738 SN |
481 | } |
482 | ||
483 | static inline void fimc_hw_clear_irq(struct fimc_dev *dev) | |
484 | { | |
485 | u32 cfg = readl(dev->regs + S5P_CIGCTRL); | |
486 | cfg |= S5P_CIGCTRL_IRQ_CLR; | |
487 | writel(cfg, dev->regs + S5P_CIGCTRL); | |
488 | } | |
489 | ||
548aafcd | 490 | static inline void fimc_hw_enable_scaler(struct fimc_dev *dev, bool on) |
5fd8f738 SN |
491 | { |
492 | u32 cfg = readl(dev->regs + S5P_CISCCTRL); | |
548aafcd SN |
493 | if (on) |
494 | cfg |= S5P_CISCCTRL_SCALERSTART; | |
495 | else | |
496 | cfg &= ~S5P_CISCCTRL_SCALERSTART; | |
5fd8f738 SN |
497 | writel(cfg, dev->regs + S5P_CISCCTRL); |
498 | } | |
499 | ||
548aafcd | 500 | static inline void fimc_hw_activate_input_dma(struct fimc_dev *dev, bool on) |
5fd8f738 | 501 | { |
548aafcd SN |
502 | u32 cfg = readl(dev->regs + S5P_MSCTRL); |
503 | if (on) | |
504 | cfg |= S5P_MSCTRL_ENVID; | |
505 | else | |
506 | cfg &= ~S5P_MSCTRL_ENVID; | |
507 | writel(cfg, dev->regs + S5P_MSCTRL); | |
5fd8f738 SN |
508 | } |
509 | ||
510 | static inline void fimc_hw_dis_capture(struct fimc_dev *dev) | |
511 | { | |
512 | u32 cfg = readl(dev->regs + S5P_CIIMGCPT); | |
513 | cfg &= ~(S5P_CIIMGCPT_IMGCPTEN | S5P_CIIMGCPT_IMGCPTEN_SC); | |
514 | writel(cfg, dev->regs + S5P_CIIMGCPT); | |
515 | } | |
516 | ||
a7d5bbcf SN |
517 | /** |
518 | * fimc_hw_set_dma_seq - configure output DMA buffer sequence | |
519 | * @mask: each bit corresponds to one of 32 output buffer registers set | |
520 | * 1 to include buffer in the sequence, 0 to disable | |
521 | * | |
522 | * This function mask output DMA ring buffers, i.e. it allows to configure | |
523 | * which of the output buffer address registers will be used by the DMA | |
524 | * engine. | |
525 | */ | |
526 | static inline void fimc_hw_set_dma_seq(struct fimc_dev *dev, u32 mask) | |
527 | { | |
528 | writel(mask, dev->regs + S5P_CIFCNTSEQ); | |
529 | } | |
530 | ||
548aafcd SN |
531 | static inline struct fimc_frame *ctx_get_frame(struct fimc_ctx *ctx, |
532 | enum v4l2_buf_type type) | |
03e30ca5 PO |
533 | { |
534 | struct fimc_frame *frame; | |
535 | ||
ef7af59b | 536 | if (V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE == type) { |
5f3cc447 SN |
537 | if (ctx->state & FIMC_CTX_M2M) |
538 | frame = &ctx->s_frame; | |
539 | else | |
540 | return ERR_PTR(-EINVAL); | |
ef7af59b | 541 | } else if (V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE == type) { |
03e30ca5 PO |
542 | frame = &ctx->d_frame; |
543 | } else { | |
544 | v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev, | |
545 | "Wrong buffer/video queue type (%d)\n", type); | |
546 | return ERR_PTR(-EINVAL); | |
547 | } | |
548 | ||
549 | return frame; | |
550 | } | |
551 | ||
798174ab | 552 | /* Return an index to the buffer actually being written. */ |
5f3cc447 SN |
553 | static inline u32 fimc_hw_get_frame_index(struct fimc_dev *dev) |
554 | { | |
798174ab SN |
555 | u32 reg; |
556 | ||
557 | if (dev->variant->has_cistatus2) { | |
558 | reg = readl(dev->regs + S5P_CISTATUS2) & 0x3F; | |
559 | return reg > 0 ? --reg : reg; | |
560 | } else { | |
561 | reg = readl(dev->regs + S5P_CISTATUS); | |
562 | return (reg & S5P_CISTATUS_FRAMECNT_MASK) >> | |
563 | S5P_CISTATUS_FRAMECNT_SHIFT; | |
564 | } | |
5f3cc447 SN |
565 | } |
566 | ||
5fd8f738 SN |
567 | /* -----------------------------------------------------*/ |
568 | /* fimc-reg.c */ | |
548aafcd | 569 | void fimc_hw_reset(struct fimc_dev *fimc); |
5fd8f738 SN |
570 | void fimc_hw_set_rotation(struct fimc_ctx *ctx); |
571 | void fimc_hw_set_target_format(struct fimc_ctx *ctx); | |
572 | void fimc_hw_set_out_dma(struct fimc_ctx *ctx); | |
548aafcd SN |
573 | void fimc_hw_en_lastirq(struct fimc_dev *fimc, int enable); |
574 | void fimc_hw_en_irq(struct fimc_dev *fimc, int enable); | |
b241c6d6 HK |
575 | void fimc_hw_set_prescaler(struct fimc_ctx *ctx); |
576 | void fimc_hw_set_mainscaler(struct fimc_ctx *ctx); | |
577 | void fimc_hw_set_mainscaler_ext(struct fimc_ctx *ctx); | |
5fd8f738 SN |
578 | void fimc_hw_en_capture(struct fimc_ctx *ctx); |
579 | void fimc_hw_set_effect(struct fimc_ctx *ctx); | |
580 | void fimc_hw_set_in_dma(struct fimc_ctx *ctx); | |
581 | void fimc_hw_set_input_path(struct fimc_ctx *ctx); | |
582 | void fimc_hw_set_output_path(struct fimc_ctx *ctx); | |
548aafcd SN |
583 | void fimc_hw_set_input_addr(struct fimc_dev *fimc, struct fimc_addr *paddr); |
584 | void fimc_hw_set_output_addr(struct fimc_dev *fimc, struct fimc_addr *paddr, | |
ef7af59b | 585 | int index); |
5f3cc447 | 586 | int fimc_hw_set_camera_source(struct fimc_dev *fimc, |
df7e09a3 | 587 | struct s5p_fimc_isp_info *cam); |
5f3cc447 SN |
588 | int fimc_hw_set_camera_offset(struct fimc_dev *fimc, struct fimc_frame *f); |
589 | int fimc_hw_set_camera_polarity(struct fimc_dev *fimc, | |
df7e09a3 | 590 | struct s5p_fimc_isp_info *cam); |
5f3cc447 | 591 | int fimc_hw_set_camera_type(struct fimc_dev *fimc, |
df7e09a3 | 592 | struct s5p_fimc_isp_info *cam); |
5f3cc447 SN |
593 | |
594 | /* -----------------------------------------------------*/ | |
595 | /* fimc-core.c */ | |
ef7af59b SN |
596 | int fimc_vidioc_enum_fmt_mplane(struct file *file, void *priv, |
597 | struct v4l2_fmtdesc *f); | |
598 | int fimc_vidioc_g_fmt_mplane(struct file *file, void *priv, | |
599 | struct v4l2_format *f); | |
600 | int fimc_vidioc_try_fmt_mplane(struct file *file, void *priv, | |
601 | struct v4l2_format *f); | |
5f3cc447 SN |
602 | int fimc_vidioc_queryctrl(struct file *file, void *priv, |
603 | struct v4l2_queryctrl *qc); | |
604 | int fimc_vidioc_g_ctrl(struct file *file, void *priv, | |
605 | struct v4l2_control *ctrl); | |
606 | ||
607 | int fimc_try_crop(struct fimc_ctx *ctx, struct v4l2_crop *cr); | |
608 | int check_ctrl_val(struct fimc_ctx *ctx, struct v4l2_control *ctrl); | |
609 | int fimc_s_ctrl(struct fimc_ctx *ctx, struct v4l2_control *ctrl); | |
610 | ||
611 | struct fimc_fmt *find_format(struct v4l2_format *f, unsigned int mask); | |
612 | struct fimc_fmt *find_mbus_format(struct v4l2_mbus_framefmt *f, | |
613 | unsigned int mask); | |
614 | ||
615 | int fimc_check_scaler_ratio(struct v4l2_rect *r, struct fimc_frame *f); | |
616 | int fimc_set_scaler_info(struct fimc_ctx *ctx); | |
617 | int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags); | |
2dab38e2 | 618 | int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb, |
5f3cc447 SN |
619 | struct fimc_frame *frame, struct fimc_addr *paddr); |
620 | ||
621 | /* -----------------------------------------------------*/ | |
622 | /* fimc-capture.c */ | |
623 | int fimc_register_capture_device(struct fimc_dev *fimc); | |
624 | void fimc_unregister_capture_device(struct fimc_dev *fimc); | |
625 | int fimc_sensor_sd_init(struct fimc_dev *fimc, int index); | |
626 | int fimc_vid_cap_buf_queue(struct fimc_dev *fimc, | |
627 | struct fimc_vid_buffer *fimc_vb); | |
548aafcd SN |
628 | |
629 | /* Locking: the caller holds fimc->slock */ | |
630 | static inline void fimc_activate_capture(struct fimc_ctx *ctx) | |
631 | { | |
632 | fimc_hw_enable_scaler(ctx->fimc_dev, ctx->scaler.enabled); | |
633 | fimc_hw_en_capture(ctx); | |
634 | } | |
635 | ||
636 | static inline void fimc_deactivate_capture(struct fimc_dev *fimc) | |
637 | { | |
638 | fimc_hw_en_lastirq(fimc, true); | |
639 | fimc_hw_dis_capture(fimc); | |
640 | fimc_hw_enable_scaler(fimc, false); | |
641 | fimc_hw_en_lastirq(fimc, false); | |
642 | } | |
5fd8f738 | 643 | |
5f3cc447 | 644 | /* |
2dab38e2 SN |
645 | * Add buf to the capture active buffers queue. |
646 | * Locking: Need to be called with fimc_dev::slock held. | |
5f3cc447 SN |
647 | */ |
648 | static inline void active_queue_add(struct fimc_vid_cap *vid_cap, | |
2dab38e2 | 649 | struct fimc_vid_buffer *buf) |
5f3cc447 | 650 | { |
2dab38e2 | 651 | list_add_tail(&buf->list, &vid_cap->active_buf_q); |
5f3cc447 SN |
652 | vid_cap->active_buf_cnt++; |
653 | } | |
654 | ||
655 | /* | |
656 | * Pop a video buffer from the capture active buffers queue | |
2dab38e2 | 657 | * Locking: Need to be called with fimc_dev::slock held. |
5f3cc447 SN |
658 | */ |
659 | static inline struct fimc_vid_buffer * | |
660 | active_queue_pop(struct fimc_vid_cap *vid_cap) | |
661 | { | |
662 | struct fimc_vid_buffer *buf; | |
663 | buf = list_entry(vid_cap->active_buf_q.next, | |
2dab38e2 SN |
664 | struct fimc_vid_buffer, list); |
665 | list_del(&buf->list); | |
5f3cc447 SN |
666 | vid_cap->active_buf_cnt--; |
667 | return buf; | |
668 | } | |
669 | ||
670 | /* Add video buffer to the capture pending buffers queue */ | |
671 | static inline void fimc_pending_queue_add(struct fimc_vid_cap *vid_cap, | |
672 | struct fimc_vid_buffer *buf) | |
673 | { | |
2dab38e2 | 674 | list_add_tail(&buf->list, &vid_cap->pending_buf_q); |
5f3cc447 SN |
675 | } |
676 | ||
677 | /* Add video buffer to the capture pending buffers queue */ | |
678 | static inline struct fimc_vid_buffer * | |
679 | pending_queue_pop(struct fimc_vid_cap *vid_cap) | |
680 | { | |
681 | struct fimc_vid_buffer *buf; | |
682 | buf = list_entry(vid_cap->pending_buf_q.next, | |
2dab38e2 SN |
683 | struct fimc_vid_buffer, list); |
684 | list_del(&buf->list); | |
5f3cc447 SN |
685 | return buf; |
686 | } | |
687 | ||
5fd8f738 | 688 | #endif /* FIMC_CORE_H_ */ |