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[media] s5p-fimc: Configure scaler registers depending on FIMC version
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / media / video / s5p-fimc / fimc-core.c
CommitLineData
5fd8f738
SN		 1/*
2 * S5P camera interface (video postprocessor) driver
3 *
5f3cc447 4 * Copyright (c) 2010 Samsung Electronics Co., Ltd
5fd8f738
SN		 5 *
6 * Sylwester Nawrocki, <s.nawrocki@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published
10 * by the Free Software Foundation, either version 2 of the License,
11 * or (at your option) any later version.
12 */
13
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/version.h>
17#include <linux/types.h>
18#include <linux/errno.h>
19#include <linux/bug.h>
20#include <linux/interrupt.h>
21#include <linux/device.h>
22#include <linux/platform_device.h>
23#include <linux/list.h>
24#include <linux/io.h>
25#include <linux/slab.h>
26#include <linux/clk.h>
27#include <media/v4l2-ioctl.h>
2dab38e2
SN		 28#include <media/videobuf2-core.h>
29#include <media/videobuf2-dma-contig.h>
5fd8f738
SN		 30
31#include "fimc-core.h"
32
a25be18d
SN		 33static char *fimc_clocks[MAX_FIMC_CLOCKS] = {
34 "sclk_fimc", "fimc", "sclk_cam"
35};
5fd8f738
SN		 36
37static struct fimc_fmt fimc_formats[] = {
38 {
ef7af59b
SN		 39 .name = "RGB565",
40 .fourcc = V4L2_PIX_FMT_RGB565X,
41 .depth = { 16 },
42 .color = S5P_FIMC_RGB565,
43 .memplanes = 1,
44 .colplanes = 1,
45 .mbus_code = V4L2_MBUS_FMT_RGB565_2X8_BE,
46 .flags = FMT_FLAGS_M2M,
5fd8f738 47 }, {
ef7af59b
SN		 48 .name = "BGR666",
49 .fourcc = V4L2_PIX_FMT_BGR666,
50 .depth = { 32 },
51 .color = S5P_FIMC_RGB666,
52 .memplanes = 1,
53 .colplanes = 1,
54 .flags = FMT_FLAGS_M2M,
5fd8f738 55 }, {
ef7af59b
SN		 56 .name = "XRGB-8-8-8-8, 32 bpp",
57 .fourcc = V4L2_PIX_FMT_RGB32,
58 .depth = { 32 },
59 .color = S5P_FIMC_RGB888,
60 .memplanes = 1,
61 .colplanes = 1,
62 .flags = FMT_FLAGS_M2M,
5fd8f738 63 }, {
ef7af59b
SN		 64 .name = "YUV 4:2:2 packed, YCbYCr",
65 .fourcc = V4L2_PIX_FMT_YUYV,
66 .depth = { 16 },
67 .color = S5P_FIMC_YCBYCR422,
68 .memplanes = 1,
69 .colplanes = 1,
70 .mbus_code = V4L2_MBUS_FMT_YUYV8_2X8,
71 .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
5f3cc447 72 }, {
ef7af59b
SN		 73 .name = "YUV 4:2:2 packed, CbYCrY",
74 .fourcc = V4L2_PIX_FMT_UYVY,
75 .depth = { 16 },
76 .color = S5P_FIMC_CBYCRY422,
77 .memplanes = 1,
78 .colplanes = 1,
79 .mbus_code = V4L2_MBUS_FMT_UYVY8_2X8,
80 .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
5fd8f738 81 }, {
ef7af59b
SN		 82 .name = "YUV 4:2:2 packed, CrYCbY",
83 .fourcc = V4L2_PIX_FMT_VYUY,
84 .depth = { 16 },
85 .color = S5P_FIMC_CRYCBY422,
86 .memplanes = 1,
87 .colplanes = 1,
88 .mbus_code = V4L2_MBUS_FMT_VYUY8_2X8,
89 .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
5fd8f738 90 }, {
ef7af59b
SN		 91 .name = "YUV 4:2:2 packed, YCrYCb",
92 .fourcc = V4L2_PIX_FMT_YVYU,
93 .depth = { 16 },
94 .color = S5P_FIMC_YCRYCB422,
95 .memplanes = 1,
96 .colplanes = 1,
97 .mbus_code = V4L2_MBUS_FMT_YVYU8_2X8,
98 .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
5fd8f738 99 }, {
ef7af59b
SN		 100 .name = "YUV 4:2:2 planar, Y/Cb/Cr",
101 .fourcc = V4L2_PIX_FMT_YUV422P,
102 .depth = { 12 },
103 .color = S5P_FIMC_YCBYCR422,
104 .memplanes = 1,
105 .colplanes = 3,
106 .flags = FMT_FLAGS_M2M,
5fd8f738 107 }, {
ef7af59b
SN		 108 .name = "YUV 4:2:2 planar, Y/CbCr",
109 .fourcc = V4L2_PIX_FMT_NV16,
110 .depth = { 16 },
111 .color = S5P_FIMC_YCBYCR422,
112 .memplanes = 1,
113 .colplanes = 2,
114 .flags = FMT_FLAGS_M2M,
5fd8f738 115 }, {
ef7af59b
SN		 116 .name = "YUV 4:2:2 planar, Y/CrCb",
117 .fourcc = V4L2_PIX_FMT_NV61,
118 .depth = { 16 },
119 .color = S5P_FIMC_YCRYCB422,
120 .memplanes = 1,
121 .colplanes = 2,
122 .flags = FMT_FLAGS_M2M,
5fd8f738 123 }, {
ef7af59b
SN		 124 .name = "YUV 4:2:0 planar, YCbCr",
125 .fourcc = V4L2_PIX_FMT_YUV420,
126 .depth = { 12 },
127 .color = S5P_FIMC_YCBCR420,
128 .memplanes = 1,
129 .colplanes = 3,
130 .flags = FMT_FLAGS_M2M,
5fd8f738 131 }, {
ef7af59b
SN		 132 .name = "YUV 4:2:0 planar, Y/CbCr",
133 .fourcc = V4L2_PIX_FMT_NV12,
134 .depth = { 12 },
135 .color = S5P_FIMC_YCBCR420,
136 .memplanes = 1,
137 .colplanes = 2,
138 .flags = FMT_FLAGS_M2M,
139 }, {
140 .name = "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr",
141 .fourcc = V4L2_PIX_FMT_NV12M,
142 .color = S5P_FIMC_YCBCR420,
143 .depth = { 8, 4 },
144 .memplanes = 2,
145 .colplanes = 2,
146 .flags = FMT_FLAGS_M2M,
147 }, {
148 .name = "YUV 4:2:0 non-contiguous 3-planar, Y/Cb/Cr",
149 .fourcc = V4L2_PIX_FMT_YUV420M,
150 .color = S5P_FIMC_YCBCR420,
151 .depth = { 8, 2, 2 },
152 .memplanes = 3,
153 .colplanes = 3,
154 .flags = FMT_FLAGS_M2M,
155 }, {
156 .name = "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr, tiled",
157 .fourcc = V4L2_PIX_FMT_NV12MT,
158 .color = S5P_FIMC_YCBCR420,
159 .depth = { 8, 4 },
160 .memplanes = 2,
161 .colplanes = 2,
162 .flags = FMT_FLAGS_M2M,
5f3cc447 163 },
548aafcd 164};
5fd8f738
SN		 165
166static struct v4l2_queryctrl fimc_ctrls[] = {
167 {
168 .id = V4L2_CID_HFLIP,
169 .type = V4L2_CTRL_TYPE_BOOLEAN,
170 .name = "Horizontal flip",
171 .minimum = 0,
172 .maximum = 1,
173 .default_value = 0,
548aafcd 174 }, {
5fd8f738
SN		 175 .id = V4L2_CID_VFLIP,
176 .type = V4L2_CTRL_TYPE_BOOLEAN,
177 .name = "Vertical flip",
178 .minimum = 0,
179 .maximum = 1,
180 .default_value = 0,
548aafcd 181 }, {
5fd8f738
SN		 182 .id = V4L2_CID_ROTATE,
183 .type = V4L2_CTRL_TYPE_INTEGER,
184 .name = "Rotation (CCW)",
185 .minimum = 0,
186 .maximum = 270,
187 .step = 90,
188 .default_value = 0,
189 },
190};
191
192
193static struct v4l2_queryctrl *get_ctrl(int id)
194{
195 int i;
196
197 for (i = 0; i < ARRAY_SIZE(fimc_ctrls); ++i)
198 if (id == fimc_ctrls[i].id)
199 return &fimc_ctrls[i];
200 return NULL;
201}
202
5f3cc447 203int fimc_check_scaler_ratio(struct v4l2_rect *r, struct fimc_frame *f)
5fd8f738
SN		 204{
205 if (r->width > f->width) {
206 if (f->width > (r->width * SCALER_MAX_HRATIO))
207 return -EINVAL;
208 } else {
209 if ((f->width * SCALER_MAX_HRATIO) < r->width)
210 return -EINVAL;
211 }
212
213 if (r->height > f->height) {
214 if (f->height > (r->height * SCALER_MAX_VRATIO))
215 return -EINVAL;
216 } else {
217 if ((f->height * SCALER_MAX_VRATIO) < r->height)
218 return -EINVAL;
219 }
220
221 return 0;
222}
223
224static int fimc_get_scaler_factor(u32 src, u32 tar, u32 *ratio, u32 *shift)
225{
548aafcd
SN		 226 u32 sh = 6;
227
228 if (src >= 64 * tar)
5fd8f738 229 return -EINVAL;
548aafcd
SN		 230
231 while (sh--) {
232 u32 tmp = 1 << sh;
233 if (src >= tar * tmp) {
234 *shift = sh, *ratio = tmp;
235 return 0;
236 }
5fd8f738
SN		 237 }
238
548aafcd
SN		 239 *shift = 0, *ratio = 1;
240
241 dbg("s: %d, t: %d, shift: %d, ratio: %d",
242 src, tar, *shift, *ratio);
5fd8f738
SN		 243 return 0;
244}
245
5f3cc447 246int fimc_set_scaler_info(struct fimc_ctx *ctx)
5fd8f738
SN		 247{
248 struct fimc_scaler *sc = &ctx->scaler;
249 struct fimc_frame *s_frame = &ctx->s_frame;
250 struct fimc_frame *d_frame = &ctx->d_frame;
b241c6d6 251 struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
5fd8f738
SN		 252 int tx, ty, sx, sy;
253 int ret;
254
47654df8
SN		 255 if (ctx->rotation == 90 || ctx->rotation == 270) {
256 ty = d_frame->width;
257 tx = d_frame->height;
258 } else {
259 tx = d_frame->width;
260 ty = d_frame->height;
261 }
5fd8f738
SN		 262 if (tx <= 0 || ty <= 0) {
263 v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
264 "invalid target size: %d x %d", tx, ty);
265 return -EINVAL;
266 }
267
268 sx = s_frame->width;
269 sy = s_frame->height;
270 if (sx <= 0 || sy <= 0) {
271 err("invalid source size: %d x %d", sx, sy);
272 return -EINVAL;
273 }
274
275 sc->real_width = sx;
276 sc->real_height = sy;
277 dbg("sx= %d, sy= %d, tx= %d, ty= %d", sx, sy, tx, ty);
278
279 ret = fimc_get_scaler_factor(sx, tx, &sc->pre_hratio, &sc->hfactor);
280 if (ret)
281 return ret;
282
283 ret = fimc_get_scaler_factor(sy, ty, &sc->pre_vratio, &sc->vfactor);
284 if (ret)
285 return ret;
286
287 sc->pre_dst_width = sx / sc->pre_hratio;
288 sc->pre_dst_height = sy / sc->pre_vratio;
289
b241c6d6
HK		 290 if (variant->has_mainscaler_ext) {
291 sc->main_hratio = (sx << 14) / (tx << sc->hfactor);
292 sc->main_vratio = (sy << 14) / (ty << sc->vfactor);
293 } else {
294 sc->main_hratio = (sx << 8) / (tx << sc->hfactor);
295 sc->main_vratio = (sy << 8) / (ty << sc->vfactor);
296
297 }
5fd8f738
SN		 298
299 sc->scaleup_h = (tx >= sx) ? 1 : 0;
300 sc->scaleup_v = (ty >= sy) ? 1 : 0;
301
302 /* check to see if input and output size/format differ */
303 if (s_frame->fmt->color == d_frame->fmt->color
304 && s_frame->width == d_frame->width
305 && s_frame->height == d_frame->height)
306 sc->copy_mode = 1;
307 else
308 sc->copy_mode = 0;
309
310 return 0;
311}
312
5f3cc447
SN		 313static void fimc_capture_handler(struct fimc_dev *fimc)
314{
315 struct fimc_vid_cap *cap = &fimc->vid_cap;
316 struct fimc_vid_buffer *v_buf = NULL;
317
318 if (!list_empty(&cap->active_buf_q)) {
319 v_buf = active_queue_pop(cap);
2dab38e2 320 vb2_buffer_done(&v_buf->vb, VB2_BUF_STATE_DONE);
5f3cc447
SN		 321 }
322
323 if (test_and_clear_bit(ST_CAPT_SHUT, &fimc->state)) {
324 wake_up(&fimc->irq_queue);
325 return;
326 }
327
328 if (!list_empty(&cap->pending_buf_q)) {
329
330 v_buf = pending_queue_pop(cap);
331 fimc_hw_set_output_addr(fimc, &v_buf->paddr, cap->buf_index);
332 v_buf->index = cap->buf_index;
333
334 dbg("hw ptr: %d, sw ptr: %d",
335 fimc_hw_get_frame_index(fimc), cap->buf_index);
336
5f3cc447
SN		 337 /* Move the buffer to the capture active queue */
338 active_queue_add(cap, v_buf);
339
340 dbg("next frame: %d, done frame: %d",
341 fimc_hw_get_frame_index(fimc), v_buf->index);
342
343 if (++cap->buf_index >= FIMC_MAX_OUT_BUFS)
344 cap->buf_index = 0;
345
346 } else if (test_and_clear_bit(ST_CAPT_STREAM, &fimc->state) &&
347 cap->active_buf_cnt <= 1) {
348 fimc_deactivate_capture(fimc);
349 }
350
351 dbg("frame: %d, active_buf_cnt= %d",
352 fimc_hw_get_frame_index(fimc), cap->active_buf_cnt);
353}
5fd8f738
SN		 354
355static irqreturn_t fimc_isr(int irq, void *priv)
356{
548aafcd 357 struct fimc_dev *fimc = priv;
5fd8f738
SN		 358
359 BUG_ON(!fimc);
360 fimc_hw_clear_irq(fimc);
361
362 spin_lock(&fimc->slock);
363
364 if (test_and_clear_bit(ST_M2M_PEND, &fimc->state)) {
2dab38e2
SN		 365 struct vb2_buffer *src_vb, *dst_vb;
366 struct fimc_ctx *ctx = v4l2_m2m_get_curr_priv(fimc->m2m.m2m_dev);
367
5fd8f738
SN		 368 if (!ctx || !ctx->m2m_ctx)
369 goto isr_unlock;
2dab38e2
SN		 370
371 src_vb = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
372 dst_vb = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
373 if (src_vb && dst_vb) {
374 v4l2_m2m_buf_done(src_vb, VB2_BUF_STATE_DONE);
375 v4l2_m2m_buf_done(dst_vb, VB2_BUF_STATE_DONE);
5fd8f738
SN		 376 v4l2_m2m_job_finish(fimc->m2m.m2m_dev, ctx->m2m_ctx);
377 }
5f3cc447
SN		 378 goto isr_unlock;
379
380 }
381
382 if (test_bit(ST_CAPT_RUN, &fimc->state))
383 fimc_capture_handler(fimc);
384
385 if (test_and_clear_bit(ST_CAPT_PEND, &fimc->state)) {
386 set_bit(ST_CAPT_RUN, &fimc->state);
387 wake_up(&fimc->irq_queue);
5fd8f738
SN		 388 }
389
390isr_unlock:
391 spin_unlock(&fimc->slock);
392 return IRQ_HANDLED;
393}
394
ef7af59b 395/* The color format (colplanes, memplanes) must be already configured. */
2dab38e2 396int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
548aafcd 397 struct fimc_frame *frame, struct fimc_addr *paddr)
5fd8f738 398{
5fd8f738 399 int ret = 0;
548aafcd 400 u32 pix_size;
5fd8f738 401
2dab38e2 402 if (vb == NULL || frame == NULL)
5fd8f738
SN		 403 return -EINVAL;
404
405 pix_size = frame->width * frame->height;
406
ef7af59b
SN		 407 dbg("memplanes= %d, colplanes= %d, pix_size= %d",
408 frame->fmt->memplanes, frame->fmt->colplanes, pix_size);
409
410 paddr->y = vb2_dma_contig_plane_paddr(vb, 0);
5fd8f738 411
ef7af59b
SN		 412 if (frame->fmt->memplanes == 1) {
413 switch (frame->fmt->colplanes) {
5fd8f738
SN		 414 case 1:
415 paddr->cb = 0;
416 paddr->cr = 0;
417 break;
418 case 2:
419 /* decompose Y into Y/Cb */
420 paddr->cb = (u32)(paddr->y + pix_size);
421 paddr->cr = 0;
422 break;
423 case 3:
424 paddr->cb = (u32)(paddr->y + pix_size);
425 /* decompose Y into Y/Cb/Cr */
426 if (S5P_FIMC_YCBCR420 == frame->fmt->color)
427 paddr->cr = (u32)(paddr->cb
428 + (pix_size >> 2));
429 else /* 422 */
430 paddr->cr = (u32)(paddr->cb
431 + (pix_size >> 1));
432 break;
433 default:
434 return -EINVAL;
435 }
ef7af59b
SN		 436 } else {
437 if (frame->fmt->memplanes >= 2)
438 paddr->cb = vb2_dma_contig_plane_paddr(vb, 1);
439
440 if (frame->fmt->memplanes == 3)
441 paddr->cr = vb2_dma_contig_plane_paddr(vb, 2);
5fd8f738
SN		 442 }
443
548aafcd
SN		 444 dbg("PHYS_ADDR: y= 0x%X cb= 0x%X cr= 0x%X ret= %d",
445 paddr->y, paddr->cb, paddr->cr, ret);
5fd8f738
SN		 446
447 return ret;
448}
449
450/* Set order for 1 and 2 plane YCBCR 4:2:2 formats. */
451static void fimc_set_yuv_order(struct fimc_ctx *ctx)
452{
453 /* The one only mode supported in SoC. */
454 ctx->in_order_2p = S5P_FIMC_LSB_CRCB;
455 ctx->out_order_2p = S5P_FIMC_LSB_CRCB;
456
457 /* Set order for 1 plane input formats. */
458 switch (ctx->s_frame.fmt->color) {
459 case S5P_FIMC_YCRYCB422:
10038bea 460 ctx->in_order_1p = S5P_MSCTRL_ORDER422_CBYCRY;
5fd8f738
SN		 461 break;
462 case S5P_FIMC_CBYCRY422:
10038bea 463 ctx->in_order_1p = S5P_MSCTRL_ORDER422_YCRYCB;
5fd8f738
SN		 464 break;
465 case S5P_FIMC_CRYCBY422:
10038bea 466 ctx->in_order_1p = S5P_MSCTRL_ORDER422_YCBYCR;
5fd8f738
SN		 467 break;
468 case S5P_FIMC_YCBYCR422:
469 default:
10038bea 470 ctx->in_order_1p = S5P_MSCTRL_ORDER422_CRYCBY;
5fd8f738
SN		 471 break;
472 }
473 dbg("ctx->in_order_1p= %d", ctx->in_order_1p);
474
475 switch (ctx->d_frame.fmt->color) {
476 case S5P_FIMC_YCRYCB422:
10038bea 477 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_CBYCRY;
5fd8f738
SN		 478 break;
479 case S5P_FIMC_CBYCRY422:
10038bea 480 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_YCRYCB;
5fd8f738
SN		 481 break;
482 case S5P_FIMC_CRYCBY422:
10038bea 483 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_YCBYCR;
5fd8f738
SN		 484 break;
485 case S5P_FIMC_YCBYCR422:
486 default:
10038bea 487 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_CRYCBY;
5fd8f738
SN		 488 break;
489 }
490 dbg("ctx->out_order_1p= %d", ctx->out_order_1p);
491}
492
ddc79e0f
SN		 493static void fimc_prepare_dma_offset(struct fimc_ctx *ctx, struct fimc_frame *f)
494{
495 struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
ef7af59b
SN		 496 u32 i, depth = 0;
497
498 for (i = 0; i < f->fmt->colplanes; i++)
499 depth += f->fmt->depth[i];
ddc79e0f
SN		 500
501 f->dma_offset.y_h = f->offs_h;
502 if (!variant->pix_hoff)
ef7af59b 503 f->dma_offset.y_h *= (depth >> 3);
ddc79e0f
SN		 504
505 f->dma_offset.y_v = f->offs_v;
506
507 f->dma_offset.cb_h = f->offs_h;
508 f->dma_offset.cb_v = f->offs_v;
509
510 f->dma_offset.cr_h = f->offs_h;
511 f->dma_offset.cr_v = f->offs_v;
512
513 if (!variant->pix_hoff) {
ef7af59b 514 if (f->fmt->colplanes == 3) {
ddc79e0f
SN		 515 f->dma_offset.cb_h >>= 1;
516 f->dma_offset.cr_h >>= 1;
517 }
518 if (f->fmt->color == S5P_FIMC_YCBCR420) {
519 f->dma_offset.cb_v >>= 1;
520 f->dma_offset.cr_v >>= 1;
521 }
522 }
523
524 dbg("in_offset: color= %d, y_h= %d, y_v= %d",
525 f->fmt->color, f->dma_offset.y_h, f->dma_offset.y_v);
526}
527
5fd8f738
SN		 528/**
529 * fimc_prepare_config - check dimensions, operation and color mode
530 * and pre-calculate offset and the scaling coefficients.
531 *
532 * @ctx: hardware context information
533 * @flags: flags indicating which parameters to check/update
534 *
535 * Return: 0 if dimensions are valid or non zero otherwise.
536 */
5f3cc447 537int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags)
5fd8f738
SN		 538{
539 struct fimc_frame *s_frame, *d_frame;
2dab38e2 540 struct vb2_buffer *vb = NULL;
5fd8f738
SN		 541 int ret = 0;
542
543 s_frame = &ctx->s_frame;
544 d_frame = &ctx->d_frame;
545
546 if (flags & FIMC_PARAMS) {
ddc79e0f
SN		 547 /* Prepare the DMA offset ratios for scaler. */
548 fimc_prepare_dma_offset(ctx, &ctx->s_frame);
549 fimc_prepare_dma_offset(ctx, &ctx->d_frame);
5fd8f738 550
5fd8f738
SN		 551 if (s_frame->height > (SCALER_MAX_VRATIO * d_frame->height) ||
552 s_frame->width > (SCALER_MAX_HRATIO * d_frame->width)) {
553 err("out of scaler range");
554 return -EINVAL;
555 }
ddc79e0f 556 fimc_set_yuv_order(ctx);
5fd8f738
SN		 557 }
558
559 /* Input DMA mode is not allowed when the scaler is disabled. */
560 ctx->scaler.enabled = 1;
561
562 if (flags & FIMC_SRC_ADDR) {
2dab38e2
SN		 563 vb = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
564 ret = fimc_prepare_addr(ctx, vb, s_frame, &s_frame->paddr);
5fd8f738
SN		 565 if (ret)
566 return ret;
567 }
568
569 if (flags & FIMC_DST_ADDR) {
2dab38e2
SN		 570 vb = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
571 ret = fimc_prepare_addr(ctx, vb, d_frame, &d_frame->paddr);
5fd8f738
SN		 572 }
573
574 return ret;
575}
576
577static void fimc_dma_run(void *priv)
578{
579 struct fimc_ctx *ctx = priv;
580 struct fimc_dev *fimc;
b241c6d6 581 struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
5fd8f738
SN		 582 unsigned long flags;
583 u32 ret;
584
1ce6a143 585 if (WARN(!ctx, "null hardware context\n"))
5fd8f738
SN		 586 return;
587
588 fimc = ctx->fimc_dev;
589
590 spin_lock_irqsave(&ctx->slock, flags);
591 set_bit(ST_M2M_PEND, &fimc->state);
592
593 ctx->state |= (FIMC_SRC_ADDR | FIMC_DST_ADDR);
594 ret = fimc_prepare_config(ctx, ctx->state);
595 if (ret) {
548aafcd 596 err("Wrong parameters");
5fd8f738
SN		 597 goto dma_unlock;
598 }
548aafcd
SN		 599 /* Reconfigure hardware if the context has changed. */
600 if (fimc->m2m.ctx != ctx) {
5fd8f738 601 ctx->state |= FIMC_PARAMS;
548aafcd
SN		 602 fimc->m2m.ctx = ctx;
603 }
5fd8f738
SN		 604
605 fimc_hw_set_input_addr(fimc, &ctx->s_frame.paddr);
606
607 if (ctx->state & FIMC_PARAMS) {
608 fimc_hw_set_input_path(ctx);
609 fimc_hw_set_in_dma(ctx);
610 if (fimc_set_scaler_info(ctx)) {
548aafcd 611 err("Scaler setup error");
5fd8f738
SN		 612 goto dma_unlock;
613 }
b241c6d6
HK		 614
615 fimc_hw_set_prescaler(ctx);
616 if (variant->has_mainscaler_ext)
617 fimc_hw_set_mainscaler_ext(ctx);
618 else
619 fimc_hw_set_mainscaler(ctx);
5fd8f738
SN		 620 fimc_hw_set_target_format(ctx);
621 fimc_hw_set_rotation(ctx);
622 fimc_hw_set_effect(ctx);
623 }
624
625 fimc_hw_set_output_path(ctx);
626 if (ctx->state & (FIMC_DST_ADDR | FIMC_PARAMS))
548aafcd 627 fimc_hw_set_output_addr(fimc, &ctx->d_frame.paddr, -1);
5fd8f738
SN		 628
629 if (ctx->state & FIMC_PARAMS)
630 fimc_hw_set_out_dma(ctx);
631
548aafcd 632 fimc_activate_capture(ctx);
5fd8f738 633
2dab38e2
SN		 634 ctx->state &= (FIMC_CTX_M2M | FIMC_CTX_CAP |
635 FIMC_SRC_FMT | FIMC_DST_FMT);
548aafcd 636 fimc_hw_activate_input_dma(fimc, true);
5fd8f738
SN		 637
638dma_unlock:
639 spin_unlock_irqrestore(&ctx->slock, flags);
640}
641
03e30ca5
PO		 642static void fimc_job_abort(void *priv)
643{
644 /* Nothing done in job_abort. */
645}
5fd8f738 646
2dab38e2 647static int fimc_queue_setup(struct vb2_queue *vq, unsigned int *num_buffers,
ef7af59b
SN		 648 unsigned int *num_planes, unsigned long sizes[],
649 void *allocators[])
5fd8f738 650{
2dab38e2 651 struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
ef7af59b
SN		 652 struct fimc_frame *f;
653 int i;
654
655 f = ctx_get_frame(ctx, vq->type);
656 if (IS_ERR(f))
657 return PTR_ERR(f);
5fd8f738 658
ef7af59b
SN		 659 /*
660 * Return number of non-contigous planes (plane buffers)
661 * depending on the configured color format.
662 */
663 if (f->fmt)
664 *num_planes = f->fmt->memplanes;
5fd8f738 665
ef7af59b
SN		 666 for (i = 0; i < f->fmt->memplanes; i++) {
667 sizes[i] = (f->width * f->height * f->fmt->depth[i]) >> 3;
668 allocators[i] = ctx->fimc_dev->alloc_ctx;
669 }
2dab38e2 670
ef7af59b
SN		 671 if (*num_buffers == 0)
672 *num_buffers = 1;
5fd8f738 673
5fd8f738
SN		 674 return 0;
675}
676
2dab38e2 677static int fimc_buf_prepare(struct vb2_buffer *vb)
5fd8f738 678{
2dab38e2 679 struct fimc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
5fd8f738 680 struct fimc_frame *frame;
ef7af59b 681 int i;
5fd8f738 682
2dab38e2 683 frame = ctx_get_frame(ctx, vb->vb2_queue->type);
03e30ca5
PO		 684 if (IS_ERR(frame))
685 return PTR_ERR(frame);
5fd8f738 686
ef7af59b
SN		 687 for (i = 0; i < frame->fmt->memplanes; i++)
688 vb2_set_plane_payload(vb, i, frame->payload[i]);
5fd8f738 689
5fd8f738
SN		 690 return 0;
691}
692
2dab38e2 693static void fimc_buf_queue(struct vb2_buffer *vb)
5fd8f738 694{
2dab38e2 695 struct fimc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
5f3cc447
SN		 696
697 dbg("ctx: %p, ctx->state: 0x%x", ctx, ctx->state);
698
2dab38e2
SN		 699 if (ctx->m2m_ctx)
700 v4l2_m2m_buf_queue(ctx->m2m_ctx, vb);
701}
5f3cc447 702
2dab38e2
SN		 703static void fimc_lock(struct vb2_queue *vq)
704{
705 struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
706 mutex_lock(&ctx->fimc_dev->lock);
707}
5f3cc447 708
2dab38e2
SN		 709static void fimc_unlock(struct vb2_queue *vq)
710{
711 struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
712 mutex_unlock(&ctx->fimc_dev->lock);
5fd8f738
SN		 713}
714
2dab38e2
SN		 715struct vb2_ops fimc_qops = {
716 .queue_setup = fimc_queue_setup,
717 .buf_prepare = fimc_buf_prepare,
718 .buf_queue = fimc_buf_queue,
719 .wait_prepare = fimc_unlock,
720 .wait_finish = fimc_lock,
5fd8f738
SN		 721};
722
723static int fimc_m2m_querycap(struct file *file, void *priv,
724 struct v4l2_capability *cap)
725{
726 struct fimc_ctx *ctx = file->private_data;
727 struct fimc_dev *fimc = ctx->fimc_dev;
728
729 strncpy(cap->driver, fimc->pdev->name, sizeof(cap->driver) - 1);
730 strncpy(cap->card, fimc->pdev->name, sizeof(cap->card) - 1);
731 cap->bus_info[0] = 0;
732 cap->version = KERNEL_VERSION(1, 0, 0);
733 cap->capabilities = V4L2_CAP_STREAMING |
ef7af59b
SN		 734 V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OUTPUT |
735 V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_VIDEO_OUTPUT_MPLANE;
5fd8f738
SN		 736
737 return 0;
738}
739
ef7af59b 740int fimc_vidioc_enum_fmt_mplane(struct file *file, void *priv,
5fd8f738
SN		 741 struct v4l2_fmtdesc *f)
742{
743 struct fimc_fmt *fmt;
744
745 if (f->index >= ARRAY_SIZE(fimc_formats))
746 return -EINVAL;
747
748 fmt = &fimc_formats[f->index];
749 strncpy(f->description, fmt->name, sizeof(f->description) - 1);
750 f->pixelformat = fmt->fourcc;
5f3cc447 751
5fd8f738
SN		 752 return 0;
753}
754
ef7af59b
SN		 755int fimc_vidioc_g_fmt_mplane(struct file *file, void *priv,
756 struct v4l2_format *f)
5fd8f738
SN		 757{
758 struct fimc_ctx *ctx = priv;
759 struct fimc_frame *frame;
760
548aafcd 761 frame = ctx_get_frame(ctx, f->type);
03e30ca5
PO		 762 if (IS_ERR(frame))
763 return PTR_ERR(frame);
5fd8f738
SN		 764
765 f->fmt.pix.width = frame->width;
766 f->fmt.pix.height = frame->height;
767 f->fmt.pix.field = V4L2_FIELD_NONE;
768 f->fmt.pix.pixelformat = frame->fmt->fourcc;
769
770 return 0;
771}
772
5f3cc447 773struct fimc_fmt *find_format(struct v4l2_format *f, unsigned int mask)
5fd8f738
SN		 774{
775 struct fimc_fmt *fmt;
776 unsigned int i;
777
778 for (i = 0; i < ARRAY_SIZE(fimc_formats); ++i) {
779 fmt = &fimc_formats[i];
5f3cc447
SN		 780 if (fmt->fourcc == f->fmt.pix.pixelformat &&
781 (fmt->flags & mask))
5fd8f738
SN		 782 break;
783 }
5fd8f738 784
5f3cc447 785 return (i == ARRAY_SIZE(fimc_formats)) ? NULL : fmt;
5fd8f738
SN		 786}
787
5f3cc447
SN		 788struct fimc_fmt *find_mbus_format(struct v4l2_mbus_framefmt *f,
789 unsigned int mask)
5fd8f738
SN		 790{
791 struct fimc_fmt *fmt;
5f3cc447
SN		 792 unsigned int i;
793
794 for (i = 0; i < ARRAY_SIZE(fimc_formats); ++i) {
795 fmt = &fimc_formats[i];
796 if (fmt->mbus_code == f->code && (fmt->flags & mask))
797 break;
798 }
799
800 return (i == ARRAY_SIZE(fimc_formats)) ? NULL : fmt;
801}
802
803
ef7af59b
SN		 804int fimc_vidioc_try_fmt_mplane(struct file *file, void *priv,
805 struct v4l2_format *f)
5f3cc447 806{
5fd8f738
SN		 807 struct fimc_ctx *ctx = priv;
808 struct fimc_dev *fimc = ctx->fimc_dev;
5fd8f738 809 struct samsung_fimc_variant *variant = fimc->variant;
ef7af59b 810 struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
5f3cc447
SN		 811 struct fimc_fmt *fmt;
812 u32 max_width, mod_x, mod_y, mask;
8293ebfc
SN		 813 int i, is_output = 0;
814
5fd8f738 815
ef7af59b 816 if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
5f3cc447
SN		 817 if (ctx->state & FIMC_CTX_CAP)
818 return -EINVAL;
819 is_output = 1;
ef7af59b 820 } else if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
5fd8f738
SN		 821 return -EINVAL;
822 }
823
ef7af59b 824 dbg("w: %d, h: %d", pix->width, pix->height);
5f3cc447
SN		 825
826 mask = is_output ? FMT_FLAGS_M2M : FMT_FLAGS_M2M | FMT_FLAGS_CAM;
827 fmt = find_format(f, mask);
828 if (!fmt) {
829 v4l2_err(&fimc->m2m.v4l2_dev, "Fourcc format (0x%X) invalid.\n",
830 pix->pixelformat);
8293ebfc 831 return -EINVAL;
5f3cc447
SN		 832 }
833
5fd8f738
SN		 834 if (pix->field == V4L2_FIELD_ANY)
835 pix->field = V4L2_FIELD_NONE;
836 else if (V4L2_FIELD_NONE != pix->field)
8293ebfc 837 return -EINVAL;
5fd8f738 838
5f3cc447 839 if (is_output) {
a7d5bbcf 840 max_width = variant->pix_limit->scaler_dis_w;
5f3cc447 841 mod_x = ffs(variant->min_inp_pixsize) - 1;
5fd8f738 842 } else {
a7d5bbcf 843 max_width = variant->pix_limit->out_rot_dis_w;
5f3cc447 844 mod_x = ffs(variant->min_out_pixsize) - 1;
5fd8f738
SN		 845 }
846
5fd8f738 847 if (tiled_fmt(fmt)) {
5f3cc447
SN		 848 mod_x = 6; /* 64 x 32 pixels tile */
849 mod_y = 5;
850 } else {
ef7af59b 851 if (fimc->id == 1 && variant->pix_hoff)
5f3cc447
SN		 852 mod_y = fimc_fmt_is_rgb(fmt->color) ? 0 : 1;
853 else
854 mod_y = mod_x;
5fd8f738
SN		 855 }
856
5f3cc447 857 dbg("mod_x: %d, mod_y: %d, max_w: %d", mod_x, mod_y, max_width);
5fd8f738 858
5f3cc447 859 v4l_bound_align_image(&pix->width, 16, max_width, mod_x,
a7d5bbcf 860 &pix->height, 8, variant->pix_limit->scaler_dis_w, mod_y, 0);
5fd8f738 861
ef7af59b
SN		 862 pix->num_planes = fmt->memplanes;
863
864 for (i = 0; i < pix->num_planes; ++i) {
865 int bpl = pix->plane_fmt[i].bytesperline;
866
867 dbg("[%d] bpl: %d, depth: %d, w: %d, h: %d",
868 i, bpl, fmt->depth[i], pix->width, pix->height);
869
870 if (!bpl || (bpl * 8 / fmt->depth[i]) > pix->width)
871 bpl = (pix->width * fmt->depth[0]) >> 3;
5fd8f738 872
ef7af59b
SN		 873 if (!pix->plane_fmt[i].sizeimage)
874 pix->plane_fmt[i].sizeimage = pix->height * bpl;
5fd8f738 875
ef7af59b
SN		 876 pix->plane_fmt[i].bytesperline = bpl;
877
878 dbg("[%d]: bpl: %d, sizeimage: %d",
879 i, pix->plane_fmt[i].bytesperline,
880 pix->plane_fmt[i].sizeimage);
881 }
5fd8f738 882
8293ebfc 883 return 0;
5f3cc447 884}
5fd8f738 885
ef7af59b
SN		 886static int fimc_m2m_s_fmt_mplane(struct file *file, void *priv,
887 struct v4l2_format *f)
5fd8f738
SN		 888{
889 struct fimc_ctx *ctx = priv;
28f06ff4 890 struct fimc_dev *fimc = ctx->fimc_dev;
2dab38e2 891 struct vb2_queue *vq;
5fd8f738 892 struct fimc_frame *frame;
ef7af59b 893 struct v4l2_pix_format_mplane *pix;
5fd8f738 894 unsigned long flags;
ef7af59b 895 int i, ret = 0;
8293ebfc 896 u32 tmp;
5fd8f738 897
ef7af59b 898 ret = fimc_vidioc_try_fmt_mplane(file, priv, f);
5fd8f738
SN		 899 if (ret)
900 return ret;
901
28f06ff4 902 vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
5fd8f738 903
2dab38e2 904 if (vb2_is_streaming(vq)) {
8293ebfc
SN		 905 v4l2_err(&fimc->m2m.v4l2_dev, "queue (%d) busy\n", f->type);
906 return -EBUSY;
28f06ff4 907 }
5fd8f738 908
ef7af59b 909 if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
5fd8f738 910 frame = &ctx->s_frame;
ef7af59b 911 } else if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
5fd8f738 912 frame = &ctx->d_frame;
5fd8f738 913 } else {
ef7af59b 914 v4l2_err(&fimc->m2m.v4l2_dev,
5fd8f738 915 "Wrong buffer/video queue type (%d)\n", f->type);
8293ebfc 916 return -EINVAL;
5fd8f738
SN		 917 }
918
ef7af59b 919 pix = &f->fmt.pix_mp;
5f3cc447 920 frame->fmt = find_format(f, FMT_FLAGS_M2M);
8293ebfc
SN		 921 if (!frame->fmt)
922 return -EINVAL;
5fd8f738 923
ef7af59b
SN		 924 for (i = 0; i < frame->fmt->colplanes; i++)
925 frame->payload[i] = pix->plane_fmt[i].bytesperline * pix->height;
926
927 frame->f_width = pix->plane_fmt[0].bytesperline * 8 /
928 frame->fmt->depth[0];
28f06ff4
SN		 929 frame->f_height = pix->height;
930 frame->width = pix->width;
931 frame->height = pix->height;
932 frame->o_width = pix->width;
5fd8f738 933 frame->o_height = pix->height;
28f06ff4
SN		 934 frame->offs_h = 0;
935 frame->offs_v = 0;
28f06ff4 936
5fd8f738 937 spin_lock_irqsave(&ctx->slock, flags);
8293ebfc
SN		 938 tmp = (frame == &ctx->d_frame) ? FIMC_DST_FMT : FIMC_SRC_FMT;
939 ctx->state |= FIMC_PARAMS | tmp;
5fd8f738
SN		 940 spin_unlock_irqrestore(&ctx->slock, flags);
941
28f06ff4 942 dbg("f_w: %d, f_h: %d", frame->f_width, frame->f_height);
5fd8f738 943
8293ebfc 944 return 0;
5fd8f738
SN		 945}
946
947static int fimc_m2m_reqbufs(struct file *file, void *priv,
948 struct v4l2_requestbuffers *reqbufs)
949{
950 struct fimc_ctx *ctx = priv;
951 return v4l2_m2m_reqbufs(file, ctx->m2m_ctx, reqbufs);
952}
953
954static int fimc_m2m_querybuf(struct file *file, void *priv,
955 struct v4l2_buffer *buf)
956{
957 struct fimc_ctx *ctx = priv;
958 return v4l2_m2m_querybuf(file, ctx->m2m_ctx, buf);
959}
960
961static int fimc_m2m_qbuf(struct file *file, void *priv,
962 struct v4l2_buffer *buf)
963{
964 struct fimc_ctx *ctx = priv;
965
966 return v4l2_m2m_qbuf(file, ctx->m2m_ctx, buf);
967}
968
969static int fimc_m2m_dqbuf(struct file *file, void *priv,
970 struct v4l2_buffer *buf)
971{
972 struct fimc_ctx *ctx = priv;
973 return v4l2_m2m_dqbuf(file, ctx->m2m_ctx, buf);
974}
975
976static int fimc_m2m_streamon(struct file *file, void *priv,
977 enum v4l2_buf_type type)
978{
979 struct fimc_ctx *ctx = priv;
2dab38e2
SN		 980
981 /* The source and target color format need to be set */
ef7af59b
SN		 982 if (V4L2_TYPE_IS_OUTPUT(type)) {
983 if (~ctx->state & FIMC_SRC_FMT)
984 return -EINVAL;
985 } else if (~ctx->state & FIMC_DST_FMT) {
2dab38e2 986 return -EINVAL;
ef7af59b 987 }
2dab38e2 988
5fd8f738
SN		 989 return v4l2_m2m_streamon(file, ctx->m2m_ctx, type);
990}
991
992static int fimc_m2m_streamoff(struct file *file, void *priv,
993 enum v4l2_buf_type type)
994{
995 struct fimc_ctx *ctx = priv;
996 return v4l2_m2m_streamoff(file, ctx->m2m_ctx, type);
997}
998
5f3cc447 999int fimc_vidioc_queryctrl(struct file *file, void *priv,
5fd8f738
SN		 1000 struct v4l2_queryctrl *qc)
1001{
5f3cc447 1002 struct fimc_ctx *ctx = priv;
5fd8f738 1003 struct v4l2_queryctrl *c;
69e05e83 1004 int ret = -EINVAL;
5f3cc447 1005
5fd8f738 1006 c = get_ctrl(qc->id);
5f3cc447
SN		 1007 if (c) {
1008 *qc = *c;
1009 return 0;
1010 }
1011
69e05e83 1012 if (ctx->state & FIMC_CTX_CAP) {
8293ebfc 1013 return v4l2_subdev_call(ctx->fimc_dev->vid_cap.sd,
5f3cc447 1014 core, queryctrl, qc);
69e05e83
SN		 1015 }
1016 return ret;
5fd8f738
SN		 1017}
1018
5f3cc447 1019int fimc_vidioc_g_ctrl(struct file *file, void *priv,
5fd8f738
SN		 1020 struct v4l2_control *ctrl)
1021{
1022 struct fimc_ctx *ctx = priv;
5f3cc447 1023 struct fimc_dev *fimc = ctx->fimc_dev;
5fd8f738
SN		 1024
1025 switch (ctrl->id) {
1026 case V4L2_CID_HFLIP:
1027 ctrl->value = (FLIP_X_AXIS & ctx->flip) ? 1 : 0;
1028 break;
1029 case V4L2_CID_VFLIP:
1030 ctrl->value = (FLIP_Y_AXIS & ctx->flip) ? 1 : 0;
1031 break;
1032 case V4L2_CID_ROTATE:
1033 ctrl->value = ctx->rotation;
1034 break;
1035 default:
5f3cc447 1036 if (ctx->state & FIMC_CTX_CAP) {
8293ebfc
SN		 1037 return v4l2_subdev_call(fimc->vid_cap.sd, core,
1038 g_ctrl, ctrl);
5f3cc447
SN		 1039 } else {
1040 v4l2_err(&fimc->m2m.v4l2_dev,
1041 "Invalid control\n");
8293ebfc 1042 return -EINVAL;
5f3cc447 1043 }
5fd8f738
SN		 1044 }
1045 dbg("ctrl->value= %d", ctrl->value);
5f3cc447 1046
8293ebfc 1047 return 0;
5fd8f738
SN		 1048}
1049
5f3cc447 1050int check_ctrl_val(struct fimc_ctx *ctx, struct v4l2_control *ctrl)
5fd8f738
SN		 1051{
1052 struct v4l2_queryctrl *c;
1053 c = get_ctrl(ctrl->id);
1054 if (!c)
1055 return -EINVAL;
1056
1057 if (ctrl->value < c->minimum || ctrl->value > c->maximum
1058 || (c->step != 0 && ctrl->value % c->step != 0)) {
1059 v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
1060 "Invalid control value\n");
1061 return -ERANGE;
1062 }
1063
1064 return 0;
1065}
1066
5f3cc447 1067int fimc_s_ctrl(struct fimc_ctx *ctx, struct v4l2_control *ctrl)
5fd8f738 1068{
5fd8f738 1069 struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
5f3cc447 1070 struct fimc_dev *fimc = ctx->fimc_dev;
5fd8f738 1071 unsigned long flags;
5fd8f738 1072
5f3cc447 1073 spin_lock_irqsave(&ctx->slock, flags);
5fd8f738
SN		 1074
1075 switch (ctrl->id) {
1076 case V4L2_CID_HFLIP:
5fd8f738
SN		 1077 if (ctrl->value)
1078 ctx->flip |= FLIP_X_AXIS;
1079 else
1080 ctx->flip &= ~FLIP_X_AXIS;
1081 break;
1082
1083 case V4L2_CID_VFLIP:
5fd8f738
SN		 1084 if (ctrl->value)
1085 ctx->flip |= FLIP_Y_AXIS;
1086 else
1087 ctx->flip &= ~FLIP_Y_AXIS;
1088 break;
1089
1090 case V4L2_CID_ROTATE:
5f3cc447
SN		 1091 /* Check for the output rotator availability */
1092 if ((ctrl->value == 90 || ctrl->value == 270) &&
1093 (ctx->in_path == FIMC_DMA && !variant->has_out_rot)) {
1094 spin_unlock_irqrestore(&ctx->slock, flags);
1095 return -EINVAL;
1096 } else {
1097 ctx->rotation = ctrl->value;
5fd8f738 1098 }
5fd8f738
SN		 1099 break;
1100
1101 default:
5f3cc447
SN		 1102 spin_unlock_irqrestore(&ctx->slock, flags);
1103 v4l2_err(&fimc->m2m.v4l2_dev, "Invalid control\n");
5fd8f738
SN		 1104 return -EINVAL;
1105 }
5fd8f738
SN		 1106 ctx->state |= FIMC_PARAMS;
1107 spin_unlock_irqrestore(&ctx->slock, flags);
5f3cc447 1108
5fd8f738
SN		 1109 return 0;
1110}
1111
5f3cc447 1112static int fimc_m2m_s_ctrl(struct file *file, void *priv,
ac75934c 1113 struct v4l2_control *ctrl)
5f3cc447
SN		 1114{
1115 struct fimc_ctx *ctx = priv;
1116 int ret = 0;
1117
1118 ret = check_ctrl_val(ctx, ctrl);
1119 if (ret)
1120 return ret;
1121
1122 ret = fimc_s_ctrl(ctx, ctrl);
1123 return 0;
1124}
5fd8f738 1125
e004e02f 1126static int fimc_m2m_cropcap(struct file *file, void *fh,
5f3cc447 1127 struct v4l2_cropcap *cr)
5fd8f738
SN		 1128{
1129 struct fimc_frame *frame;
1130 struct fimc_ctx *ctx = fh;
1131
548aafcd 1132 frame = ctx_get_frame(ctx, cr->type);
03e30ca5
PO		 1133 if (IS_ERR(frame))
1134 return PTR_ERR(frame);
5fd8f738 1135
5f3cc447
SN		 1136 cr->bounds.left = 0;
1137 cr->bounds.top = 0;
1138 cr->bounds.width = frame->f_width;
1139 cr->bounds.height = frame->f_height;
1140 cr->defrect = cr->bounds;
1141
5fd8f738
SN		 1142 return 0;
1143}
1144
e004e02f 1145static int fimc_m2m_g_crop(struct file *file, void *fh, struct v4l2_crop *cr)
5fd8f738
SN		 1146{
1147 struct fimc_frame *frame;
1148 struct fimc_ctx *ctx = file->private_data;
1149
548aafcd 1150 frame = ctx_get_frame(ctx, cr->type);
03e30ca5
PO		 1151 if (IS_ERR(frame))
1152 return PTR_ERR(frame);
5fd8f738
SN		 1153
1154 cr->c.left = frame->offs_h;
1155 cr->c.top = frame->offs_v;
1156 cr->c.width = frame->width;
1157 cr->c.height = frame->height;
1158
1159 return 0;
1160}
1161
5f3cc447 1162int fimc_try_crop(struct fimc_ctx *ctx, struct v4l2_crop *cr)
5fd8f738 1163{
5fd8f738 1164 struct fimc_dev *fimc = ctx->fimc_dev;
5fd8f738 1165 struct fimc_frame *f;
ef7af59b
SN		 1166 u32 min_size, halign, depth = 0;
1167 int i;
5f3cc447 1168
5fd8f738
SN		 1169 if (cr->c.top < 0 || cr->c.left < 0) {
1170 v4l2_err(&fimc->m2m.v4l2_dev,
1171 "doesn't support negative values for top & left\n");
1172 return -EINVAL;
1173 }
1174
ef7af59b 1175 if (cr->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
e004e02f 1176 f = (ctx->state & FIMC_CTX_CAP) ? &ctx->s_frame : &ctx->d_frame;
ef7af59b 1177 else if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE &&
e004e02f
SN		 1178 ctx->state & FIMC_CTX_M2M)
1179 f = &ctx->s_frame;
1180 else
1181 return -EINVAL;
5fd8f738 1182
e004e02f
SN		 1183 min_size = (f == &ctx->s_frame) ?
1184 fimc->variant->min_inp_pixsize : fimc->variant->min_out_pixsize;
5fd8f738 1185
5f3cc447
SN		 1186 if (ctx->state & FIMC_CTX_M2M) {
1187 if (fimc->id == 1 && fimc->variant->pix_hoff)
1188 halign = fimc_fmt_is_rgb(f->fmt->color) ? 0 : 1;
1189 else
1190 halign = ffs(min_size) - 1;
1191 /* there are more strict aligment requirements at camera interface */
1192 } else {
1193 min_size = 16;
1194 halign = 4;
5fd8f738
SN		 1195 }
1196
ef7af59b
SN		 1197 for (i = 0; i < f->fmt->colplanes; i++)
1198 depth += f->fmt->depth[i];
1199
5f3cc447
SN		 1200 v4l_bound_align_image(&cr->c.width, min_size, f->o_width,
1201 ffs(min_size) - 1,
1202 &cr->c.height, min_size, f->o_height,
ef7af59b 1203 halign, 64/(ALIGN(depth, 8)));
5f3cc447
SN		 1204
1205 /* adjust left/top if cropping rectangle is out of bounds */
1206 if (cr->c.left + cr->c.width > f->o_width)
1207 cr->c.left = f->o_width - cr->c.width;
1208 if (cr->c.top + cr->c.height > f->o_height)
1209 cr->c.top = f->o_height - cr->c.height;
1210
1211 cr->c.left = round_down(cr->c.left, min_size);
1212 cr->c.top = round_down(cr->c.top,
1213 ctx->state & FIMC_CTX_M2M ? 8 : 16);
1214
1215 dbg("l:%d, t:%d, w:%d, h:%d, f_w: %d, f_h: %d",
1216 cr->c.left, cr->c.top, cr->c.width, cr->c.height,
1217 f->f_width, f->f_height);
1218
1219 return 0;
1220}
1221
1222
1223static int fimc_m2m_s_crop(struct file *file, void *fh, struct v4l2_crop *cr)
1224{
1225 struct fimc_ctx *ctx = file->private_data;
1226 struct fimc_dev *fimc = ctx->fimc_dev;
1227 unsigned long flags;
1228 struct fimc_frame *f;
1229 int ret;
1230
1231 ret = fimc_try_crop(ctx, cr);
1232 if (ret)
1233 return ret;
1234
ef7af59b 1235 f = (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) ?
5f3cc447
SN		 1236 &ctx->s_frame : &ctx->d_frame;
1237
5fd8f738 1238 spin_lock_irqsave(&ctx->slock, flags);
5f3cc447
SN		 1239 if (~ctx->state & (FIMC_SRC_FMT | FIMC_DST_FMT)) {
1240 /* Check to see if scaling ratio is within supported range */
ef7af59b 1241 if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
5fd8f738 1242 ret = fimc_check_scaler_ratio(&cr->c, &ctx->d_frame);
5f3cc447 1243 else
5fd8f738 1244 ret = fimc_check_scaler_ratio(&cr->c, &ctx->s_frame);
5fd8f738 1245 if (ret) {
5f3cc447 1246 v4l2_err(&fimc->m2m.v4l2_dev, "Out of scaler range");
8293ebfc
SN		 1247 spin_unlock_irqrestore(&ctx->slock, flags);
1248 return -EINVAL;
5fd8f738
SN		 1249 }
1250 }
1251 ctx->state |= FIMC_PARAMS;
5fd8f738
SN		 1252
1253 f->offs_h = cr->c.left;
1254 f->offs_v = cr->c.top;
5f3cc447 1255 f->width = cr->c.width;
5fd8f738 1256 f->height = cr->c.height;
5f3cc447
SN		 1257
1258 spin_unlock_irqrestore(&ctx->slock, flags);
5fd8f738
SN		 1259 return 0;
1260}
1261
1262static const struct v4l2_ioctl_ops fimc_m2m_ioctl_ops = {
1263 .vidioc_querycap = fimc_m2m_querycap,
1264
ef7af59b
SN		 1265 .vidioc_enum_fmt_vid_cap_mplane = fimc_vidioc_enum_fmt_mplane,
1266 .vidioc_enum_fmt_vid_out_mplane = fimc_vidioc_enum_fmt_mplane,
5fd8f738 1267
ef7af59b
SN		 1268 .vidioc_g_fmt_vid_cap_mplane = fimc_vidioc_g_fmt_mplane,
1269 .vidioc_g_fmt_vid_out_mplane = fimc_vidioc_g_fmt_mplane,
5fd8f738 1270
ef7af59b
SN		 1271 .vidioc_try_fmt_vid_cap_mplane = fimc_vidioc_try_fmt_mplane,
1272 .vidioc_try_fmt_vid_out_mplane = fimc_vidioc_try_fmt_mplane,
5fd8f738 1273
ef7af59b
SN		 1274 .vidioc_s_fmt_vid_cap_mplane = fimc_m2m_s_fmt_mplane,
1275 .vidioc_s_fmt_vid_out_mplane = fimc_m2m_s_fmt_mplane,
5fd8f738
SN		 1276
1277 .vidioc_reqbufs = fimc_m2m_reqbufs,
1278 .vidioc_querybuf = fimc_m2m_querybuf,
1279
1280 .vidioc_qbuf = fimc_m2m_qbuf,
1281 .vidioc_dqbuf = fimc_m2m_dqbuf,
1282
1283 .vidioc_streamon = fimc_m2m_streamon,
1284 .vidioc_streamoff = fimc_m2m_streamoff,
1285
5f3cc447
SN		 1286 .vidioc_queryctrl = fimc_vidioc_queryctrl,
1287 .vidioc_g_ctrl = fimc_vidioc_g_ctrl,
5fd8f738
SN		 1288 .vidioc_s_ctrl = fimc_m2m_s_ctrl,
1289
e004e02f 1290 .vidioc_g_crop = fimc_m2m_g_crop,
5fd8f738 1291 .vidioc_s_crop = fimc_m2m_s_crop,
e004e02f 1292 .vidioc_cropcap = fimc_m2m_cropcap
5fd8f738
SN		 1293
1294};
1295
ef7af59b
SN		 1296static int queue_init(void *priv, struct vb2_queue *src_vq,
1297 struct vb2_queue *dst_vq)
5fd8f738
SN		 1298{
1299 struct fimc_ctx *ctx = priv;
2dab38e2
SN		 1300 int ret;
1301
1302 memset(src_vq, 0, sizeof(*src_vq));
1303 src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
1304 src_vq->io_modes = VB2_MMAP | VB2_USERPTR;
1305 src_vq->drv_priv = ctx;
1306 src_vq->ops = &fimc_qops;
1307 src_vq->mem_ops = &vb2_dma_contig_memops;
1308 src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
5fd8f738 1309
2dab38e2
SN		 1310 ret = vb2_queue_init(src_vq);
1311 if (ret)
1312 return ret;
1313
1314 memset(dst_vq, 0, sizeof(*dst_vq));
1315 dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
1316 dst_vq->io_modes = VB2_MMAP | VB2_USERPTR;
1317 dst_vq->drv_priv = ctx;
1318 dst_vq->ops = &fimc_qops;
1319 dst_vq->mem_ops = &vb2_dma_contig_memops;
1320 dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1321
1322 return vb2_queue_init(dst_vq);
5fd8f738
SN		 1323}
1324
1325static int fimc_m2m_open(struct file *file)
1326{
1327 struct fimc_dev *fimc = video_drvdata(file);
1328 struct fimc_ctx *ctx = NULL;
5f3cc447
SN		 1329
1330 dbg("pid: %d, state: 0x%lx, refcnt: %d",
1331 task_pid_nr(current), fimc->state, fimc->vid_cap.refcnt);
1332
1333 /*
1334 * Return if the corresponding video capture node
1335 * is already opened.
1336 */
8293ebfc
SN		 1337 if (fimc->vid_cap.refcnt > 0)
1338 return -EBUSY;
5f3cc447 1339
5fd8f738
SN		 1340 fimc->m2m.refcnt++;
1341 set_bit(ST_OUTDMA_RUN, &fimc->state);
5fd8f738
SN		 1342
1343 ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
8293ebfc
SN		 1344 if (!ctx)
1345 return -ENOMEM;
5fd8f738
SN		 1346
1347 file->private_data = ctx;
1348 ctx->fimc_dev = fimc;
548aafcd 1349 /* Default color format */
5fd8f738
SN		 1350 ctx->s_frame.fmt = &fimc_formats[0];
1351 ctx->d_frame.fmt = &fimc_formats[0];
5f3cc447
SN		 1352 /* Setup the device context for mem2mem mode. */
1353 ctx->state = FIMC_CTX_M2M;
5fd8f738 1354 ctx->flags = 0;
5fd8f738
SN		 1355 ctx->in_path = FIMC_DMA;
1356 ctx->out_path = FIMC_DMA;
1357 spin_lock_init(&ctx->slock);
1358
2dab38e2 1359 ctx->m2m_ctx = v4l2_m2m_ctx_init(fimc->m2m.m2m_dev, ctx, queue_init);
5fd8f738 1360 if (IS_ERR(ctx->m2m_ctx)) {
8293ebfc 1361 int err = PTR_ERR(ctx->m2m_ctx);
5fd8f738 1362 kfree(ctx);
8293ebfc 1363 return err;
5fd8f738 1364 }
5f3cc447 1365
8293ebfc 1366 return 0;
5fd8f738
SN		 1367}
1368
1369static int fimc_m2m_release(struct file *file)
1370{
1371 struct fimc_ctx *ctx = file->private_data;
1372 struct fimc_dev *fimc = ctx->fimc_dev;
1373
5f3cc447
SN		 1374 dbg("pid: %d, state: 0x%lx, refcnt= %d",
1375 task_pid_nr(current), fimc->state, fimc->m2m.refcnt);
1376
5fd8f738
SN		 1377 v4l2_m2m_ctx_release(ctx->m2m_ctx);
1378 kfree(ctx);
5fd8f738
SN		 1379 if (--fimc->m2m.refcnt <= 0)
1380 clear_bit(ST_OUTDMA_RUN, &fimc->state);
5f3cc447 1381
5fd8f738
SN		 1382 return 0;
1383}
1384
1385static unsigned int fimc_m2m_poll(struct file *file,
1386 struct poll_table_struct *wait)
1387{
1388 struct fimc_ctx *ctx = file->private_data;
5f3cc447 1389
5fd8f738
SN		 1390 return v4l2_m2m_poll(file, ctx->m2m_ctx, wait);
1391}
1392
1393
1394static int fimc_m2m_mmap(struct file *file, struct vm_area_struct *vma)
1395{
1396 struct fimc_ctx *ctx = file->private_data;
5f3cc447 1397
5fd8f738
SN		 1398 return v4l2_m2m_mmap(file, ctx->m2m_ctx, vma);
1399}
1400
1401static const struct v4l2_file_operations fimc_m2m_fops = {
1402 .owner = THIS_MODULE,
1403 .open = fimc_m2m_open,
1404 .release = fimc_m2m_release,
1405 .poll = fimc_m2m_poll,
69e05e83 1406 .unlocked_ioctl = video_ioctl2,
5fd8f738
SN		 1407 .mmap = fimc_m2m_mmap,
1408};
1409
1410static struct v4l2_m2m_ops m2m_ops = {
1411 .device_run = fimc_dma_run,
1412 .job_abort = fimc_job_abort,
1413};
1414
5fd8f738
SN		 1415static int fimc_register_m2m_device(struct fimc_dev *fimc)
1416{
1417 struct video_device *vfd;
1418 struct platform_device *pdev;
1419 struct v4l2_device *v4l2_dev;
1420 int ret = 0;
1421
1422 if (!fimc)
1423 return -ENODEV;
1424
1425 pdev = fimc->pdev;
1426 v4l2_dev = &fimc->m2m.v4l2_dev;
1427
1428 /* set name if it is empty */
1429 if (!v4l2_dev->name[0])
1430 snprintf(v4l2_dev->name, sizeof(v4l2_dev->name),
1431 "%s.m2m", dev_name(&pdev->dev));
1432
1433 ret = v4l2_device_register(&pdev->dev, v4l2_dev);
1434 if (ret)
548aafcd 1435 goto err_m2m_r1;
5fd8f738
SN		 1436
1437 vfd = video_device_alloc();
1438 if (!vfd) {
1439 v4l2_err(v4l2_dev, "Failed to allocate video device\n");
1440 goto err_m2m_r1;
1441 }
1442
1443 vfd->fops = &fimc_m2m_fops;
1444 vfd->ioctl_ops = &fimc_m2m_ioctl_ops;
1445 vfd->minor = -1;
1446 vfd->release = video_device_release;
8293ebfc 1447 vfd->lock = &fimc->lock;
5fd8f738
SN		 1448
1449 snprintf(vfd->name, sizeof(vfd->name), "%s:m2m", dev_name(&pdev->dev));
1450
1451 video_set_drvdata(vfd, fimc);
1452 platform_set_drvdata(pdev, fimc);
1453
1454 fimc->m2m.vfd = vfd;
1455 fimc->m2m.m2m_dev = v4l2_m2m_init(&m2m_ops);
1456 if (IS_ERR(fimc->m2m.m2m_dev)) {
1457 v4l2_err(v4l2_dev, "failed to initialize v4l2-m2m device\n");
1458 ret = PTR_ERR(fimc->m2m.m2m_dev);
1459 goto err_m2m_r2;
1460 }
1461
1462 ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1);
1463 if (ret) {
1464 v4l2_err(v4l2_dev,
1465 "%s(): failed to register video device\n", __func__);
1466 goto err_m2m_r3;
1467 }
1468 v4l2_info(v4l2_dev,
1469 "FIMC m2m driver registered as /dev/video%d\n", vfd->num);
1470
1471 return 0;
1472
1473err_m2m_r3:
1474 v4l2_m2m_release(fimc->m2m.m2m_dev);
1475err_m2m_r2:
1476 video_device_release(fimc->m2m.vfd);
1477err_m2m_r1:
1478 v4l2_device_unregister(v4l2_dev);
1479
1480 return ret;
1481}
1482
1483static void fimc_unregister_m2m_device(struct fimc_dev *fimc)
1484{
1485 if (fimc) {
1486 v4l2_m2m_release(fimc->m2m.m2m_dev);
1487 video_unregister_device(fimc->m2m.vfd);
548aafcd 1488
5fd8f738
SN		 1489 v4l2_device_unregister(&fimc->m2m.v4l2_dev);
1490 }
1491}
1492
1493static void fimc_clk_release(struct fimc_dev *fimc)
1494{
1495 int i;
a25be18d 1496 for (i = 0; i < fimc->num_clocks; i++) {
5fd8f738
SN		 1497 if (fimc->clock[i]) {
1498 clk_disable(fimc->clock[i]);
1499 clk_put(fimc->clock[i]);
1500 }
1501 }
1502}
1503
1504static int fimc_clk_get(struct fimc_dev *fimc)
1505{
1506 int i;
a25be18d
SN		 1507 for (i = 0; i < fimc->num_clocks; i++) {
1508 fimc->clock[i] = clk_get(&fimc->pdev->dev, fimc_clocks[i]);
1509
1510 if (!IS_ERR_OR_NULL(fimc->clock[i])) {
1511 clk_enable(fimc->clock[i]);
1512 continue;
5fd8f738 1513 }
a25be18d
SN		 1514 dev_err(&fimc->pdev->dev, "failed to get fimc clock: %s\n",
1515 fimc_clocks[i]);
1516 return -ENXIO;
5fd8f738
SN		 1517 }
1518 return 0;
1519}
1520
1521static int fimc_probe(struct platform_device *pdev)
1522{
1523 struct fimc_dev *fimc;
1524 struct resource *res;
1525 struct samsung_fimc_driverdata *drv_data;
1526 int ret = 0;
a25be18d 1527 int cap_input_index = -1;
5fd8f738
SN		 1528
1529 dev_dbg(&pdev->dev, "%s():\n", __func__);
1530
1531 drv_data = (struct samsung_fimc_driverdata *)
1532 platform_get_device_id(pdev)->driver_data;
1533
a7d5bbcf 1534 if (pdev->id >= drv_data->num_entities) {
5fd8f738
SN		 1535 dev_err(&pdev->dev, "Invalid platform device id: %d\n",
1536 pdev->id);
1537 return -EINVAL;
1538 }
1539
1540 fimc = kzalloc(sizeof(struct fimc_dev), GFP_KERNEL);
1541 if (!fimc)
1542 return -ENOMEM;
1543
1544 fimc->id = pdev->id;
1545 fimc->variant = drv_data->variant[fimc->id];
1546 fimc->pdev = pdev;
5f3cc447 1547 fimc->pdata = pdev->dev.platform_data;
5fd8f738
SN		 1548 fimc->state = ST_IDLE;
1549
5f3cc447 1550 init_waitqueue_head(&fimc->irq_queue);
5fd8f738
SN		 1551 spin_lock_init(&fimc->slock);
1552
1553 mutex_init(&fimc->lock);
1554
1555 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1556 if (!res) {
1557 dev_err(&pdev->dev, "failed to find the registers\n");
1558 ret = -ENOENT;
1559 goto err_info;
1560 }
1561
1562 fimc->regs_res = request_mem_region(res->start, resource_size(res),
1563 dev_name(&pdev->dev));
1564 if (!fimc->regs_res) {
1565 dev_err(&pdev->dev, "failed to obtain register region\n");
1566 ret = -ENOENT;
1567 goto err_info;
1568 }
1569
1570 fimc->regs = ioremap(res->start, resource_size(res));
1571 if (!fimc->regs) {
1572 dev_err(&pdev->dev, "failed to map registers\n");
1573 ret = -ENXIO;
1574 goto err_req_region;
1575 }
1576
a25be18d
SN		 1577 fimc->num_clocks = MAX_FIMC_CLOCKS - 1;
1578 /*
1579 * Check if vide capture node needs to be registered for this device
1580 * instance.
1581 */
1582 if (fimc->pdata) {
1583 int i;
1584 for (i = 0; i < FIMC_MAX_CAMIF_CLIENTS; ++i)
1585 if (fimc->pdata->isp_info[i])
1586 break;
1587 if (i < FIMC_MAX_CAMIF_CLIENTS) {
1588 cap_input_index = i;
1589 fimc->num_clocks++;
1590 }
1591 }
1592
5fd8f738
SN		 1593 ret = fimc_clk_get(fimc);
1594 if (ret)
1595 goto err_regs_unmap;
a25be18d 1596 clk_set_rate(fimc->clock[CLK_BUS], drv_data->lclk_frequency);
5fd8f738
SN		 1597
1598 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1599 if (!res) {
1600 dev_err(&pdev->dev, "failed to get IRQ resource\n");
1601 ret = -ENXIO;
1602 goto err_clk;
1603 }
1604 fimc->irq = res->start;
1605
1606 fimc_hw_reset(fimc);
1607
1608 ret = request_irq(fimc->irq, fimc_isr, 0, pdev->name, fimc);
1609 if (ret) {
1610 dev_err(&pdev->dev, "failed to install irq (%d)\n", ret);
1611 goto err_clk;
1612 }
1613
2dab38e2
SN		 1614 /* Initialize contiguous memory allocator */
1615 fimc->alloc_ctx = vb2_dma_contig_init_ctx(&fimc->pdev->dev);
1616 if (IS_ERR(fimc->alloc_ctx)) {
1617 ret = PTR_ERR(fimc->alloc_ctx);
1618 goto err_irq;
1619 }
1620
5fd8f738
SN		 1621 ret = fimc_register_m2m_device(fimc);
1622 if (ret)
548aafcd 1623 goto err_irq;
5fd8f738 1624
5f3cc447 1625 /* At least one camera sensor is required to register capture node */
a25be18d
SN		 1626 if (cap_input_index >= 0) {
1627 ret = fimc_register_capture_device(fimc);
1628 if (ret)
1629 goto err_m2m;
1630 clk_disable(fimc->clock[CLK_CAM]);
5f3cc447 1631 }
a7d5bbcf
SN		 1632 /*
1633 * Exclude the additional output DMA address registers by masking
1634 * them out on HW revisions that provide extended capabilites.
1635 */
1636 if (fimc->variant->out_buf_count > 4)
1637 fimc_hw_set_dma_seq(fimc, 0xF);
1638
5fd8f738
SN		 1639 dev_dbg(&pdev->dev, "%s(): fimc-%d registered successfully\n",
1640 __func__, fimc->id);
1641
1642 return 0;
1643
5f3cc447
SN		 1644err_m2m:
1645 fimc_unregister_m2m_device(fimc);
5fd8f738
SN		 1646err_irq:
1647 free_irq(fimc->irq, fimc);
1648err_clk:
1649 fimc_clk_release(fimc);
1650err_regs_unmap:
1651 iounmap(fimc->regs);
1652err_req_region:
1653 release_resource(fimc->regs_res);
1654 kfree(fimc->regs_res);
1655err_info:
1656 kfree(fimc);
548aafcd 1657
5fd8f738
SN		 1658 return ret;
1659}
1660
1661static int __devexit fimc_remove(struct platform_device *pdev)
1662{
1663 struct fimc_dev *fimc =
1664 (struct fimc_dev *)platform_get_drvdata(pdev);
1665
5fd8f738 1666 free_irq(fimc->irq, fimc);
5fd8f738
SN		 1667 fimc_hw_reset(fimc);
1668
1669 fimc_unregister_m2m_device(fimc);
5f3cc447
SN		 1670 fimc_unregister_capture_device(fimc);
1671
5fd8f738 1672 fimc_clk_release(fimc);
2dab38e2
SN		 1673
1674 vb2_dma_contig_cleanup_ctx(fimc->alloc_ctx);
1675
5fd8f738
SN		 1676 iounmap(fimc->regs);
1677 release_resource(fimc->regs_res);
1678 kfree(fimc->regs_res);
1679 kfree(fimc);
548aafcd
SN		 1680
1681 dev_info(&pdev->dev, "%s driver unloaded\n", pdev->name);
5fd8f738
SN		 1682 return 0;
1683}
1684
a7d5bbcf
SN		 1685/* Image pixel limits, similar across several FIMC HW revisions. */
1686static struct fimc_pix_limit s5p_pix_limit[3] = {
1687 [0] = {
1688 .scaler_en_w = 3264,
1689 .scaler_dis_w = 8192,
1690 .in_rot_en_h = 1920,
1691 .in_rot_dis_w = 8192,
1692 .out_rot_en_w = 1920,
1693 .out_rot_dis_w = 4224,
1694 },
1695 [1] = {
1696 .scaler_en_w = 4224,
1697 .scaler_dis_w = 8192,
1698 .in_rot_en_h = 1920,
1699 .in_rot_dis_w = 8192,
1700 .out_rot_en_w = 1920,
1701 .out_rot_dis_w = 4224,
1702 },
1703 [2] = {
1704 .scaler_en_w = 1920,
1705 .scaler_dis_w = 8192,
1706 .in_rot_en_h = 1280,
1707 .in_rot_dis_w = 8192,
1708 .out_rot_en_w = 1280,
1709 .out_rot_dis_w = 1920,
1710 },
1711};
1712
1713static struct samsung_fimc_variant fimc0_variant_s5p = {
1714 .has_inp_rot = 1,
1715 .has_out_rot = 1,
5fd8f738
SN		 1716 .min_inp_pixsize = 16,
1717 .min_out_pixsize = 16,
a7d5bbcf
SN		 1718 .hor_offs_align = 8,
1719 .out_buf_count = 4,
1720 .pix_limit = &s5p_pix_limit[0],
5fd8f738
SN		 1721};
1722
1723static struct samsung_fimc_variant fimc2_variant_s5p = {
1724 .min_inp_pixsize = 16,
1725 .min_out_pixsize = 16,
a7d5bbcf
SN		 1726 .hor_offs_align = 8,
1727 .out_buf_count = 4,
1728 .pix_limit = &s5p_pix_limit[1],
5fd8f738
SN		 1729};
1730
a7d5bbcf
SN		 1731static struct samsung_fimc_variant fimc0_variant_s5pv210 = {
1732 .pix_hoff = 1,
1733 .has_inp_rot = 1,
1734 .has_out_rot = 1,
5fd8f738 1735 .min_inp_pixsize = 16,
548aafcd 1736 .min_out_pixsize = 16,
a7d5bbcf
SN		 1737 .hor_offs_align = 8,
1738 .out_buf_count = 4,
1739 .pix_limit = &s5p_pix_limit[1],
1740};
5fd8f738 1741
a7d5bbcf
SN		 1742static struct samsung_fimc_variant fimc1_variant_s5pv210 = {
1743 .pix_hoff = 1,
1744 .has_inp_rot = 1,
1745 .has_out_rot = 1,
b241c6d6 1746 .has_mainscaler_ext = 1,
a7d5bbcf
SN		 1747 .min_inp_pixsize = 16,
1748 .min_out_pixsize = 16,
1749 .hor_offs_align = 1,
1750 .out_buf_count = 4,
1751 .pix_limit = &s5p_pix_limit[2],
5fd8f738
SN		 1752};
1753
1754static struct samsung_fimc_variant fimc2_variant_s5pv210 = {
ddc79e0f 1755 .pix_hoff = 1,
5fd8f738 1756 .min_inp_pixsize = 16,
548aafcd 1757 .min_out_pixsize = 16,
a7d5bbcf
SN		 1758 .hor_offs_align = 8,
1759 .out_buf_count = 4,
1760 .pix_limit = &s5p_pix_limit[2],
1761};
5fd8f738 1762
a7d5bbcf
SN		 1763static struct samsung_fimc_variant fimc0_variant_s5pv310 = {
1764 .pix_hoff = 1,
1765 .has_inp_rot = 1,
1766 .has_out_rot = 1,
798174ab 1767 .has_cistatus2 = 1,
b241c6d6 1768 .has_mainscaler_ext = 1,
a7d5bbcf
SN		 1769 .min_inp_pixsize = 16,
1770 .min_out_pixsize = 16,
1771 .hor_offs_align = 1,
1772 .out_buf_count = 32,
1773 .pix_limit = &s5p_pix_limit[1],
1774};
1775
1776static struct samsung_fimc_variant fimc2_variant_s5pv310 = {
1777 .pix_hoff = 1,
798174ab 1778 .has_cistatus2 = 1,
b241c6d6 1779 .has_mainscaler_ext = 1,
a7d5bbcf
SN		 1780 .min_inp_pixsize = 16,
1781 .min_out_pixsize = 16,
1782 .hor_offs_align = 1,
1783 .out_buf_count = 32,
1784 .pix_limit = &s5p_pix_limit[2],
5fd8f738
SN		 1785};
1786
a7d5bbcf 1787/* S5PC100 */
5fd8f738
SN		 1788static struct samsung_fimc_driverdata fimc_drvdata_s5p = {
1789 .variant = {
a7d5bbcf
SN		 1790 [0] = &fimc0_variant_s5p,
1791 [1] = &fimc0_variant_s5p,
5fd8f738
SN		 1792 [2] = &fimc2_variant_s5p,
1793 },
a7d5bbcf
SN		 1794 .num_entities = 3,
1795 .lclk_frequency = 133000000UL,
5fd8f738
SN		 1796};
1797
a7d5bbcf 1798/* S5PV210, S5PC110 */
5fd8f738
SN		 1799static struct samsung_fimc_driverdata fimc_drvdata_s5pv210 = {
1800 .variant = {
a7d5bbcf
SN		 1801 [0] = &fimc0_variant_s5pv210,
1802 [1] = &fimc1_variant_s5pv210,
5fd8f738
SN		 1803 [2] = &fimc2_variant_s5pv210,
1804 },
a7d5bbcf
SN		 1805 .num_entities = 3,
1806 .lclk_frequency = 166000000UL,
1807};
1808
1809/* S5PV310, S5PC210 */
1810static struct samsung_fimc_driverdata fimc_drvdata_s5pv310 = {
1811 .variant = {
1812 [0] = &fimc0_variant_s5pv310,
1813 [1] = &fimc0_variant_s5pv310,
1814 [2] = &fimc0_variant_s5pv310,
1815 [3] = &fimc2_variant_s5pv310,
1816 },
1817 .num_entities = 4,
1818 .lclk_frequency = 166000000UL,
5fd8f738
SN		 1819};
1820
1821static struct platform_device_id fimc_driver_ids[] = {
1822 {
1823 .name = "s5p-fimc",
1824 .driver_data = (unsigned long)&fimc_drvdata_s5p,
1825 }, {
1826 .name = "s5pv210-fimc",
1827 .driver_data = (unsigned long)&fimc_drvdata_s5pv210,
a7d5bbcf
SN		 1828 }, {
1829 .name = "s5pv310-fimc",
1830 .driver_data = (unsigned long)&fimc_drvdata_s5pv310,
5fd8f738
SN		 1831 },
1832 {},
1833};
1834MODULE_DEVICE_TABLE(platform, fimc_driver_ids);
1835
1836static struct platform_driver fimc_driver = {
1837 .probe = fimc_probe,
1838 .remove = __devexit_p(fimc_remove),
1839 .id_table = fimc_driver_ids,
1840 .driver = {
1841 .name = MODULE_NAME,
1842 .owner = THIS_MODULE,
1843 }
1844};
1845
5fd8f738
SN		 1846static int __init fimc_init(void)
1847{
548aafcd
SN		 1848 int ret = platform_driver_register(&fimc_driver);
1849 if (ret)
1850 err("platform_driver_register failed: %d\n", ret);
1851 return ret;
5fd8f738
SN		 1852}
1853
1854static void __exit fimc_exit(void)
1855{
1856 platform_driver_unregister(&fimc_driver);
1857}
1858
1859module_init(fimc_init);
1860module_exit(fimc_exit);
1861
5f3cc447
SN		 1862MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
1863MODULE_DESCRIPTION("S5P FIMC camera host interface/video postprocessor driver");
5fd8f738 1864MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)