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3bc43840 GL |
1 | /* |
2 | * V4L2 Driver for PXA camera host | |
3 | * | |
4 | * Copyright (C) 2006, Sascha Hauer, Pengutronix | |
5 | * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | */ | |
12 | ||
3bc43840 GL |
13 | #include <linux/init.h> |
14 | #include <linux/module.h> | |
7102b773 | 15 | #include <linux/io.h> |
3bc43840 GL |
16 | #include <linux/delay.h> |
17 | #include <linux/dma-mapping.h> | |
18 | #include <linux/errno.h> | |
19 | #include <linux/fs.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/mm.h> | |
23 | #include <linux/moduleparam.h> | |
24 | #include <linux/time.h> | |
25 | #include <linux/version.h> | |
26 | #include <linux/device.h> | |
27 | #include <linux/platform_device.h> | |
3bc43840 | 28 | #include <linux/clk.h> |
d514edac | 29 | #include <linux/sched.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
3bc43840 GL |
31 | |
32 | #include <media/v4l2-common.h> | |
33 | #include <media/v4l2-dev.h> | |
092d3921 | 34 | #include <media/videobuf-dma-sg.h> |
3bc43840 | 35 | #include <media/soc_camera.h> |
760697be | 36 | #include <media/soc_mediabus.h> |
3bc43840 GL |
37 | |
38 | #include <linux/videodev2.h> | |
39 | ||
cfbaf4df | 40 | #include <mach/dma.h> |
a09e64fb | 41 | #include <mach/camera.h> |
3bc43840 GL |
42 | |
43 | #define PXA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5) | |
44 | #define PXA_CAM_DRV_NAME "pxa27x-camera" | |
45 | ||
5ca11fa3 EM |
46 | /* Camera Interface */ |
47 | #define CICR0 0x0000 | |
48 | #define CICR1 0x0004 | |
49 | #define CICR2 0x0008 | |
50 | #define CICR3 0x000C | |
51 | #define CICR4 0x0010 | |
52 | #define CISR 0x0014 | |
53 | #define CIFR 0x0018 | |
54 | #define CITOR 0x001C | |
55 | #define CIBR0 0x0028 | |
56 | #define CIBR1 0x0030 | |
57 | #define CIBR2 0x0038 | |
58 | ||
59 | #define CICR0_DMAEN (1 << 31) /* DMA request enable */ | |
60 | #define CICR0_PAR_EN (1 << 30) /* Parity enable */ | |
61 | #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */ | |
62 | #define CICR0_ENB (1 << 28) /* Camera interface enable */ | |
63 | #define CICR0_DIS (1 << 27) /* Camera interface disable */ | |
64 | #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */ | |
65 | #define CICR0_TOM (1 << 9) /* Time-out mask */ | |
66 | #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */ | |
67 | #define CICR0_FEM (1 << 7) /* FIFO-empty mask */ | |
68 | #define CICR0_EOLM (1 << 6) /* End-of-line mask */ | |
69 | #define CICR0_PERRM (1 << 5) /* Parity-error mask */ | |
70 | #define CICR0_QDM (1 << 4) /* Quick-disable mask */ | |
71 | #define CICR0_CDM (1 << 3) /* Disable-done mask */ | |
72 | #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */ | |
73 | #define CICR0_EOFM (1 << 1) /* End-of-frame mask */ | |
74 | #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */ | |
75 | ||
76 | #define CICR1_TBIT (1 << 31) /* Transparency bit */ | |
77 | #define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */ | |
78 | #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */ | |
79 | #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */ | |
80 | #define CICR1_RGB_F (1 << 11) /* RGB format */ | |
81 | #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */ | |
82 | #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */ | |
83 | #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */ | |
84 | #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */ | |
85 | #define CICR1_DW (0x7 << 0) /* Data width mask */ | |
86 | ||
87 | #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock | |
88 | wait count mask */ | |
89 | #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock | |
90 | wait count mask */ | |
91 | #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */ | |
92 | #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock | |
93 | wait count mask */ | |
94 | #define CICR2_FSW (0x7 << 0) /* Frame stabilization | |
95 | wait count mask */ | |
96 | ||
97 | #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock | |
98 | wait count mask */ | |
99 | #define CICR3_EFW (0xff << 16) /* End-of-frame line clock | |
100 | wait count mask */ | |
101 | #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */ | |
102 | #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock | |
103 | wait count mask */ | |
104 | #define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */ | |
105 | ||
106 | #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */ | |
107 | #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */ | |
108 | #define CICR4_PCP (1 << 22) /* Pixel clock polarity */ | |
109 | #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */ | |
110 | #define CICR4_VSP (1 << 20) /* Vertical sync polarity */ | |
111 | #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */ | |
112 | #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */ | |
113 | #define CICR4_DIV (0xff << 0) /* Clock divisor mask */ | |
114 | ||
115 | #define CISR_FTO (1 << 15) /* FIFO time-out */ | |
116 | #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */ | |
117 | #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */ | |
118 | #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */ | |
119 | #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */ | |
120 | #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */ | |
121 | #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */ | |
122 | #define CISR_EOL (1 << 8) /* End of line */ | |
123 | #define CISR_PAR_ERR (1 << 7) /* Parity error */ | |
124 | #define CISR_CQD (1 << 6) /* Camera interface quick disable */ | |
125 | #define CISR_CDD (1 << 5) /* Camera interface disable done */ | |
126 | #define CISR_SOF (1 << 4) /* Start of frame */ | |
127 | #define CISR_EOF (1 << 3) /* End of frame */ | |
128 | #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */ | |
129 | #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */ | |
130 | #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */ | |
131 | ||
132 | #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */ | |
133 | #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */ | |
134 | #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */ | |
135 | #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */ | |
136 | #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */ | |
137 | #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */ | |
138 | #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */ | |
139 | #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */ | |
140 | ||
7102b773 GL |
141 | #define CICR0_SIM_MP (0 << 24) |
142 | #define CICR0_SIM_SP (1 << 24) | |
143 | #define CICR0_SIM_MS (2 << 24) | |
144 | #define CICR0_SIM_EP (3 << 24) | |
145 | #define CICR0_SIM_ES (4 << 24) | |
146 | ||
147 | #define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */ | |
148 | #define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */ | |
a5462e5b MR |
149 | #define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */ |
150 | #define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */ | |
151 | #define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */ | |
7102b773 GL |
152 | |
153 | #define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */ | |
154 | #define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */ | |
155 | #define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */ | |
156 | #define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */ | |
157 | #define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */ | |
158 | ||
159 | #define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */ | |
160 | #define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */ | |
161 | #define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */ | |
162 | #define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */ | |
163 | ||
3bc43840 GL |
164 | #define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \ |
165 | CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \ | |
166 | CICR0_EOFM | CICR0_FOM) | |
167 | ||
3bc43840 GL |
168 | /* |
169 | * Structures | |
170 | */ | |
a5462e5b MR |
171 | enum pxa_camera_active_dma { |
172 | DMA_Y = 0x1, | |
173 | DMA_U = 0x2, | |
174 | DMA_V = 0x4, | |
175 | }; | |
176 | ||
177 | /* descriptor needed for the PXA DMA engine */ | |
178 | struct pxa_cam_dma { | |
179 | dma_addr_t sg_dma; | |
180 | struct pxa_dma_desc *sg_cpu; | |
181 | size_t sg_size; | |
182 | int sglen; | |
183 | }; | |
3bc43840 GL |
184 | |
185 | /* buffer for one video frame */ | |
186 | struct pxa_buffer { | |
187 | /* common v4l buffer stuff -- must be first */ | |
760697be GL |
188 | struct videobuf_buffer vb; |
189 | enum v4l2_mbus_pixelcode code; | |
a5462e5b | 190 | /* our descriptor lists for Y, U and V channels */ |
760697be GL |
191 | struct pxa_cam_dma dmas[3]; |
192 | int inwork; | |
193 | enum pxa_camera_active_dma active_dma; | |
3bc43840 GL |
194 | }; |
195 | ||
3bc43840 | 196 | struct pxa_camera_dev { |
eb6c8558 | 197 | struct soc_camera_host soc_host; |
5d28d525 GL |
198 | /* |
199 | * PXA27x is only supposed to handle one camera on its Quick Capture | |
3bc43840 | 200 | * interface. If anyone ever builds hardware to enable more than |
5d28d525 GL |
201 | * one camera, they will have to modify this driver too |
202 | */ | |
3bc43840 GL |
203 | struct soc_camera_device *icd; |
204 | struct clk *clk; | |
205 | ||
206 | unsigned int irq; | |
207 | void __iomem *base; | |
a5462e5b | 208 | |
e7c50688 | 209 | int channels; |
a5462e5b | 210 | unsigned int dma_chans[3]; |
3bc43840 | 211 | |
3bc43840 GL |
212 | struct pxacamera_platform_data *pdata; |
213 | struct resource *res; | |
214 | unsigned long platform_flags; | |
cf34cba7 GL |
215 | unsigned long ciclk; |
216 | unsigned long mclk; | |
217 | u32 mclk_divisor; | |
3bc43840 GL |
218 | |
219 | struct list_head capture; | |
220 | ||
221 | spinlock_t lock; | |
222 | ||
3bc43840 | 223 | struct pxa_buffer *active; |
5aa2110f | 224 | struct pxa_dma_desc *sg_tail[3]; |
3f6ac497 RJ |
225 | |
226 | u32 save_cicr[5]; | |
3bc43840 GL |
227 | }; |
228 | ||
6a6c8786 GL |
229 | struct pxa_cam { |
230 | unsigned long flags; | |
231 | }; | |
232 | ||
3bc43840 GL |
233 | static const char *pxa_cam_driver_description = "PXA_Camera"; |
234 | ||
235 | static unsigned int vid_limit = 16; /* Video memory limit, in Mb */ | |
236 | ||
237 | /* | |
238 | * Videobuf operations | |
239 | */ | |
7102b773 GL |
240 | static int pxa_videobuf_setup(struct videobuf_queue *vq, unsigned int *count, |
241 | unsigned int *size) | |
3bc43840 GL |
242 | { |
243 | struct soc_camera_device *icd = vq->priv_data; | |
760697be GL |
244 | int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width, |
245 | icd->current_fmt->host_fmt); | |
246 | ||
247 | if (bytes_per_line < 0) | |
248 | return bytes_per_line; | |
3bc43840 | 249 | |
0166b743 | 250 | dev_dbg(icd->dev.parent, "count=%d, size=%d\n", *count, *size); |
3bc43840 | 251 | |
760697be | 252 | *size = bytes_per_line * icd->user_height; |
3bc43840 GL |
253 | |
254 | if (0 == *count) | |
255 | *count = 32; | |
256 | while (*size * *count > vid_limit * 1024 * 1024) | |
257 | (*count)--; | |
258 | ||
259 | return 0; | |
260 | } | |
261 | ||
262 | static void free_buffer(struct videobuf_queue *vq, struct pxa_buffer *buf) | |
263 | { | |
264 | struct soc_camera_device *icd = vq->priv_data; | |
64f5905e | 265 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
3bc43840 | 266 | struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb); |
a5462e5b | 267 | int i; |
3bc43840 GL |
268 | |
269 | BUG_ON(in_interrupt()); | |
270 | ||
0166b743 | 271 | dev_dbg(icd->dev.parent, "%s (vb=0x%p) 0x%08lx %d\n", __func__, |
3bc43840 GL |
272 | &buf->vb, buf->vb.baddr, buf->vb.bsize); |
273 | ||
5d28d525 GL |
274 | /* |
275 | * This waits until this buffer is out of danger, i.e., until it is no | |
276 | * longer in STATE_QUEUED or STATE_ACTIVE | |
277 | */ | |
3bc43840 GL |
278 | videobuf_waiton(&buf->vb, 0, 0); |
279 | videobuf_dma_unmap(vq, dma); | |
280 | videobuf_dma_free(dma); | |
281 | ||
a5462e5b MR |
282 | for (i = 0; i < ARRAY_SIZE(buf->dmas); i++) { |
283 | if (buf->dmas[i].sg_cpu) | |
96c75399 GL |
284 | dma_free_coherent(ici->v4l2_dev.dev, |
285 | buf->dmas[i].sg_size, | |
a5462e5b MR |
286 | buf->dmas[i].sg_cpu, |
287 | buf->dmas[i].sg_dma); | |
288 | buf->dmas[i].sg_cpu = NULL; | |
289 | } | |
3bc43840 GL |
290 | |
291 | buf->vb.state = VIDEOBUF_NEEDS_INIT; | |
292 | } | |
293 | ||
37f5aefd RJ |
294 | static int calculate_dma_sglen(struct scatterlist *sglist, int sglen, |
295 | int sg_first_ofs, int size) | |
296 | { | |
297 | int i, offset, dma_len, xfer_len; | |
298 | struct scatterlist *sg; | |
299 | ||
300 | offset = sg_first_ofs; | |
301 | for_each_sg(sglist, sg, sglen, i) { | |
302 | dma_len = sg_dma_len(sg); | |
303 | ||
304 | /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */ | |
305 | xfer_len = roundup(min(dma_len - offset, size), 8); | |
306 | ||
307 | size = max(0, size - xfer_len); | |
308 | offset = 0; | |
309 | if (size == 0) | |
310 | break; | |
311 | } | |
312 | ||
313 | BUG_ON(size != 0); | |
314 | return i + 1; | |
315 | } | |
316 | ||
317 | /** | |
318 | * pxa_init_dma_channel - init dma descriptors | |
319 | * @pcdev: pxa camera device | |
320 | * @buf: pxa buffer to find pxa dma channel | |
321 | * @dma: dma video buffer | |
322 | * @channel: dma channel (0 => 'Y', 1 => 'U', 2 => 'V') | |
323 | * @cibr: camera Receive Buffer Register | |
324 | * @size: bytes to transfer | |
325 | * @sg_first: first element of sg_list | |
326 | * @sg_first_ofs: offset in first element of sg_list | |
327 | * | |
328 | * Prepares the pxa dma descriptors to transfer one camera channel. | |
329 | * Beware sg_first and sg_first_ofs are both input and output parameters. | |
330 | * | |
331 | * Returns 0 or -ENOMEM if no coherent memory is available | |
332 | */ | |
a5462e5b MR |
333 | static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev, |
334 | struct pxa_buffer *buf, | |
335 | struct videobuf_dmabuf *dma, int channel, | |
37f5aefd RJ |
336 | int cibr, int size, |
337 | struct scatterlist **sg_first, int *sg_first_ofs) | |
a5462e5b MR |
338 | { |
339 | struct pxa_cam_dma *pxa_dma = &buf->dmas[channel]; | |
979ea1dd | 340 | struct device *dev = pcdev->soc_host.v4l2_dev.dev; |
37f5aefd RJ |
341 | struct scatterlist *sg; |
342 | int i, offset, sglen; | |
343 | int dma_len = 0, xfer_len = 0; | |
a5462e5b MR |
344 | |
345 | if (pxa_dma->sg_cpu) | |
979ea1dd | 346 | dma_free_coherent(dev, pxa_dma->sg_size, |
a5462e5b MR |
347 | pxa_dma->sg_cpu, pxa_dma->sg_dma); |
348 | ||
37f5aefd RJ |
349 | sglen = calculate_dma_sglen(*sg_first, dma->sglen, |
350 | *sg_first_ofs, size); | |
351 | ||
a5462e5b | 352 | pxa_dma->sg_size = (sglen + 1) * sizeof(struct pxa_dma_desc); |
979ea1dd | 353 | pxa_dma->sg_cpu = dma_alloc_coherent(dev, pxa_dma->sg_size, |
a5462e5b MR |
354 | &pxa_dma->sg_dma, GFP_KERNEL); |
355 | if (!pxa_dma->sg_cpu) | |
356 | return -ENOMEM; | |
357 | ||
358 | pxa_dma->sglen = sglen; | |
37f5aefd | 359 | offset = *sg_first_ofs; |
a5462e5b | 360 | |
979ea1dd | 361 | dev_dbg(dev, "DMA: sg_first=%p, sglen=%d, ofs=%d, dma.desc=%x\n", |
37f5aefd | 362 | *sg_first, sglen, *sg_first_ofs, pxa_dma->sg_dma); |
a5462e5b | 363 | |
37f5aefd RJ |
364 | |
365 | for_each_sg(*sg_first, sg, sglen, i) { | |
366 | dma_len = sg_dma_len(sg); | |
a5462e5b MR |
367 | |
368 | /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */ | |
37f5aefd | 369 | xfer_len = roundup(min(dma_len - offset, size), 8); |
a5462e5b | 370 | |
37f5aefd RJ |
371 | size = max(0, size - xfer_len); |
372 | ||
373 | pxa_dma->sg_cpu[i].dsadr = pcdev->res->start + cibr; | |
374 | pxa_dma->sg_cpu[i].dtadr = sg_dma_address(sg) + offset; | |
a5462e5b MR |
375 | pxa_dma->sg_cpu[i].dcmd = |
376 | DCMD_FLOWSRC | DCMD_BURST8 | DCMD_INCTRGADDR | xfer_len; | |
256b0233 RJ |
377 | #ifdef DEBUG |
378 | if (!i) | |
379 | pxa_dma->sg_cpu[i].dcmd |= DCMD_STARTIRQEN; | |
380 | #endif | |
a5462e5b MR |
381 | pxa_dma->sg_cpu[i].ddadr = |
382 | pxa_dma->sg_dma + (i + 1) * sizeof(struct pxa_dma_desc); | |
37f5aefd | 383 | |
979ea1dd | 384 | dev_vdbg(dev, "DMA: desc.%08x->@phys=0x%08x, len=%d\n", |
37f5aefd RJ |
385 | pxa_dma->sg_dma + i * sizeof(struct pxa_dma_desc), |
386 | sg_dma_address(sg) + offset, xfer_len); | |
387 | offset = 0; | |
388 | ||
389 | if (size == 0) | |
390 | break; | |
a5462e5b MR |
391 | } |
392 | ||
256b0233 RJ |
393 | pxa_dma->sg_cpu[sglen].ddadr = DDADR_STOP; |
394 | pxa_dma->sg_cpu[sglen].dcmd = DCMD_FLOWSRC | DCMD_BURST8 | DCMD_ENDIRQEN; | |
a5462e5b | 395 | |
37f5aefd RJ |
396 | /* |
397 | * Handle 1 special case : | |
398 | * - in 3 planes (YUV422P format), we might finish with xfer_len equal | |
399 | * to dma_len (end on PAGE boundary). In this case, the sg element | |
400 | * for next plane should be the next after the last used to store the | |
401 | * last scatter gather RAM page | |
402 | */ | |
403 | if (xfer_len >= dma_len) { | |
404 | *sg_first_ofs = xfer_len - dma_len; | |
405 | *sg_first = sg_next(sg); | |
406 | } else { | |
407 | *sg_first_ofs = xfer_len; | |
408 | *sg_first = sg; | |
409 | } | |
410 | ||
a5462e5b MR |
411 | return 0; |
412 | } | |
413 | ||
256b0233 RJ |
414 | static void pxa_videobuf_set_actdma(struct pxa_camera_dev *pcdev, |
415 | struct pxa_buffer *buf) | |
416 | { | |
417 | buf->active_dma = DMA_Y; | |
418 | if (pcdev->channels == 3) | |
419 | buf->active_dma |= DMA_U | DMA_V; | |
420 | } | |
421 | ||
422 | /* | |
423 | * Please check the DMA prepared buffer structure in : | |
424 | * Documentation/video4linux/pxa_camera.txt | |
425 | * Please check also in pxa_camera_check_link_miss() to understand why DMA chain | |
426 | * modification while DMA chain is running will work anyway. | |
427 | */ | |
7102b773 GL |
428 | static int pxa_videobuf_prepare(struct videobuf_queue *vq, |
429 | struct videobuf_buffer *vb, enum v4l2_field field) | |
3bc43840 GL |
430 | { |
431 | struct soc_camera_device *icd = vq->priv_data; | |
64f5905e | 432 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
3bc43840 | 433 | struct pxa_camera_dev *pcdev = ici->priv; |
979ea1dd | 434 | struct device *dev = pcdev->soc_host.v4l2_dev.dev; |
3bc43840 | 435 | struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb); |
a5462e5b | 436 | int ret; |
a5462e5b | 437 | int size_y, size_u = 0, size_v = 0; |
760697be GL |
438 | int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width, |
439 | icd->current_fmt->host_fmt); | |
440 | ||
441 | if (bytes_per_line < 0) | |
442 | return bytes_per_line; | |
3bc43840 | 443 | |
979ea1dd | 444 | dev_dbg(dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, |
3bc43840 GL |
445 | vb, vb->baddr, vb->bsize); |
446 | ||
447 | /* Added list head initialization on alloc */ | |
448 | WARN_ON(!list_empty(&vb->queue)); | |
449 | ||
450 | #ifdef DEBUG | |
5d28d525 GL |
451 | /* |
452 | * This can be useful if you want to see if we actually fill | |
453 | * the buffer with something | |
454 | */ | |
3bc43840 GL |
455 | memset((void *)vb->baddr, 0xaa, vb->bsize); |
456 | #endif | |
457 | ||
458 | BUG_ON(NULL == icd->current_fmt); | |
459 | ||
5d28d525 GL |
460 | /* |
461 | * I think, in buf_prepare you only have to protect global data, | |
462 | * the actual buffer is yours | |
463 | */ | |
3bc43840 GL |
464 | buf->inwork = 1; |
465 | ||
760697be | 466 | if (buf->code != icd->current_fmt->code || |
6a6c8786 GL |
467 | vb->width != icd->user_width || |
468 | vb->height != icd->user_height || | |
3bc43840 | 469 | vb->field != field) { |
760697be | 470 | buf->code = icd->current_fmt->code; |
6a6c8786 GL |
471 | vb->width = icd->user_width; |
472 | vb->height = icd->user_height; | |
3bc43840 GL |
473 | vb->field = field; |
474 | vb->state = VIDEOBUF_NEEDS_INIT; | |
475 | } | |
476 | ||
760697be | 477 | vb->size = bytes_per_line * vb->height; |
3bc43840 GL |
478 | if (0 != vb->baddr && vb->bsize < vb->size) { |
479 | ret = -EINVAL; | |
480 | goto out; | |
481 | } | |
482 | ||
483 | if (vb->state == VIDEOBUF_NEEDS_INIT) { | |
37f5aefd RJ |
484 | int size = vb->size; |
485 | int next_ofs = 0; | |
3bc43840 | 486 | struct videobuf_dmabuf *dma = videobuf_to_dma(vb); |
37f5aefd | 487 | struct scatterlist *sg; |
3bc43840 GL |
488 | |
489 | ret = videobuf_iolock(vq, vb, NULL); | |
490 | if (ret) | |
491 | goto fail; | |
492 | ||
5aa2110f | 493 | if (pcdev->channels == 3) { |
a5462e5b MR |
494 | size_y = size / 2; |
495 | size_u = size_v = size / 4; | |
496 | } else { | |
a5462e5b MR |
497 | size_y = size; |
498 | } | |
499 | ||
37f5aefd | 500 | sg = dma->sglist; |
3bc43840 | 501 | |
37f5aefd RJ |
502 | /* init DMA for Y channel */ |
503 | ret = pxa_init_dma_channel(pcdev, buf, dma, 0, CIBR0, size_y, | |
504 | &sg, &next_ofs); | |
a5462e5b | 505 | if (ret) { |
979ea1dd | 506 | dev_err(dev, "DMA initialization for Y/RGB failed\n"); |
3bc43840 GL |
507 | goto fail; |
508 | } | |
509 | ||
37f5aefd RJ |
510 | /* init DMA for U channel */ |
511 | if (size_u) | |
512 | ret = pxa_init_dma_channel(pcdev, buf, dma, 1, CIBR1, | |
513 | size_u, &sg, &next_ofs); | |
514 | if (ret) { | |
979ea1dd | 515 | dev_err(dev, "DMA initialization for U failed\n"); |
37f5aefd RJ |
516 | goto fail_u; |
517 | } | |
518 | ||
519 | /* init DMA for V channel */ | |
520 | if (size_v) | |
521 | ret = pxa_init_dma_channel(pcdev, buf, dma, 2, CIBR2, | |
522 | size_v, &sg, &next_ofs); | |
523 | if (ret) { | |
979ea1dd | 524 | dev_err(dev, "DMA initialization for V failed\n"); |
37f5aefd | 525 | goto fail_v; |
3bc43840 | 526 | } |
3bc43840 GL |
527 | |
528 | vb->state = VIDEOBUF_PREPARED; | |
529 | } | |
530 | ||
531 | buf->inwork = 0; | |
256b0233 | 532 | pxa_videobuf_set_actdma(pcdev, buf); |
3bc43840 GL |
533 | |
534 | return 0; | |
535 | ||
a5462e5b | 536 | fail_v: |
979ea1dd | 537 | dma_free_coherent(dev, buf->dmas[1].sg_size, |
a5462e5b MR |
538 | buf->dmas[1].sg_cpu, buf->dmas[1].sg_dma); |
539 | fail_u: | |
979ea1dd | 540 | dma_free_coherent(dev, buf->dmas[0].sg_size, |
a5462e5b | 541 | buf->dmas[0].sg_cpu, buf->dmas[0].sg_dma); |
3bc43840 GL |
542 | fail: |
543 | free_buffer(vq, buf); | |
544 | out: | |
545 | buf->inwork = 0; | |
546 | return ret; | |
547 | } | |
548 | ||
256b0233 RJ |
549 | /** |
550 | * pxa_dma_start_channels - start DMA channel for active buffer | |
551 | * @pcdev: pxa camera device | |
552 | * | |
553 | * Initialize DMA channels to the beginning of the active video buffer, and | |
554 | * start these channels. | |
555 | */ | |
556 | static void pxa_dma_start_channels(struct pxa_camera_dev *pcdev) | |
557 | { | |
558 | int i; | |
559 | struct pxa_buffer *active; | |
560 | ||
561 | active = pcdev->active; | |
562 | ||
563 | for (i = 0; i < pcdev->channels; i++) { | |
0166b743 GL |
564 | dev_dbg(pcdev->soc_host.v4l2_dev.dev, |
565 | "%s (channel=%d) ddadr=%08x\n", __func__, | |
256b0233 RJ |
566 | i, active->dmas[i].sg_dma); |
567 | DDADR(pcdev->dma_chans[i]) = active->dmas[i].sg_dma; | |
568 | DCSR(pcdev->dma_chans[i]) = DCSR_RUN; | |
569 | } | |
570 | } | |
571 | ||
572 | static void pxa_dma_stop_channels(struct pxa_camera_dev *pcdev) | |
573 | { | |
574 | int i; | |
575 | ||
576 | for (i = 0; i < pcdev->channels; i++) { | |
0166b743 GL |
577 | dev_dbg(pcdev->soc_host.v4l2_dev.dev, |
578 | "%s (channel=%d)\n", __func__, i); | |
256b0233 RJ |
579 | DCSR(pcdev->dma_chans[i]) = 0; |
580 | } | |
581 | } | |
582 | ||
256b0233 RJ |
583 | static void pxa_dma_add_tail_buf(struct pxa_camera_dev *pcdev, |
584 | struct pxa_buffer *buf) | |
585 | { | |
586 | int i; | |
587 | struct pxa_dma_desc *buf_last_desc; | |
588 | ||
589 | for (i = 0; i < pcdev->channels; i++) { | |
590 | buf_last_desc = buf->dmas[i].sg_cpu + buf->dmas[i].sglen; | |
591 | buf_last_desc->ddadr = DDADR_STOP; | |
592 | ||
ae7410e7 GL |
593 | if (pcdev->sg_tail[i]) |
594 | /* Link the new buffer to the old tail */ | |
595 | pcdev->sg_tail[i]->ddadr = buf->dmas[i].sg_dma; | |
256b0233 | 596 | |
ae7410e7 GL |
597 | /* Update the channel tail */ |
598 | pcdev->sg_tail[i] = buf_last_desc; | |
599 | } | |
256b0233 RJ |
600 | } |
601 | ||
602 | /** | |
603 | * pxa_camera_start_capture - start video capturing | |
604 | * @pcdev: camera device | |
605 | * | |
606 | * Launch capturing. DMA channels should not be active yet. They should get | |
607 | * activated at the end of frame interrupt, to capture only whole frames, and | |
608 | * never begin the capture of a partial frame. | |
609 | */ | |
610 | static void pxa_camera_start_capture(struct pxa_camera_dev *pcdev) | |
611 | { | |
612 | unsigned long cicr0, cifr; | |
613 | ||
979ea1dd | 614 | dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s\n", __func__); |
256b0233 RJ |
615 | /* Reset the FIFOs */ |
616 | cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F; | |
617 | __raw_writel(cifr, pcdev->base + CIFR); | |
618 | /* Enable End-Of-Frame Interrupt */ | |
619 | cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB; | |
620 | cicr0 &= ~CICR0_EOFM; | |
621 | __raw_writel(cicr0, pcdev->base + CICR0); | |
622 | } | |
623 | ||
624 | static void pxa_camera_stop_capture(struct pxa_camera_dev *pcdev) | |
625 | { | |
626 | unsigned long cicr0; | |
627 | ||
628 | pxa_dma_stop_channels(pcdev); | |
629 | ||
630 | cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB; | |
631 | __raw_writel(cicr0, pcdev->base + CICR0); | |
632 | ||
8c62e221 | 633 | pcdev->active = NULL; |
979ea1dd | 634 | dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s\n", __func__); |
256b0233 RJ |
635 | } |
636 | ||
2dd54a54 | 637 | /* Called under spinlock_irqsave(&pcdev->lock, ...) */ |
7102b773 GL |
638 | static void pxa_videobuf_queue(struct videobuf_queue *vq, |
639 | struct videobuf_buffer *vb) | |
3bc43840 GL |
640 | { |
641 | struct soc_camera_device *icd = vq->priv_data; | |
64f5905e | 642 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
3bc43840 GL |
643 | struct pxa_camera_dev *pcdev = ici->priv; |
644 | struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb); | |
3bc43840 | 645 | |
0166b743 GL |
646 | dev_dbg(icd->dev.parent, "%s (vb=0x%p) 0x%08lx %d active=%p\n", |
647 | __func__, vb, vb->baddr, vb->bsize, pcdev->active); | |
256b0233 | 648 | |
3bc43840 GL |
649 | list_add_tail(&vb->queue, &pcdev->capture); |
650 | ||
651 | vb->state = VIDEOBUF_ACTIVE; | |
256b0233 | 652 | pxa_dma_add_tail_buf(pcdev, buf); |
3bc43840 | 653 | |
256b0233 RJ |
654 | if (!pcdev->active) |
655 | pxa_camera_start_capture(pcdev); | |
3bc43840 GL |
656 | } |
657 | ||
658 | static void pxa_videobuf_release(struct videobuf_queue *vq, | |
659 | struct videobuf_buffer *vb) | |
660 | { | |
661 | struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb); | |
662 | #ifdef DEBUG | |
663 | struct soc_camera_device *icd = vq->priv_data; | |
0166b743 | 664 | struct device *dev = icd->dev.parent; |
3bc43840 | 665 | |
0166b743 | 666 | dev_dbg(dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, |
3bc43840 GL |
667 | vb, vb->baddr, vb->bsize); |
668 | ||
669 | switch (vb->state) { | |
670 | case VIDEOBUF_ACTIVE: | |
0166b743 | 671 | dev_dbg(dev, "%s (active)\n", __func__); |
3bc43840 GL |
672 | break; |
673 | case VIDEOBUF_QUEUED: | |
0166b743 | 674 | dev_dbg(dev, "%s (queued)\n", __func__); |
3bc43840 GL |
675 | break; |
676 | case VIDEOBUF_PREPARED: | |
0166b743 | 677 | dev_dbg(dev, "%s (prepared)\n", __func__); |
3bc43840 GL |
678 | break; |
679 | default: | |
0166b743 | 680 | dev_dbg(dev, "%s (unknown)\n", __func__); |
3bc43840 GL |
681 | break; |
682 | } | |
683 | #endif | |
684 | ||
685 | free_buffer(vq, buf); | |
686 | } | |
687 | ||
a5462e5b MR |
688 | static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev, |
689 | struct videobuf_buffer *vb, | |
690 | struct pxa_buffer *buf) | |
691 | { | |
256b0233 | 692 | int i; |
5ca11fa3 | 693 | |
a5462e5b MR |
694 | /* _init is used to debug races, see comment in pxa_camera_reqbufs() */ |
695 | list_del_init(&vb->queue); | |
696 | vb->state = VIDEOBUF_DONE; | |
697 | do_gettimeofday(&vb->ts); | |
698 | vb->field_count++; | |
699 | wake_up(&vb->done); | |
979ea1dd GL |
700 | dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s dequeud buffer (vb=0x%p)\n", |
701 | __func__, vb); | |
a5462e5b MR |
702 | |
703 | if (list_empty(&pcdev->capture)) { | |
256b0233 | 704 | pxa_camera_stop_capture(pcdev); |
256b0233 RJ |
705 | for (i = 0; i < pcdev->channels; i++) |
706 | pcdev->sg_tail[i] = NULL; | |
a5462e5b MR |
707 | return; |
708 | } | |
709 | ||
710 | pcdev->active = list_entry(pcdev->capture.next, | |
711 | struct pxa_buffer, vb.queue); | |
712 | } | |
713 | ||
256b0233 RJ |
714 | /** |
715 | * pxa_camera_check_link_miss - check missed DMA linking | |
716 | * @pcdev: camera device | |
717 | * | |
718 | * The DMA chaining is done with DMA running. This means a tiny temporal window | |
719 | * remains, where a buffer is queued on the chain, while the chain is already | |
720 | * stopped. This means the tailed buffer would never be transfered by DMA. | |
721 | * This function restarts the capture for this corner case, where : | |
722 | * - DADR() == DADDR_STOP | |
723 | * - a videobuffer is queued on the pcdev->capture list | |
724 | * | |
725 | * Please check the "DMA hot chaining timeslice issue" in | |
726 | * Documentation/video4linux/pxa_camera.txt | |
727 | * | |
728 | * Context: should only be called within the dma irq handler | |
729 | */ | |
730 | static void pxa_camera_check_link_miss(struct pxa_camera_dev *pcdev) | |
731 | { | |
732 | int i, is_dma_stopped = 1; | |
733 | ||
734 | for (i = 0; i < pcdev->channels; i++) | |
735 | if (DDADR(pcdev->dma_chans[i]) != DDADR_STOP) | |
736 | is_dma_stopped = 0; | |
979ea1dd GL |
737 | dev_dbg(pcdev->soc_host.v4l2_dev.dev, |
738 | "%s : top queued buffer=%p, dma_stopped=%d\n", | |
256b0233 RJ |
739 | __func__, pcdev->active, is_dma_stopped); |
740 | if (pcdev->active && is_dma_stopped) | |
741 | pxa_camera_start_capture(pcdev); | |
742 | } | |
743 | ||
a5462e5b MR |
744 | static void pxa_camera_dma_irq(int channel, struct pxa_camera_dev *pcdev, |
745 | enum pxa_camera_active_dma act_dma) | |
3bc43840 | 746 | { |
979ea1dd | 747 | struct device *dev = pcdev->soc_host.v4l2_dev.dev; |
3bc43840 GL |
748 | struct pxa_buffer *buf; |
749 | unsigned long flags; | |
e7c50688 | 750 | u32 status, camera_status, overrun; |
3bc43840 GL |
751 | struct videobuf_buffer *vb; |
752 | ||
753 | spin_lock_irqsave(&pcdev->lock, flags); | |
754 | ||
a5462e5b | 755 | status = DCSR(channel); |
256b0233 RJ |
756 | DCSR(channel) = status; |
757 | ||
758 | camera_status = __raw_readl(pcdev->base + CISR); | |
759 | overrun = CISR_IFO_0; | |
760 | if (pcdev->channels == 3) | |
761 | overrun |= CISR_IFO_1 | CISR_IFO_2; | |
7102b773 | 762 | |
3bc43840 | 763 | if (status & DCSR_BUSERR) { |
979ea1dd | 764 | dev_err(dev, "DMA Bus Error IRQ!\n"); |
3bc43840 GL |
765 | goto out; |
766 | } | |
767 | ||
256b0233 | 768 | if (!(status & (DCSR_ENDINTR | DCSR_STARTINTR))) { |
979ea1dd GL |
769 | dev_err(dev, "Unknown DMA IRQ source, status: 0x%08x\n", |
770 | status); | |
3bc43840 GL |
771 | goto out; |
772 | } | |
773 | ||
8c62e221 RJ |
774 | /* |
775 | * pcdev->active should not be NULL in DMA irq handler. | |
776 | * | |
777 | * But there is one corner case : if capture was stopped due to an | |
778 | * overrun of channel 1, and at that same channel 2 was completed. | |
779 | * | |
780 | * When handling the overrun in DMA irq for channel 1, we'll stop the | |
781 | * capture and restart it (and thus set pcdev->active to NULL). But the | |
782 | * DMA irq handler will already be pending for channel 2. So on entering | |
783 | * the DMA irq handler for channel 2 there will be no active buffer, yet | |
784 | * that is normal. | |
785 | */ | |
786 | if (!pcdev->active) | |
3bc43840 | 787 | goto out; |
3bc43840 GL |
788 | |
789 | vb = &pcdev->active->vb; | |
790 | buf = container_of(vb, struct pxa_buffer, vb); | |
791 | WARN_ON(buf->inwork || list_empty(&vb->queue)); | |
3bc43840 | 792 | |
979ea1dd | 793 | dev_dbg(dev, "%s channel=%d %s%s(vb=0x%p) dma.desc=%x\n", |
256b0233 RJ |
794 | __func__, channel, status & DCSR_STARTINTR ? "SOF " : "", |
795 | status & DCSR_ENDINTR ? "EOF " : "", vb, DDADR(channel)); | |
796 | ||
797 | if (status & DCSR_ENDINTR) { | |
8c62e221 RJ |
798 | /* |
799 | * It's normal if the last frame creates an overrun, as there | |
800 | * are no more DMA descriptors to fetch from QCI fifos | |
801 | */ | |
802 | if (camera_status & overrun && | |
803 | !list_is_last(pcdev->capture.next, &pcdev->capture)) { | |
979ea1dd | 804 | dev_dbg(dev, "FIFO overrun! CISR: %x\n", |
256b0233 RJ |
805 | camera_status); |
806 | pxa_camera_stop_capture(pcdev); | |
807 | pxa_camera_start_capture(pcdev); | |
808 | goto out; | |
809 | } | |
810 | buf->active_dma &= ~act_dma; | |
811 | if (!buf->active_dma) { | |
812 | pxa_camera_wakeup(pcdev, vb, buf); | |
813 | pxa_camera_check_link_miss(pcdev); | |
814 | } | |
815 | } | |
3bc43840 GL |
816 | |
817 | out: | |
818 | spin_unlock_irqrestore(&pcdev->lock, flags); | |
819 | } | |
820 | ||
a5462e5b MR |
821 | static void pxa_camera_dma_irq_y(int channel, void *data) |
822 | { | |
823 | struct pxa_camera_dev *pcdev = data; | |
824 | pxa_camera_dma_irq(channel, pcdev, DMA_Y); | |
825 | } | |
826 | ||
827 | static void pxa_camera_dma_irq_u(int channel, void *data) | |
828 | { | |
829 | struct pxa_camera_dev *pcdev = data; | |
830 | pxa_camera_dma_irq(channel, pcdev, DMA_U); | |
831 | } | |
832 | ||
833 | static void pxa_camera_dma_irq_v(int channel, void *data) | |
834 | { | |
835 | struct pxa_camera_dev *pcdev = data; | |
836 | pxa_camera_dma_irq(channel, pcdev, DMA_V); | |
837 | } | |
838 | ||
7102b773 | 839 | static struct videobuf_queue_ops pxa_videobuf_ops = { |
3bc43840 GL |
840 | .buf_setup = pxa_videobuf_setup, |
841 | .buf_prepare = pxa_videobuf_prepare, | |
842 | .buf_queue = pxa_videobuf_queue, | |
843 | .buf_release = pxa_videobuf_release, | |
844 | }; | |
845 | ||
a034d1b7 | 846 | static void pxa_camera_init_videobuf(struct videobuf_queue *q, |
092d3921 PZ |
847 | struct soc_camera_device *icd) |
848 | { | |
a034d1b7 MD |
849 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
850 | struct pxa_camera_dev *pcdev = ici->priv; | |
851 | ||
5d28d525 GL |
852 | /* |
853 | * We must pass NULL as dev pointer, then all pci_* dma operations | |
854 | * transform to normal dma_* ones. | |
855 | */ | |
a034d1b7 | 856 | videobuf_queue_sg_init(q, &pxa_videobuf_ops, NULL, &pcdev->lock, |
092d3921 PZ |
857 | V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_NONE, |
858 | sizeof(struct pxa_buffer), icd); | |
859 | } | |
860 | ||
40e2e092 GL |
861 | static u32 mclk_get_divisor(struct platform_device *pdev, |
862 | struct pxa_camera_dev *pcdev) | |
3bc43840 | 863 | { |
cf34cba7 | 864 | unsigned long mclk = pcdev->mclk; |
6a6c8786 | 865 | struct device *dev = &pdev->dev; |
cf34cba7 | 866 | u32 div; |
3bc43840 GL |
867 | unsigned long lcdclk; |
868 | ||
cf34cba7 GL |
869 | lcdclk = clk_get_rate(pcdev->clk); |
870 | pcdev->ciclk = lcdclk; | |
3bc43840 | 871 | |
cf34cba7 GL |
872 | /* mclk <= ciclk / 4 (27.4.2) */ |
873 | if (mclk > lcdclk / 4) { | |
874 | mclk = lcdclk / 4; | |
979ea1dd | 875 | dev_warn(dev, "Limiting master clock to %lu\n", mclk); |
cf34cba7 GL |
876 | } |
877 | ||
878 | /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */ | |
879 | div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1; | |
3bc43840 | 880 | |
cf34cba7 GL |
881 | /* If we're not supplying MCLK, leave it at 0 */ |
882 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | |
883 | pcdev->mclk = lcdclk / (2 * (div + 1)); | |
3bc43840 | 884 | |
979ea1dd | 885 | dev_dbg(dev, "LCD clock %luHz, target freq %luHz, divisor %u\n", |
40e2e092 | 886 | lcdclk, mclk, div); |
3bc43840 GL |
887 | |
888 | return div; | |
889 | } | |
890 | ||
cf34cba7 GL |
891 | static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev, |
892 | unsigned long pclk) | |
893 | { | |
894 | /* We want a timeout > 1 pixel time, not ">=" */ | |
895 | u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1; | |
896 | ||
897 | __raw_writel(ciclk_per_pixel, pcdev->base + CITOR); | |
898 | } | |
899 | ||
7102b773 | 900 | static void pxa_camera_activate(struct pxa_camera_dev *pcdev) |
3bc43840 | 901 | { |
3bc43840 GL |
902 | u32 cicr4 = 0; |
903 | ||
5ca11fa3 EM |
904 | /* disable all interrupts */ |
905 | __raw_writel(0x3ff, pcdev->base + CICR0); | |
3bc43840 GL |
906 | |
907 | if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) | |
908 | cicr4 |= CICR4_PCLK_EN; | |
909 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | |
910 | cicr4 |= CICR4_MCLK_EN; | |
911 | if (pcdev->platform_flags & PXA_CAMERA_PCP) | |
912 | cicr4 |= CICR4_PCP; | |
913 | if (pcdev->platform_flags & PXA_CAMERA_HSP) | |
914 | cicr4 |= CICR4_HSP; | |
915 | if (pcdev->platform_flags & PXA_CAMERA_VSP) | |
916 | cicr4 |= CICR4_VSP; | |
917 | ||
cf34cba7 GL |
918 | __raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4); |
919 | ||
920 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | |
921 | /* Initialise the timeout under the assumption pclk = mclk */ | |
922 | recalculate_fifo_timeout(pcdev, pcdev->mclk); | |
923 | else | |
924 | /* "Safe default" - 13MHz */ | |
925 | recalculate_fifo_timeout(pcdev, 13000000); | |
3bc43840 GL |
926 | |
927 | clk_enable(pcdev->clk); | |
928 | } | |
929 | ||
7102b773 | 930 | static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev) |
3bc43840 | 931 | { |
3bc43840 | 932 | clk_disable(pcdev->clk); |
3bc43840 GL |
933 | } |
934 | ||
935 | static irqreturn_t pxa_camera_irq(int irq, void *data) | |
936 | { | |
937 | struct pxa_camera_dev *pcdev = data; | |
5ca11fa3 | 938 | unsigned long status, cicr0; |
256b0233 RJ |
939 | struct pxa_buffer *buf; |
940 | struct videobuf_buffer *vb; | |
3bc43840 | 941 | |
5ca11fa3 | 942 | status = __raw_readl(pcdev->base + CISR); |
0166b743 GL |
943 | dev_dbg(pcdev->soc_host.v4l2_dev.dev, |
944 | "Camera interrupt status 0x%lx\n", status); | |
3bc43840 | 945 | |
e7c50688 GL |
946 | if (!status) |
947 | return IRQ_NONE; | |
948 | ||
5ca11fa3 | 949 | __raw_writel(status, pcdev->base + CISR); |
e7c50688 GL |
950 | |
951 | if (status & CISR_EOF) { | |
256b0233 RJ |
952 | pcdev->active = list_first_entry(&pcdev->capture, |
953 | struct pxa_buffer, vb.queue); | |
954 | vb = &pcdev->active->vb; | |
955 | buf = container_of(vb, struct pxa_buffer, vb); | |
956 | pxa_videobuf_set_actdma(pcdev, buf); | |
957 | ||
958 | pxa_dma_start_channels(pcdev); | |
959 | ||
5ca11fa3 EM |
960 | cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM; |
961 | __raw_writel(cicr0, pcdev->base + CICR0); | |
e7c50688 GL |
962 | } |
963 | ||
3bc43840 GL |
964 | return IRQ_HANDLED; |
965 | } | |
966 | ||
1c3bb743 GL |
967 | /* |
968 | * The following two functions absolutely depend on the fact, that | |
969 | * there can be only one camera on PXA quick capture interface | |
970 | * Called with .video_lock held | |
971 | */ | |
7102b773 | 972 | static int pxa_camera_add_device(struct soc_camera_device *icd) |
3bc43840 GL |
973 | { |
974 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); | |
975 | struct pxa_camera_dev *pcdev = ici->priv; | |
3bc43840 | 976 | |
979ea1dd GL |
977 | if (pcdev->icd) |
978 | return -EBUSY; | |
3bc43840 | 979 | |
7102b773 | 980 | pxa_camera_activate(pcdev); |
40e2e092 GL |
981 | |
982 | pcdev->icd = icd; | |
3bc43840 | 983 | |
0166b743 | 984 | dev_info(icd->dev.parent, "PXA Camera driver attached to camera %d\n", |
40e2e092 | 985 | icd->devnum); |
3bc43840 | 986 | |
40e2e092 | 987 | return 0; |
3bc43840 GL |
988 | } |
989 | ||
1c3bb743 | 990 | /* Called with .video_lock held */ |
7102b773 | 991 | static void pxa_camera_remove_device(struct soc_camera_device *icd) |
3bc43840 GL |
992 | { |
993 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); | |
994 | struct pxa_camera_dev *pcdev = ici->priv; | |
995 | ||
996 | BUG_ON(icd != pcdev->icd); | |
997 | ||
0166b743 | 998 | dev_info(icd->dev.parent, "PXA Camera driver detached from camera %d\n", |
3bc43840 GL |
999 | icd->devnum); |
1000 | ||
1001 | /* disable capture, disable interrupts */ | |
5ca11fa3 | 1002 | __raw_writel(0x3ff, pcdev->base + CICR0); |
a5462e5b | 1003 | |
3bc43840 | 1004 | /* Stop DMA engine */ |
a5462e5b MR |
1005 | DCSR(pcdev->dma_chans[0]) = 0; |
1006 | DCSR(pcdev->dma_chans[1]) = 0; | |
1007 | DCSR(pcdev->dma_chans[2]) = 0; | |
3bc43840 | 1008 | |
7102b773 | 1009 | pxa_camera_deactivate(pcdev); |
3bc43840 GL |
1010 | |
1011 | pcdev->icd = NULL; | |
1012 | } | |
1013 | ||
ad5f2e85 GL |
1014 | static int test_platform_param(struct pxa_camera_dev *pcdev, |
1015 | unsigned char buswidth, unsigned long *flags) | |
3bc43840 | 1016 | { |
ad5f2e85 GL |
1017 | /* |
1018 | * Platform specified synchronization and pixel clock polarities are | |
1019 | * only a recommendation and are only used during probing. The PXA270 | |
1020 | * quick capture interface supports both. | |
1021 | */ | |
1022 | *flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ? | |
1023 | SOCAM_MASTER : SOCAM_SLAVE) | | |
1024 | SOCAM_HSYNC_ACTIVE_HIGH | | |
1025 | SOCAM_HSYNC_ACTIVE_LOW | | |
1026 | SOCAM_VSYNC_ACTIVE_HIGH | | |
1027 | SOCAM_VSYNC_ACTIVE_LOW | | |
2d9329f3 | 1028 | SOCAM_DATA_ACTIVE_HIGH | |
ad5f2e85 GL |
1029 | SOCAM_PCLK_SAMPLE_RISING | |
1030 | SOCAM_PCLK_SAMPLE_FALLING; | |
3bc43840 GL |
1031 | |
1032 | /* If requested data width is supported by the platform, use it */ | |
ad5f2e85 | 1033 | switch (buswidth) { |
3bc43840 | 1034 | case 10: |
ad5f2e85 GL |
1035 | if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10)) |
1036 | return -EINVAL; | |
1037 | *flags |= SOCAM_DATAWIDTH_10; | |
3bc43840 GL |
1038 | break; |
1039 | case 9: | |
ad5f2e85 GL |
1040 | if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9)) |
1041 | return -EINVAL; | |
1042 | *flags |= SOCAM_DATAWIDTH_9; | |
3bc43840 GL |
1043 | break; |
1044 | case 8: | |
ad5f2e85 GL |
1045 | if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8)) |
1046 | return -EINVAL; | |
1047 | *flags |= SOCAM_DATAWIDTH_8; | |
2a48fc73 RJ |
1048 | break; |
1049 | default: | |
1050 | return -EINVAL; | |
3bc43840 | 1051 | } |
ad5f2e85 GL |
1052 | |
1053 | return 0; | |
1054 | } | |
1055 | ||
6a6c8786 GL |
1056 | static void pxa_camera_setup_cicr(struct soc_camera_device *icd, |
1057 | unsigned long flags, __u32 pixfmt) | |
ad5f2e85 | 1058 | { |
64f5905e | 1059 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
ad5f2e85 | 1060 | struct pxa_camera_dev *pcdev = ici->priv; |
32536108 | 1061 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
6a6c8786 | 1062 | unsigned long dw, bpp; |
32536108 GL |
1063 | u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0, y_skip_top; |
1064 | int ret = v4l2_subdev_call(sd, sensor, g_skip_top_lines, &y_skip_top); | |
1065 | ||
1066 | if (ret < 0) | |
1067 | y_skip_top = 0; | |
3bc43840 | 1068 | |
5d28d525 GL |
1069 | /* |
1070 | * Datawidth is now guaranteed to be equal to one of the three values. | |
1071 | * We fix bit-per-pixel equal to data-width... | |
1072 | */ | |
6a6c8786 | 1073 | switch (flags & SOCAM_DATAWIDTH_MASK) { |
ad5f2e85 | 1074 | case SOCAM_DATAWIDTH_10: |
3bc43840 GL |
1075 | dw = 4; |
1076 | bpp = 0x40; | |
1077 | break; | |
ad5f2e85 | 1078 | case SOCAM_DATAWIDTH_9: |
3bc43840 GL |
1079 | dw = 3; |
1080 | bpp = 0x20; | |
1081 | break; | |
1082 | default: | |
5d28d525 GL |
1083 | /* |
1084 | * Actually it can only be 8 now, | |
1085 | * default is just to silence compiler warnings | |
1086 | */ | |
ad5f2e85 | 1087 | case SOCAM_DATAWIDTH_8: |
3bc43840 GL |
1088 | dw = 2; |
1089 | bpp = 0; | |
1090 | } | |
1091 | ||
1092 | if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) | |
1093 | cicr4 |= CICR4_PCLK_EN; | |
1094 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | |
1095 | cicr4 |= CICR4_MCLK_EN; | |
6a6c8786 | 1096 | if (flags & SOCAM_PCLK_SAMPLE_FALLING) |
3bc43840 | 1097 | cicr4 |= CICR4_PCP; |
6a6c8786 | 1098 | if (flags & SOCAM_HSYNC_ACTIVE_LOW) |
3bc43840 | 1099 | cicr4 |= CICR4_HSP; |
6a6c8786 | 1100 | if (flags & SOCAM_VSYNC_ACTIVE_LOW) |
3bc43840 GL |
1101 | cicr4 |= CICR4_VSP; |
1102 | ||
5ca11fa3 | 1103 | cicr0 = __raw_readl(pcdev->base + CICR0); |
3bc43840 | 1104 | if (cicr0 & CICR0_ENB) |
5ca11fa3 | 1105 | __raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0); |
a5462e5b | 1106 | |
6a6c8786 | 1107 | cicr1 = CICR1_PPL_VAL(icd->user_width - 1) | bpp | dw; |
a5462e5b MR |
1108 | |
1109 | switch (pixfmt) { | |
1110 | case V4L2_PIX_FMT_YUV422P: | |
e7c50688 | 1111 | pcdev->channels = 3; |
a5462e5b | 1112 | cicr1 |= CICR1_YCBCR_F; |
2a48fc73 RJ |
1113 | /* |
1114 | * Normally, pxa bus wants as input UYVY format. We allow all | |
1115 | * reorderings of the YUV422 format, as no processing is done, | |
1116 | * and the YUV stream is just passed through without any | |
1117 | * transformation. Note that UYVY is the only format that | |
1118 | * should be used if pxa framebuffer Overlay2 is used. | |
1119 | */ | |
1120 | case V4L2_PIX_FMT_UYVY: | |
1121 | case V4L2_PIX_FMT_VYUY: | |
a5462e5b | 1122 | case V4L2_PIX_FMT_YUYV: |
2a48fc73 | 1123 | case V4L2_PIX_FMT_YVYU: |
a5462e5b MR |
1124 | cicr1 |= CICR1_COLOR_SP_VAL(2); |
1125 | break; | |
1126 | case V4L2_PIX_FMT_RGB555: | |
1127 | cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) | | |
1128 | CICR1_TBIT | CICR1_COLOR_SP_VAL(1); | |
1129 | break; | |
1130 | case V4L2_PIX_FMT_RGB565: | |
1131 | cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2); | |
1132 | break; | |
1133 | } | |
1134 | ||
5ca11fa3 | 1135 | cicr2 = 0; |
6a6c8786 | 1136 | cicr3 = CICR3_LPF_VAL(icd->user_height - 1) | |
32536108 | 1137 | CICR3_BFW_VAL(min((u32)255, y_skip_top)); |
cf34cba7 | 1138 | cicr4 |= pcdev->mclk_divisor; |
5ca11fa3 EM |
1139 | |
1140 | __raw_writel(cicr1, pcdev->base + CICR1); | |
1141 | __raw_writel(cicr2, pcdev->base + CICR2); | |
1142 | __raw_writel(cicr3, pcdev->base + CICR3); | |
1143 | __raw_writel(cicr4, pcdev->base + CICR4); | |
3bc43840 GL |
1144 | |
1145 | /* CIF interrupts are not used, only DMA */ | |
5ca11fa3 EM |
1146 | cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ? |
1147 | CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP)); | |
1148 | cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK; | |
1149 | __raw_writel(cicr0, pcdev->base + CICR0); | |
6a6c8786 GL |
1150 | } |
1151 | ||
1152 | static int pxa_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt) | |
1153 | { | |
1154 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); | |
1155 | struct pxa_camera_dev *pcdev = ici->priv; | |
1156 | unsigned long bus_flags, camera_flags, common_flags; | |
760697be GL |
1157 | const struct soc_mbus_pixelfmt *fmt; |
1158 | int ret; | |
6a6c8786 GL |
1159 | struct pxa_cam *cam = icd->host_priv; |
1160 | ||
760697be GL |
1161 | fmt = soc_mbus_get_fmtdesc(icd->current_fmt->code); |
1162 | if (!fmt) | |
1163 | return -EINVAL; | |
1164 | ||
1165 | ret = test_platform_param(pcdev, fmt->bits_per_sample, &bus_flags); | |
6a6c8786 GL |
1166 | if (ret < 0) |
1167 | return ret; | |
1168 | ||
1169 | camera_flags = icd->ops->query_bus_param(icd); | |
1170 | ||
1171 | common_flags = soc_camera_bus_param_compatible(camera_flags, bus_flags); | |
1172 | if (!common_flags) | |
1173 | return -EINVAL; | |
1174 | ||
1175 | pcdev->channels = 1; | |
1176 | ||
1177 | /* Make choises, based on platform preferences */ | |
1178 | if ((common_flags & SOCAM_HSYNC_ACTIVE_HIGH) && | |
1179 | (common_flags & SOCAM_HSYNC_ACTIVE_LOW)) { | |
1180 | if (pcdev->platform_flags & PXA_CAMERA_HSP) | |
1181 | common_flags &= ~SOCAM_HSYNC_ACTIVE_HIGH; | |
1182 | else | |
1183 | common_flags &= ~SOCAM_HSYNC_ACTIVE_LOW; | |
1184 | } | |
1185 | ||
1186 | if ((common_flags & SOCAM_VSYNC_ACTIVE_HIGH) && | |
1187 | (common_flags & SOCAM_VSYNC_ACTIVE_LOW)) { | |
1188 | if (pcdev->platform_flags & PXA_CAMERA_VSP) | |
1189 | common_flags &= ~SOCAM_VSYNC_ACTIVE_HIGH; | |
1190 | else | |
1191 | common_flags &= ~SOCAM_VSYNC_ACTIVE_LOW; | |
1192 | } | |
1193 | ||
1194 | if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) && | |
1195 | (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) { | |
1196 | if (pcdev->platform_flags & PXA_CAMERA_PCP) | |
1197 | common_flags &= ~SOCAM_PCLK_SAMPLE_RISING; | |
1198 | else | |
1199 | common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING; | |
1200 | } | |
1201 | ||
1202 | cam->flags = common_flags; | |
1203 | ||
1204 | ret = icd->ops->set_bus_param(icd, common_flags); | |
1205 | if (ret < 0) | |
1206 | return ret; | |
1207 | ||
1208 | pxa_camera_setup_cicr(icd, common_flags, pixfmt); | |
3bc43840 GL |
1209 | |
1210 | return 0; | |
1211 | } | |
1212 | ||
2a48fc73 RJ |
1213 | static int pxa_camera_try_bus_param(struct soc_camera_device *icd, |
1214 | unsigned char buswidth) | |
ad5f2e85 | 1215 | { |
cf34cba7 | 1216 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
ad5f2e85 GL |
1217 | struct pxa_camera_dev *pcdev = ici->priv; |
1218 | unsigned long bus_flags, camera_flags; | |
2a48fc73 | 1219 | int ret = test_platform_param(pcdev, buswidth, &bus_flags); |
ad5f2e85 GL |
1220 | |
1221 | if (ret < 0) | |
1222 | return ret; | |
1223 | ||
1224 | camera_flags = icd->ops->query_bus_param(icd); | |
1225 | ||
1226 | return soc_camera_bus_param_compatible(camera_flags, bus_flags) ? 0 : -EINVAL; | |
1227 | } | |
1228 | ||
760697be | 1229 | static const struct soc_mbus_pixelfmt pxa_camera_formats[] = { |
2a48fc73 | 1230 | { |
760697be GL |
1231 | .fourcc = V4L2_PIX_FMT_YUV422P, |
1232 | .name = "Planar YUV422 16 bit", | |
1233 | .bits_per_sample = 8, | |
1234 | .packing = SOC_MBUS_PACKING_2X8_PADHI, | |
1235 | .order = SOC_MBUS_ORDER_LE, | |
2a48fc73 RJ |
1236 | }, |
1237 | }; | |
1238 | ||
760697be GL |
1239 | /* This will be corrected as we get more formats */ |
1240 | static bool pxa_camera_packing_supported(const struct soc_mbus_pixelfmt *fmt) | |
ad5f2e85 | 1241 | { |
760697be GL |
1242 | return fmt->packing == SOC_MBUS_PACKING_NONE || |
1243 | (fmt->bits_per_sample == 8 && | |
1244 | fmt->packing == SOC_MBUS_PACKING_2X8_PADHI) || | |
1245 | (fmt->bits_per_sample > 8 && | |
1246 | fmt->packing == SOC_MBUS_PACKING_EXTEND16); | |
2a48fc73 RJ |
1247 | } |
1248 | ||
1249 | static int pxa_camera_get_formats(struct soc_camera_device *icd, int idx, | |
1250 | struct soc_camera_format_xlate *xlate) | |
1251 | { | |
760697be | 1252 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
0166b743 | 1253 | struct device *dev = icd->dev.parent; |
760697be | 1254 | int formats = 0, ret; |
6a6c8786 | 1255 | struct pxa_cam *cam; |
760697be GL |
1256 | enum v4l2_mbus_pixelcode code; |
1257 | const struct soc_mbus_pixelfmt *fmt; | |
2a48fc73 | 1258 | |
760697be GL |
1259 | ret = v4l2_subdev_call(sd, video, enum_mbus_fmt, idx, &code); |
1260 | if (ret < 0) | |
1261 | /* No more formats */ | |
1262 | return 0; | |
2a48fc73 | 1263 | |
760697be GL |
1264 | fmt = soc_mbus_get_fmtdesc(code); |
1265 | if (!fmt) { | |
1266 | dev_err(dev, "Invalid format code #%d: %d\n", idx, code); | |
2a48fc73 | 1267 | return 0; |
760697be | 1268 | } |
3bc43840 | 1269 | |
760697be GL |
1270 | /* This also checks support for the requested bits-per-sample */ |
1271 | ret = pxa_camera_try_bus_param(icd, fmt->bits_per_sample); | |
2a48fc73 RJ |
1272 | if (ret < 0) |
1273 | return 0; | |
1274 | ||
6a6c8786 GL |
1275 | if (!icd->host_priv) { |
1276 | cam = kzalloc(sizeof(*cam), GFP_KERNEL); | |
1277 | if (!cam) | |
1278 | return -ENOMEM; | |
1279 | ||
1280 | icd->host_priv = cam; | |
1281 | } else { | |
1282 | cam = icd->host_priv; | |
1283 | } | |
1284 | ||
760697be GL |
1285 | switch (code) { |
1286 | case V4L2_MBUS_FMT_YUYV8_2X8_BE: | |
2a48fc73 RJ |
1287 | formats++; |
1288 | if (xlate) { | |
760697be GL |
1289 | xlate->host_fmt = &pxa_camera_formats[0]; |
1290 | xlate->code = code; | |
2a48fc73 | 1291 | xlate++; |
760697be GL |
1292 | dev_dbg(dev, "Providing format %s using code %d\n", |
1293 | pxa_camera_formats[0].name, code); | |
2a48fc73 | 1294 | } |
760697be GL |
1295 | case V4L2_MBUS_FMT_YVYU8_2X8_BE: |
1296 | case V4L2_MBUS_FMT_YUYV8_2X8_LE: | |
1297 | case V4L2_MBUS_FMT_YVYU8_2X8_LE: | |
1298 | case V4L2_MBUS_FMT_RGB565_2X8_LE: | |
1299 | case V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE: | |
1300 | if (xlate) | |
0166b743 | 1301 | dev_dbg(dev, "Providing format %s packed\n", |
760697be | 1302 | fmt->name); |
2a48fc73 RJ |
1303 | break; |
1304 | default: | |
760697be GL |
1305 | if (!pxa_camera_packing_supported(fmt)) |
1306 | return 0; | |
1307 | if (xlate) | |
0166b743 | 1308 | dev_dbg(dev, |
2a48fc73 | 1309 | "Providing format %s in pass-through mode\n", |
760697be GL |
1310 | fmt->name); |
1311 | } | |
1312 | ||
1313 | /* Generic pass-through */ | |
1314 | formats++; | |
1315 | if (xlate) { | |
1316 | xlate->host_fmt = fmt; | |
1317 | xlate->code = code; | |
1318 | xlate++; | |
2a48fc73 RJ |
1319 | } |
1320 | ||
1321 | return formats; | |
1322 | } | |
1323 | ||
6a6c8786 GL |
1324 | static void pxa_camera_put_formats(struct soc_camera_device *icd) |
1325 | { | |
1326 | kfree(icd->host_priv); | |
1327 | icd->host_priv = NULL; | |
1328 | } | |
1329 | ||
760697be | 1330 | static int pxa_camera_check_frame(u32 width, u32 height) |
6a6c8786 GL |
1331 | { |
1332 | /* limit to pxa hardware capabilities */ | |
760697be GL |
1333 | return height < 32 || height > 2048 || width < 48 || width > 2048 || |
1334 | (width & 0x01); | |
6a6c8786 GL |
1335 | } |
1336 | ||
09e231b3 | 1337 | static int pxa_camera_set_crop(struct soc_camera_device *icd, |
08590b96 | 1338 | struct v4l2_crop *a) |
09e231b3 | 1339 | { |
08590b96 | 1340 | struct v4l2_rect *rect = &a->c; |
09e231b3 GL |
1341 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
1342 | struct pxa_camera_dev *pcdev = ici->priv; | |
0166b743 | 1343 | struct device *dev = icd->dev.parent; |
c9c1f1c0 | 1344 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
09e231b3 GL |
1345 | struct soc_camera_sense sense = { |
1346 | .master_clock = pcdev->mclk, | |
1347 | .pixel_clock_max = pcdev->ciclk / 4, | |
1348 | }; | |
760697be | 1349 | struct v4l2_mbus_framefmt mf; |
6a6c8786 | 1350 | struct pxa_cam *cam = icd->host_priv; |
760697be | 1351 | u32 fourcc = icd->current_fmt->host_fmt->fourcc; |
09e231b3 GL |
1352 | int ret; |
1353 | ||
1354 | /* If PCLK is used to latch data from the sensor, check sense */ | |
1355 | if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) | |
1356 | icd->sense = &sense; | |
1357 | ||
08590b96 | 1358 | ret = v4l2_subdev_call(sd, video, s_crop, a); |
09e231b3 GL |
1359 | |
1360 | icd->sense = NULL; | |
1361 | ||
1362 | if (ret < 0) { | |
0166b743 | 1363 | dev_warn(dev, "Failed to crop to %ux%u@%u:%u\n", |
09e231b3 | 1364 | rect->width, rect->height, rect->left, rect->top); |
6a6c8786 GL |
1365 | return ret; |
1366 | } | |
1367 | ||
760697be | 1368 | ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf); |
6a6c8786 GL |
1369 | if (ret < 0) |
1370 | return ret; | |
1371 | ||
760697be | 1372 | if (pxa_camera_check_frame(mf.width, mf.height)) { |
6a6c8786 GL |
1373 | /* |
1374 | * Camera cropping produced a frame beyond our capabilities. | |
1375 | * FIXME: just extract a subframe, that we can process. | |
1376 | */ | |
760697be GL |
1377 | v4l_bound_align_image(&mf.width, 48, 2048, 1, |
1378 | &mf.height, 32, 2048, 0, | |
1379 | fourcc == V4L2_PIX_FMT_YUV422P ? 4 : 0); | |
1380 | ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf); | |
6a6c8786 GL |
1381 | if (ret < 0) |
1382 | return ret; | |
1383 | ||
760697be | 1384 | if (pxa_camera_check_frame(mf.width, mf.height)) { |
6a6c8786 GL |
1385 | dev_warn(icd->dev.parent, |
1386 | "Inconsistent state. Use S_FMT to repair\n"); | |
1387 | return -EINVAL; | |
1388 | } | |
1389 | } | |
1390 | ||
1391 | if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) { | |
09e231b3 | 1392 | if (sense.pixel_clock > sense.pixel_clock_max) { |
0166b743 | 1393 | dev_err(dev, |
09e231b3 GL |
1394 | "pixel clock %lu set by the camera too high!", |
1395 | sense.pixel_clock); | |
1396 | return -EIO; | |
1397 | } | |
1398 | recalculate_fifo_timeout(pcdev, sense.pixel_clock); | |
1399 | } | |
1400 | ||
760697be GL |
1401 | icd->user_width = mf.width; |
1402 | icd->user_height = mf.height; | |
6a6c8786 | 1403 | |
760697be | 1404 | pxa_camera_setup_cicr(icd, cam->flags, fourcc); |
6a6c8786 | 1405 | |
09e231b3 GL |
1406 | return ret; |
1407 | } | |
1408 | ||
d8fac217 | 1409 | static int pxa_camera_set_fmt(struct soc_camera_device *icd, |
09e231b3 | 1410 | struct v4l2_format *f) |
ad5f2e85 | 1411 | { |
2a48fc73 | 1412 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
cf34cba7 | 1413 | struct pxa_camera_dev *pcdev = ici->priv; |
0166b743 | 1414 | struct device *dev = icd->dev.parent; |
c9c1f1c0 | 1415 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
0ad675eb | 1416 | const struct soc_camera_format_xlate *xlate = NULL; |
cf34cba7 GL |
1417 | struct soc_camera_sense sense = { |
1418 | .master_clock = pcdev->mclk, | |
1419 | .pixel_clock_max = pcdev->ciclk / 4, | |
1420 | }; | |
09e231b3 | 1421 | struct v4l2_pix_format *pix = &f->fmt.pix; |
760697be | 1422 | struct v4l2_mbus_framefmt mf; |
0ad675eb | 1423 | int ret; |
25c4d74e | 1424 | |
09e231b3 GL |
1425 | xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat); |
1426 | if (!xlate) { | |
0166b743 | 1427 | dev_warn(dev, "Format %x not found\n", pix->pixelformat); |
09e231b3 | 1428 | return -EINVAL; |
0ad675eb | 1429 | } |
2a48fc73 | 1430 | |
cf34cba7 GL |
1431 | /* If PCLK is used to latch data from the sensor, check sense */ |
1432 | if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) | |
760697be | 1433 | /* The caller holds a mutex. */ |
cf34cba7 GL |
1434 | icd->sense = &sense; |
1435 | ||
760697be GL |
1436 | mf.width = pix->width; |
1437 | mf.height = pix->height; | |
1438 | mf.field = pix->field; | |
1439 | mf.colorspace = pix->colorspace; | |
1440 | mf.code = xlate->code; | |
1441 | ||
1442 | ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf); | |
1443 | ||
1444 | if (mf.code != xlate->code) | |
1445 | return -EINVAL; | |
2a48fc73 | 1446 | |
cf34cba7 GL |
1447 | icd->sense = NULL; |
1448 | ||
1449 | if (ret < 0) { | |
0166b743 | 1450 | dev_warn(dev, "Failed to configure for format %x\n", |
09e231b3 | 1451 | pix->pixelformat); |
760697be | 1452 | } else if (pxa_camera_check_frame(mf.width, mf.height)) { |
6a6c8786 GL |
1453 | dev_warn(dev, |
1454 | "Camera driver produced an unsupported frame %dx%d\n", | |
760697be | 1455 | mf.width, mf.height); |
6a6c8786 | 1456 | ret = -EINVAL; |
cf34cba7 GL |
1457 | } else if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) { |
1458 | if (sense.pixel_clock > sense.pixel_clock_max) { | |
0166b743 | 1459 | dev_err(dev, |
cf34cba7 GL |
1460 | "pixel clock %lu set by the camera too high!", |
1461 | sense.pixel_clock); | |
1462 | return -EIO; | |
1463 | } | |
1464 | recalculate_fifo_timeout(pcdev, sense.pixel_clock); | |
1465 | } | |
2a48fc73 | 1466 | |
760697be GL |
1467 | if (ret < 0) |
1468 | return ret; | |
1469 | ||
1470 | pix->width = mf.width; | |
1471 | pix->height = mf.height; | |
1472 | pix->field = mf.field; | |
1473 | pix->colorspace = mf.colorspace; | |
1474 | icd->current_fmt = xlate; | |
25c4d74e GL |
1475 | |
1476 | return ret; | |
ad5f2e85 GL |
1477 | } |
1478 | ||
d8fac217 GL |
1479 | static int pxa_camera_try_fmt(struct soc_camera_device *icd, |
1480 | struct v4l2_format *f) | |
3bc43840 | 1481 | { |
c9c1f1c0 | 1482 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
2a48fc73 RJ |
1483 | const struct soc_camera_format_xlate *xlate; |
1484 | struct v4l2_pix_format *pix = &f->fmt.pix; | |
760697be | 1485 | struct v4l2_mbus_framefmt mf; |
2a48fc73 | 1486 | __u32 pixfmt = pix->pixelformat; |
bf507158 | 1487 | int ret; |
a2c8c68c | 1488 | |
2a48fc73 RJ |
1489 | xlate = soc_camera_xlate_by_fourcc(icd, pixfmt); |
1490 | if (!xlate) { | |
760697be | 1491 | dev_warn(icd->dev.parent, "Format %x not found\n", pixfmt); |
25c4d74e | 1492 | return -EINVAL; |
2a48fc73 | 1493 | } |
25c4d74e | 1494 | |
92a8337b | 1495 | /* |
4a6b8df2 TP |
1496 | * Limit to pxa hardware capabilities. YUV422P planar format requires |
1497 | * images size to be a multiple of 16 bytes. If not, zeros will be | |
1498 | * inserted between Y and U planes, and U and V planes, which violates | |
1499 | * the YUV422P standard. | |
92a8337b | 1500 | */ |
4a6b8df2 TP |
1501 | v4l_bound_align_image(&pix->width, 48, 2048, 1, |
1502 | &pix->height, 32, 2048, 0, | |
6a6c8786 | 1503 | pixfmt == V4L2_PIX_FMT_YUV422P ? 4 : 0); |
92a8337b | 1504 | |
760697be GL |
1505 | pix->bytesperline = soc_mbus_bytes_per_line(pix->width, |
1506 | xlate->host_fmt); | |
1507 | if (pix->bytesperline < 0) | |
1508 | return pix->bytesperline; | |
2a48fc73 | 1509 | pix->sizeimage = pix->height * pix->bytesperline; |
25c4d74e | 1510 | |
ad5f2e85 | 1511 | /* limit to sensor capabilities */ |
760697be GL |
1512 | mf.width = pix->width; |
1513 | mf.height = pix->height; | |
1514 | mf.field = pix->field; | |
1515 | mf.colorspace = pix->colorspace; | |
1516 | mf.code = xlate->code; | |
bf507158 | 1517 | |
760697be GL |
1518 | ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf); |
1519 | if (ret < 0) | |
1520 | return ret; | |
06daa1af | 1521 | |
760697be GL |
1522 | pix->width = mf.width; |
1523 | pix->height = mf.height; | |
1524 | pix->colorspace = mf.colorspace; | |
1525 | ||
1526 | switch (mf.field) { | |
1527 | case V4L2_FIELD_ANY: | |
1528 | case V4L2_FIELD_NONE: | |
1529 | pix->field = V4L2_FIELD_NONE; | |
1530 | break; | |
1531 | default: | |
1532 | /* TODO: support interlaced at least in pass-through mode */ | |
1533 | dev_err(icd->dev.parent, "Field type %d unsupported.\n", | |
1534 | mf.field); | |
06daa1af GL |
1535 | return -EINVAL; |
1536 | } | |
1537 | ||
bf507158 | 1538 | return ret; |
3bc43840 GL |
1539 | } |
1540 | ||
7102b773 GL |
1541 | static int pxa_camera_reqbufs(struct soc_camera_file *icf, |
1542 | struct v4l2_requestbuffers *p) | |
3bc43840 GL |
1543 | { |
1544 | int i; | |
1545 | ||
5d28d525 GL |
1546 | /* |
1547 | * This is for locking debugging only. I removed spinlocks and now I | |
3bc43840 GL |
1548 | * check whether .prepare is ever called on a linked buffer, or whether |
1549 | * a dma IRQ can occur for an in-work or unlinked buffer. Until now | |
5d28d525 GL |
1550 | * it hadn't triggered |
1551 | */ | |
3bc43840 GL |
1552 | for (i = 0; i < p->count; i++) { |
1553 | struct pxa_buffer *buf = container_of(icf->vb_vidq.bufs[i], | |
1554 | struct pxa_buffer, vb); | |
1555 | buf->inwork = 0; | |
1556 | INIT_LIST_HEAD(&buf->vb.queue); | |
1557 | } | |
1558 | ||
1559 | return 0; | |
1560 | } | |
1561 | ||
7102b773 | 1562 | static unsigned int pxa_camera_poll(struct file *file, poll_table *pt) |
3bc43840 GL |
1563 | { |
1564 | struct soc_camera_file *icf = file->private_data; | |
1565 | struct pxa_buffer *buf; | |
1566 | ||
1567 | buf = list_entry(icf->vb_vidq.stream.next, struct pxa_buffer, | |
1568 | vb.stream); | |
1569 | ||
1570 | poll_wait(file, &buf->vb.done, pt); | |
1571 | ||
1572 | if (buf->vb.state == VIDEOBUF_DONE || | |
1573 | buf->vb.state == VIDEOBUF_ERROR) | |
1574 | return POLLIN|POLLRDNORM; | |
1575 | ||
1576 | return 0; | |
1577 | } | |
1578 | ||
7102b773 GL |
1579 | static int pxa_camera_querycap(struct soc_camera_host *ici, |
1580 | struct v4l2_capability *cap) | |
3bc43840 GL |
1581 | { |
1582 | /* cap->name is set by the firendly caller:-> */ | |
1583 | strlcpy(cap->card, pxa_cam_driver_description, sizeof(cap->card)); | |
1584 | cap->version = PXA_CAM_VERSION_CODE; | |
1585 | cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; | |
1586 | ||
1587 | return 0; | |
1588 | } | |
1589 | ||
3f6ac497 RJ |
1590 | static int pxa_camera_suspend(struct soc_camera_device *icd, pm_message_t state) |
1591 | { | |
64f5905e | 1592 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
3f6ac497 RJ |
1593 | struct pxa_camera_dev *pcdev = ici->priv; |
1594 | int i = 0, ret = 0; | |
1595 | ||
5ca11fa3 EM |
1596 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0); |
1597 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1); | |
1598 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2); | |
1599 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3); | |
1600 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4); | |
3f6ac497 RJ |
1601 | |
1602 | if ((pcdev->icd) && (pcdev->icd->ops->suspend)) | |
1603 | ret = pcdev->icd->ops->suspend(pcdev->icd, state); | |
1604 | ||
1605 | return ret; | |
1606 | } | |
1607 | ||
1608 | static int pxa_camera_resume(struct soc_camera_device *icd) | |
1609 | { | |
64f5905e | 1610 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
3f6ac497 RJ |
1611 | struct pxa_camera_dev *pcdev = ici->priv; |
1612 | int i = 0, ret = 0; | |
1613 | ||
87f3dd77 EM |
1614 | DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD; |
1615 | DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD; | |
1616 | DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD; | |
3f6ac497 | 1617 | |
5ca11fa3 EM |
1618 | __raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0); |
1619 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1); | |
1620 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2); | |
1621 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3); | |
1622 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4); | |
3f6ac497 RJ |
1623 | |
1624 | if ((pcdev->icd) && (pcdev->icd->ops->resume)) | |
1625 | ret = pcdev->icd->ops->resume(pcdev->icd); | |
1626 | ||
1627 | /* Restart frame capture if active buffer exists */ | |
256b0233 RJ |
1628 | if (!ret && pcdev->active) |
1629 | pxa_camera_start_capture(pcdev); | |
3f6ac497 RJ |
1630 | |
1631 | return ret; | |
1632 | } | |
1633 | ||
b8d9904c GL |
1634 | static struct soc_camera_host_ops pxa_soc_camera_host_ops = { |
1635 | .owner = THIS_MODULE, | |
1636 | .add = pxa_camera_add_device, | |
1637 | .remove = pxa_camera_remove_device, | |
3f6ac497 RJ |
1638 | .suspend = pxa_camera_suspend, |
1639 | .resume = pxa_camera_resume, | |
09e231b3 | 1640 | .set_crop = pxa_camera_set_crop, |
2a48fc73 | 1641 | .get_formats = pxa_camera_get_formats, |
6a6c8786 | 1642 | .put_formats = pxa_camera_put_formats, |
d8fac217 GL |
1643 | .set_fmt = pxa_camera_set_fmt, |
1644 | .try_fmt = pxa_camera_try_fmt, | |
092d3921 | 1645 | .init_videobuf = pxa_camera_init_videobuf, |
b8d9904c GL |
1646 | .reqbufs = pxa_camera_reqbufs, |
1647 | .poll = pxa_camera_poll, | |
1648 | .querycap = pxa_camera_querycap, | |
b8d9904c GL |
1649 | .set_bus_param = pxa_camera_set_bus_param, |
1650 | }; | |
1651 | ||
e36bc31f | 1652 | static int __devinit pxa_camera_probe(struct platform_device *pdev) |
3bc43840 GL |
1653 | { |
1654 | struct pxa_camera_dev *pcdev; | |
1655 | struct resource *res; | |
1656 | void __iomem *base; | |
02da4659 | 1657 | int irq; |
3bc43840 GL |
1658 | int err = 0; |
1659 | ||
1660 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1661 | irq = platform_get_irq(pdev, 0); | |
02da4659 | 1662 | if (!res || irq < 0) { |
3bc43840 GL |
1663 | err = -ENODEV; |
1664 | goto exit; | |
1665 | } | |
1666 | ||
1667 | pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL); | |
1668 | if (!pcdev) { | |
7102b773 | 1669 | dev_err(&pdev->dev, "Could not allocate pcdev\n"); |
3bc43840 GL |
1670 | err = -ENOMEM; |
1671 | goto exit; | |
1672 | } | |
1673 | ||
e0d8b13a | 1674 | pcdev->clk = clk_get(&pdev->dev, NULL); |
3bc43840 GL |
1675 | if (IS_ERR(pcdev->clk)) { |
1676 | err = PTR_ERR(pcdev->clk); | |
1677 | goto exit_kfree; | |
1678 | } | |
1679 | ||
3bc43840 GL |
1680 | pcdev->res = res; |
1681 | ||
1682 | pcdev->pdata = pdev->dev.platform_data; | |
1683 | pcdev->platform_flags = pcdev->pdata->flags; | |
ad5f2e85 GL |
1684 | if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 | |
1685 | PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) { | |
5d28d525 GL |
1686 | /* |
1687 | * Platform hasn't set available data widths. This is bad. | |
1688 | * Warn and use a default. | |
1689 | */ | |
3bc43840 GL |
1690 | dev_warn(&pdev->dev, "WARNING! Platform hasn't set available " |
1691 | "data widths, using default 10 bit\n"); | |
1692 | pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10; | |
1693 | } | |
cf34cba7 GL |
1694 | pcdev->mclk = pcdev->pdata->mclk_10khz * 10000; |
1695 | if (!pcdev->mclk) { | |
3bc43840 | 1696 | dev_warn(&pdev->dev, |
cf34cba7 | 1697 | "mclk == 0! Please, fix your platform data. " |
3bc43840 | 1698 | "Using default 20MHz\n"); |
cf34cba7 | 1699 | pcdev->mclk = 20000000; |
3bc43840 GL |
1700 | } |
1701 | ||
40e2e092 | 1702 | pcdev->mclk_divisor = mclk_get_divisor(pdev, pcdev); |
cf34cba7 | 1703 | |
3bc43840 GL |
1704 | INIT_LIST_HEAD(&pcdev->capture); |
1705 | spin_lock_init(&pcdev->lock); | |
1706 | ||
1707 | /* | |
1708 | * Request the regions. | |
1709 | */ | |
eb6c8558 | 1710 | if (!request_mem_region(res->start, resource_size(res), |
3bc43840 GL |
1711 | PXA_CAM_DRV_NAME)) { |
1712 | err = -EBUSY; | |
1713 | goto exit_clk; | |
1714 | } | |
1715 | ||
eb6c8558 | 1716 | base = ioremap(res->start, resource_size(res)); |
3bc43840 GL |
1717 | if (!base) { |
1718 | err = -ENOMEM; | |
1719 | goto exit_release; | |
1720 | } | |
1721 | pcdev->irq = irq; | |
1722 | pcdev->base = base; | |
3bc43840 GL |
1723 | |
1724 | /* request dma */ | |
de3e3b82 | 1725 | err = pxa_request_dma("CI_Y", DMA_PRIO_HIGH, |
1726 | pxa_camera_dma_irq_y, pcdev); | |
1727 | if (err < 0) { | |
eff505fa | 1728 | dev_err(&pdev->dev, "Can't request DMA for Y\n"); |
3bc43840 GL |
1729 | goto exit_iounmap; |
1730 | } | |
de3e3b82 | 1731 | pcdev->dma_chans[0] = err; |
eff505fa | 1732 | dev_dbg(&pdev->dev, "got DMA channel %d\n", pcdev->dma_chans[0]); |
a5462e5b | 1733 | |
de3e3b82 | 1734 | err = pxa_request_dma("CI_U", DMA_PRIO_HIGH, |
1735 | pxa_camera_dma_irq_u, pcdev); | |
1736 | if (err < 0) { | |
eff505fa | 1737 | dev_err(&pdev->dev, "Can't request DMA for U\n"); |
a5462e5b MR |
1738 | goto exit_free_dma_y; |
1739 | } | |
de3e3b82 | 1740 | pcdev->dma_chans[1] = err; |
eff505fa | 1741 | dev_dbg(&pdev->dev, "got DMA channel (U) %d\n", pcdev->dma_chans[1]); |
a5462e5b | 1742 | |
de3e3b82 | 1743 | err = pxa_request_dma("CI_V", DMA_PRIO_HIGH, |
1744 | pxa_camera_dma_irq_v, pcdev); | |
1745 | if (err < 0) { | |
eff505fa | 1746 | dev_err(&pdev->dev, "Can't request DMA for V\n"); |
a5462e5b MR |
1747 | goto exit_free_dma_u; |
1748 | } | |
de3e3b82 | 1749 | pcdev->dma_chans[2] = err; |
eff505fa | 1750 | dev_dbg(&pdev->dev, "got DMA channel (V) %d\n", pcdev->dma_chans[2]); |
3bc43840 | 1751 | |
87f3dd77 EM |
1752 | DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD; |
1753 | DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD; | |
1754 | DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD; | |
3bc43840 GL |
1755 | |
1756 | /* request irq */ | |
1757 | err = request_irq(pcdev->irq, pxa_camera_irq, 0, PXA_CAM_DRV_NAME, | |
1758 | pcdev); | |
1759 | if (err) { | |
eff505fa | 1760 | dev_err(&pdev->dev, "Camera interrupt register failed \n"); |
3bc43840 GL |
1761 | goto exit_free_dma; |
1762 | } | |
1763 | ||
eb6c8558 GL |
1764 | pcdev->soc_host.drv_name = PXA_CAM_DRV_NAME; |
1765 | pcdev->soc_host.ops = &pxa_soc_camera_host_ops; | |
1766 | pcdev->soc_host.priv = pcdev; | |
979ea1dd | 1767 | pcdev->soc_host.v4l2_dev.dev = &pdev->dev; |
eb6c8558 | 1768 | pcdev->soc_host.nr = pdev->id; |
eff505fa | 1769 | |
eb6c8558 | 1770 | err = soc_camera_host_register(&pcdev->soc_host); |
3bc43840 GL |
1771 | if (err) |
1772 | goto exit_free_irq; | |
1773 | ||
1774 | return 0; | |
1775 | ||
1776 | exit_free_irq: | |
1777 | free_irq(pcdev->irq, pcdev); | |
1778 | exit_free_dma: | |
a5462e5b MR |
1779 | pxa_free_dma(pcdev->dma_chans[2]); |
1780 | exit_free_dma_u: | |
1781 | pxa_free_dma(pcdev->dma_chans[1]); | |
1782 | exit_free_dma_y: | |
1783 | pxa_free_dma(pcdev->dma_chans[0]); | |
3bc43840 GL |
1784 | exit_iounmap: |
1785 | iounmap(base); | |
1786 | exit_release: | |
eb6c8558 | 1787 | release_mem_region(res->start, resource_size(res)); |
3bc43840 GL |
1788 | exit_clk: |
1789 | clk_put(pcdev->clk); | |
1790 | exit_kfree: | |
1791 | kfree(pcdev); | |
1792 | exit: | |
1793 | return err; | |
1794 | } | |
1795 | ||
1796 | static int __devexit pxa_camera_remove(struct platform_device *pdev) | |
1797 | { | |
eff505fa GL |
1798 | struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev); |
1799 | struct pxa_camera_dev *pcdev = container_of(soc_host, | |
1800 | struct pxa_camera_dev, soc_host); | |
3bc43840 GL |
1801 | struct resource *res; |
1802 | ||
1803 | clk_put(pcdev->clk); | |
1804 | ||
a5462e5b MR |
1805 | pxa_free_dma(pcdev->dma_chans[0]); |
1806 | pxa_free_dma(pcdev->dma_chans[1]); | |
1807 | pxa_free_dma(pcdev->dma_chans[2]); | |
3bc43840 GL |
1808 | free_irq(pcdev->irq, pcdev); |
1809 | ||
eff505fa | 1810 | soc_camera_host_unregister(soc_host); |
3bc43840 GL |
1811 | |
1812 | iounmap(pcdev->base); | |
1813 | ||
1814 | res = pcdev->res; | |
eb6c8558 | 1815 | release_mem_region(res->start, resource_size(res)); |
3bc43840 GL |
1816 | |
1817 | kfree(pcdev); | |
1818 | ||
7102b773 | 1819 | dev_info(&pdev->dev, "PXA Camera driver unloaded\n"); |
3bc43840 | 1820 | |
3bc43840 GL |
1821 | return 0; |
1822 | } | |
1823 | ||
3bc43840 GL |
1824 | static struct platform_driver pxa_camera_driver = { |
1825 | .driver = { | |
1826 | .name = PXA_CAM_DRV_NAME, | |
1827 | }, | |
1828 | .probe = pxa_camera_probe, | |
e36bc31f | 1829 | .remove = __devexit_p(pxa_camera_remove), |
3bc43840 GL |
1830 | }; |
1831 | ||
1832 | ||
e36bc31f | 1833 | static int __init pxa_camera_init(void) |
3bc43840 GL |
1834 | { |
1835 | return platform_driver_register(&pxa_camera_driver); | |
1836 | } | |
1837 | ||
1838 | static void __exit pxa_camera_exit(void) | |
1839 | { | |
01c1e4ca | 1840 | platform_driver_unregister(&pxa_camera_driver); |
3bc43840 GL |
1841 | } |
1842 | ||
1843 | module_init(pxa_camera_init); | |
1844 | module_exit(pxa_camera_exit); | |
1845 | ||
1846 | MODULE_DESCRIPTION("PXA27x SoC Camera Host driver"); | |
1847 | MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>"); | |
1848 | MODULE_LICENSE("GPL"); | |
40e2e092 | 1849 | MODULE_ALIAS("platform:" PXA_CAM_DRV_NAME); |