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V4L/DVB (8337): soc_camera: make videobuf independent
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / media / video / pxa_camera.c
CommitLineData
3bc43840
GL		 1/*
2 * V4L2 Driver for PXA camera host
3 *
4 * Copyright (C) 2006, Sascha Hauer, Pengutronix
5 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
3bc43840
GL		 13#include <linux/init.h>
14#include <linux/module.h>
7102b773 15#include <linux/io.h>
3bc43840
GL		 16#include <linux/delay.h>
17#include <linux/dma-mapping.h>
18#include <linux/errno.h>
19#include <linux/fs.h>
20#include <linux/interrupt.h>
21#include <linux/kernel.h>
22#include <linux/mm.h>
23#include <linux/moduleparam.h>
24#include <linux/time.h>
25#include <linux/version.h>
26#include <linux/device.h>
27#include <linux/platform_device.h>
28#include <linux/mutex.h>
29#include <linux/clk.h>
30
31#include <media/v4l2-common.h>
32#include <media/v4l2-dev.h>
092d3921 33#include <media/videobuf-dma-sg.h>
3bc43840
GL		 34#include <media/soc_camera.h>
35
36#include <linux/videodev2.h>
37
38#include <asm/dma.h>
39#include <asm/arch/pxa-regs.h>
40#include <asm/arch/camera.h>
41
42#define PXA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5)
43#define PXA_CAM_DRV_NAME "pxa27x-camera"
44
7102b773
GL		 45#define CICR0_SIM_MP (0 << 24)
46#define CICR0_SIM_SP (1 << 24)
47#define CICR0_SIM_MS (2 << 24)
48#define CICR0_SIM_EP (3 << 24)
49#define CICR0_SIM_ES (4 << 24)
50
51#define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */
52#define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */
a5462e5b
MR		 53#define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */
54#define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */
55#define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */
7102b773
GL		 56
57#define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */
58#define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */
59#define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */
60#define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */
61#define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */
62
63#define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */
64#define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */
65#define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */
66#define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */
67
3bc43840
GL		 68#define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \
69 CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \
70 CICR0_EOFM | CICR0_FOM)
71
72static DEFINE_MUTEX(camera_lock);
73
74/*
75 * Structures
76 */
a5462e5b
MR		 77enum pxa_camera_active_dma {
78 DMA_Y = 0x1,
79 DMA_U = 0x2,
80 DMA_V = 0x4,
81};
82
83/* descriptor needed for the PXA DMA engine */
84struct pxa_cam_dma {
85 dma_addr_t sg_dma;
86 struct pxa_dma_desc *sg_cpu;
87 size_t sg_size;
88 int sglen;
89};
3bc43840
GL		 90
91/* buffer for one video frame */
92struct pxa_buffer {
93 /* common v4l buffer stuff -- must be first */
94 struct videobuf_buffer vb;
95
96 const struct soc_camera_data_format *fmt;
97
a5462e5b
MR		 98 /* our descriptor lists for Y, U and V channels */
99 struct pxa_cam_dma dmas[3];
100
3bc43840 101 int inwork;
a5462e5b
MR		 102
103 enum pxa_camera_active_dma active_dma;
3bc43840
GL		 104};
105
3bc43840
GL		 106struct pxa_camera_dev {
107 struct device *dev;
108 /* PXA27x is only supposed to handle one camera on its Quick Capture
109 * interface. If anyone ever builds hardware to enable more than
110 * one camera, they will have to modify this driver too */
111 struct soc_camera_device *icd;
112 struct clk *clk;
113
114 unsigned int irq;
115 void __iomem *base;
a5462e5b 116
e7c50688 117 int channels;
a5462e5b 118 unsigned int dma_chans[3];
3bc43840 119
3bc43840
GL		 120 struct pxacamera_platform_data *pdata;
121 struct resource *res;
122 unsigned long platform_flags;
123 unsigned long platform_mclk_10khz;
124
125 struct list_head capture;
126
127 spinlock_t lock;
128
3bc43840 129 struct pxa_buffer *active;
5aa2110f 130 struct pxa_dma_desc *sg_tail[3];
3bc43840
GL		 131};
132
133static const char *pxa_cam_driver_description = "PXA_Camera";
134
135static unsigned int vid_limit = 16; /* Video memory limit, in Mb */
136
137/*
138 * Videobuf operations
139 */
7102b773
GL		 140static int pxa_videobuf_setup(struct videobuf_queue *vq, unsigned int *count,
141 unsigned int *size)
3bc43840
GL		 142{
143 struct soc_camera_device *icd = vq->priv_data;
5aa2110f
GL		 144 struct soc_camera_host *ici =
145 to_soc_camera_host(icd->dev.parent);
146 struct pxa_camera_dev *pcdev = ici->priv;
3bc43840
GL		 147
148 dev_dbg(&icd->dev, "count=%d, size=%d\n", *count, *size);
149
a5462e5b 150 /* planar capture requires Y, U and V buffers to be page aligned */
5aa2110f 151 if (pcdev->channels == 3) {
a5462e5b
MR		 152 *size = PAGE_ALIGN(icd->width * icd->height); /* Y pages */
153 *size += PAGE_ALIGN(icd->width * icd->height / 2); /* U pages */
154 *size += PAGE_ALIGN(icd->width * icd->height / 2); /* V pages */
155 } else {
156 *size = icd->width * icd->height *
157 ((icd->current_fmt->depth + 7) >> 3);
158 }
3bc43840
GL		 159
160 if (0 == *count)
161 *count = 32;
162 while (*size * *count > vid_limit * 1024 * 1024)
163 (*count)--;
164
165 return 0;
166}
167
168static void free_buffer(struct videobuf_queue *vq, struct pxa_buffer *buf)
169{
170 struct soc_camera_device *icd = vq->priv_data;
171 struct soc_camera_host *ici =
172 to_soc_camera_host(icd->dev.parent);
173 struct pxa_camera_dev *pcdev = ici->priv;
174 struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
a5462e5b 175 int i;
3bc43840
GL		 176
177 BUG_ON(in_interrupt());
178
7e28adb2 179 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
3bc43840
GL		 180 &buf->vb, buf->vb.baddr, buf->vb.bsize);
181
182 /* This waits until this buffer is out of danger, i.e., until it is no
183 * longer in STATE_QUEUED or STATE_ACTIVE */
184 videobuf_waiton(&buf->vb, 0, 0);
185 videobuf_dma_unmap(vq, dma);
186 videobuf_dma_free(dma);
187
a5462e5b
MR		 188 for (i = 0; i < ARRAY_SIZE(buf->dmas); i++) {
189 if (buf->dmas[i].sg_cpu)
190 dma_free_coherent(pcdev->dev, buf->dmas[i].sg_size,
191 buf->dmas[i].sg_cpu,
192 buf->dmas[i].sg_dma);
193 buf->dmas[i].sg_cpu = NULL;
194 }
3bc43840
GL		 195
196 buf->vb.state = VIDEOBUF_NEEDS_INIT;
197}
198
a5462e5b
MR		 199static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev,
200 struct pxa_buffer *buf,
201 struct videobuf_dmabuf *dma, int channel,
202 int sglen, int sg_start, int cibr,
203 unsigned int size)
204{
205 struct pxa_cam_dma *pxa_dma = &buf->dmas[channel];
206 int i;
207
208 if (pxa_dma->sg_cpu)
209 dma_free_coherent(pcdev->dev, pxa_dma->sg_size,
210 pxa_dma->sg_cpu, pxa_dma->sg_dma);
211
212 pxa_dma->sg_size = (sglen + 1) * sizeof(struct pxa_dma_desc);
213 pxa_dma->sg_cpu = dma_alloc_coherent(pcdev->dev, pxa_dma->sg_size,
214 &pxa_dma->sg_dma, GFP_KERNEL);
215 if (!pxa_dma->sg_cpu)
216 return -ENOMEM;
217
218 pxa_dma->sglen = sglen;
219
220 for (i = 0; i < sglen; i++) {
221 int sg_i = sg_start + i;
222 struct scatterlist *sg = dma->sglist;
223 unsigned int dma_len = sg_dma_len(&sg[sg_i]), xfer_len;
224
225 pxa_dma->sg_cpu[i].dsadr = pcdev->res->start + cibr;
226 pxa_dma->sg_cpu[i].dtadr = sg_dma_address(&sg[sg_i]);
227
228 /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
229 xfer_len = (min(dma_len, size) + 7) & ~7;
230
231 pxa_dma->sg_cpu[i].dcmd =
232 DCMD_FLOWSRC | DCMD_BURST8 | DCMD_INCTRGADDR | xfer_len;
233 size -= dma_len;
234 pxa_dma->sg_cpu[i].ddadr =
235 pxa_dma->sg_dma + (i + 1) * sizeof(struct pxa_dma_desc);
236 }
237
238 pxa_dma->sg_cpu[sglen - 1].ddadr = DDADR_STOP;
239 pxa_dma->sg_cpu[sglen - 1].dcmd |= DCMD_ENDIRQEN;
240
241 return 0;
242}
243
7102b773
GL		 244static int pxa_videobuf_prepare(struct videobuf_queue *vq,
245 struct videobuf_buffer *vb, enum v4l2_field field)
3bc43840
GL		 246{
247 struct soc_camera_device *icd = vq->priv_data;
248 struct soc_camera_host *ici =
249 to_soc_camera_host(icd->dev.parent);
250 struct pxa_camera_dev *pcdev = ici->priv;
251 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
a5462e5b
MR		 252 int ret;
253 int sglen_y, sglen_yu = 0, sglen_u = 0, sglen_v = 0;
254 int size_y, size_u = 0, size_v = 0;
3bc43840 255
7e28adb2 256 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
3bc43840
GL		 257 vb, vb->baddr, vb->bsize);
258
259 /* Added list head initialization on alloc */
260 WARN_ON(!list_empty(&vb->queue));
261
262#ifdef DEBUG
263 /* This can be useful if you want to see if we actually fill
264 * the buffer with something */
265 memset((void *)vb->baddr, 0xaa, vb->bsize);
266#endif
267
268 BUG_ON(NULL == icd->current_fmt);
269
270 /* I think, in buf_prepare you only have to protect global data,
271 * the actual buffer is yours */
272 buf->inwork = 1;
273
274 if (buf->fmt != icd->current_fmt ||
275 vb->width != icd->width ||
276 vb->height != icd->height ||
277 vb->field != field) {
278 buf->fmt = icd->current_fmt;
279 vb->width = icd->width;
280 vb->height = icd->height;
281 vb->field = field;
282 vb->state = VIDEOBUF_NEEDS_INIT;
283 }
284
285 vb->size = vb->width * vb->height * ((buf->fmt->depth + 7) >> 3);
286 if (0 != vb->baddr && vb->bsize < vb->size) {
287 ret = -EINVAL;
288 goto out;
289 }
290
291 if (vb->state == VIDEOBUF_NEEDS_INIT) {
292 unsigned int size = vb->size;
293 struct videobuf_dmabuf *dma = videobuf_to_dma(vb);
294
295 ret = videobuf_iolock(vq, vb, NULL);
296 if (ret)
297 goto fail;
298
5aa2110f 299 if (pcdev->channels == 3) {
a5462e5b
MR		 300 /* FIXME the calculations should be more precise */
301 sglen_y = dma->sglen / 2;
302 sglen_u = sglen_v = dma->sglen / 4 + 1;
303 sglen_yu = sglen_y + sglen_u;
304 size_y = size / 2;
305 size_u = size_v = size / 4;
306 } else {
307 sglen_y = dma->sglen;
308 size_y = size;
309 }
310
311 /* init DMA for Y channel */
312 ret = pxa_init_dma_channel(pcdev, buf, dma, 0, sglen_y,
313 0, 0x28, size_y);
3bc43840 314
a5462e5b
MR		 315 if (ret) {
316 dev_err(pcdev->dev,
317 "DMA initialization for Y/RGB failed\n");
3bc43840
GL		 318 goto fail;
319 }
320
5aa2110f 321 if (pcdev->channels == 3) {
a5462e5b
MR		 322 /* init DMA for U channel */
323 ret = pxa_init_dma_channel(pcdev, buf, dma, 1, sglen_u,
324 sglen_y, 0x30, size_u);
325 if (ret) {
326 dev_err(pcdev->dev,
327 "DMA initialization for U failed\n");
328 goto fail_u;
329 }
330
331 /* init DMA for V channel */
332 ret = pxa_init_dma_channel(pcdev, buf, dma, 2, sglen_v,
333 sglen_yu, 0x38, size_v);
334 if (ret) {
335 dev_err(pcdev->dev,
336 "DMA initialization for V failed\n");
337 goto fail_v;
338 }
3bc43840 339 }
3bc43840
GL		 340
341 vb->state = VIDEOBUF_PREPARED;
342 }
343
344 buf->inwork = 0;
a5462e5b 345 buf->active_dma = DMA_Y;
5aa2110f 346 if (pcdev->channels == 3)
a5462e5b 347 buf->active_dma |= DMA_U | DMA_V;
3bc43840
GL		 348
349 return 0;
350
a5462e5b
MR		 351fail_v:
352 dma_free_coherent(pcdev->dev, buf->dmas[1].sg_size,
353 buf->dmas[1].sg_cpu, buf->dmas[1].sg_dma);
354fail_u:
355 dma_free_coherent(pcdev->dev, buf->dmas[0].sg_size,
356 buf->dmas[0].sg_cpu, buf->dmas[0].sg_dma);
3bc43840
GL		 357fail:
358 free_buffer(vq, buf);
359out:
360 buf->inwork = 0;
361 return ret;
362}
363
7102b773
GL		 364static void pxa_videobuf_queue(struct videobuf_queue *vq,
365 struct videobuf_buffer *vb)
3bc43840
GL		 366{
367 struct soc_camera_device *icd = vq->priv_data;
368 struct soc_camera_host *ici =
369 to_soc_camera_host(icd->dev.parent);
370 struct pxa_camera_dev *pcdev = ici->priv;
371 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
7102b773 372 struct pxa_buffer *active;
3bc43840 373 unsigned long flags;
5aa2110f 374 int i;
3bc43840 375
7e28adb2 376 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
3bc43840
GL		 377 vb, vb->baddr, vb->bsize);
378 spin_lock_irqsave(&pcdev->lock, flags);
379
380 list_add_tail(&vb->queue, &pcdev->capture);
381
382 vb->state = VIDEOBUF_ACTIVE;
7102b773 383 active = pcdev->active;
3bc43840 384
7102b773 385 if (!active) {
3bc43840 386 CIFR |= CIFR_RESET_F;
a5462e5b 387
5aa2110f
GL		 388 for (i = 0; i < pcdev->channels; i++) {
389 DDADR(pcdev->dma_chans[i]) = buf->dmas[i].sg_dma;
390 DCSR(pcdev->dma_chans[i]) = DCSR_RUN;
391 pcdev->sg_tail[i] = buf->dmas[i].sg_cpu + buf->dmas[i].sglen - 1;
a5462e5b
MR		 392 }
393
3bc43840
GL		 394 pcdev->active = buf;
395 CICR0 |= CICR0_ENB;
396 } else {
a5462e5b
MR		 397 struct pxa_cam_dma *buf_dma;
398 struct pxa_cam_dma *act_dma;
a5462e5b 399 int nents;
a5462e5b 400
e7c50688 401 for (i = 0; i < pcdev->channels; i++) {
a5462e5b
MR		 402 buf_dma = &buf->dmas[i];
403 act_dma = &active->dmas[i];
404 nents = buf_dma->sglen;
405
406 /* Stop DMA engine */
407 DCSR(pcdev->dma_chans[i]) = 0;
408
409 /* Add the descriptors we just initialized to
410 the currently running chain */
5aa2110f
GL		 411 pcdev->sg_tail[i]->ddadr = buf_dma->sg_dma;
412 pcdev->sg_tail[i] = buf_dma->sg_cpu + buf_dma->sglen - 1;
a5462e5b
MR		 413
414 /* Setup a dummy descriptor with the DMA engines current
415 * state
3bc43840 416 */
a5462e5b
MR		 417 buf_dma->sg_cpu[nents].dsadr =
418 pcdev->res->start + 0x28 + i*8; /* CIBRx */
419 buf_dma->sg_cpu[nents].dtadr =
420 DTADR(pcdev->dma_chans[i]);
421 buf_dma->sg_cpu[nents].dcmd =
422 DCMD(pcdev->dma_chans[i]);
423
424 if (DDADR(pcdev->dma_chans[i]) == DDADR_STOP) {
425 /* The DMA engine is on the last
426 descriptor, set the next descriptors
427 address to the descriptors we just
428 initialized */
429 buf_dma->sg_cpu[nents].ddadr = buf_dma->sg_dma;
430 } else {
431 buf_dma->sg_cpu[nents].ddadr =
432 DDADR(pcdev->dma_chans[i]);
433 }
434
435 /* The next descriptor is the dummy descriptor */
436 DDADR(pcdev->dma_chans[i]) = buf_dma->sg_dma + nents *
437 sizeof(struct pxa_dma_desc);
438
439 DCSR(pcdev->dma_chans[i]) = DCSR_RUN;
3bc43840 440 }
3bc43840
GL		 441 }
442
443 spin_unlock_irqrestore(&pcdev->lock, flags);
3bc43840
GL		 444}
445
446static void pxa_videobuf_release(struct videobuf_queue *vq,
447 struct videobuf_buffer *vb)
448{
449 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
450#ifdef DEBUG
451 struct soc_camera_device *icd = vq->priv_data;
452
7e28adb2 453 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
3bc43840
GL		 454 vb, vb->baddr, vb->bsize);
455
456 switch (vb->state) {
457 case VIDEOBUF_ACTIVE:
7e28adb2 458 dev_dbg(&icd->dev, "%s (active)\n", __func__);
3bc43840
GL		 459 break;
460 case VIDEOBUF_QUEUED:
7e28adb2 461 dev_dbg(&icd->dev, "%s (queued)\n", __func__);
3bc43840
GL		 462 break;
463 case VIDEOBUF_PREPARED:
7e28adb2 464 dev_dbg(&icd->dev, "%s (prepared)\n", __func__);
3bc43840
GL		 465 break;
466 default:
7e28adb2 467 dev_dbg(&icd->dev, "%s (unknown)\n", __func__);
3bc43840
GL		 468 break;
469 }
470#endif
471
472 free_buffer(vq, buf);
473}
474
a5462e5b
MR		 475static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev,
476 struct videobuf_buffer *vb,
477 struct pxa_buffer *buf)
478{
479 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
480 list_del_init(&vb->queue);
481 vb->state = VIDEOBUF_DONE;
482 do_gettimeofday(&vb->ts);
483 vb->field_count++;
484 wake_up(&vb->done);
485
486 if (list_empty(&pcdev->capture)) {
487 pcdev->active = NULL;
488 DCSR(pcdev->dma_chans[0]) = 0;
489 DCSR(pcdev->dma_chans[1]) = 0;
490 DCSR(pcdev->dma_chans[2]) = 0;
491 CICR0 &= ~CICR0_ENB;
492 return;
493 }
494
495 pcdev->active = list_entry(pcdev->capture.next,
496 struct pxa_buffer, vb.queue);
497}
498
499static void pxa_camera_dma_irq(int channel, struct pxa_camera_dev *pcdev,
500 enum pxa_camera_active_dma act_dma)
3bc43840 501{
3bc43840
GL		 502 struct pxa_buffer *buf;
503 unsigned long flags;
e7c50688 504 u32 status, camera_status, overrun;
3bc43840
GL		 505 struct videobuf_buffer *vb;
506
507 spin_lock_irqsave(&pcdev->lock, flags);
508
a5462e5b
MR		 509 status = DCSR(channel);
510 DCSR(channel) = status | DCSR_ENDINTR;
7102b773 511
3bc43840 512 if (status & DCSR_BUSERR) {
7102b773 513 dev_err(pcdev->dev, "DMA Bus Error IRQ!\n");
3bc43840
GL		 514 goto out;
515 }
516
517 if (!(status & DCSR_ENDINTR)) {
7102b773
GL		 518 dev_err(pcdev->dev, "Unknown DMA IRQ source, "
519 "status: 0x%08x\n", status);
3bc43840
GL		 520 goto out;
521 }
522
3bc43840 523 if (!pcdev->active) {
7102b773 524 dev_err(pcdev->dev, "DMA End IRQ with no active buffer!\n");
3bc43840
GL		 525 goto out;
526 }
527
e7c50688
GL		 528 camera_status = CISR;
529 overrun = CISR_IFO_0;
530 if (pcdev->channels == 3)
531 overrun |= CISR_IFO_1 | CISR_IFO_2;
532 if (camera_status & overrun) {
533 dev_dbg(pcdev->dev, "FIFO overrun! CISR: %x\n", camera_status);
534 /* Stop the Capture Interface */
535 CICR0 &= ~CICR0_ENB;
536 /* Stop DMA */
537 DCSR(channel) = 0;
538 /* Reset the FIFOs */
539 CIFR |= CIFR_RESET_F;
540 /* Enable End-Of-Frame Interrupt */
541 CICR0 &= ~CICR0_EOFM;
542 /* Restart the Capture Interface */
543 CICR0 |= CICR0_ENB;
544 goto out;
545 }
546
3bc43840
GL		 547 vb = &pcdev->active->vb;
548 buf = container_of(vb, struct pxa_buffer, vb);
549 WARN_ON(buf->inwork || list_empty(&vb->queue));
7e28adb2 550 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
3bc43840
GL		 551 vb, vb->baddr, vb->bsize);
552
a5462e5b
MR		 553 buf->active_dma &= ~act_dma;
554 if (!buf->active_dma)
555 pxa_camera_wakeup(pcdev, vb, buf);
3bc43840
GL		 556
557out:
558 spin_unlock_irqrestore(&pcdev->lock, flags);
559}
560
a5462e5b
MR		 561static void pxa_camera_dma_irq_y(int channel, void *data)
562{
563 struct pxa_camera_dev *pcdev = data;
564 pxa_camera_dma_irq(channel, pcdev, DMA_Y);
565}
566
567static void pxa_camera_dma_irq_u(int channel, void *data)
568{
569 struct pxa_camera_dev *pcdev = data;
570 pxa_camera_dma_irq(channel, pcdev, DMA_U);
571}
572
573static void pxa_camera_dma_irq_v(int channel, void *data)
574{
575 struct pxa_camera_dev *pcdev = data;
576 pxa_camera_dma_irq(channel, pcdev, DMA_V);
577}
578
7102b773 579static struct videobuf_queue_ops pxa_videobuf_ops = {
3bc43840
GL		 580 .buf_setup = pxa_videobuf_setup,
581 .buf_prepare = pxa_videobuf_prepare,
582 .buf_queue = pxa_videobuf_queue,
583 .buf_release = pxa_videobuf_release,
584};
585
092d3921
PZ		 586static void pxa_camera_init_videobuf(struct videobuf_queue *q, spinlock_t *lock,
587 struct soc_camera_device *icd)
588{
589 /* We must pass NULL as dev pointer, then all pci_* dma operations
590 * transform to normal dma_* ones. */
591 videobuf_queue_sg_init(q, &pxa_videobuf_ops, NULL, lock,
592 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_NONE,
593 sizeof(struct pxa_buffer), icd);
594}
595
3bc43840
GL		 596static int mclk_get_divisor(struct pxa_camera_dev *pcdev)
597{
598 unsigned int mclk_10khz = pcdev->platform_mclk_10khz;
599 unsigned long div;
600 unsigned long lcdclk;
601
602 lcdclk = clk_get_rate(pcdev->clk) / 10000;
603
604 /* We verify platform_mclk_10khz != 0, so if anyone breaks it, here
605 * they get a nice Oops */
606 div = (lcdclk + 2 * mclk_10khz - 1) / (2 * mclk_10khz) - 1;
607
608 dev_dbg(pcdev->dev, "LCD clock %lukHz, target freq %dkHz, "
609 "divisor %lu\n", lcdclk * 10, mclk_10khz * 10, div);
610
611 return div;
612}
613
7102b773 614static void pxa_camera_activate(struct pxa_camera_dev *pcdev)
3bc43840
GL		 615{
616 struct pxacamera_platform_data *pdata = pcdev->pdata;
617 u32 cicr4 = 0;
618
619 dev_dbg(pcdev->dev, "Registered platform device at %p data %p\n",
620 pcdev, pdata);
621
622 if (pdata && pdata->init) {
7e28adb2 623 dev_dbg(pcdev->dev, "%s: Init gpios\n", __func__);
3bc43840
GL		 624 pdata->init(pcdev->dev);
625 }
626
627 if (pdata && pdata->power) {
7e28adb2 628 dev_dbg(pcdev->dev, "%s: Power on camera\n", __func__);
3bc43840
GL		 629 pdata->power(pcdev->dev, 1);
630 }
631
632 if (pdata && pdata->reset) {
633 dev_dbg(pcdev->dev, "%s: Releasing camera reset\n",
7e28adb2 634 __func__);
3bc43840
GL		 635 pdata->reset(pcdev->dev, 1);
636 }
637
638 CICR0 = 0x3FF; /* disable all interrupts */
639
640 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
641 cicr4 |= CICR4_PCLK_EN;
642 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
643 cicr4 |= CICR4_MCLK_EN;
644 if (pcdev->platform_flags & PXA_CAMERA_PCP)
645 cicr4 |= CICR4_PCP;
646 if (pcdev->platform_flags & PXA_CAMERA_HSP)
647 cicr4 |= CICR4_HSP;
648 if (pcdev->platform_flags & PXA_CAMERA_VSP)
649 cicr4 |= CICR4_VSP;
650
651 CICR4 = mclk_get_divisor(pcdev) | cicr4;
652
653 clk_enable(pcdev->clk);
654}
655
7102b773 656static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev)
3bc43840
GL		 657{
658 struct pxacamera_platform_data *board = pcdev->pdata;
659
660 clk_disable(pcdev->clk);
661
662 if (board && board->reset) {
663 dev_dbg(pcdev->dev, "%s: Asserting camera reset\n",
7e28adb2 664 __func__);
3bc43840
GL		 665 board->reset(pcdev->dev, 0);
666 }
667
668 if (board && board->power) {
7e28adb2 669 dev_dbg(pcdev->dev, "%s: Power off camera\n", __func__);
3bc43840
GL		 670 board->power(pcdev->dev, 0);
671 }
672}
673
674static irqreturn_t pxa_camera_irq(int irq, void *data)
675{
676 struct pxa_camera_dev *pcdev = data;
677 unsigned int status = CISR;
678
679 dev_dbg(pcdev->dev, "Camera interrupt status 0x%x\n", status);
680
e7c50688
GL		 681 if (!status)
682 return IRQ_NONE;
683
3bc43840 684 CISR = status;
e7c50688
GL		 685
686 if (status & CISR_EOF) {
687 int i;
688 for (i = 0; i < pcdev->channels; i++) {
689 DDADR(pcdev->dma_chans[i]) =
690 pcdev->active->dmas[i].sg_dma;
691 DCSR(pcdev->dma_chans[i]) = DCSR_RUN;
692 }
693 CICR0 |= CICR0_EOFM;
694 }
695
3bc43840
GL		 696 return IRQ_HANDLED;
697}
698
699/* The following two functions absolutely depend on the fact, that
700 * there can be only one camera on PXA quick capture interface */
7102b773 701static int pxa_camera_add_device(struct soc_camera_device *icd)
3bc43840
GL		 702{
703 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
704 struct pxa_camera_dev *pcdev = ici->priv;
705 int ret;
706
707 mutex_lock(&camera_lock);
708
709 if (pcdev->icd) {
710 ret = -EBUSY;
711 goto ebusy;
712 }
713
714 dev_info(&icd->dev, "PXA Camera driver attached to camera %d\n",
715 icd->devnum);
716
7102b773 717 pxa_camera_activate(pcdev);
3bc43840
GL		 718 ret = icd->ops->init(icd);
719
720 if (!ret)
721 pcdev->icd = icd;
722
723ebusy:
724 mutex_unlock(&camera_lock);
725
726 return ret;
727}
728
7102b773 729static void pxa_camera_remove_device(struct soc_camera_device *icd)
3bc43840
GL		 730{
731 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
732 struct pxa_camera_dev *pcdev = ici->priv;
733
734 BUG_ON(icd != pcdev->icd);
735
736 dev_info(&icd->dev, "PXA Camera driver detached from camera %d\n",
737 icd->devnum);
738
739 /* disable capture, disable interrupts */
740 CICR0 = 0x3ff;
a5462e5b 741
3bc43840 742 /* Stop DMA engine */
a5462e5b
MR		 743 DCSR(pcdev->dma_chans[0]) = 0;
744 DCSR(pcdev->dma_chans[1]) = 0;
745 DCSR(pcdev->dma_chans[2]) = 0;
3bc43840
GL		 746
747 icd->ops->release(icd);
748
7102b773 749 pxa_camera_deactivate(pcdev);
3bc43840
GL		 750
751 pcdev->icd = NULL;
752}
753
ad5f2e85
GL		 754static int test_platform_param(struct pxa_camera_dev *pcdev,
755 unsigned char buswidth, unsigned long *flags)
3bc43840 756{
ad5f2e85
GL		 757 /*
758 * Platform specified synchronization and pixel clock polarities are
759 * only a recommendation and are only used during probing. The PXA270
760 * quick capture interface supports both.
761 */
762 *flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ?
763 SOCAM_MASTER : SOCAM_SLAVE) |
764 SOCAM_HSYNC_ACTIVE_HIGH |
765 SOCAM_HSYNC_ACTIVE_LOW |
766 SOCAM_VSYNC_ACTIVE_HIGH |
767 SOCAM_VSYNC_ACTIVE_LOW |
768 SOCAM_PCLK_SAMPLE_RISING |
769 SOCAM_PCLK_SAMPLE_FALLING;
3bc43840
GL		 770
771 /* If requested data width is supported by the platform, use it */
ad5f2e85 772 switch (buswidth) {
3bc43840 773 case 10:
ad5f2e85
GL		 774 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10))
775 return -EINVAL;
776 *flags |= SOCAM_DATAWIDTH_10;
3bc43840
GL		 777 break;
778 case 9:
ad5f2e85
GL		 779 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9))
780 return -EINVAL;
781 *flags |= SOCAM_DATAWIDTH_9;
3bc43840
GL		 782 break;
783 case 8:
ad5f2e85
GL		 784 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8))
785 return -EINVAL;
786 *flags |= SOCAM_DATAWIDTH_8;
3bc43840 787 }
ad5f2e85
GL		 788
789 return 0;
790}
791
792static int pxa_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt)
793{
794 struct soc_camera_host *ici =
795 to_soc_camera_host(icd->dev.parent);
796 struct pxa_camera_dev *pcdev = ici->priv;
797 unsigned long dw, bpp, bus_flags, camera_flags, common_flags;
a5462e5b 798 u32 cicr0, cicr1, cicr4 = 0;
ad5f2e85
GL		 799 int ret = test_platform_param(pcdev, icd->buswidth, &bus_flags);
800
801 if (ret < 0)
802 return ret;
803
804 camera_flags = icd->ops->query_bus_param(icd);
805
806 common_flags = soc_camera_bus_param_compatible(camera_flags, bus_flags);
807 if (!common_flags)
3bc43840
GL		 808 return -EINVAL;
809
e7c50688
GL		 810 pcdev->channels = 1;
811
ad5f2e85
GL		 812 /* Make choises, based on platform preferences */
813 if ((common_flags & SOCAM_HSYNC_ACTIVE_HIGH) &&
814 (common_flags & SOCAM_HSYNC_ACTIVE_LOW)) {
815 if (pcdev->platform_flags & PXA_CAMERA_HSP)
816 common_flags &= ~SOCAM_HSYNC_ACTIVE_HIGH;
817 else
818 common_flags &= ~SOCAM_HSYNC_ACTIVE_LOW;
819 }
820
821 if ((common_flags & SOCAM_VSYNC_ACTIVE_HIGH) &&
822 (common_flags & SOCAM_VSYNC_ACTIVE_LOW)) {
823 if (pcdev->platform_flags & PXA_CAMERA_VSP)
824 common_flags &= ~SOCAM_VSYNC_ACTIVE_HIGH;
825 else
826 common_flags &= ~SOCAM_VSYNC_ACTIVE_LOW;
827 }
828
829 if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) &&
830 (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) {
831 if (pcdev->platform_flags & PXA_CAMERA_PCP)
832 common_flags &= ~SOCAM_PCLK_SAMPLE_RISING;
833 else
834 common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING;
835 }
836
837 ret = icd->ops->set_bus_param(icd, common_flags);
3bc43840
GL		 838 if (ret < 0)
839 return ret;
840
841 /* Datawidth is now guaranteed to be equal to one of the three values.
842 * We fix bit-per-pixel equal to data-width... */
ad5f2e85
GL		 843 switch (common_flags & SOCAM_DATAWIDTH_MASK) {
844 case SOCAM_DATAWIDTH_10:
845 icd->buswidth = 10;
3bc43840
GL		 846 dw = 4;
847 bpp = 0x40;
848 break;
ad5f2e85
GL		 849 case SOCAM_DATAWIDTH_9:
850 icd->buswidth = 9;
3bc43840
GL		 851 dw = 3;
852 bpp = 0x20;
853 break;
854 default:
855 /* Actually it can only be 8 now,
856 * default is just to silence compiler warnings */
ad5f2e85
GL		 857 case SOCAM_DATAWIDTH_8:
858 icd->buswidth = 8;
3bc43840
GL		 859 dw = 2;
860 bpp = 0;
861 }
862
863 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
864 cicr4 |= CICR4_PCLK_EN;
865 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
866 cicr4 |= CICR4_MCLK_EN;
ad5f2e85 867 if (common_flags & SOCAM_PCLK_SAMPLE_FALLING)
3bc43840 868 cicr4 |= CICR4_PCP;
ad5f2e85 869 if (common_flags & SOCAM_HSYNC_ACTIVE_LOW)
3bc43840 870 cicr4 |= CICR4_HSP;
ad5f2e85 871 if (common_flags & SOCAM_VSYNC_ACTIVE_LOW)
3bc43840
GL		 872 cicr4 |= CICR4_VSP;
873
874 cicr0 = CICR0;
875 if (cicr0 & CICR0_ENB)
876 CICR0 = cicr0 & ~CICR0_ENB;
a5462e5b
MR		 877
878 cicr1 = CICR1_PPL_VAL(icd->width - 1) | bpp | dw;
879
880 switch (pixfmt) {
881 case V4L2_PIX_FMT_YUV422P:
e7c50688 882 pcdev->channels = 3;
a5462e5b
MR		 883 cicr1 |= CICR1_YCBCR_F;
884 case V4L2_PIX_FMT_YUYV:
885 cicr1 |= CICR1_COLOR_SP_VAL(2);
886 break;
887 case V4L2_PIX_FMT_RGB555:
888 cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) |
889 CICR1_TBIT | CICR1_COLOR_SP_VAL(1);
890 break;
891 case V4L2_PIX_FMT_RGB565:
892 cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2);
893 break;
894 }
895
896 CICR1 = cicr1;
3bc43840 897 CICR2 = 0;
ad5f2e85 898 CICR3 = CICR3_LPF_VAL(icd->height - 1) |
3bc43840
GL		 899 CICR3_BFW_VAL(min((unsigned short)255, icd->y_skip_top));
900 CICR4 = mclk_get_divisor(pcdev) | cicr4;
901
902 /* CIF interrupts are not used, only DMA */
903 CICR0 = (pcdev->platform_flags & PXA_CAMERA_MASTER ?
7102b773 904 CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP)) |
3bc43840
GL		 905 CICR0_DMAEN | CICR0_IRQ_MASK | (cicr0 & CICR0_ENB);
906
907 return 0;
908}
909
ad5f2e85
GL		 910static int pxa_camera_try_bus_param(struct soc_camera_device *icd, __u32 pixfmt)
911{
912 struct soc_camera_host *ici =
913 to_soc_camera_host(icd->dev.parent);
914 struct pxa_camera_dev *pcdev = ici->priv;
915 unsigned long bus_flags, camera_flags;
916 int ret = test_platform_param(pcdev, icd->buswidth, &bus_flags);
917
918 if (ret < 0)
919 return ret;
920
921 camera_flags = icd->ops->query_bus_param(icd);
922
923 return soc_camera_bus_param_compatible(camera_flags, bus_flags) ? 0 : -EINVAL;
924}
925
926static int pxa_camera_set_fmt_cap(struct soc_camera_device *icd,
927 __u32 pixfmt, struct v4l2_rect *rect)
928{
929 return icd->ops->set_fmt_cap(icd, pixfmt, rect);
930}
931
932static int pxa_camera_try_fmt_cap(struct soc_camera_device *icd,
7102b773 933 struct v4l2_format *f)
3bc43840
GL		 934{
935 /* limit to pxa hardware capabilities */
936 if (f->fmt.pix.height < 32)
937 f->fmt.pix.height = 32;
938 if (f->fmt.pix.height > 2048)
939 f->fmt.pix.height = 2048;
940 if (f->fmt.pix.width < 48)
941 f->fmt.pix.width = 48;
942 if (f->fmt.pix.width > 2048)
943 f->fmt.pix.width = 2048;
944 f->fmt.pix.width &= ~0x01;
945
ad5f2e85
GL		 946 /* limit to sensor capabilities */
947 return icd->ops->try_fmt_cap(icd, f);
3bc43840
GL		 948}
949
7102b773
GL		 950static int pxa_camera_reqbufs(struct soc_camera_file *icf,
951 struct v4l2_requestbuffers *p)
3bc43840
GL		 952{
953 int i;
954
955 /* This is for locking debugging only. I removed spinlocks and now I
956 * check whether .prepare is ever called on a linked buffer, or whether
957 * a dma IRQ can occur for an in-work or unlinked buffer. Until now
958 * it hadn't triggered */
959 for (i = 0; i < p->count; i++) {
960 struct pxa_buffer *buf = container_of(icf->vb_vidq.bufs[i],
961 struct pxa_buffer, vb);
962 buf->inwork = 0;
963 INIT_LIST_HEAD(&buf->vb.queue);
964 }
965
966 return 0;
967}
968
7102b773 969static unsigned int pxa_camera_poll(struct file *file, poll_table *pt)
3bc43840
GL		 970{
971 struct soc_camera_file *icf = file->private_data;
972 struct pxa_buffer *buf;
973
974 buf = list_entry(icf->vb_vidq.stream.next, struct pxa_buffer,
975 vb.stream);
976
977 poll_wait(file, &buf->vb.done, pt);
978
979 if (buf->vb.state == VIDEOBUF_DONE ||
980 buf->vb.state == VIDEOBUF_ERROR)
981 return POLLIN|POLLRDNORM;
982
983 return 0;
984}
985
7102b773
GL		 986static int pxa_camera_querycap(struct soc_camera_host *ici,
987 struct v4l2_capability *cap)
3bc43840
GL		 988{
989 /* cap->name is set by the firendly caller:-> */
990 strlcpy(cap->card, pxa_cam_driver_description, sizeof(cap->card));
991 cap->version = PXA_CAM_VERSION_CODE;
992 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
993
994 return 0;
995}
996
1a0063a9
GL		 997static spinlock_t *pxa_camera_spinlock_alloc(struct soc_camera_file *icf)
998{
999 struct soc_camera_host *ici =
1000 to_soc_camera_host(icf->icd->dev.parent);
1001 struct pxa_camera_dev *pcdev = ici->priv;
1002
1003 return &pcdev->lock;
1004}
1005
b8d9904c
GL		 1006static struct soc_camera_host_ops pxa_soc_camera_host_ops = {
1007 .owner = THIS_MODULE,
1008 .add = pxa_camera_add_device,
1009 .remove = pxa_camera_remove_device,
1010 .set_fmt_cap = pxa_camera_set_fmt_cap,
1011 .try_fmt_cap = pxa_camera_try_fmt_cap,
092d3921 1012 .init_videobuf = pxa_camera_init_videobuf,
b8d9904c
GL		 1013 .reqbufs = pxa_camera_reqbufs,
1014 .poll = pxa_camera_poll,
1015 .querycap = pxa_camera_querycap,
1016 .try_bus_param = pxa_camera_try_bus_param,
1017 .set_bus_param = pxa_camera_set_bus_param,
1a0063a9 1018 .spinlock_alloc = pxa_camera_spinlock_alloc,
b8d9904c
GL		 1019};
1020
1021/* Should be allocated dynamically too, but we have only one. */
3bc43840
GL		 1022static struct soc_camera_host pxa_soc_camera_host = {
1023 .drv_name = PXA_CAM_DRV_NAME,
b8d9904c 1024 .ops = &pxa_soc_camera_host_ops,
3bc43840
GL		 1025};
1026
1027static int pxa_camera_probe(struct platform_device *pdev)
1028{
1029 struct pxa_camera_dev *pcdev;
1030 struct resource *res;
1031 void __iomem *base;
02da4659 1032 int irq;
3bc43840
GL		 1033 int err = 0;
1034
1035 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1036 irq = platform_get_irq(pdev, 0);
02da4659 1037 if (!res || irq < 0) {
3bc43840
GL		 1038 err = -ENODEV;
1039 goto exit;
1040 }
1041
1042 pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL);
1043 if (!pcdev) {
7102b773 1044 dev_err(&pdev->dev, "Could not allocate pcdev\n");
3bc43840
GL		 1045 err = -ENOMEM;
1046 goto exit;
1047 }
1048
1049 pcdev->clk = clk_get(&pdev->dev, "CAMCLK");
1050 if (IS_ERR(pcdev->clk)) {
1051 err = PTR_ERR(pcdev->clk);
1052 goto exit_kfree;
1053 }
1054
1055 dev_set_drvdata(&pdev->dev, pcdev);
1056 pcdev->res = res;
1057
1058 pcdev->pdata = pdev->dev.platform_data;
1059 pcdev->platform_flags = pcdev->pdata->flags;
ad5f2e85
GL		 1060 if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 |
1061 PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) {
3bc43840
GL		 1062 /* Platform hasn't set available data widths. This is bad.
1063 * Warn and use a default. */
1064 dev_warn(&pdev->dev, "WARNING! Platform hasn't set available "
1065 "data widths, using default 10 bit\n");
1066 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
1067 }
1068 pcdev->platform_mclk_10khz = pcdev->pdata->mclk_10khz;
1069 if (!pcdev->platform_mclk_10khz) {
1070 dev_warn(&pdev->dev,
1071 "mclk_10khz == 0! Please, fix your platform data. "
1072 "Using default 20MHz\n");
1073 pcdev->platform_mclk_10khz = 2000;
1074 }
1075
1076 INIT_LIST_HEAD(&pcdev->capture);
1077 spin_lock_init(&pcdev->lock);
1078
1079 /*
1080 * Request the regions.
1081 */
1082 if (!request_mem_region(res->start, res->end - res->start + 1,
1083 PXA_CAM_DRV_NAME)) {
1084 err = -EBUSY;
1085 goto exit_clk;
1086 }
1087
1088 base = ioremap(res->start, res->end - res->start + 1);
1089 if (!base) {
1090 err = -ENOMEM;
1091 goto exit_release;
1092 }
1093 pcdev->irq = irq;
1094 pcdev->base = base;
1095 pcdev->dev = &pdev->dev;
1096
1097 /* request dma */
a5462e5b
MR		 1098 pcdev->dma_chans[0] = pxa_request_dma("CI_Y", DMA_PRIO_HIGH,
1099 pxa_camera_dma_irq_y, pcdev);
1100 if (pcdev->dma_chans[0] < 0) {
3bc43840
GL		 1101 dev_err(pcdev->dev, "Can't request DMA for Y\n");
1102 err = -ENOMEM;
1103 goto exit_iounmap;
1104 }
a5462e5b
MR		 1105 dev_dbg(pcdev->dev, "got DMA channel %d\n", pcdev->dma_chans[0]);
1106
1107 pcdev->dma_chans[1] = pxa_request_dma("CI_U", DMA_PRIO_HIGH,
1108 pxa_camera_dma_irq_u, pcdev);
1109 if (pcdev->dma_chans[1] < 0) {
1110 dev_err(pcdev->dev, "Can't request DMA for U\n");
1111 err = -ENOMEM;
1112 goto exit_free_dma_y;
1113 }
1114 dev_dbg(pcdev->dev, "got DMA channel (U) %d\n", pcdev->dma_chans[1]);
1115
1116 pcdev->dma_chans[2] = pxa_request_dma("CI_V", DMA_PRIO_HIGH,
1117 pxa_camera_dma_irq_v, pcdev);
1118 if (pcdev->dma_chans[0] < 0) {
1119 dev_err(pcdev->dev, "Can't request DMA for V\n");
1120 err = -ENOMEM;
1121 goto exit_free_dma_u;
1122 }
1123 dev_dbg(pcdev->dev, "got DMA channel (V) %d\n", pcdev->dma_chans[2]);
3bc43840 1124
a5462e5b
MR		 1125 DRCMR68 = pcdev->dma_chans[0] | DRCMR_MAPVLD;
1126 DRCMR69 = pcdev->dma_chans[1] | DRCMR_MAPVLD;
1127 DRCMR70 = pcdev->dma_chans[2] | DRCMR_MAPVLD;
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GL		 1128
1129 /* request irq */
1130 err = request_irq(pcdev->irq, pxa_camera_irq, 0, PXA_CAM_DRV_NAME,
1131 pcdev);
1132 if (err) {
1133 dev_err(pcdev->dev, "Camera interrupt register failed \n");
1134 goto exit_free_dma;
1135 }
1136
1137 pxa_soc_camera_host.priv = pcdev;
1138 pxa_soc_camera_host.dev.parent = &pdev->dev;
1139 pxa_soc_camera_host.nr = pdev->id;
b8d9904c 1140 err = soc_camera_host_register(&pxa_soc_camera_host);
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GL		 1141 if (err)
1142 goto exit_free_irq;
1143
1144 return 0;
1145
1146exit_free_irq:
1147 free_irq(pcdev->irq, pcdev);
1148exit_free_dma:
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MR		 1149 pxa_free_dma(pcdev->dma_chans[2]);
1150exit_free_dma_u:
1151 pxa_free_dma(pcdev->dma_chans[1]);
1152exit_free_dma_y:
1153 pxa_free_dma(pcdev->dma_chans[0]);
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GL		 1154exit_iounmap:
1155 iounmap(base);
1156exit_release:
1157 release_mem_region(res->start, res->end - res->start + 1);
1158exit_clk:
1159 clk_put(pcdev->clk);
1160exit_kfree:
1161 kfree(pcdev);
1162exit:
1163 return err;
1164}
1165
1166static int __devexit pxa_camera_remove(struct platform_device *pdev)
1167{
1168 struct pxa_camera_dev *pcdev = platform_get_drvdata(pdev);
1169 struct resource *res;
1170
1171 clk_put(pcdev->clk);
1172
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MR		 1173 pxa_free_dma(pcdev->dma_chans[0]);
1174 pxa_free_dma(pcdev->dma_chans[1]);
1175 pxa_free_dma(pcdev->dma_chans[2]);
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GL		 1176 free_irq(pcdev->irq, pcdev);
1177
1178 soc_camera_host_unregister(&pxa_soc_camera_host);
1179
1180 iounmap(pcdev->base);
1181
1182 res = pcdev->res;
1183 release_mem_region(res->start, res->end - res->start + 1);
1184
1185 kfree(pcdev);
1186
7102b773 1187 dev_info(&pdev->dev, "PXA Camera driver unloaded\n");
3bc43840 1188
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GL		 1189 return 0;
1190}
1191
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GL		 1192static struct platform_driver pxa_camera_driver = {
1193 .driver = {
1194 .name = PXA_CAM_DRV_NAME,
1195 },
1196 .probe = pxa_camera_probe,
1197 .remove = __exit_p(pxa_camera_remove),
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GL		 1198};
1199
1200
1201static int __devinit pxa_camera_init(void)
1202{
1203 return platform_driver_register(&pxa_camera_driver);
1204}
1205
1206static void __exit pxa_camera_exit(void)
1207{
1208 return platform_driver_unregister(&pxa_camera_driver);
1209}
1210
1211module_init(pxa_camera_init);
1212module_exit(pxa_camera_exit);
1213
1214MODULE_DESCRIPTION("PXA27x SoC Camera Host driver");
1215MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
1216MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)