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V4L/DVB (7094): static memory
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / media / video / pvrusb2 / pvrusb2-hdw.c
CommitLineData
d855497e
MI		 1/*
2 *
3 * $Id$
4 *
5 * Copyright (C) 2005 Mike Isely <isely@pobox.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 */
21
22#include <linux/errno.h>
23#include <linux/string.h>
24#include <linux/slab.h>
25#include <linux/firmware.h>
d855497e 26#include <linux/videodev2.h>
32ffa9ae 27#include <media/v4l2-common.h>
d855497e
MI		 28#include "pvrusb2.h"
29#include "pvrusb2-std.h"
30#include "pvrusb2-util.h"
31#include "pvrusb2-hdw.h"
32#include "pvrusb2-i2c-core.h"
33#include "pvrusb2-tuner.h"
34#include "pvrusb2-eeprom.h"
35#include "pvrusb2-hdw-internal.h"
36#include "pvrusb2-encoder.h"
37#include "pvrusb2-debug.h"
8d364363 38#include "pvrusb2-fx2-cmd.h"
d855497e 39
1bde0289
MI		 40#define TV_MIN_FREQ 55250000L
41#define TV_MAX_FREQ 850000000L
25d8527a 42
a0fd1cb1 43static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
8df0c87c 44static DEFINE_MUTEX(pvr2_unit_mtx);
d855497e 45
ff699e6b 46static int ctlchg;
d855497e 47static int initusbreset = 1;
ff699e6b 48static int procreload;
d855497e
MI		 49static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
50static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
51static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
ff699e6b 52static int init_pause_msec;
d855497e
MI		 53
54module_param(ctlchg, int, S_IRUGO|S_IWUSR);
55MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
56module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
57MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
58module_param(initusbreset, int, S_IRUGO|S_IWUSR);
59MODULE_PARM_DESC(initusbreset, "Do USB reset device on probe");
60module_param(procreload, int, S_IRUGO|S_IWUSR);
61MODULE_PARM_DESC(procreload,
62 "Attempt init failure recovery with firmware reload");
63module_param_array(tuner, int, NULL, 0444);
64MODULE_PARM_DESC(tuner,"specify installed tuner type");
65module_param_array(video_std, int, NULL, 0444);
66MODULE_PARM_DESC(video_std,"specify initial video standard");
67module_param_array(tolerance, int, NULL, 0444);
68MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
69
70#define PVR2_CTL_WRITE_ENDPOINT 0x01
71#define PVR2_CTL_READ_ENDPOINT 0x81
72
73#define PVR2_GPIO_IN 0x9008
74#define PVR2_GPIO_OUT 0x900c
75#define PVR2_GPIO_DIR 0x9020
76
77#define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
78
79#define PVR2_FIRMWARE_ENDPOINT 0x02
80
81/* size of a firmware chunk */
82#define FIRMWARE_CHUNK_SIZE 0x2000
83
b30d2441
MI		 84/* Define the list of additional controls we'll dynamically construct based
85 on query of the cx2341x module. */
86struct pvr2_mpeg_ids {
87 const char *strid;
88 int id;
89};
90static const struct pvr2_mpeg_ids mpeg_ids[] = {
91 {
92 .strid = "audio_layer",
93 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
94 },{
95 .strid = "audio_bitrate",
96 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
97 },{
98 /* Already using audio_mode elsewhere :-( */
99 .strid = "mpeg_audio_mode",
100 .id = V4L2_CID_MPEG_AUDIO_MODE,
101 },{
102 .strid = "mpeg_audio_mode_extension",
103 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
104 },{
105 .strid = "audio_emphasis",
106 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
107 },{
108 .strid = "audio_crc",
109 .id = V4L2_CID_MPEG_AUDIO_CRC,
110 },{
111 .strid = "video_aspect",
112 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
113 },{
114 .strid = "video_b_frames",
115 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
116 },{
117 .strid = "video_gop_size",
118 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
119 },{
120 .strid = "video_gop_closure",
121 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
b30d2441
MI		 122 },{
123 .strid = "video_bitrate_mode",
124 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
125 },{
126 .strid = "video_bitrate",
127 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
128 },{
129 .strid = "video_bitrate_peak",
130 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
131 },{
132 .strid = "video_temporal_decimation",
133 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
134 },{
135 .strid = "stream_type",
136 .id = V4L2_CID_MPEG_STREAM_TYPE,
137 },{
138 .strid = "video_spatial_filter_mode",
139 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
140 },{
141 .strid = "video_spatial_filter",
142 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
143 },{
144 .strid = "video_luma_spatial_filter_type",
145 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
146 },{
147 .strid = "video_chroma_spatial_filter_type",
148 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
149 },{
150 .strid = "video_temporal_filter_mode",
151 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
152 },{
153 .strid = "video_temporal_filter",
154 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
155 },{
156 .strid = "video_median_filter_type",
157 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
158 },{
159 .strid = "video_luma_median_filter_top",
160 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
161 },{
162 .strid = "video_luma_median_filter_bottom",
163 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
164 },{
165 .strid = "video_chroma_median_filter_top",
166 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
167 },{
168 .strid = "video_chroma_median_filter_bottom",
169 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
170 }
171};
eca8ebfc 172#define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
c05c0462 173
434449f4 174
d855497e 175static const char *control_values_srate[] = {
434449f4
MI		 176 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100] = "44.1 kHz",
177 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000] = "48 kHz",
178 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000] = "32 kHz",
d855497e
MI		 179};
180
181
d855497e 182
d855497e
MI		 183static const char *control_values_input[] = {
184 [PVR2_CVAL_INPUT_TV] = "television", /*xawtv needs this name*/
185 [PVR2_CVAL_INPUT_RADIO] = "radio",
186 [PVR2_CVAL_INPUT_SVIDEO] = "s-video",
187 [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
188};
189
190
191static const char *control_values_audiomode[] = {
192 [V4L2_TUNER_MODE_MONO] = "Mono",
193 [V4L2_TUNER_MODE_STEREO] = "Stereo",
194 [V4L2_TUNER_MODE_LANG1] = "Lang1",
195 [V4L2_TUNER_MODE_LANG2] = "Lang2",
196 [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
197};
198
199
200static const char *control_values_hsm[] = {
201 [PVR2_CVAL_HSM_FAIL] = "Fail",
202 [PVR2_CVAL_HSM_HIGH] = "High",
203 [PVR2_CVAL_HSM_FULL] = "Full",
204};
205
206
681c7399
MI		 207static const char *pvr2_state_names[] = {
208 [PVR2_STATE_NONE] = "none",
209 [PVR2_STATE_DEAD] = "dead",
210 [PVR2_STATE_COLD] = "cold",
211 [PVR2_STATE_WARM] = "warm",
212 [PVR2_STATE_ERROR] = "error",
213 [PVR2_STATE_READY] = "ready",
214 [PVR2_STATE_RUN] = "run",
d855497e
MI		 215};
216
681c7399
MI		 217
218static void pvr2_hdw_state_sched(struct pvr2_hdw *);
219static int pvr2_hdw_state_eval(struct pvr2_hdw *);
1bde0289 220static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
681c7399
MI		 221static void pvr2_hdw_worker_i2c(struct work_struct *work);
222static void pvr2_hdw_worker_poll(struct work_struct *work);
223static void pvr2_hdw_worker_init(struct work_struct *work);
224static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
225static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
226static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
07e337ee 227static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
681c7399 228static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
07e337ee 229static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
07e337ee
AB		 230static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
231static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
681c7399
MI		 232static void pvr2_hdw_quiescent_timeout(unsigned long);
233static void pvr2_hdw_encoder_wait_timeout(unsigned long);
07e337ee
AB		 234static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
235 unsigned int timeout,int probe_fl,
236 void *write_data,unsigned int write_len,
237 void *read_data,unsigned int read_len);
d855497e 238
681c7399
MI		 239
240static void trace_stbit(const char *name,int val)
241{
242 pvr2_trace(PVR2_TRACE_STBITS,
243 "State bit %s <-- %s",
244 name,(val ? "true" : "false"));
245}
246
d855497e
MI		 247static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
248{
249 struct pvr2_hdw *hdw = cptr->hdw;
250 if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
251 *vp = hdw->freqTable[hdw->freqProgSlot-1];
252 } else {
253 *vp = 0;
254 }
255 return 0;
256}
257
258static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
259{
260 struct pvr2_hdw *hdw = cptr->hdw;
1bde0289
MI		 261 unsigned int slotId = hdw->freqProgSlot;
262 if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
263 hdw->freqTable[slotId-1] = v;
264 /* Handle side effects correctly - if we're tuned to this
265 slot, then forgot the slot id relation since the stored
266 frequency has been changed. */
267 if (hdw->freqSelector) {
268 if (hdw->freqSlotRadio == slotId) {
269 hdw->freqSlotRadio = 0;
270 }
271 } else {
272 if (hdw->freqSlotTelevision == slotId) {
273 hdw->freqSlotTelevision = 0;
274 }
275 }
d855497e
MI		 276 }
277 return 0;
278}
279
280static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
281{
282 *vp = cptr->hdw->freqProgSlot;
283 return 0;
284}
285
286static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
287{
288 struct pvr2_hdw *hdw = cptr->hdw;
289 if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
290 hdw->freqProgSlot = v;
291 }
292 return 0;
293}
294
295static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
296{
1bde0289
MI		 297 struct pvr2_hdw *hdw = cptr->hdw;
298 *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
d855497e
MI		 299 return 0;
300}
301
1bde0289 302static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
d855497e
MI		 303{
304 unsigned freq = 0;
305 struct pvr2_hdw *hdw = cptr->hdw;
1bde0289
MI		 306 if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
307 if (slotId > 0) {
308 freq = hdw->freqTable[slotId-1];
309 if (!freq) return 0;
310 pvr2_hdw_set_cur_freq(hdw,freq);
d855497e 311 }
1bde0289
MI		 312 if (hdw->freqSelector) {
313 hdw->freqSlotRadio = slotId;
314 } else {
315 hdw->freqSlotTelevision = slotId;
d855497e
MI		 316 }
317 return 0;
318}
319
320static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
321{
1bde0289 322 *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
d855497e
MI		 323 return 0;
324}
325
326static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
327{
328 return cptr->hdw->freqDirty != 0;
329}
330
331static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
332{
333 cptr->hdw->freqDirty = 0;
334}
335
336static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
337{
1bde0289 338 pvr2_hdw_set_cur_freq(cptr->hdw,v);
d855497e
MI		 339 return 0;
340}
341
3ad9fc37
MI		 342static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
343{
344 /* Actual maximum depends on the video standard in effect. */
345 if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
346 *vp = 480;
347 } else {
348 *vp = 576;
349 }
350 return 0;
351}
352
353static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
354{
989eb154
MI		 355 /* Actual minimum depends on device digitizer type. */
356 if (cptr->hdw->hdw_desc->flag_has_cx25840) {
3ad9fc37
MI		 357 *vp = 75;
358 } else {
359 *vp = 17;
360 }
361 return 0;
362}
363
1bde0289 364static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
5549f54f 365{
1bde0289
MI		 366 *vp = cptr->hdw->input_val;
367 return 0;
368}
369
370static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
371{
372 struct pvr2_hdw *hdw = cptr->hdw;
373
374 if (hdw->input_val != v) {
375 hdw->input_val = v;
376 hdw->input_dirty = !0;
377 }
378
379 /* Handle side effects - if we switch to a mode that needs the RF
380 tuner, then select the right frequency choice as well and mark
381 it dirty. */
382 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
383 hdw->freqSelector = 0;
384 hdw->freqDirty = !0;
385 } else if (hdw->input_val == PVR2_CVAL_INPUT_TV) {
386 hdw->freqSelector = 1;
387 hdw->freqDirty = !0;
5549f54f 388 }
1bde0289
MI		 389 return 0;
390}
391
392static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
393{
394 return cptr->hdw->input_dirty != 0;
395}
396
397static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
398{
399 cptr->hdw->input_dirty = 0;
400}
401
5549f54f 402
25d8527a
PK		 403static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
404{
644afdb9
MI		 405 unsigned long fv;
406 struct pvr2_hdw *hdw = cptr->hdw;
407 if (hdw->tuner_signal_stale) {
408 pvr2_i2c_core_status_poll(hdw);
409 }
410 fv = hdw->tuner_signal_info.rangehigh;
411 if (!fv) {
412 /* Safety fallback */
25d8527a 413 *vp = TV_MAX_FREQ;
644afdb9 414 return 0;
25d8527a 415 }
644afdb9
MI		 416 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
417 fv = (fv * 125) / 2;
418 } else {
419 fv = fv * 62500;
420 }
421 *vp = fv;
25d8527a
PK		 422 return 0;
423}
424
425static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
426{
644afdb9
MI		 427 unsigned long fv;
428 struct pvr2_hdw *hdw = cptr->hdw;
429 if (hdw->tuner_signal_stale) {
430 pvr2_i2c_core_status_poll(hdw);
431 }
432 fv = hdw->tuner_signal_info.rangelow;
433 if (!fv) {
434 /* Safety fallback */
25d8527a 435 *vp = TV_MIN_FREQ;
644afdb9
MI		 436 return 0;
437 }
438 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
439 fv = (fv * 125) / 2;
440 } else {
441 fv = fv * 62500;
25d8527a 442 }
644afdb9 443 *vp = fv;
25d8527a
PK		 444 return 0;
445}
446
b30d2441
MI		 447static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
448{
449 return cptr->hdw->enc_stale != 0;
450}
451
452static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
453{
454 cptr->hdw->enc_stale = 0;
681c7399 455 cptr->hdw->enc_unsafe_stale = 0;
b30d2441
MI		 456}
457
458static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
459{
460 int ret;
461 struct v4l2_ext_controls cs;
462 struct v4l2_ext_control c1;
463 memset(&cs,0,sizeof(cs));
464 memset(&c1,0,sizeof(c1));
465 cs.controls = &c1;
466 cs.count = 1;
467 c1.id = cptr->info->v4l_id;
01f1e44f 468 ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
b30d2441
MI		 469 VIDIOC_G_EXT_CTRLS);
470 if (ret) return ret;
471 *vp = c1.value;
472 return 0;
473}
474
475static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
476{
477 int ret;
681c7399 478 struct pvr2_hdw *hdw = cptr->hdw;
b30d2441
MI		 479 struct v4l2_ext_controls cs;
480 struct v4l2_ext_control c1;
481 memset(&cs,0,sizeof(cs));
482 memset(&c1,0,sizeof(c1));
483 cs.controls = &c1;
484 cs.count = 1;
485 c1.id = cptr->info->v4l_id;
486 c1.value = v;
681c7399
MI		 487 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
488 hdw->state_encoder_run, &cs,
b30d2441 489 VIDIOC_S_EXT_CTRLS);
681c7399
MI		 490 if (ret == -EBUSY) {
491 /* Oops. cx2341x is telling us it's not safe to change
492 this control while we're capturing. Make a note of this
493 fact so that the pipeline will be stopped the next time
494 controls are committed. Then go on ahead and store this
495 change anyway. */
496 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
497 0, &cs,
498 VIDIOC_S_EXT_CTRLS);
499 if (!ret) hdw->enc_unsafe_stale = !0;
500 }
b30d2441 501 if (ret) return ret;
681c7399 502 hdw->enc_stale = !0;
b30d2441
MI		 503 return 0;
504}
505
506static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
507{
508 struct v4l2_queryctrl qctrl;
509 struct pvr2_ctl_info *info;
510 qctrl.id = cptr->info->v4l_id;
511 cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
512 /* Strip out the const so we can adjust a function pointer. It's
513 OK to do this here because we know this is a dynamically created
514 control, so the underlying storage for the info pointer is (a)
515 private to us, and (b) not in read-only storage. Either we do
516 this or we significantly complicate the underlying control
517 implementation. */
518 info = (struct pvr2_ctl_info *)(cptr->info);
519 if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
520 if (info->set_value) {
a0fd1cb1 521 info->set_value = NULL;
b30d2441
MI		 522 }
523 } else {
524 if (!(info->set_value)) {
525 info->set_value = ctrl_cx2341x_set;
526 }
527 }
528 return qctrl.flags;
529}
530
d855497e
MI		 531static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
532{
681c7399
MI		 533 *vp = cptr->hdw->state_pipeline_req;
534 return 0;
535}
536
537static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
538{
539 *vp = cptr->hdw->master_state;
d855497e
MI		 540 return 0;
541}
542
543static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
544{
545 int result = pvr2_hdw_is_hsm(cptr->hdw);
546 *vp = PVR2_CVAL_HSM_FULL;
547 if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
548 if (result) *vp = PVR2_CVAL_HSM_HIGH;
549 return 0;
550}
551
552static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
553{
554 *vp = cptr->hdw->std_mask_avail;
555 return 0;
556}
557
558static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
559{
560 struct pvr2_hdw *hdw = cptr->hdw;
561 v4l2_std_id ns;
562 ns = hdw->std_mask_avail;
563 ns = (ns & ~m) | (v & m);
564 if (ns == hdw->std_mask_avail) return 0;
565 hdw->std_mask_avail = ns;
566 pvr2_hdw_internal_set_std_avail(hdw);
567 pvr2_hdw_internal_find_stdenum(hdw);
568 return 0;
569}
570
571static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
572 char *bufPtr,unsigned int bufSize,
573 unsigned int *len)
574{
575 *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
576 return 0;
577}
578
579static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
580 const char *bufPtr,unsigned int bufSize,
581 int *mskp,int *valp)
582{
583 int ret;
584 v4l2_std_id id;
585 ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
586 if (ret < 0) return ret;
587 if (mskp) *mskp = id;
588 if (valp) *valp = id;
589 return 0;
590}
591
592static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
593{
594 *vp = cptr->hdw->std_mask_cur;
595 return 0;
596}
597
598static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
599{
600 struct pvr2_hdw *hdw = cptr->hdw;
601 v4l2_std_id ns;
602 ns = hdw->std_mask_cur;
603 ns = (ns & ~m) | (v & m);
604 if (ns == hdw->std_mask_cur) return 0;
605 hdw->std_mask_cur = ns;
606 hdw->std_dirty = !0;
607 pvr2_hdw_internal_find_stdenum(hdw);
608 return 0;
609}
610
611static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
612{
613 return cptr->hdw->std_dirty != 0;
614}
615
616static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
617{
618 cptr->hdw->std_dirty = 0;
619}
620
621static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
622{
18103c57
MI		 623 struct pvr2_hdw *hdw = cptr->hdw;
624 pvr2_i2c_core_status_poll(hdw);
625 *vp = hdw->tuner_signal_info.signal;
626 return 0;
627}
628
629static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
630{
631 int val = 0;
632 unsigned int subchan;
633 struct pvr2_hdw *hdw = cptr->hdw;
644afdb9 634 pvr2_i2c_core_status_poll(hdw);
18103c57
MI		 635 subchan = hdw->tuner_signal_info.rxsubchans;
636 if (subchan & V4L2_TUNER_SUB_MONO) {
637 val |= (1 << V4L2_TUNER_MODE_MONO);
638 }
639 if (subchan & V4L2_TUNER_SUB_STEREO) {
640 val |= (1 << V4L2_TUNER_MODE_STEREO);
641 }
642 if (subchan & V4L2_TUNER_SUB_LANG1) {
643 val |= (1 << V4L2_TUNER_MODE_LANG1);
644 }
645 if (subchan & V4L2_TUNER_SUB_LANG2) {
646 val |= (1 << V4L2_TUNER_MODE_LANG2);
647 }
648 *vp = val;
d855497e
MI		 649 return 0;
650}
651
d855497e
MI		 652
653static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
654{
655 struct pvr2_hdw *hdw = cptr->hdw;
656 if (v < 0) return -EINVAL;
657 if (v > hdw->std_enum_cnt) return -EINVAL;
658 hdw->std_enum_cur = v;
659 if (!v) return 0;
660 v--;
661 if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
662 hdw->std_mask_cur = hdw->std_defs[v].id;
663 hdw->std_dirty = !0;
664 return 0;
665}
666
667
668static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
669{
670 *vp = cptr->hdw->std_enum_cur;
671 return 0;
672}
673
674
675static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
676{
677 return cptr->hdw->std_dirty != 0;
678}
679
680
681static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
682{
683 cptr->hdw->std_dirty = 0;
684}
685
686
687#define DEFINT(vmin,vmax) \
688 .type = pvr2_ctl_int, \
689 .def.type_int.min_value = vmin, \
690 .def.type_int.max_value = vmax
691
692#define DEFENUM(tab) \
693 .type = pvr2_ctl_enum, \
27c7b710 694 .def.type_enum.count = ARRAY_SIZE(tab), \
d855497e
MI		 695 .def.type_enum.value_names = tab
696
33213963
MI		 697#define DEFBOOL \
698 .type = pvr2_ctl_bool
699
d855497e
MI		 700#define DEFMASK(msk,tab) \
701 .type = pvr2_ctl_bitmask, \
702 .def.type_bitmask.valid_bits = msk, \
703 .def.type_bitmask.bit_names = tab
704
705#define DEFREF(vname) \
706 .set_value = ctrl_set_##vname, \
707 .get_value = ctrl_get_##vname, \
708 .is_dirty = ctrl_isdirty_##vname, \
709 .clear_dirty = ctrl_cleardirty_##vname
710
711
712#define VCREATE_FUNCS(vname) \
713static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
714{*vp = cptr->hdw->vname##_val; return 0;} \
715static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
716{cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
717static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
718{return cptr->hdw->vname##_dirty != 0;} \
719static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
720{cptr->hdw->vname##_dirty = 0;}
721
722VCREATE_FUNCS(brightness)
723VCREATE_FUNCS(contrast)
724VCREATE_FUNCS(saturation)
725VCREATE_FUNCS(hue)
726VCREATE_FUNCS(volume)
727VCREATE_FUNCS(balance)
728VCREATE_FUNCS(bass)
729VCREATE_FUNCS(treble)
730VCREATE_FUNCS(mute)
c05c0462
MI		 731VCREATE_FUNCS(audiomode)
732VCREATE_FUNCS(res_hor)
733VCREATE_FUNCS(res_ver)
d855497e 734VCREATE_FUNCS(srate)
d855497e 735
d855497e
MI		 736/* Table definition of all controls which can be manipulated */
737static const struct pvr2_ctl_info control_defs[] = {
738 {
739 .v4l_id = V4L2_CID_BRIGHTNESS,
740 .desc = "Brightness",
741 .name = "brightness",
742 .default_value = 128,
743 DEFREF(brightness),
744 DEFINT(0,255),
745 },{
746 .v4l_id = V4L2_CID_CONTRAST,
747 .desc = "Contrast",
748 .name = "contrast",
749 .default_value = 68,
750 DEFREF(contrast),
751 DEFINT(0,127),
752 },{
753 .v4l_id = V4L2_CID_SATURATION,
754 .desc = "Saturation",
755 .name = "saturation",
756 .default_value = 64,
757 DEFREF(saturation),
758 DEFINT(0,127),
759 },{
760 .v4l_id = V4L2_CID_HUE,
761 .desc = "Hue",
762 .name = "hue",
763 .default_value = 0,
764 DEFREF(hue),
765 DEFINT(-128,127),
766 },{
767 .v4l_id = V4L2_CID_AUDIO_VOLUME,
768 .desc = "Volume",
769 .name = "volume",
139eecf9 770 .default_value = 62000,
d855497e
MI		 771 DEFREF(volume),
772 DEFINT(0,65535),
773 },{
774 .v4l_id = V4L2_CID_AUDIO_BALANCE,
775 .desc = "Balance",
776 .name = "balance",
777 .default_value = 0,
778 DEFREF(balance),
779 DEFINT(-32768,32767),
780 },{
781 .v4l_id = V4L2_CID_AUDIO_BASS,
782 .desc = "Bass",
783 .name = "bass",
784 .default_value = 0,
785 DEFREF(bass),
786 DEFINT(-32768,32767),
787 },{
788 .v4l_id = V4L2_CID_AUDIO_TREBLE,
789 .desc = "Treble",
790 .name = "treble",
791 .default_value = 0,
792 DEFREF(treble),
793 DEFINT(-32768,32767),
794 },{
795 .v4l_id = V4L2_CID_AUDIO_MUTE,
796 .desc = "Mute",
797 .name = "mute",
798 .default_value = 0,
799 DEFREF(mute),
33213963 800 DEFBOOL,
c05c0462
MI		 801 },{
802 .desc = "Video Source",
803 .name = "input",
804 .internal_id = PVR2_CID_INPUT,
805 .default_value = PVR2_CVAL_INPUT_TV,
806 DEFREF(input),
807 DEFENUM(control_values_input),
808 },{
809 .desc = "Audio Mode",
810 .name = "audio_mode",
811 .internal_id = PVR2_CID_AUDIOMODE,
812 .default_value = V4L2_TUNER_MODE_STEREO,
813 DEFREF(audiomode),
814 DEFENUM(control_values_audiomode),
815 },{
816 .desc = "Horizontal capture resolution",
817 .name = "resolution_hor",
818 .internal_id = PVR2_CID_HRES,
819 .default_value = 720,
820 DEFREF(res_hor),
3ad9fc37 821 DEFINT(19,720),
c05c0462
MI		 822 },{
823 .desc = "Vertical capture resolution",
824 .name = "resolution_ver",
825 .internal_id = PVR2_CID_VRES,
826 .default_value = 480,
827 DEFREF(res_ver),
3ad9fc37
MI		 828 DEFINT(17,576),
829 /* Hook in check for video standard and adjust maximum
830 depending on the standard. */
831 .get_max_value = ctrl_vres_max_get,
832 .get_min_value = ctrl_vres_min_get,
d855497e 833 },{
b30d2441 834 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
434449f4
MI		 835 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
836 .desc = "Audio Sampling Frequency",
d855497e 837 .name = "srate",
d855497e
MI		 838 DEFREF(srate),
839 DEFENUM(control_values_srate),
d855497e
MI		 840 },{
841 .desc = "Tuner Frequency (Hz)",
842 .name = "frequency",
843 .internal_id = PVR2_CID_FREQUENCY,
1bde0289 844 .default_value = 0,
d855497e
MI		 845 .set_value = ctrl_freq_set,
846 .get_value = ctrl_freq_get,
847 .is_dirty = ctrl_freq_is_dirty,
848 .clear_dirty = ctrl_freq_clear_dirty,
644afdb9 849 DEFINT(0,0),
25d8527a
PK		 850 /* Hook in check for input value (tv/radio) and adjust
851 max/min values accordingly */
852 .get_max_value = ctrl_freq_max_get,
853 .get_min_value = ctrl_freq_min_get,
d855497e
MI		 854 },{
855 .desc = "Channel",
856 .name = "channel",
857 .set_value = ctrl_channel_set,
858 .get_value = ctrl_channel_get,
859 DEFINT(0,FREQTABLE_SIZE),
860 },{
861 .desc = "Channel Program Frequency",
862 .name = "freq_table_value",
863 .set_value = ctrl_channelfreq_set,
864 .get_value = ctrl_channelfreq_get,
644afdb9 865 DEFINT(0,0),
1bde0289
MI		 866 /* Hook in check for input value (tv/radio) and adjust
867 max/min values accordingly */
1bde0289
MI		 868 .get_max_value = ctrl_freq_max_get,
869 .get_min_value = ctrl_freq_min_get,
d855497e
MI		 870 },{
871 .desc = "Channel Program ID",
872 .name = "freq_table_channel",
873 .set_value = ctrl_channelprog_set,
874 .get_value = ctrl_channelprog_get,
875 DEFINT(0,FREQTABLE_SIZE),
d855497e
MI		 876 },{
877 .desc = "Streaming Enabled",
878 .name = "streaming_enabled",
879 .get_value = ctrl_streamingenabled_get,
33213963 880 DEFBOOL,
d855497e
MI		 881 },{
882 .desc = "USB Speed",
883 .name = "usb_speed",
884 .get_value = ctrl_hsm_get,
885 DEFENUM(control_values_hsm),
681c7399
MI		 886 },{
887 .desc = "Master State",
888 .name = "master_state",
889 .get_value = ctrl_masterstate_get,
890 DEFENUM(pvr2_state_names),
d855497e
MI		 891 },{
892 .desc = "Signal Present",
893 .name = "signal_present",
894 .get_value = ctrl_signal_get,
18103c57
MI		 895 DEFINT(0,65535),
896 },{
897 .desc = "Audio Modes Present",
898 .name = "audio_modes_present",
899 .get_value = ctrl_audio_modes_present_get,
900 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
901 v4l. Nothing outside of this module cares about this,
902 but I reuse it in order to also reuse the
903 control_values_audiomode string table. */
904 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
905 (1 << V4L2_TUNER_MODE_STEREO)|
906 (1 << V4L2_TUNER_MODE_LANG1)|
907 (1 << V4L2_TUNER_MODE_LANG2)),
908 control_values_audiomode),
d855497e
MI		 909 },{
910 .desc = "Video Standards Available Mask",
911 .name = "video_standard_mask_available",
912 .internal_id = PVR2_CID_STDAVAIL,
913 .skip_init = !0,
914 .get_value = ctrl_stdavail_get,
915 .set_value = ctrl_stdavail_set,
916 .val_to_sym = ctrl_std_val_to_sym,
917 .sym_to_val = ctrl_std_sym_to_val,
918 .type = pvr2_ctl_bitmask,
919 },{
920 .desc = "Video Standards In Use Mask",
921 .name = "video_standard_mask_active",
922 .internal_id = PVR2_CID_STDCUR,
923 .skip_init = !0,
924 .get_value = ctrl_stdcur_get,
925 .set_value = ctrl_stdcur_set,
926 .is_dirty = ctrl_stdcur_is_dirty,
927 .clear_dirty = ctrl_stdcur_clear_dirty,
928 .val_to_sym = ctrl_std_val_to_sym,
929 .sym_to_val = ctrl_std_sym_to_val,
930 .type = pvr2_ctl_bitmask,
d855497e
MI		 931 },{
932 .desc = "Video Standard Name",
933 .name = "video_standard",
934 .internal_id = PVR2_CID_STDENUM,
935 .skip_init = !0,
936 .get_value = ctrl_stdenumcur_get,
937 .set_value = ctrl_stdenumcur_set,
938 .is_dirty = ctrl_stdenumcur_is_dirty,
939 .clear_dirty = ctrl_stdenumcur_clear_dirty,
940 .type = pvr2_ctl_enum,
941 }
942};
943
eca8ebfc 944#define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
d855497e
MI		 945
946
947const char *pvr2_config_get_name(enum pvr2_config cfg)
948{
949 switch (cfg) {
950 case pvr2_config_empty: return "empty";
951 case pvr2_config_mpeg: return "mpeg";
952 case pvr2_config_vbi: return "vbi";
16eb40d3
MI		 953 case pvr2_config_pcm: return "pcm";
954 case pvr2_config_rawvideo: return "raw video";
d855497e
MI		 955 }
956 return "<unknown>";
957}
958
959
960struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
961{
962 return hdw->usb_dev;
963}
964
965
966unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
967{
968 return hdw->serial_number;
969}
970
31a18547
MI		 971
972const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
973{
974 return hdw->bus_info;
975}
976
977
1bde0289
MI		 978unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
979{
980 return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
981}
982
983/* Set the currently tuned frequency and account for all possible
984 driver-core side effects of this action. */
985void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
986{
7c74e57e 987 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1bde0289
MI		 988 if (hdw->freqSelector) {
989 /* Swing over to radio frequency selection */
990 hdw->freqSelector = 0;
991 hdw->freqDirty = !0;
992 }
1bde0289
MI		 993 if (hdw->freqValRadio != val) {
994 hdw->freqValRadio = val;
995 hdw->freqSlotRadio = 0;
7c74e57e 996 hdw->freqDirty = !0;
1bde0289 997 }
7c74e57e 998 } else {
1bde0289
MI		 999 if (!(hdw->freqSelector)) {
1000 /* Swing over to television frequency selection */
1001 hdw->freqSelector = 1;
1002 hdw->freqDirty = !0;
1003 }
1bde0289
MI		 1004 if (hdw->freqValTelevision != val) {
1005 hdw->freqValTelevision = val;
1006 hdw->freqSlotTelevision = 0;
7c74e57e 1007 hdw->freqDirty = !0;
1bde0289 1008 }
1bde0289
MI		 1009 }
1010}
1011
d855497e
MI		 1012int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1013{
1014 return hdw->unit_number;
1015}
1016
1017
1018/* Attempt to locate one of the given set of files. Messages are logged
1019 appropriate to what has been found. The return value will be 0 or
1020 greater on success (it will be the index of the file name found) and
1021 fw_entry will be filled in. Otherwise a negative error is returned on
1022 failure. If the return value is -ENOENT then no viable firmware file
1023 could be located. */
1024static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1025 const struct firmware **fw_entry,
1026 const char *fwtypename,
1027 unsigned int fwcount,
1028 const char *fwnames[])
1029{
1030 unsigned int idx;
1031 int ret = -EINVAL;
1032 for (idx = 0; idx < fwcount; idx++) {
1033 ret = request_firmware(fw_entry,
1034 fwnames[idx],
1035 &hdw->usb_dev->dev);
1036 if (!ret) {
1037 trace_firmware("Located %s firmware: %s;"
1038 " uploading...",
1039 fwtypename,
1040 fwnames[idx]);
1041 return idx;
1042 }
1043 if (ret == -ENOENT) continue;
1044 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1045 "request_firmware fatal error with code=%d",ret);
1046 return ret;
1047 }
1048 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1049 "***WARNING***"
1050 " Device %s firmware"
1051 " seems to be missing.",
1052 fwtypename);
1053 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1054 "Did you install the pvrusb2 firmware files"
1055 " in their proper location?");
1056 if (fwcount == 1) {
1057 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1058 "request_firmware unable to locate %s file %s",
1059 fwtypename,fwnames[0]);
1060 } else {
1061 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1062 "request_firmware unable to locate"
1063 " one of the following %s files:",
1064 fwtypename);
1065 for (idx = 0; idx < fwcount; idx++) {
1066 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1067 "request_firmware: Failed to find %s",
1068 fwnames[idx]);
1069 }
1070 }
1071 return ret;
1072}
1073
1074
1075/*
1076 * pvr2_upload_firmware1().
1077 *
1078 * Send the 8051 firmware to the device. After the upload, arrange for
1079 * device to re-enumerate.
1080 *
1081 * NOTE : the pointer to the firmware data given by request_firmware()
1082 * is not suitable for an usb transaction.
1083 *
1084 */
07e337ee 1085static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
d855497e 1086{
a0fd1cb1 1087 const struct firmware *fw_entry = NULL;
d855497e
MI		 1088 void *fw_ptr;
1089 unsigned int pipe;
1090 int ret;
1091 u16 address;
1d643a37 1092
989eb154 1093 if (!hdw->hdw_desc->fx2_firmware.cnt) {
1d643a37 1094 hdw->fw1_state = FW1_STATE_OK;
56dcbfa0
MI		 1095 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1096 "Connected device type defines"
1097 " no firmware to upload; ignoring firmware");
1098 return -ENOTTY;
1d643a37
MI		 1099 }
1100
d855497e
MI		 1101 hdw->fw1_state = FW1_STATE_FAILED; // default result
1102
1103 trace_firmware("pvr2_upload_firmware1");
1104
1105 ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
989eb154
MI		 1106 hdw->hdw_desc->fx2_firmware.cnt,
1107 hdw->hdw_desc->fx2_firmware.lst);
d855497e
MI		 1108 if (ret < 0) {
1109 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1110 return ret;
1111 }
1112
1113 usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0);
1114 usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1115
1116 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1117
1118 if (fw_entry->size != 0x2000){
1119 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
1120 release_firmware(fw_entry);
1121 return -ENOMEM;
1122 }
1123
1124 fw_ptr = kmalloc(0x800, GFP_KERNEL);
1125 if (fw_ptr == NULL){
1126 release_firmware(fw_entry);
1127 return -ENOMEM;
1128 }
1129
1130 /* We have to hold the CPU during firmware upload. */
1131 pvr2_hdw_cpureset_assert(hdw,1);
1132
1133 /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1134 chunk. */
1135
1136 ret = 0;
1137 for(address = 0; address < fw_entry->size; address += 0x800) {
1138 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1139 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1140 0, fw_ptr, 0x800, HZ);
1141 }
1142
1143 trace_firmware("Upload done, releasing device's CPU");
1144
1145 /* Now release the CPU. It will disconnect and reconnect later. */
1146 pvr2_hdw_cpureset_assert(hdw,0);
1147
1148 kfree(fw_ptr);
1149 release_firmware(fw_entry);
1150
1151 trace_firmware("Upload done (%d bytes sent)",ret);
1152
1153 /* We should have written 8192 bytes */
1154 if (ret == 8192) {
1155 hdw->fw1_state = FW1_STATE_RELOAD;
1156 return 0;
1157 }
1158
1159 return -EIO;
1160}
1161
1162
1163/*
1164 * pvr2_upload_firmware2()
1165 *
1166 * This uploads encoder firmware on endpoint 2.
1167 *
1168 */
1169
1170int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1171{
a0fd1cb1 1172 const struct firmware *fw_entry = NULL;
d855497e 1173 void *fw_ptr;
90060d32 1174 unsigned int pipe, fw_len, fw_done, bcnt, icnt;
d855497e
MI		 1175 int actual_length;
1176 int ret = 0;
1177 int fwidx;
1178 static const char *fw_files[] = {
1179 CX2341X_FIRM_ENC_FILENAME,
1180 };
1181
989eb154 1182 if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1d643a37
MI		 1183 return 0;
1184 }
1185
d855497e
MI		 1186 trace_firmware("pvr2_upload_firmware2");
1187
1188 ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
eca8ebfc 1189 ARRAY_SIZE(fw_files), fw_files);
d855497e
MI		 1190 if (ret < 0) return ret;
1191 fwidx = ret;
1192 ret = 0;
b30d2441
MI		 1193 /* Since we're about to completely reinitialize the encoder,
1194 invalidate our cached copy of its configuration state. Next
1195 time we configure the encoder, then we'll fully configure it. */
1196 hdw->enc_cur_valid = 0;
d855497e
MI		 1197
1198 /* First prepare firmware loading */
1199 ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1200 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1201 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1202 ret |= pvr2_hdw_cmd_deep_reset(hdw);
1203 ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1204 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1205 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1206 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1207 ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1208 ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1209 ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1210 ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1211 ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1212 ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1213 ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1214 ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
567d7115
MI		 1215 LOCK_TAKE(hdw->ctl_lock); do {
1216 hdw->cmd_buffer[0] = FX2CMD_FWPOST1;
89952d13 1217 ret |= pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
567d7115
MI		 1218 hdw->cmd_buffer[0] = FX2CMD_MEMSEL;
1219 hdw->cmd_buffer[1] = 0;
89952d13 1220 ret |= pvr2_send_request(hdw,hdw->cmd_buffer,2,NULL,0);
567d7115 1221 } while (0); LOCK_GIVE(hdw->ctl_lock);
d855497e
MI		 1222
1223 if (ret) {
1224 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1225 "firmware2 upload prep failed, ret=%d",ret);
1226 release_firmware(fw_entry);
1227 return ret;
1228 }
1229
1230 /* Now send firmware */
1231
1232 fw_len = fw_entry->size;
1233
90060d32 1234 if (fw_len % sizeof(u32)) {
d855497e
MI		 1235 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1236 "size of %s firmware"
48dc30a1 1237 " must be a multiple of %zu bytes",
90060d32 1238 fw_files[fwidx],sizeof(u32));
d855497e
MI		 1239 release_firmware(fw_entry);
1240 return -1;
1241 }
1242
1243 fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1244 if (fw_ptr == NULL){
1245 release_firmware(fw_entry);
1246 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1247 "failed to allocate memory for firmware2 upload");
1248 return -ENOMEM;
1249 }
1250
1251 pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1252
90060d32
MI		 1253 fw_done = 0;
1254 for (fw_done = 0; fw_done < fw_len;) {
1255 bcnt = fw_len - fw_done;
1256 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1257 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1258 /* Usbsnoop log shows that we must swap bytes... */
1259 for (icnt = 0; icnt < bcnt/4 ; icnt++)
1260 ((u32 *)fw_ptr)[icnt] =
1261 ___swab32(((u32 *)fw_ptr)[icnt]);
1262
1263 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
d855497e 1264 &actual_length, HZ);
90060d32
MI		 1265 ret |= (actual_length != bcnt);
1266 if (ret) break;
1267 fw_done += bcnt;
d855497e
MI		 1268 }
1269
1270 trace_firmware("upload of %s : %i / %i ",
1271 fw_files[fwidx],fw_done,fw_len);
1272
1273 kfree(fw_ptr);
1274 release_firmware(fw_entry);
1275
1276 if (ret) {
1277 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1278 "firmware2 upload transfer failure");
1279 return ret;
1280 }
1281
1282 /* Finish upload */
1283
1284 ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1285 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
567d7115
MI		 1286 LOCK_TAKE(hdw->ctl_lock); do {
1287 hdw->cmd_buffer[0] = FX2CMD_MEMSEL;
1288 hdw->cmd_buffer[1] = 0;
89952d13 1289 ret |= pvr2_send_request(hdw,hdw->cmd_buffer,2,NULL,0);
567d7115 1290 } while (0); LOCK_GIVE(hdw->ctl_lock);
d855497e
MI		 1291
1292 if (ret) {
1293 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1294 "firmware2 upload post-proc failure");
d855497e
MI		 1295 }
1296 return ret;
1297}
1298
1299
681c7399
MI		 1300static const char *pvr2_get_state_name(unsigned int st)
1301{
1302 if (st < ARRAY_SIZE(pvr2_state_names)) {
1303 return pvr2_state_names[st];
d855497e 1304 }
681c7399 1305 return "???";
d855497e
MI		 1306}
1307
681c7399 1308static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
d855497e 1309{
681c7399
MI		 1310 if (!hdw->decoder_ctrl) {
1311 if (!hdw->flag_decoder_missed) {
1312 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1313 "WARNING: No decoder present");
1314 hdw->flag_decoder_missed = !0;
1315 trace_stbit("flag_decoder_missed",
1316 hdw->flag_decoder_missed);
1317 }
1318 return -EIO;
1319 }
1320 hdw->decoder_ctrl->enable(hdw->decoder_ctrl->ctxt,enablefl);
1321 return 0;
d855497e
MI		 1322}
1323
1324
681c7399 1325void pvr2_hdw_set_decoder(struct pvr2_hdw *hdw,struct pvr2_decoder_ctrl *ptr)
d855497e 1326{
681c7399
MI		 1327 if (hdw->decoder_ctrl == ptr) return;
1328 hdw->decoder_ctrl = ptr;
1329 if (hdw->decoder_ctrl && hdw->flag_decoder_missed) {
1330 hdw->flag_decoder_missed = 0;
1331 trace_stbit("flag_decoder_missed",
1332 hdw->flag_decoder_missed);
1333 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1334 "Decoder has appeared");
1335 pvr2_hdw_state_sched(hdw);
1336 }
d855497e
MI		 1337}
1338
1339
681c7399 1340int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
d855497e 1341{
681c7399 1342 return hdw->master_state;
d855497e
MI		 1343}
1344
1345
681c7399 1346static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
d855497e 1347{
681c7399
MI		 1348 if (!hdw->flag_tripped) return 0;
1349 hdw->flag_tripped = 0;
1350 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1351 "Clearing driver error statuss");
1352 return !0;
d855497e
MI		 1353}
1354
1355
681c7399 1356int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
d855497e 1357{
681c7399 1358 int fl;
d855497e 1359 LOCK_TAKE(hdw->big_lock); do {
681c7399 1360 fl = pvr2_hdw_untrip_unlocked(hdw);
d855497e 1361 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1362 if (fl) pvr2_hdw_state_sched(hdw);
1363 return 0;
d855497e
MI		 1364}
1365
1366
681c7399 1367const char *pvr2_hdw_get_state_name(unsigned int id)
d855497e 1368{
681c7399
MI		 1369 if (id >= ARRAY_SIZE(pvr2_state_names)) return NULL;
1370 return pvr2_state_names[id];
d855497e
MI		 1371}
1372
1373
1374int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1375{
681c7399 1376 return hdw->state_pipeline_req != 0;
d855497e
MI		 1377}
1378
1379
1380int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1381{
681c7399 1382 int ret,st;
d855497e 1383 LOCK_TAKE(hdw->big_lock); do {
681c7399
MI		 1384 pvr2_hdw_untrip_unlocked(hdw);
1385 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1386 hdw->state_pipeline_req = enable_flag != 0;
1387 pvr2_trace(PVR2_TRACE_START_STOP,
1388 "/*--TRACE_STREAM--*/ %s",
1389 enable_flag ? "enable" : "disable");
1390 }
1391 pvr2_hdw_state_sched(hdw);
d855497e 1392 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1393 if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1394 if (enable_flag) {
1395 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1396 if (st != PVR2_STATE_READY) return -EIO;
1397 if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1398 }
1399 }
d855497e
MI		 1400 return 0;
1401}
1402
1403
1404int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1405{
681c7399 1406 int fl;
d855497e 1407 LOCK_TAKE(hdw->big_lock);
681c7399
MI		 1408 if ((fl = (hdw->desired_stream_type != config)) != 0) {
1409 hdw->desired_stream_type = config;
1410 hdw->state_pipeline_config = 0;
1411 trace_stbit("state_pipeline_config",
1412 hdw->state_pipeline_config);
1413 pvr2_hdw_state_sched(hdw);
1414 }
d855497e 1415 LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1416 if (fl) return 0;
1417 return pvr2_hdw_wait(hdw,0);
d855497e
MI		 1418}
1419
1420
1421static int get_default_tuner_type(struct pvr2_hdw *hdw)
1422{
1423 int unit_number = hdw->unit_number;
1424 int tp = -1;
1425 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1426 tp = tuner[unit_number];
1427 }
1428 if (tp < 0) return -EINVAL;
1429 hdw->tuner_type = tp;
aaf7884d 1430 hdw->tuner_updated = !0;
d855497e
MI		 1431 return 0;
1432}
1433
1434
1435static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1436{
1437 int unit_number = hdw->unit_number;
1438 int tp = 0;
1439 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1440 tp = video_std[unit_number];
6a540254 1441 if (tp) return tp;
d855497e 1442 }
6a540254 1443 return 0;
d855497e
MI		 1444}
1445
1446
1447static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1448{
1449 int unit_number = hdw->unit_number;
1450 int tp = 0;
1451 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1452 tp = tolerance[unit_number];
1453 }
1454 return tp;
1455}
1456
1457
1458static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1459{
1460 /* Try a harmless request to fetch the eeprom's address over
1461 endpoint 1. See what happens. Only the full FX2 image can
1462 respond to this. If this probe fails then likely the FX2
1463 firmware needs be loaded. */
1464 int result;
1465 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 1466 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
d855497e
MI		 1467 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1468 hdw->cmd_buffer,1,
1469 hdw->cmd_buffer,1);
1470 if (result < 0) break;
1471 } while(0); LOCK_GIVE(hdw->ctl_lock);
1472 if (result) {
1473 pvr2_trace(PVR2_TRACE_INIT,
1474 "Probe of device endpoint 1 result status %d",
1475 result);
1476 } else {
1477 pvr2_trace(PVR2_TRACE_INIT,
1478 "Probe of device endpoint 1 succeeded");
1479 }
1480 return result == 0;
1481}
1482
9f66d4ea
MI		 1483struct pvr2_std_hack {
1484 v4l2_std_id pat; /* Pattern to match */
1485 v4l2_std_id msk; /* Which bits we care about */
1486 v4l2_std_id std; /* What additional standards or default to set */
1487};
1488
1489/* This data structure labels specific combinations of standards from
1490 tveeprom that we'll try to recognize. If we recognize one, then assume
1491 a specified default standard to use. This is here because tveeprom only
1492 tells us about available standards not the intended default standard (if
1493 any) for the device in question. We guess the default based on what has
1494 been reported as available. Note that this is only for guessing a
1495 default - which can always be overridden explicitly - and if the user
1496 has otherwise named a default then that default will always be used in
1497 place of this table. */
1498const static struct pvr2_std_hack std_eeprom_maps[] = {
1499 { /* PAL(B/G) */
1500 .pat = V4L2_STD_B|V4L2_STD_GH,
1501 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1502 },
1503 { /* NTSC(M) */
1504 .pat = V4L2_STD_MN,
1505 .std = V4L2_STD_NTSC_M,
1506 },
1507 { /* PAL(I) */
1508 .pat = V4L2_STD_PAL_I,
1509 .std = V4L2_STD_PAL_I,
1510 },
1511 { /* SECAM(L/L') */
1512 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1513 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1514 },
1515 { /* PAL(D/D1/K) */
1516 .pat = V4L2_STD_DK,
ea2562d9 1517 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
9f66d4ea
MI		 1518 },
1519};
1520
d855497e
MI		 1521static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1522{
1523 char buf[40];
1524 unsigned int bcnt;
3d290bdb 1525 v4l2_std_id std1,std2,std3;
d855497e
MI		 1526
1527 std1 = get_default_standard(hdw);
3d290bdb 1528 std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
d855497e
MI		 1529
1530 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
56585386 1531 pvr2_trace(PVR2_TRACE_STD,
56dcbfa0
MI		 1532 "Supported video standard(s) reported available"
1533 " in hardware: %.*s",
d855497e
MI		 1534 bcnt,buf);
1535
1536 hdw->std_mask_avail = hdw->std_mask_eeprom;
1537
3d290bdb 1538 std2 = (std1|std3) & ~hdw->std_mask_avail;
d855497e
MI		 1539 if (std2) {
1540 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
56585386 1541 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1542 "Expanding supported video standards"
1543 " to include: %.*s",
1544 bcnt,buf);
1545 hdw->std_mask_avail |= std2;
1546 }
1547
1548 pvr2_hdw_internal_set_std_avail(hdw);
1549
1550 if (std1) {
1551 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
56585386 1552 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1553 "Initial video standard forced to %.*s",
1554 bcnt,buf);
1555 hdw->std_mask_cur = std1;
1556 hdw->std_dirty = !0;
1557 pvr2_hdw_internal_find_stdenum(hdw);
1558 return;
1559 }
3d290bdb
MI		 1560 if (std3) {
1561 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1562 pvr2_trace(PVR2_TRACE_STD,
1563 "Initial video standard"
1564 " (determined by device type): %.*s",bcnt,buf);
1565 hdw->std_mask_cur = std3;
1566 hdw->std_dirty = !0;
1567 pvr2_hdw_internal_find_stdenum(hdw);
1568 return;
1569 }
d855497e 1570
9f66d4ea
MI		 1571 {
1572 unsigned int idx;
1573 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1574 if (std_eeprom_maps[idx].msk ?
1575 ((std_eeprom_maps[idx].pat ^
1576 hdw->std_mask_eeprom) &
1577 std_eeprom_maps[idx].msk) :
1578 (std_eeprom_maps[idx].pat !=
1579 hdw->std_mask_eeprom)) continue;
1580 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1581 std_eeprom_maps[idx].std);
56585386 1582 pvr2_trace(PVR2_TRACE_STD,
9f66d4ea
MI		 1583 "Initial video standard guessed as %.*s",
1584 bcnt,buf);
1585 hdw->std_mask_cur = std_eeprom_maps[idx].std;
1586 hdw->std_dirty = !0;
1587 pvr2_hdw_internal_find_stdenum(hdw);
1588 return;
1589 }
1590 }
1591
d855497e
MI		 1592 if (hdw->std_enum_cnt > 1) {
1593 // Autoselect the first listed standard
1594 hdw->std_enum_cur = 1;
1595 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1596 hdw->std_dirty = !0;
56585386 1597 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1598 "Initial video standard auto-selected to %s",
1599 hdw->std_defs[hdw->std_enum_cur-1].name);
1600 return;
1601 }
1602
0885ba1d 1603 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
d855497e
MI		 1604 "Unable to select a viable initial video standard");
1605}
1606
1607
1608static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
1609{
1610 int ret;
1611 unsigned int idx;
1612 struct pvr2_ctrl *cptr;
1613 int reloadFl = 0;
989eb154 1614 if (hdw->hdw_desc->fx2_firmware.cnt) {
1d643a37
MI		 1615 if (!reloadFl) {
1616 reloadFl =
1617 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
1618 == 0);
1619 if (reloadFl) {
1620 pvr2_trace(PVR2_TRACE_INIT,
1621 "USB endpoint config looks strange"
1622 "; possibly firmware needs to be"
1623 " loaded");
1624 }
d855497e 1625 }
1d643a37
MI		 1626 if (!reloadFl) {
1627 reloadFl = !pvr2_hdw_check_firmware(hdw);
1628 if (reloadFl) {
1629 pvr2_trace(PVR2_TRACE_INIT,
1630 "Check for FX2 firmware failed"
1631 "; possibly firmware needs to be"
1632 " loaded");
1633 }
d855497e 1634 }
1d643a37
MI		 1635 if (reloadFl) {
1636 if (pvr2_upload_firmware1(hdw) != 0) {
1637 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1638 "Failure uploading firmware1");
1639 }
1640 return;
d855497e 1641 }
d855497e
MI		 1642 }
1643 hdw->fw1_state = FW1_STATE_OK;
1644
1645 if (initusbreset) {
1646 pvr2_hdw_device_reset(hdw);
1647 }
1648 if (!pvr2_hdw_dev_ok(hdw)) return;
1649
989eb154
MI		 1650 for (idx = 0; idx < hdw->hdw_desc->client_modules.cnt; idx++) {
1651 request_module(hdw->hdw_desc->client_modules.lst[idx]);
d855497e
MI		 1652 }
1653
989eb154 1654 if (!hdw->hdw_desc->flag_no_powerup) {
1d643a37
MI		 1655 pvr2_hdw_cmd_powerup(hdw);
1656 if (!pvr2_hdw_dev_ok(hdw)) return;
d855497e
MI		 1657 }
1658
1659 // This step MUST happen after the earlier powerup step.
1660 pvr2_i2c_core_init(hdw);
1661 if (!pvr2_hdw_dev_ok(hdw)) return;
1662
c05c0462 1663 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
d855497e
MI		 1664 cptr = hdw->controls + idx;
1665 if (cptr->info->skip_init) continue;
1666 if (!cptr->info->set_value) continue;
1667 cptr->info->set_value(cptr,~0,cptr->info->default_value);
1668 }
1669
1bde0289
MI		 1670 /* Set up special default values for the television and radio
1671 frequencies here. It's not really important what these defaults
1672 are, but I set them to something usable in the Chicago area just
1673 to make driver testing a little easier. */
1674
1675 /* US Broadcast channel 7 (175.25 MHz) */
1676 hdw->freqValTelevision = 175250000L;
1677 /* 104.3 MHz, a usable FM station for my area */
1678 hdw->freqValRadio = 104300000L;
1679
d855497e
MI		 1680 // Do not use pvr2_reset_ctl_endpoints() here. It is not
1681 // thread-safe against the normal pvr2_send_request() mechanism.
1682 // (We should make it thread safe).
1683
aaf7884d
MI		 1684 if (hdw->hdw_desc->flag_has_hauppauge_rom) {
1685 ret = pvr2_hdw_get_eeprom_addr(hdw);
d855497e 1686 if (!pvr2_hdw_dev_ok(hdw)) return;
aaf7884d
MI		 1687 if (ret < 0) {
1688 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1689 "Unable to determine location of eeprom,"
1690 " skipping");
1691 } else {
1692 hdw->eeprom_addr = ret;
1693 pvr2_eeprom_analyze(hdw);
1694 if (!pvr2_hdw_dev_ok(hdw)) return;
1695 }
1696 } else {
1697 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
1698 hdw->tuner_updated = !0;
1699 hdw->std_mask_eeprom = V4L2_STD_ALL;
d855497e
MI		 1700 }
1701
1702 pvr2_hdw_setup_std(hdw);
1703
1704 if (!get_default_tuner_type(hdw)) {
1705 pvr2_trace(PVR2_TRACE_INIT,
1706 "pvr2_hdw_setup: Tuner type overridden to %d",
1707 hdw->tuner_type);
1708 }
1709
d855497e
MI		 1710 pvr2_i2c_core_check_stale(hdw);
1711 hdw->tuner_updated = 0;
1712
1713 if (!pvr2_hdw_dev_ok(hdw)) return;
1714
681c7399 1715 pvr2_hdw_commit_setup(hdw);
d855497e
MI		 1716
1717 hdw->vid_stream = pvr2_stream_create();
1718 if (!pvr2_hdw_dev_ok(hdw)) return;
1719 pvr2_trace(PVR2_TRACE_INIT,
1720 "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
1721 if (hdw->vid_stream) {
1722 idx = get_default_error_tolerance(hdw);
1723 if (idx) {
1724 pvr2_trace(PVR2_TRACE_INIT,
1725 "pvr2_hdw_setup: video stream %p"
1726 " setting tolerance %u",
1727 hdw->vid_stream,idx);
1728 }
1729 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
1730 PVR2_VID_ENDPOINT,idx);
1731 }
1732
1733 if (!pvr2_hdw_dev_ok(hdw)) return;
1734
d855497e 1735 hdw->flag_init_ok = !0;
681c7399
MI		 1736
1737 pvr2_hdw_state_sched(hdw);
d855497e
MI		 1738}
1739
1740
681c7399
MI		 1741/* Set up the structure and attempt to put the device into a usable state.
1742 This can be a time-consuming operation, which is why it is not done
1743 internally as part of the create() step. */
1744static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
d855497e
MI		 1745{
1746 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
681c7399 1747 do {
d855497e
MI		 1748 pvr2_hdw_setup_low(hdw);
1749 pvr2_trace(PVR2_TRACE_INIT,
1750 "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
681c7399 1751 hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
d855497e 1752 if (pvr2_hdw_dev_ok(hdw)) {
681c7399 1753 if (hdw->flag_init_ok) {
d855497e
MI		 1754 pvr2_trace(
1755 PVR2_TRACE_INFO,
1756 "Device initialization"
1757 " completed successfully.");
1758 break;
1759 }
1760 if (hdw->fw1_state == FW1_STATE_RELOAD) {
1761 pvr2_trace(
1762 PVR2_TRACE_INFO,
1763 "Device microcontroller firmware"
1764 " (re)loaded; it should now reset"
1765 " and reconnect.");
1766 break;
1767 }
1768 pvr2_trace(
1769 PVR2_TRACE_ERROR_LEGS,
1770 "Device initialization was not successful.");
1771 if (hdw->fw1_state == FW1_STATE_MISSING) {
1772 pvr2_trace(
1773 PVR2_TRACE_ERROR_LEGS,
1774 "Giving up since device"
1775 " microcontroller firmware"
1776 " appears to be missing.");
1777 break;
1778 }
1779 }
1780 if (procreload) {
1781 pvr2_trace(
1782 PVR2_TRACE_ERROR_LEGS,
1783 "Attempting pvrusb2 recovery by reloading"
1784 " primary firmware.");
1785 pvr2_trace(
1786 PVR2_TRACE_ERROR_LEGS,
1787 "If this works, device should disconnect"
1788 " and reconnect in a sane state.");
1789 hdw->fw1_state = FW1_STATE_UNKNOWN;
1790 pvr2_upload_firmware1(hdw);
1791 } else {
1792 pvr2_trace(
1793 PVR2_TRACE_ERROR_LEGS,
1794 "***WARNING*** pvrusb2 device hardware"
1795 " appears to be jammed"
1796 " and I can't clear it.");
1797 pvr2_trace(
1798 PVR2_TRACE_ERROR_LEGS,
1799 "You might need to power cycle"
1800 " the pvrusb2 device"
1801 " in order to recover.");
1802 }
681c7399 1803 } while (0);
d855497e 1804 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
d855497e
MI		 1805}
1806
1807
1808/* Create and return a structure for interacting with the underlying
1809 hardware */
1810struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
1811 const struct usb_device_id *devid)
1812{
1813 unsigned int idx,cnt1,cnt2;
1814 struct pvr2_hdw *hdw;
d855497e
MI		 1815 int valid_std_mask;
1816 struct pvr2_ctrl *cptr;
989eb154 1817 const struct pvr2_device_desc *hdw_desc;
d855497e 1818 __u8 ifnum;
b30d2441
MI		 1819 struct v4l2_queryctrl qctrl;
1820 struct pvr2_ctl_info *ciptr;
d855497e 1821
d130fa8a 1822 hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
d855497e 1823
ca545f7c 1824 hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
d855497e 1825 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
989eb154 1826 hdw,hdw_desc->description);
d855497e 1827 if (!hdw) goto fail;
681c7399
MI		 1828
1829 init_timer(&hdw->quiescent_timer);
1830 hdw->quiescent_timer.data = (unsigned long)hdw;
1831 hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
1832
1833 init_timer(&hdw->encoder_wait_timer);
1834 hdw->encoder_wait_timer.data = (unsigned long)hdw;
1835 hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
1836
1837 hdw->master_state = PVR2_STATE_DEAD;
1838
1839 init_waitqueue_head(&hdw->state_wait_data);
1840
18103c57 1841 hdw->tuner_signal_stale = !0;
b30d2441 1842 cx2341x_fill_defaults(&hdw->enc_ctl_state);
d855497e 1843
c05c0462 1844 hdw->control_cnt = CTRLDEF_COUNT;
b30d2441 1845 hdw->control_cnt += MPEGDEF_COUNT;
ca545f7c 1846 hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
d855497e
MI		 1847 GFP_KERNEL);
1848 if (!hdw->controls) goto fail;
989eb154 1849 hdw->hdw_desc = hdw_desc;
c05c0462
MI		 1850 for (idx = 0; idx < hdw->control_cnt; idx++) {
1851 cptr = hdw->controls + idx;
1852 cptr->hdw = hdw;
1853 }
d855497e
MI		 1854 for (idx = 0; idx < 32; idx++) {
1855 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
1856 }
c05c0462 1857 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
d855497e 1858 cptr = hdw->controls + idx;
d855497e
MI		 1859 cptr->info = control_defs+idx;
1860 }
b30d2441 1861 /* Define and configure additional controls from cx2341x module. */
ca545f7c 1862 hdw->mpeg_ctrl_info = kzalloc(
b30d2441
MI		 1863 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
1864 if (!hdw->mpeg_ctrl_info) goto fail;
b30d2441
MI		 1865 for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
1866 cptr = hdw->controls + idx + CTRLDEF_COUNT;
1867 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
1868 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
1869 ciptr->name = mpeg_ids[idx].strid;
1870 ciptr->v4l_id = mpeg_ids[idx].id;
1871 ciptr->skip_init = !0;
1872 ciptr->get_value = ctrl_cx2341x_get;
1873 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
1874 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
1875 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
1876 qctrl.id = ciptr->v4l_id;
1877 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
1878 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
1879 ciptr->set_value = ctrl_cx2341x_set;
1880 }
1881 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
1882 PVR2_CTLD_INFO_DESC_SIZE);
1883 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
1884 ciptr->default_value = qctrl.default_value;
1885 switch (qctrl.type) {
1886 default:
1887 case V4L2_CTRL_TYPE_INTEGER:
1888 ciptr->type = pvr2_ctl_int;
1889 ciptr->def.type_int.min_value = qctrl.minimum;
1890 ciptr->def.type_int.max_value = qctrl.maximum;
1891 break;
1892 case V4L2_CTRL_TYPE_BOOLEAN:
1893 ciptr->type = pvr2_ctl_bool;
1894 break;
1895 case V4L2_CTRL_TYPE_MENU:
1896 ciptr->type = pvr2_ctl_enum;
1897 ciptr->def.type_enum.value_names =
1898 cx2341x_ctrl_get_menu(ciptr->v4l_id);
1899 for (cnt1 = 0;
1900 ciptr->def.type_enum.value_names[cnt1] != NULL;
1901 cnt1++) { }
1902 ciptr->def.type_enum.count = cnt1;
1903 break;
1904 }
1905 cptr->info = ciptr;
1906 }
d855497e
MI		 1907
1908 // Initialize video standard enum dynamic control
1909 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
1910 if (cptr) {
1911 memcpy(&hdw->std_info_enum,cptr->info,
1912 sizeof(hdw->std_info_enum));
1913 cptr->info = &hdw->std_info_enum;
1914
1915 }
1916 // Initialize control data regarding video standard masks
1917 valid_std_mask = pvr2_std_get_usable();
1918 for (idx = 0; idx < 32; idx++) {
1919 if (!(valid_std_mask & (1 << idx))) continue;
1920 cnt1 = pvr2_std_id_to_str(
1921 hdw->std_mask_names[idx],
1922 sizeof(hdw->std_mask_names[idx])-1,
1923 1 << idx);
1924 hdw->std_mask_names[idx][cnt1] = 0;
1925 }
1926 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
1927 if (cptr) {
1928 memcpy(&hdw->std_info_avail,cptr->info,
1929 sizeof(hdw->std_info_avail));
1930 cptr->info = &hdw->std_info_avail;
1931 hdw->std_info_avail.def.type_bitmask.bit_names =
1932 hdw->std_mask_ptrs;
1933 hdw->std_info_avail.def.type_bitmask.valid_bits =
1934 valid_std_mask;
1935 }
1936 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
1937 if (cptr) {
1938 memcpy(&hdw->std_info_cur,cptr->info,
1939 sizeof(hdw->std_info_cur));
1940 cptr->info = &hdw->std_info_cur;
1941 hdw->std_info_cur.def.type_bitmask.bit_names =
1942 hdw->std_mask_ptrs;
1943 hdw->std_info_avail.def.type_bitmask.valid_bits =
1944 valid_std_mask;
1945 }
1946
1947 hdw->eeprom_addr = -1;
1948 hdw->unit_number = -1;
8079384e
MI		 1949 hdw->v4l_minor_number_video = -1;
1950 hdw->v4l_minor_number_vbi = -1;
fd5a75fe 1951 hdw->v4l_minor_number_radio = -1;
d855497e
MI		 1952 hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
1953 if (!hdw->ctl_write_buffer) goto fail;
1954 hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
1955 if (!hdw->ctl_read_buffer) goto fail;
1956 hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
1957 if (!hdw->ctl_write_urb) goto fail;
1958 hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
1959 if (!hdw->ctl_read_urb) goto fail;
1960
8df0c87c 1961 mutex_lock(&pvr2_unit_mtx); do {
d855497e
MI		 1962 for (idx = 0; idx < PVR_NUM; idx++) {
1963 if (unit_pointers[idx]) continue;
1964 hdw->unit_number = idx;
1965 unit_pointers[idx] = hdw;
1966 break;
1967 }
8df0c87c 1968 } while (0); mutex_unlock(&pvr2_unit_mtx);
d855497e
MI		 1969
1970 cnt1 = 0;
1971 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
1972 cnt1 += cnt2;
1973 if (hdw->unit_number >= 0) {
1974 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
1975 ('a' + hdw->unit_number));
1976 cnt1 += cnt2;
1977 }
1978 if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
1979 hdw->name[cnt1] = 0;
1980
681c7399
MI		 1981 hdw->workqueue = create_singlethread_workqueue(hdw->name);
1982 INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
1983 INIT_WORK(&hdw->worki2csync,pvr2_hdw_worker_i2c);
1984 INIT_WORK(&hdw->workinit,pvr2_hdw_worker_init);
1985
d855497e
MI		 1986 pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
1987 hdw->unit_number,hdw->name);
1988
1989 hdw->tuner_type = -1;
1990 hdw->flag_ok = !0;
d855497e
MI		 1991
1992 hdw->usb_intf = intf;
1993 hdw->usb_dev = interface_to_usbdev(intf);
1994
31a18547
MI		 1995 scnprintf(hdw->bus_info,sizeof(hdw->bus_info),
1996 "usb %s address %d",
1997 hdw->usb_dev->dev.bus_id,
1998 hdw->usb_dev->devnum);
1999
d855497e
MI		 2000 ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2001 usb_set_interface(hdw->usb_dev,ifnum,0);
2002
2003 mutex_init(&hdw->ctl_lock_mutex);
2004 mutex_init(&hdw->big_lock_mutex);
2005
681c7399 2006 queue_work(hdw->workqueue,&hdw->workinit);
d855497e
MI		 2007 return hdw;
2008 fail:
2009 if (hdw) {
681c7399
MI		 2010 del_timer_sync(&hdw->quiescent_timer);
2011 del_timer_sync(&hdw->encoder_wait_timer);
2012 if (hdw->workqueue) {
2013 flush_workqueue(hdw->workqueue);
2014 destroy_workqueue(hdw->workqueue);
2015 hdw->workqueue = NULL;
2016 }
5e55d2ce
MK		 2017 usb_free_urb(hdw->ctl_read_urb);
2018 usb_free_urb(hdw->ctl_write_urb);
22071a42
MK		 2019 kfree(hdw->ctl_read_buffer);
2020 kfree(hdw->ctl_write_buffer);
2021 kfree(hdw->controls);
2022 kfree(hdw->mpeg_ctrl_info);
681c7399
MI		 2023 kfree(hdw->std_defs);
2024 kfree(hdw->std_enum_names);
d855497e
MI		 2025 kfree(hdw);
2026 }
a0fd1cb1 2027 return NULL;
d855497e
MI		 2028}
2029
2030
2031/* Remove _all_ associations between this driver and the underlying USB
2032 layer. */
07e337ee 2033static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
d855497e
MI		 2034{
2035 if (hdw->flag_disconnected) return;
2036 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2037 if (hdw->ctl_read_urb) {
2038 usb_kill_urb(hdw->ctl_read_urb);
2039 usb_free_urb(hdw->ctl_read_urb);
a0fd1cb1 2040 hdw->ctl_read_urb = NULL;
d855497e
MI		 2041 }
2042 if (hdw->ctl_write_urb) {
2043 usb_kill_urb(hdw->ctl_write_urb);
2044 usb_free_urb(hdw->ctl_write_urb);
a0fd1cb1 2045 hdw->ctl_write_urb = NULL;
d855497e
MI		 2046 }
2047 if (hdw->ctl_read_buffer) {
2048 kfree(hdw->ctl_read_buffer);
a0fd1cb1 2049 hdw->ctl_read_buffer = NULL;
d855497e
MI		 2050 }
2051 if (hdw->ctl_write_buffer) {
2052 kfree(hdw->ctl_write_buffer);
a0fd1cb1 2053 hdw->ctl_write_buffer = NULL;
d855497e 2054 }
d855497e 2055 hdw->flag_disconnected = !0;
a0fd1cb1
MI		 2056 hdw->usb_dev = NULL;
2057 hdw->usb_intf = NULL;
681c7399 2058 pvr2_hdw_render_useless(hdw);
d855497e
MI		 2059}
2060
2061
2062/* Destroy hardware interaction structure */
2063void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2064{
401c27ce 2065 if (!hdw) return;
d855497e 2066 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
681c7399
MI		 2067 del_timer_sync(&hdw->quiescent_timer);
2068 del_timer_sync(&hdw->encoder_wait_timer);
2069 if (hdw->workqueue) {
2070 flush_workqueue(hdw->workqueue);
2071 destroy_workqueue(hdw->workqueue);
2072 hdw->workqueue = NULL;
2073 }
d855497e
MI		 2074 if (hdw->fw_buffer) {
2075 kfree(hdw->fw_buffer);
a0fd1cb1 2076 hdw->fw_buffer = NULL;
d855497e
MI		 2077 }
2078 if (hdw->vid_stream) {
2079 pvr2_stream_destroy(hdw->vid_stream);
a0fd1cb1 2080 hdw->vid_stream = NULL;
d855497e 2081 }
d855497e
MI		 2082 if (hdw->decoder_ctrl) {
2083 hdw->decoder_ctrl->detach(hdw->decoder_ctrl->ctxt);
2084 }
2085 pvr2_i2c_core_done(hdw);
2086 pvr2_hdw_remove_usb_stuff(hdw);
8df0c87c 2087 mutex_lock(&pvr2_unit_mtx); do {
d855497e
MI		 2088 if ((hdw->unit_number >= 0) &&
2089 (hdw->unit_number < PVR_NUM) &&
2090 (unit_pointers[hdw->unit_number] == hdw)) {
a0fd1cb1 2091 unit_pointers[hdw->unit_number] = NULL;
d855497e 2092 }
8df0c87c 2093 } while (0); mutex_unlock(&pvr2_unit_mtx);
22071a42
MK		 2094 kfree(hdw->controls);
2095 kfree(hdw->mpeg_ctrl_info);
2096 kfree(hdw->std_defs);
2097 kfree(hdw->std_enum_names);
d855497e
MI		 2098 kfree(hdw);
2099}
2100
2101
d855497e
MI		 2102int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2103{
2104 return (hdw && hdw->flag_ok);
2105}
2106
2107
2108/* Called when hardware has been unplugged */
2109void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2110{
2111 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2112 LOCK_TAKE(hdw->big_lock);
2113 LOCK_TAKE(hdw->ctl_lock);
2114 pvr2_hdw_remove_usb_stuff(hdw);
2115 LOCK_GIVE(hdw->ctl_lock);
2116 LOCK_GIVE(hdw->big_lock);
2117}
2118
2119
2120// Attempt to autoselect an appropriate value for std_enum_cur given
2121// whatever is currently in std_mask_cur
07e337ee 2122static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
d855497e
MI		 2123{
2124 unsigned int idx;
2125 for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2126 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2127 hdw->std_enum_cur = idx;
2128 return;
2129 }
2130 }
2131 hdw->std_enum_cur = 0;
2132}
2133
2134
2135// Calculate correct set of enumerated standards based on currently known
2136// set of available standards bits.
07e337ee 2137static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
d855497e
MI		 2138{
2139 struct v4l2_standard *newstd;
2140 unsigned int std_cnt;
2141 unsigned int idx;
2142
2143 newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2144
2145 if (hdw->std_defs) {
2146 kfree(hdw->std_defs);
a0fd1cb1 2147 hdw->std_defs = NULL;
d855497e
MI		 2148 }
2149 hdw->std_enum_cnt = 0;
2150 if (hdw->std_enum_names) {
2151 kfree(hdw->std_enum_names);
a0fd1cb1 2152 hdw->std_enum_names = NULL;
d855497e
MI		 2153 }
2154
2155 if (!std_cnt) {
2156 pvr2_trace(
2157 PVR2_TRACE_ERROR_LEGS,
2158 "WARNING: Failed to identify any viable standards");
2159 }
2160 hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2161 hdw->std_enum_names[0] = "none";
2162 for (idx = 0; idx < std_cnt; idx++) {
2163 hdw->std_enum_names[idx+1] =
2164 newstd[idx].name;
2165 }
2166 // Set up the dynamic control for this standard
2167 hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2168 hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2169 hdw->std_defs = newstd;
2170 hdw->std_enum_cnt = std_cnt+1;
2171 hdw->std_enum_cur = 0;
2172 hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2173}
2174
2175
2176int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2177 struct v4l2_standard *std,
2178 unsigned int idx)
2179{
2180 int ret = -EINVAL;
2181 if (!idx) return ret;
2182 LOCK_TAKE(hdw->big_lock); do {
2183 if (idx >= hdw->std_enum_cnt) break;
2184 idx--;
2185 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2186 ret = 0;
2187 } while (0); LOCK_GIVE(hdw->big_lock);
2188 return ret;
2189}
2190
2191
2192/* Get the number of defined controls */
2193unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2194{
c05c0462 2195 return hdw->control_cnt;
d855497e
MI		 2196}
2197
2198
2199/* Retrieve a control handle given its index (0..count-1) */
2200struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2201 unsigned int idx)
2202{
a0fd1cb1 2203 if (idx >= hdw->control_cnt) return NULL;
d855497e
MI		 2204 return hdw->controls + idx;
2205}
2206
2207
2208/* Retrieve a control handle given its index (0..count-1) */
2209struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2210 unsigned int ctl_id)
2211{
2212 struct pvr2_ctrl *cptr;
2213 unsigned int idx;
2214 int i;
2215
2216 /* This could be made a lot more efficient, but for now... */
c05c0462 2217 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2218 cptr = hdw->controls + idx;
2219 i = cptr->info->internal_id;
2220 if (i && (i == ctl_id)) return cptr;
2221 }
a0fd1cb1 2222 return NULL;
d855497e
MI		 2223}
2224
2225
a761f431 2226/* Given a V4L ID, retrieve the control structure associated with it. */
d855497e
MI		 2227struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2228{
2229 struct pvr2_ctrl *cptr;
2230 unsigned int idx;
2231 int i;
2232
2233 /* This could be made a lot more efficient, but for now... */
c05c0462 2234 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2235 cptr = hdw->controls + idx;
2236 i = cptr->info->v4l_id;
2237 if (i && (i == ctl_id)) return cptr;
2238 }
a0fd1cb1 2239 return NULL;
d855497e
MI		 2240}
2241
2242
a761f431
MI		 2243/* Given a V4L ID for its immediate predecessor, retrieve the control
2244 structure associated with it. */
2245struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2246 unsigned int ctl_id)
2247{
2248 struct pvr2_ctrl *cptr,*cp2;
2249 unsigned int idx;
2250 int i;
2251
2252 /* This could be made a lot more efficient, but for now... */
a0fd1cb1 2253 cp2 = NULL;
a761f431
MI		 2254 for (idx = 0; idx < hdw->control_cnt; idx++) {
2255 cptr = hdw->controls + idx;
2256 i = cptr->info->v4l_id;
2257 if (!i) continue;
2258 if (i <= ctl_id) continue;
2259 if (cp2 && (cp2->info->v4l_id < i)) continue;
2260 cp2 = cptr;
2261 }
2262 return cp2;
a0fd1cb1 2263 return NULL;
a761f431
MI		 2264}
2265
2266
d855497e
MI		 2267static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2268{
2269 switch (tp) {
2270 case pvr2_ctl_int: return "integer";
2271 case pvr2_ctl_enum: return "enum";
33213963 2272 case pvr2_ctl_bool: return "boolean";
d855497e
MI		 2273 case pvr2_ctl_bitmask: return "bitmask";
2274 }
2275 return "";
2276}
2277
2278
681c7399
MI		 2279/* Figure out if we need to commit control changes. If so, mark internal
2280 state flags to indicate this fact and return true. Otherwise do nothing
2281 else and return false. */
2282static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
d855497e 2283{
d855497e
MI		 2284 unsigned int idx;
2285 struct pvr2_ctrl *cptr;
2286 int value;
2287 int commit_flag = 0;
2288 char buf[100];
2289 unsigned int bcnt,ccnt;
2290
c05c0462 2291 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e 2292 cptr = hdw->controls + idx;
5fa1247a 2293 if (!cptr->info->is_dirty) continue;
d855497e 2294 if (!cptr->info->is_dirty(cptr)) continue;
fe23a280 2295 commit_flag = !0;
d855497e 2296
fe23a280 2297 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
d855497e
MI		 2298 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
2299 cptr->info->name);
2300 value = 0;
2301 cptr->info->get_value(cptr,&value);
2302 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
2303 buf+bcnt,
2304 sizeof(buf)-bcnt,&ccnt);
2305 bcnt += ccnt;
2306 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
2307 get_ctrl_typename(cptr->info->type));
2308 pvr2_trace(PVR2_TRACE_CTL,
2309 "/*--TRACE_COMMIT--*/ %.*s",
2310 bcnt,buf);
2311 }
2312
2313 if (!commit_flag) {
2314 /* Nothing has changed */
2315 return 0;
2316 }
2317
681c7399
MI		 2318 hdw->state_pipeline_config = 0;
2319 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
2320 pvr2_hdw_state_sched(hdw);
2321
2322 return !0;
2323}
2324
2325
2326/* Perform all operations needed to commit all control changes. This must
2327 be performed in synchronization with the pipeline state and is thus
2328 expected to be called as part of the driver's worker thread. Return
2329 true if commit successful, otherwise return false to indicate that
2330 commit isn't possible at this time. */
2331static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
2332{
2333 unsigned int idx;
2334 struct pvr2_ctrl *cptr;
2335 int disruptive_change;
2336
d855497e
MI		 2337 /* When video standard changes, reset the hres and vres values -
2338 but if the user has pending changes there, then let the changes
2339 take priority. */
2340 if (hdw->std_dirty) {
2341 /* Rewrite the vertical resolution to be appropriate to the
2342 video standard that has been selected. */
2343 int nvres;
2344 if (hdw->std_mask_cur & V4L2_STD_525_60) {
2345 nvres = 480;
2346 } else {
2347 nvres = 576;
2348 }
2349 if (nvres != hdw->res_ver_val) {
2350 hdw->res_ver_val = nvres;
2351 hdw->res_ver_dirty = !0;
2352 }
d855497e
MI		 2353 }
2354
681c7399
MI		 2355 /* If any of the below has changed, then we can't do the update
2356 while the pipeline is running. Pipeline must be paused first
2357 and decoder -> encoder connection be made quiescent before we
2358 can proceed. */
2359 disruptive_change =
2360 (hdw->std_dirty ||
2361 hdw->enc_unsafe_stale ||
2362 hdw->srate_dirty ||
2363 hdw->res_ver_dirty ||
2364 hdw->res_hor_dirty ||
2365 hdw->input_dirty ||
2366 (hdw->active_stream_type != hdw->desired_stream_type));
2367 if (disruptive_change && !hdw->state_pipeline_idle) {
2368 /* Pipeline is not idle; we can't proceed. Arrange to
2369 cause pipeline to stop so that we can try this again
2370 later.... */
2371 hdw->state_pipeline_pause = !0;
2372 return 0;
275b2e28
PK		 2373 }
2374
b30d2441
MI		 2375 if (hdw->srate_dirty) {
2376 /* Write new sample rate into control structure since
2377 * the master copy is stale. We must track srate
2378 * separate from the mpeg control structure because
2379 * other logic also uses this value. */
2380 struct v4l2_ext_controls cs;
2381 struct v4l2_ext_control c1;
2382 memset(&cs,0,sizeof(cs));
2383 memset(&c1,0,sizeof(c1));
2384 cs.controls = &c1;
2385 cs.count = 1;
2386 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
2387 c1.value = hdw->srate_val;
01f1e44f 2388 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
b30d2441 2389 }
c05c0462 2390
d855497e
MI		 2391 /* Scan i2c core at this point - before we clear all the dirty
2392 bits. Various parts of the i2c core will notice dirty bits as
2393 appropriate and arrange to broadcast or directly send updates to
2394 the client drivers in order to keep everything in sync */
2395 pvr2_i2c_core_check_stale(hdw);
2396
c05c0462 2397 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2398 cptr = hdw->controls + idx;
2399 if (!cptr->info->clear_dirty) continue;
2400 cptr->info->clear_dirty(cptr);
2401 }
2402
681c7399
MI		 2403 if (hdw->active_stream_type != hdw->desired_stream_type) {
2404 /* Handle any side effects of stream config here */
2405 hdw->active_stream_type = hdw->desired_stream_type;
2406 }
2407
d855497e
MI		 2408 /* Now execute i2c core update */
2409 pvr2_i2c_core_sync(hdw);
2410
681c7399
MI		 2411 if (hdw->state_encoder_run) {
2412 /* If encoder isn't running, then this will get worked out
2413 later when we start the encoder. */
2414 if (pvr2_encoder_adjust(hdw) < 0) return !0;
2415 }
d855497e 2416
681c7399
MI		 2417 hdw->state_pipeline_config = !0;
2418 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
2419 return !0;
d855497e
MI		 2420}
2421
2422
2423int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
2424{
681c7399
MI		 2425 int fl;
2426 LOCK_TAKE(hdw->big_lock);
2427 fl = pvr2_hdw_commit_setup(hdw);
2428 LOCK_GIVE(hdw->big_lock);
2429 if (!fl) return 0;
2430 return pvr2_hdw_wait(hdw,0);
2431}
2432
2433
2434static void pvr2_hdw_worker_i2c(struct work_struct *work)
2435{
2436 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,worki2csync);
d855497e 2437 LOCK_TAKE(hdw->big_lock); do {
681c7399 2438 pvr2_i2c_core_sync(hdw);
d855497e 2439 } while (0); LOCK_GIVE(hdw->big_lock);
d855497e
MI		 2440}
2441
2442
681c7399 2443static void pvr2_hdw_worker_poll(struct work_struct *work)
d855497e 2444{
681c7399
MI		 2445 int fl = 0;
2446 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
d855497e 2447 LOCK_TAKE(hdw->big_lock); do {
681c7399 2448 fl = pvr2_hdw_state_eval(hdw);
d855497e 2449 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 2450 if (fl && hdw->state_func) {
2451 hdw->state_func(hdw->state_data);
2452 }
d855497e
MI		 2453}
2454
2455
681c7399 2456static void pvr2_hdw_worker_init(struct work_struct *work)
d855497e 2457{
681c7399 2458 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workinit);
d855497e 2459 LOCK_TAKE(hdw->big_lock); do {
681c7399 2460 pvr2_hdw_setup(hdw);
d855497e
MI		 2461 } while (0); LOCK_GIVE(hdw->big_lock);
2462}
2463
2464
681c7399 2465static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
d855497e 2466{
681c7399
MI		 2467 return wait_event_interruptible(
2468 hdw->state_wait_data,
2469 (hdw->state_stale == 0) &&
2470 (!state || (hdw->master_state != state)));
2471}
2472
2473
2474void pvr2_hdw_set_state_callback(struct pvr2_hdw *hdw,
2475 void (*callback_func)(void *),
2476 void *callback_data)
2477{
2478 LOCK_TAKE(hdw->big_lock); do {
2479 hdw->state_data = callback_data;
2480 hdw->state_func = callback_func;
2481 } while (0); LOCK_GIVE(hdw->big_lock);
d855497e
MI		 2482}
2483
681c7399 2484
d855497e
MI		 2485/* Return name for this driver instance */
2486const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
2487{
2488 return hdw->name;
2489}
2490
2491
78a47101
MI		 2492const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
2493{
2494 return hdw->hdw_desc->description;
2495}
2496
2497
2498const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
2499{
2500 return hdw->hdw_desc->shortname;
2501}
2502
2503
d855497e
MI		 2504int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
2505{
2506 int result;
2507 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 2508 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
d855497e
MI		 2509 result = pvr2_send_request(hdw,
2510 hdw->cmd_buffer,1,
2511 hdw->cmd_buffer,1);
2512 if (result < 0) break;
2513 result = (hdw->cmd_buffer[0] != 0);
2514 } while(0); LOCK_GIVE(hdw->ctl_lock);
2515 return result;
2516}
2517
2518
18103c57
MI		 2519/* Execute poll of tuner status */
2520void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
d855497e 2521{
d855497e 2522 LOCK_TAKE(hdw->big_lock); do {
18103c57 2523 pvr2_i2c_core_status_poll(hdw);
d855497e 2524 } while (0); LOCK_GIVE(hdw->big_lock);
18103c57
MI		 2525}
2526
2527
2528/* Return information about the tuner */
2529int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
2530{
2531 LOCK_TAKE(hdw->big_lock); do {
2532 if (hdw->tuner_signal_stale) {
2533 pvr2_i2c_core_status_poll(hdw);
2534 }
2535 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
2536 } while (0); LOCK_GIVE(hdw->big_lock);
2537 return 0;
d855497e
MI		 2538}
2539
2540
2541/* Get handle to video output stream */
2542struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
2543{
2544 return hp->vid_stream;
2545}
2546
2547
2548void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
2549{
4f1a3e5b 2550 int nr = pvr2_hdw_get_unit_number(hdw);
d855497e
MI		 2551 LOCK_TAKE(hdw->big_lock); do {
2552 hdw->log_requested = !0;
4f1a3e5b 2553 printk(KERN_INFO "pvrusb2: ================= START STATUS CARD #%d =================\n", nr);
d855497e
MI		 2554 pvr2_i2c_core_check_stale(hdw);
2555 hdw->log_requested = 0;
2556 pvr2_i2c_core_sync(hdw);
b30d2441 2557 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
99eb44fe 2558 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
681c7399 2559 pvr2_hdw_state_log_state(hdw);
4f1a3e5b 2560 printk(KERN_INFO "pvrusb2: ================== END STATUS CARD #%d ==================\n", nr);
d855497e
MI		 2561 } while (0); LOCK_GIVE(hdw->big_lock);
2562}
2563
4db666cc
MI		 2564
2565/* Grab EEPROM contents, needed for direct method. */
2566#define EEPROM_SIZE 8192
2567#define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
2568static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
2569{
2570 struct i2c_msg msg[2];
2571 u8 *eeprom;
2572 u8 iadd[2];
2573 u8 addr;
2574 u16 eepromSize;
2575 unsigned int offs;
2576 int ret;
2577 int mode16 = 0;
2578 unsigned pcnt,tcnt;
2579 eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
2580 if (!eeprom) {
2581 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2582 "Failed to allocate memory"
2583 " required to read eeprom");
2584 return NULL;
2585 }
2586
2587 trace_eeprom("Value for eeprom addr from controller was 0x%x",
2588 hdw->eeprom_addr);
2589 addr = hdw->eeprom_addr;
2590 /* Seems that if the high bit is set, then the *real* eeprom
2591 address is shifted right now bit position (noticed this in
2592 newer PVR USB2 hardware) */
2593 if (addr & 0x80) addr >>= 1;
2594
2595 /* FX2 documentation states that a 16bit-addressed eeprom is
2596 expected if the I2C address is an odd number (yeah, this is
2597 strange but it's what they do) */
2598 mode16 = (addr & 1);
2599 eepromSize = (mode16 ? EEPROM_SIZE : 256);
2600 trace_eeprom("Examining %d byte eeprom at location 0x%x"
2601 " using %d bit addressing",eepromSize,addr,
2602 mode16 ? 16 : 8);
2603
2604 msg[0].addr = addr;
2605 msg[0].flags = 0;
2606 msg[0].len = mode16 ? 2 : 1;
2607 msg[0].buf = iadd;
2608 msg[1].addr = addr;
2609 msg[1].flags = I2C_M_RD;
2610
2611 /* We have to do the actual eeprom data fetch ourselves, because
2612 (1) we're only fetching part of the eeprom, and (2) if we were
2613 getting the whole thing our I2C driver can't grab it in one
2614 pass - which is what tveeprom is otherwise going to attempt */
2615 memset(eeprom,0,EEPROM_SIZE);
2616 for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
2617 pcnt = 16;
2618 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
2619 offs = tcnt + (eepromSize - EEPROM_SIZE);
2620 if (mode16) {
2621 iadd[0] = offs >> 8;
2622 iadd[1] = offs;
2623 } else {
2624 iadd[0] = offs;
2625 }
2626 msg[1].len = pcnt;
2627 msg[1].buf = eeprom+tcnt;
2628 if ((ret = i2c_transfer(&hdw->i2c_adap,
2629 msg,ARRAY_SIZE(msg))) != 2) {
2630 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2631 "eeprom fetch set offs err=%d",ret);
2632 kfree(eeprom);
2633 return NULL;
2634 }
2635 }
2636 return eeprom;
2637}
2638
2639
2640void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
2641 int prom_flag,
2642 int enable_flag)
d855497e
MI		 2643{
2644 int ret;
2645 u16 address;
2646 unsigned int pipe;
2647 LOCK_TAKE(hdw->big_lock); do {
5fa1247a 2648 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
d855497e
MI		 2649
2650 if (!enable_flag) {
2651 pvr2_trace(PVR2_TRACE_FIRMWARE,
2652 "Cleaning up after CPU firmware fetch");
2653 kfree(hdw->fw_buffer);
a0fd1cb1 2654 hdw->fw_buffer = NULL;
d855497e 2655 hdw->fw_size = 0;
4db666cc
MI		 2656 if (hdw->fw_cpu_flag) {
2657 /* Now release the CPU. It will disconnect
2658 and reconnect later. */
2659 pvr2_hdw_cpureset_assert(hdw,0);
2660 }
d855497e
MI		 2661 break;
2662 }
2663
4db666cc
MI		 2664 hdw->fw_cpu_flag = (prom_flag == 0);
2665 if (hdw->fw_cpu_flag) {
2666 pvr2_trace(PVR2_TRACE_FIRMWARE,
2667 "Preparing to suck out CPU firmware");
2668 hdw->fw_size = 0x2000;
2669 hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
2670 if (!hdw->fw_buffer) {
2671 hdw->fw_size = 0;
2672 break;
2673 }
d855497e 2674
4db666cc
MI		 2675 /* We have to hold the CPU during firmware upload. */
2676 pvr2_hdw_cpureset_assert(hdw,1);
d855497e 2677
4db666cc
MI		 2678 /* download the firmware from address 0000-1fff in 2048
2679 (=0x800) bytes chunk. */
d855497e 2680
4db666cc
MI		 2681 pvr2_trace(PVR2_TRACE_FIRMWARE,
2682 "Grabbing CPU firmware");
2683 pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
2684 for(address = 0; address < hdw->fw_size;
2685 address += 0x800) {
2686 ret = usb_control_msg(hdw->usb_dev,pipe,
2687 0xa0,0xc0,
2688 address,0,
2689 hdw->fw_buffer+address,
2690 0x800,HZ);
2691 if (ret < 0) break;
2692 }
d855497e 2693
4db666cc
MI		 2694 pvr2_trace(PVR2_TRACE_FIRMWARE,
2695 "Done grabbing CPU firmware");
2696 } else {
2697 pvr2_trace(PVR2_TRACE_FIRMWARE,
2698 "Sucking down EEPROM contents");
2699 hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
2700 if (!hdw->fw_buffer) {
2701 pvr2_trace(PVR2_TRACE_FIRMWARE,
2702 "EEPROM content suck failed.");
2703 break;
2704 }
2705 hdw->fw_size = EEPROM_SIZE;
2706 pvr2_trace(PVR2_TRACE_FIRMWARE,
2707 "Done sucking down EEPROM contents");
2708 }
d855497e
MI		 2709
2710 } while (0); LOCK_GIVE(hdw->big_lock);
2711}
2712
2713
2714/* Return true if we're in a mode for retrieval CPU firmware */
2715int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
2716{
5fa1247a 2717 return hdw->fw_buffer != NULL;
d855497e
MI		 2718}
2719
2720
2721int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
2722 char *buf,unsigned int cnt)
2723{
2724 int ret = -EINVAL;
2725 LOCK_TAKE(hdw->big_lock); do {
2726 if (!buf) break;
2727 if (!cnt) break;
2728
2729 if (!hdw->fw_buffer) {
2730 ret = -EIO;
2731 break;
2732 }
2733
2734 if (offs >= hdw->fw_size) {
2735 pvr2_trace(PVR2_TRACE_FIRMWARE,
2736 "Read firmware data offs=%d EOF",
2737 offs);
2738 ret = 0;
2739 break;
2740 }
2741
2742 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
2743
2744 memcpy(buf,hdw->fw_buffer+offs,cnt);
2745
2746 pvr2_trace(PVR2_TRACE_FIRMWARE,
2747 "Read firmware data offs=%d cnt=%d",
2748 offs,cnt);
2749 ret = cnt;
2750 } while (0); LOCK_GIVE(hdw->big_lock);
2751
2752 return ret;
2753}
2754
2755
fd5a75fe 2756int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
8079384e 2757 enum pvr2_v4l_type index)
d855497e 2758{
fd5a75fe 2759 switch (index) {
8079384e
MI		 2760 case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
2761 case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
2762 case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
fd5a75fe
MI		 2763 default: return -1;
2764 }
d855497e
MI		 2765}
2766
2767
2fdf3d9c 2768/* Store a v4l minor device number */
fd5a75fe 2769void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
8079384e 2770 enum pvr2_v4l_type index,int v)
d855497e 2771{
fd5a75fe 2772 switch (index) {
8079384e
MI		 2773 case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
2774 case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
2775 case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
fd5a75fe
MI		 2776 default: break;
2777 }
d855497e
MI		 2778}
2779
2780
7d12e780 2781static void pvr2_ctl_write_complete(struct urb *urb)
d855497e
MI		 2782{
2783 struct pvr2_hdw *hdw = urb->context;
2784 hdw->ctl_write_pend_flag = 0;
2785 if (hdw->ctl_read_pend_flag) return;
2786 complete(&hdw->ctl_done);
2787}
2788
2789
7d12e780 2790static void pvr2_ctl_read_complete(struct urb *urb)
d855497e
MI		 2791{
2792 struct pvr2_hdw *hdw = urb->context;
2793 hdw->ctl_read_pend_flag = 0;
2794 if (hdw->ctl_write_pend_flag) return;
2795 complete(&hdw->ctl_done);
2796}
2797
2798
2799static void pvr2_ctl_timeout(unsigned long data)
2800{
2801 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
2802 if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2803 hdw->ctl_timeout_flag = !0;
5e55d2ce 2804 if (hdw->ctl_write_pend_flag)
d855497e 2805 usb_unlink_urb(hdw->ctl_write_urb);
5e55d2ce 2806 if (hdw->ctl_read_pend_flag)
d855497e 2807 usb_unlink_urb(hdw->ctl_read_urb);
d855497e
MI		 2808 }
2809}
2810
2811
e61b6fc5
MI		 2812/* Issue a command and get a response from the device. This extended
2813 version includes a probe flag (which if set means that device errors
2814 should not be logged or treated as fatal) and a timeout in jiffies.
2815 This can be used to non-lethally probe the health of endpoint 1. */
07e337ee
AB		 2816static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
2817 unsigned int timeout,int probe_fl,
2818 void *write_data,unsigned int write_len,
2819 void *read_data,unsigned int read_len)
d855497e
MI		 2820{
2821 unsigned int idx;
2822 int status = 0;
2823 struct timer_list timer;
2824 if (!hdw->ctl_lock_held) {
2825 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2826 "Attempted to execute control transfer"
2827 " without lock!!");
2828 return -EDEADLK;
2829 }
681c7399 2830 if (!hdw->flag_ok && !probe_fl) {
d855497e
MI		 2831 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2832 "Attempted to execute control transfer"
2833 " when device not ok");
2834 return -EIO;
2835 }
2836 if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
2837 if (!probe_fl) {
2838 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2839 "Attempted to execute control transfer"
2840 " when USB is disconnected");
2841 }
2842 return -ENOTTY;
2843 }
2844
2845 /* Ensure that we have sane parameters */
2846 if (!write_data) write_len = 0;
2847 if (!read_data) read_len = 0;
2848 if (write_len > PVR2_CTL_BUFFSIZE) {
2849 pvr2_trace(
2850 PVR2_TRACE_ERROR_LEGS,
2851 "Attempted to execute %d byte"
2852 " control-write transfer (limit=%d)",
2853 write_len,PVR2_CTL_BUFFSIZE);
2854 return -EINVAL;
2855 }
2856 if (read_len > PVR2_CTL_BUFFSIZE) {
2857 pvr2_trace(
2858 PVR2_TRACE_ERROR_LEGS,
2859 "Attempted to execute %d byte"
2860 " control-read transfer (limit=%d)",
2861 write_len,PVR2_CTL_BUFFSIZE);
2862 return -EINVAL;
2863 }
2864 if ((!write_len) && (!read_len)) {
2865 pvr2_trace(
2866 PVR2_TRACE_ERROR_LEGS,
2867 "Attempted to execute null control transfer?");
2868 return -EINVAL;
2869 }
2870
2871
2872 hdw->cmd_debug_state = 1;
2873 if (write_len) {
2874 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
2875 } else {
2876 hdw->cmd_debug_code = 0;
2877 }
2878 hdw->cmd_debug_write_len = write_len;
2879 hdw->cmd_debug_read_len = read_len;
2880
2881 /* Initialize common stuff */
2882 init_completion(&hdw->ctl_done);
2883 hdw->ctl_timeout_flag = 0;
2884 hdw->ctl_write_pend_flag = 0;
2885 hdw->ctl_read_pend_flag = 0;
2886 init_timer(&timer);
2887 timer.expires = jiffies + timeout;
2888 timer.data = (unsigned long)hdw;
2889 timer.function = pvr2_ctl_timeout;
2890
2891 if (write_len) {
2892 hdw->cmd_debug_state = 2;
2893 /* Transfer write data to internal buffer */
2894 for (idx = 0; idx < write_len; idx++) {
2895 hdw->ctl_write_buffer[idx] =
2896 ((unsigned char *)write_data)[idx];
2897 }
2898 /* Initiate a write request */
2899 usb_fill_bulk_urb(hdw->ctl_write_urb,
2900 hdw->usb_dev,
2901 usb_sndbulkpipe(hdw->usb_dev,
2902 PVR2_CTL_WRITE_ENDPOINT),
2903 hdw->ctl_write_buffer,
2904 write_len,
2905 pvr2_ctl_write_complete,
2906 hdw);
2907 hdw->ctl_write_urb->actual_length = 0;
2908 hdw->ctl_write_pend_flag = !0;
2909 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
2910 if (status < 0) {
2911 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2912 "Failed to submit write-control"
2913 " URB status=%d",status);
2914 hdw->ctl_write_pend_flag = 0;
2915 goto done;
2916 }
2917 }
2918
2919 if (read_len) {
2920 hdw->cmd_debug_state = 3;
2921 memset(hdw->ctl_read_buffer,0x43,read_len);
2922 /* Initiate a read request */
2923 usb_fill_bulk_urb(hdw->ctl_read_urb,
2924 hdw->usb_dev,
2925 usb_rcvbulkpipe(hdw->usb_dev,
2926 PVR2_CTL_READ_ENDPOINT),
2927 hdw->ctl_read_buffer,
2928 read_len,
2929 pvr2_ctl_read_complete,
2930 hdw);
2931 hdw->ctl_read_urb->actual_length = 0;
2932 hdw->ctl_read_pend_flag = !0;
2933 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
2934 if (status < 0) {
2935 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2936 "Failed to submit read-control"
2937 " URB status=%d",status);
2938 hdw->ctl_read_pend_flag = 0;
2939 goto done;
2940 }
2941 }
2942
2943 /* Start timer */
2944 add_timer(&timer);
2945
2946 /* Now wait for all I/O to complete */
2947 hdw->cmd_debug_state = 4;
2948 while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2949 wait_for_completion(&hdw->ctl_done);
2950 }
2951 hdw->cmd_debug_state = 5;
2952
2953 /* Stop timer */
2954 del_timer_sync(&timer);
2955
2956 hdw->cmd_debug_state = 6;
2957 status = 0;
2958
2959 if (hdw->ctl_timeout_flag) {
2960 status = -ETIMEDOUT;
2961 if (!probe_fl) {
2962 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2963 "Timed out control-write");
2964 }
2965 goto done;
2966 }
2967
2968 if (write_len) {
2969 /* Validate results of write request */
2970 if ((hdw->ctl_write_urb->status != 0) &&
2971 (hdw->ctl_write_urb->status != -ENOENT) &&
2972 (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
2973 (hdw->ctl_write_urb->status != -ECONNRESET)) {
2974 /* USB subsystem is reporting some kind of failure
2975 on the write */
2976 status = hdw->ctl_write_urb->status;
2977 if (!probe_fl) {
2978 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2979 "control-write URB failure,"
2980 " status=%d",
2981 status);
2982 }
2983 goto done;
2984 }
2985 if (hdw->ctl_write_urb->actual_length < write_len) {
2986 /* Failed to write enough data */
2987 status = -EIO;
2988 if (!probe_fl) {
2989 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2990 "control-write URB short,"
2991 " expected=%d got=%d",
2992 write_len,
2993 hdw->ctl_write_urb->actual_length);
2994 }
2995 goto done;
2996 }
2997 }
2998 if (read_len) {
2999 /* Validate results of read request */
3000 if ((hdw->ctl_read_urb->status != 0) &&
3001 (hdw->ctl_read_urb->status != -ENOENT) &&
3002 (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3003 (hdw->ctl_read_urb->status != -ECONNRESET)) {
3004 /* USB subsystem is reporting some kind of failure
3005 on the read */
3006 status = hdw->ctl_read_urb->status;
3007 if (!probe_fl) {
3008 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3009 "control-read URB failure,"
3010 " status=%d",
3011 status);
3012 }
3013 goto done;
3014 }
3015 if (hdw->ctl_read_urb->actual_length < read_len) {
3016 /* Failed to read enough data */
3017 status = -EIO;
3018 if (!probe_fl) {
3019 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3020 "control-read URB short,"
3021 " expected=%d got=%d",
3022 read_len,
3023 hdw->ctl_read_urb->actual_length);
3024 }
3025 goto done;
3026 }
3027 /* Transfer retrieved data out from internal buffer */
3028 for (idx = 0; idx < read_len; idx++) {
3029 ((unsigned char *)read_data)[idx] =
3030 hdw->ctl_read_buffer[idx];
3031 }
3032 }
3033
3034 done:
3035
3036 hdw->cmd_debug_state = 0;
3037 if ((status < 0) && (!probe_fl)) {
681c7399 3038 pvr2_hdw_render_useless(hdw);
d855497e
MI		 3039 }
3040 return status;
3041}
3042
3043
3044int pvr2_send_request(struct pvr2_hdw *hdw,
3045 void *write_data,unsigned int write_len,
3046 void *read_data,unsigned int read_len)
3047{
3048 return pvr2_send_request_ex(hdw,HZ*4,0,
3049 write_data,write_len,
3050 read_data,read_len);
3051}
3052
3053int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3054{
3055 int ret;
3056
3057 LOCK_TAKE(hdw->ctl_lock);
3058
8d364363 3059 hdw->cmd_buffer[0] = FX2CMD_REG_WRITE; /* write register prefix */
d855497e
MI		 3060 PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
3061 hdw->cmd_buffer[5] = 0;
3062 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3063 hdw->cmd_buffer[7] = reg & 0xff;
3064
3065
3066 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
3067
3068 LOCK_GIVE(hdw->ctl_lock);
3069
3070 return ret;
3071}
3072
3073
07e337ee 3074static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
d855497e
MI		 3075{
3076 int ret = 0;
3077
3078 LOCK_TAKE(hdw->ctl_lock);
3079
8d364363 3080 hdw->cmd_buffer[0] = FX2CMD_REG_READ; /* read register prefix */
d855497e
MI		 3081 hdw->cmd_buffer[1] = 0;
3082 hdw->cmd_buffer[2] = 0;
3083 hdw->cmd_buffer[3] = 0;
3084 hdw->cmd_buffer[4] = 0;
3085 hdw->cmd_buffer[5] = 0;
3086 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3087 hdw->cmd_buffer[7] = reg & 0xff;
3088
3089 ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
3090 *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
3091
3092 LOCK_GIVE(hdw->ctl_lock);
3093
3094 return ret;
3095}
3096
3097
681c7399 3098void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
d855497e
MI		 3099{
3100 if (!hdw->flag_ok) return;
681c7399
MI		 3101 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3102 "Device being rendered inoperable");
d855497e 3103 if (hdw->vid_stream) {
a0fd1cb1 3104 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
d855497e 3105 }
681c7399
MI		 3106 hdw->flag_ok = 0;
3107 trace_stbit("flag_ok",hdw->flag_ok);
3108 pvr2_hdw_state_sched(hdw);
d855497e
MI		 3109}
3110
3111
3112void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
3113{
3114 int ret;
3115 pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
a0fd1cb1 3116 ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
d855497e
MI		 3117 if (ret == 1) {
3118 ret = usb_reset_device(hdw->usb_dev);
3119 usb_unlock_device(hdw->usb_dev);
3120 } else {
3121 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3122 "Failed to lock USB device ret=%d",ret);
3123 }
3124 if (init_pause_msec) {
3125 pvr2_trace(PVR2_TRACE_INFO,
3126 "Waiting %u msec for hardware to settle",
3127 init_pause_msec);
3128 msleep(init_pause_msec);
3129 }
3130
3131}
3132
3133
3134void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
3135{
3136 char da[1];
3137 unsigned int pipe;
3138 int ret;
3139
3140 if (!hdw->usb_dev) return;
3141
3142 pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
3143
3144 da[0] = val ? 0x01 : 0x00;
3145
3146 /* Write the CPUCS register on the 8051. The lsb of the register
3147 is the reset bit; a 1 asserts reset while a 0 clears it. */
3148 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
3149 ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
3150 if (ret < 0) {
3151 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3152 "cpureset_assert(%d) error=%d",val,ret);
3153 pvr2_hdw_render_useless(hdw);
3154 }
3155}
3156
3157
3158int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
3159{
3160 int status;
3161 LOCK_TAKE(hdw->ctl_lock); do {
3162 pvr2_trace(PVR2_TRACE_INIT,"Requesting uproc hard reset");
8d364363 3163 hdw->cmd_buffer[0] = FX2CMD_DEEP_RESET;
a0fd1cb1 3164 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
d855497e
MI		 3165 } while (0); LOCK_GIVE(hdw->ctl_lock);
3166 return status;
3167}
3168
3169
3170int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
3171{
3172 int status;
3173 LOCK_TAKE(hdw->ctl_lock); do {
3174 pvr2_trace(PVR2_TRACE_INIT,"Requesting powerup");
8d364363 3175 hdw->cmd_buffer[0] = FX2CMD_POWER_ON;
a0fd1cb1 3176 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
d855497e
MI		 3177 } while (0); LOCK_GIVE(hdw->ctl_lock);
3178 return status;
3179}
3180
3181
3182int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
3183{
3184 if (!hdw->decoder_ctrl) {
3185 pvr2_trace(PVR2_TRACE_INIT,
3186 "Unable to reset decoder: nothing attached");
3187 return -ENOTTY;
3188 }
3189
3190 if (!hdw->decoder_ctrl->force_reset) {
3191 pvr2_trace(PVR2_TRACE_INIT,
3192 "Unable to reset decoder: not implemented");
3193 return -ENOTTY;
3194 }
3195
3196 pvr2_trace(PVR2_TRACE_INIT,
3197 "Requesting decoder reset");
3198 hdw->decoder_ctrl->force_reset(hdw->decoder_ctrl->ctxt);
3199 return 0;
3200}
3201
3202
e61b6fc5 3203/* Stop / start video stream transport */
07e337ee 3204static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
d855497e
MI		 3205{
3206 int status;
3207 LOCK_TAKE(hdw->ctl_lock); do {
8d364363
MK		 3208 hdw->cmd_buffer[0] =
3209 (runFl ? FX2CMD_STREAMING_ON : FX2CMD_STREAMING_OFF);
a0fd1cb1 3210 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
d855497e 3211 } while (0); LOCK_GIVE(hdw->ctl_lock);
d855497e
MI		 3212 return status;
3213}
3214
3215
681c7399
MI		 3216/* Evaluate whether or not state_encoder_ok can change */
3217static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
3218{
3219 if (hdw->state_encoder_ok) return 0;
3220 if (hdw->flag_tripped) return 0;
3221 if (hdw->state_encoder_run) return 0;
3222 if (hdw->state_encoder_config) return 0;
3223 if (hdw->state_decoder_run) return 0;
3224 if (hdw->state_usbstream_run) return 0;
3225 if (pvr2_upload_firmware2(hdw) < 0) {
3226 hdw->flag_tripped = !0;
3227 trace_stbit("flag_tripped",hdw->flag_tripped);
3228 return !0;
3229 }
3230 hdw->state_encoder_ok = !0;
3231 trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
3232 return !0;
3233}
3234
3235
3236/* Evaluate whether or not state_encoder_config can change */
3237static int state_eval_encoder_config(struct pvr2_hdw *hdw)
3238{
3239 if (hdw->state_encoder_config) {
3240 if (hdw->state_encoder_ok) {
3241 if (hdw->state_pipeline_req &&
3242 !hdw->state_pipeline_pause) return 0;
3243 }
3244 hdw->state_encoder_config = 0;
3245 hdw->state_encoder_waitok = 0;
3246 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
3247 /* paranoia - solve race if timer just completed */
3248 del_timer_sync(&hdw->encoder_wait_timer);
3249 } else {
3250 if (!hdw->state_encoder_ok ||
3251 !hdw->state_pipeline_idle ||
3252 hdw->state_pipeline_pause ||
3253 !hdw->state_pipeline_req ||
3254 !hdw->state_pipeline_config) {
3255 /* We must reset the enforced wait interval if
3256 anything has happened that might have disturbed
3257 the encoder. This should be a rare case. */
3258 if (timer_pending(&hdw->encoder_wait_timer)) {
3259 del_timer_sync(&hdw->encoder_wait_timer);
3260 }
3261 if (hdw->state_encoder_waitok) {
3262 /* Must clear the state - therefore we did
3263 something to a state bit and must also
3264 return true. */
3265 hdw->state_encoder_waitok = 0;
3266 trace_stbit("state_encoder_waitok",
3267 hdw->state_encoder_waitok);
3268 return !0;
3269 }
3270 return 0;
3271 }
3272 if (!hdw->state_encoder_waitok) {
3273 if (!timer_pending(&hdw->encoder_wait_timer)) {
3274 /* waitok flag wasn't set and timer isn't
3275 running. Check flag once more to avoid
3276 a race then start the timer. This is
3277 the point when we measure out a minimal
3278 quiet interval before doing something to
3279 the encoder. */
3280 if (!hdw->state_encoder_waitok) {
3281 hdw->encoder_wait_timer.expires =
3282 jiffies + (HZ*50/1000);
3283 add_timer(&hdw->encoder_wait_timer);
3284 }
3285 }
3286 /* We can't continue until we know we have been
3287 quiet for the interval measured by this
3288 timer. */
3289 return 0;
3290 }
3291 pvr2_encoder_configure(hdw);
3292 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
3293 }
3294 trace_stbit("state_encoder_config",hdw->state_encoder_config);
3295 return !0;
3296}
3297
3298
3299/* Evaluate whether or not state_encoder_run can change */
3300static int state_eval_encoder_run(struct pvr2_hdw *hdw)
3301{
3302 if (hdw->state_encoder_run) {
3303 if (hdw->state_encoder_ok) {
3304 if (hdw->state_decoder_run) return 0;
3305 if (pvr2_encoder_stop(hdw) < 0) return !0;
3306 }
3307 hdw->state_encoder_run = 0;
3308 } else {
3309 if (!hdw->state_encoder_ok) return 0;
3310 if (!hdw->state_decoder_run) return 0;
3311 if (pvr2_encoder_start(hdw) < 0) return !0;
3312 hdw->state_encoder_run = !0;
3313 }
3314 trace_stbit("state_encoder_run",hdw->state_encoder_run);
3315 return !0;
3316}
3317
3318
3319/* Timeout function for quiescent timer. */
3320static void pvr2_hdw_quiescent_timeout(unsigned long data)
3321{
3322 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3323 hdw->state_decoder_quiescent = !0;
3324 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
3325 hdw->state_stale = !0;
3326 queue_work(hdw->workqueue,&hdw->workpoll);
3327}
3328
3329
3330/* Timeout function for encoder wait timer. */
3331static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
3332{
3333 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3334 hdw->state_encoder_waitok = !0;
3335 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
3336 hdw->state_stale = !0;
3337 queue_work(hdw->workqueue,&hdw->workpoll);
3338}
3339
3340
3341/* Evaluate whether or not state_decoder_run can change */
3342static int state_eval_decoder_run(struct pvr2_hdw *hdw)
3343{
3344 if (hdw->state_decoder_run) {
3345 if (hdw->state_encoder_ok) {
3346 if (hdw->state_pipeline_req &&
3347 !hdw->state_pipeline_pause) return 0;
3348 }
3349 if (!hdw->flag_decoder_missed) {
3350 pvr2_decoder_enable(hdw,0);
3351 }
3352 hdw->state_decoder_quiescent = 0;
3353 hdw->state_decoder_run = 0;
3354 /* paranoia - solve race if timer just completed */
3355 del_timer_sync(&hdw->quiescent_timer);
3356 } else {
3357 if (!hdw->state_decoder_quiescent) {
3358 if (!timer_pending(&hdw->quiescent_timer)) {
3359 /* We don't do something about the
3360 quiescent timer until right here because
3361 we also want to catch cases where the
3362 decoder was already not running (like
3363 after initialization) as opposed to
3364 knowing that we had just stopped it.
3365 The second flag check is here to cover a
3366 race - the timer could have run and set
3367 this flag just after the previous check
3368 but before we did the pending check. */
3369 if (!hdw->state_decoder_quiescent) {
3370 hdw->quiescent_timer.expires =
3371 jiffies + (HZ*50/1000);
3372 add_timer(&hdw->quiescent_timer);
3373 }
3374 }
3375 /* Don't allow decoder to start again until it has
3376 been quiesced first. This little detail should
3377 hopefully further stabilize the encoder. */
3378 return 0;
3379 }
3380 if (!hdw->state_pipeline_req ||
3381 hdw->state_pipeline_pause ||
3382 !hdw->state_pipeline_config ||
3383 !hdw->state_encoder_config ||
3384 !hdw->state_encoder_ok) return 0;
3385 del_timer_sync(&hdw->quiescent_timer);
3386 if (hdw->flag_decoder_missed) return 0;
3387 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
3388 hdw->state_decoder_quiescent = 0;
3389 hdw->state_decoder_run = !0;
3390 }
3391 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
3392 trace_stbit("state_decoder_run",hdw->state_decoder_run);
3393 return !0;
3394}
3395
3396
3397/* Evaluate whether or not state_usbstream_run can change */
3398static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
3399{
3400 if (hdw->state_usbstream_run) {
3401 if (hdw->state_encoder_ok) {
3402 if (hdw->state_encoder_run) return 0;
3403 }
3404 pvr2_hdw_cmd_usbstream(hdw,0);
3405 hdw->state_usbstream_run = 0;
3406 } else {
3407 if (!hdw->state_encoder_ok ||
3408 !hdw->state_encoder_run ||
3409 !hdw->state_pipeline_req ||
3410 hdw->state_pipeline_pause) return 0;
3411 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
3412 hdw->state_usbstream_run = !0;
3413 }
3414 trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
3415 return !0;
3416}
3417
3418
3419/* Attempt to configure pipeline, if needed */
3420static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
3421{
3422 if (hdw->state_pipeline_config ||
3423 hdw->state_pipeline_pause) return 0;
3424 pvr2_hdw_commit_execute(hdw);
3425 return !0;
3426}
3427
3428
3429/* Update pipeline idle and pipeline pause tracking states based on other
3430 inputs. This must be called whenever the other relevant inputs have
3431 changed. */
3432static int state_update_pipeline_state(struct pvr2_hdw *hdw)
3433{
3434 unsigned int st;
3435 int updatedFl = 0;
3436 /* Update pipeline state */
3437 st = !(hdw->state_encoder_run ||
3438 hdw->state_decoder_run ||
3439 hdw->state_usbstream_run ||
3440 (!hdw->state_decoder_quiescent));
3441 if (!st != !hdw->state_pipeline_idle) {
3442 hdw->state_pipeline_idle = st;
3443 updatedFl = !0;
3444 }
3445 if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
3446 hdw->state_pipeline_pause = 0;
3447 updatedFl = !0;
3448 }
3449 return updatedFl;
3450}
3451
3452
3453typedef int (*state_eval_func)(struct pvr2_hdw *);
3454
3455/* Set of functions to be run to evaluate various states in the driver. */
3456const static state_eval_func eval_funcs[] = {
3457 state_eval_pipeline_config,
3458 state_eval_encoder_ok,
3459 state_eval_encoder_config,
3460 state_eval_decoder_run,
3461 state_eval_encoder_run,
3462 state_eval_usbstream_run,
3463};
3464
3465
3466/* Process various states and return true if we did anything interesting. */
3467static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
3468{
3469 unsigned int i;
3470 int state_updated = 0;
3471 int check_flag;
3472
3473 if (!hdw->state_stale) return 0;
3474 if ((hdw->fw1_state != FW1_STATE_OK) ||
3475 !hdw->flag_ok) {
3476 hdw->state_stale = 0;
3477 return !0;
3478 }
3479 /* This loop is the heart of the entire driver. It keeps trying to
3480 evaluate various bits of driver state until nothing changes for
3481 one full iteration. Each "bit of state" tracks some global
3482 aspect of the driver, e.g. whether decoder should run, if
3483 pipeline is configured, usb streaming is on, etc. We separately
3484 evaluate each of those questions based on other driver state to
3485 arrive at the correct running configuration. */
3486 do {
3487 check_flag = 0;
3488 state_update_pipeline_state(hdw);
3489 /* Iterate over each bit of state */
3490 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
3491 if ((*eval_funcs[i])(hdw)) {
3492 check_flag = !0;
3493 state_updated = !0;
3494 state_update_pipeline_state(hdw);
3495 }
3496 }
3497 } while (check_flag && hdw->flag_ok);
3498 hdw->state_stale = 0;
3499 trace_stbit("state_stale",hdw->state_stale);
3500 return state_updated;
3501}
3502
3503
3504static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
3505 char *buf,unsigned int acnt)
3506{
3507 switch (which) {
3508 case 0:
3509 return scnprintf(
3510 buf,acnt,
3511 "driver:%s%s%s%s%s",
3512 (hdw->flag_ok ? " <ok>" : " <fail>"),
3513 (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
3514 (hdw->flag_disconnected ? " <disconnected>" :
3515 " <connected>"),
3516 (hdw->flag_tripped ? " <tripped>" : ""),
3517 (hdw->flag_decoder_missed ? " <no decoder>" : ""));
3518 case 1:
3519 return scnprintf(
3520 buf,acnt,
3521 "pipeline:%s%s%s%s",
3522 (hdw->state_pipeline_idle ? " <idle>" : ""),
3523 (hdw->state_pipeline_config ?
3524 " <configok>" : " <stale>"),
3525 (hdw->state_pipeline_req ? " <req>" : ""),
3526 (hdw->state_pipeline_pause ? " <pause>" : ""));
3527 case 2:
3528 return scnprintf(
3529 buf,acnt,
3530 "worker:%s%s%s%s%s%s",
3531 (hdw->state_decoder_run ?
3532 " <decode:run>" :
3533 (hdw->state_decoder_quiescent ?
3534 "" : " <decode:stop>")),
3535 (hdw->state_decoder_quiescent ?
3536 " <decode:quiescent>" : ""),
3537 (hdw->state_encoder_ok ?
3538 "" : " <encode:init>"),
3539 (hdw->state_encoder_run ?
3540 " <encode:run>" : " <encode:stop>"),
3541 (hdw->state_encoder_config ?
3542 " <encode:configok>" :
3543 (hdw->state_encoder_waitok ?
3544 "" : " <encode:wait>")),
3545 (hdw->state_usbstream_run ?
3546 " <usb:run>" : " <usb:stop>"));
3547 break;
3548 case 3:
3549 return scnprintf(
3550 buf,acnt,
3551 "state: %s",
3552 pvr2_get_state_name(hdw->master_state));
3553 break;
3554 default: break;
3555 }
3556 return 0;
3557}
3558
3559
3560unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
3561 char *buf,unsigned int acnt)
3562{
3563 unsigned int bcnt,ccnt,idx;
3564 bcnt = 0;
3565 LOCK_TAKE(hdw->big_lock);
3566 for (idx = 0; ; idx++) {
3567 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
3568 if (!ccnt) break;
3569 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
3570 if (!acnt) break;
3571 buf[0] = '\n'; ccnt = 1;
3572 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
3573 }
3574 LOCK_GIVE(hdw->big_lock);
3575 return bcnt;
3576}
3577
3578
3579static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
3580{
3581 char buf[128];
3582 unsigned int idx,ccnt;
3583
3584 for (idx = 0; ; idx++) {
3585 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
3586 if (!ccnt) break;
3587 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
3588 }
3589}
3590
3591
3592/* Evaluate and update the driver's current state, taking various actions
3593 as appropriate for the update. */
3594static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
3595{
3596 unsigned int st;
3597 int state_updated = 0;
3598 int callback_flag = 0;
3599
3600 pvr2_trace(PVR2_TRACE_STBITS,
3601 "Drive state check START");
3602 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
3603 pvr2_hdw_state_log_state(hdw);
3604 }
3605
3606 /* Process all state and get back over disposition */
3607 state_updated = pvr2_hdw_state_update(hdw);
3608
3609 /* Update master state based upon all other states. */
3610 if (!hdw->flag_ok) {
3611 st = PVR2_STATE_DEAD;
3612 } else if (hdw->fw1_state != FW1_STATE_OK) {
3613 st = PVR2_STATE_COLD;
3614 } else if (!hdw->state_encoder_ok) {
3615 st = PVR2_STATE_WARM;
3616 } else if (hdw->flag_tripped || hdw->flag_decoder_missed) {
3617 st = PVR2_STATE_ERROR;
3618 } else if (hdw->state_encoder_run &&
3619 hdw->state_decoder_run &&
3620 hdw->state_usbstream_run) {
3621 st = PVR2_STATE_RUN;
3622 } else {
3623 st = PVR2_STATE_READY;
3624 }
3625 if (hdw->master_state != st) {
3626 pvr2_trace(PVR2_TRACE_STATE,
3627 "Device state change from %s to %s",
3628 pvr2_get_state_name(hdw->master_state),
3629 pvr2_get_state_name(st));
3630 hdw->master_state = st;
3631 state_updated = !0;
3632 callback_flag = !0;
3633 }
3634 if (state_updated) {
3635 /* Trigger anyone waiting on any state changes here. */
3636 wake_up(&hdw->state_wait_data);
3637 }
3638
3639 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
3640 pvr2_hdw_state_log_state(hdw);
3641 }
3642 pvr2_trace(PVR2_TRACE_STBITS,
3643 "Drive state check DONE callback=%d",callback_flag);
3644
3645 return callback_flag;
3646}
3647
3648
3649/* Cause kernel thread to check / update driver state */
3650static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
3651{
3652 if (hdw->state_stale) return;
3653 hdw->state_stale = !0;
3654 trace_stbit("state_stale",hdw->state_stale);
3655 queue_work(hdw->workqueue,&hdw->workpoll);
3656}
3657
3658
3659void pvr2_hdw_get_debug_info_unlocked(const struct pvr2_hdw *hdw,
3660 struct pvr2_hdw_debug_info *ptr)
d855497e
MI		 3661{
3662 ptr->big_lock_held = hdw->big_lock_held;
3663 ptr->ctl_lock_held = hdw->ctl_lock_held;
d855497e
MI		 3664 ptr->flag_disconnected = hdw->flag_disconnected;
3665 ptr->flag_init_ok = hdw->flag_init_ok;
681c7399
MI		 3666 ptr->flag_ok = hdw->flag_ok;
3667 ptr->fw1_state = hdw->fw1_state;
3668 ptr->flag_decoder_missed = hdw->flag_decoder_missed;
3669 ptr->flag_tripped = hdw->flag_tripped;
3670 ptr->state_encoder_ok = hdw->state_encoder_ok;
3671 ptr->state_encoder_run = hdw->state_encoder_run;
3672 ptr->state_decoder_run = hdw->state_decoder_run;
3673 ptr->state_usbstream_run = hdw->state_usbstream_run;
3674 ptr->state_decoder_quiescent = hdw->state_decoder_quiescent;
3675 ptr->state_pipeline_config = hdw->state_pipeline_config;
3676 ptr->state_pipeline_req = hdw->state_pipeline_req;
3677 ptr->state_pipeline_pause = hdw->state_pipeline_pause;
3678 ptr->state_pipeline_idle = hdw->state_pipeline_idle;
d855497e
MI		 3679 ptr->cmd_debug_state = hdw->cmd_debug_state;
3680 ptr->cmd_code = hdw->cmd_debug_code;
3681 ptr->cmd_debug_write_len = hdw->cmd_debug_write_len;
3682 ptr->cmd_debug_read_len = hdw->cmd_debug_read_len;
3683 ptr->cmd_debug_timeout = hdw->ctl_timeout_flag;
3684 ptr->cmd_debug_write_pend = hdw->ctl_write_pend_flag;
3685 ptr->cmd_debug_read_pend = hdw->ctl_read_pend_flag;
3686 ptr->cmd_debug_rstatus = hdw->ctl_read_urb->status;
3687 ptr->cmd_debug_wstatus = hdw->ctl_read_urb->status;
3688}
3689
3690
681c7399
MI		 3691void pvr2_hdw_get_debug_info_locked(struct pvr2_hdw *hdw,
3692 struct pvr2_hdw_debug_info *ptr)
3693{
3694 LOCK_TAKE(hdw->ctl_lock); do {
3695 pvr2_hdw_get_debug_info_unlocked(hdw,ptr);
3696 } while(0); LOCK_GIVE(hdw->ctl_lock);
3697}
3698
3699
d855497e
MI		 3700int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
3701{
3702 return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
3703}
3704
3705
3706int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
3707{
3708 return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
3709}
3710
3711
3712int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
3713{
3714 return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
3715}
3716
3717
3718int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
3719{
3720 u32 cval,nval;
3721 int ret;
3722 if (~msk) {
3723 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
3724 if (ret) return ret;
3725 nval = (cval & ~msk) | (val & msk);
3726 pvr2_trace(PVR2_TRACE_GPIO,
3727 "GPIO direction changing 0x%x:0x%x"
3728 " from 0x%x to 0x%x",
3729 msk,val,cval,nval);
3730 } else {
3731 nval = val;
3732 pvr2_trace(PVR2_TRACE_GPIO,
3733 "GPIO direction changing to 0x%x",nval);
3734 }
3735 return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
3736}
3737
3738
3739int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
3740{
3741 u32 cval,nval;
3742 int ret;
3743 if (~msk) {
3744 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
3745 if (ret) return ret;
3746 nval = (cval & ~msk) | (val & msk);
3747 pvr2_trace(PVR2_TRACE_GPIO,
3748 "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
3749 msk,val,cval,nval);
3750 } else {
3751 nval = val;
3752 pvr2_trace(PVR2_TRACE_GPIO,
3753 "GPIO output changing to 0x%x",nval);
3754 }
3755 return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
3756}
3757
3758
e61b6fc5 3759/* Find I2C address of eeprom */
07e337ee 3760static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
d855497e
MI		 3761{
3762 int result;
3763 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 3764 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
d855497e
MI		 3765 result = pvr2_send_request(hdw,
3766 hdw->cmd_buffer,1,
3767 hdw->cmd_buffer,1);
3768 if (result < 0) break;
3769 result = hdw->cmd_buffer[0];
3770 } while(0); LOCK_GIVE(hdw->ctl_lock);
3771 return result;
3772}
3773
3774
32ffa9ae 3775int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
f3d092b8
HV		 3776 u32 match_type, u32 match_chip, u64 reg_id,
3777 int setFl,u64 *val_ptr)
32ffa9ae
MI		 3778{
3779#ifdef CONFIG_VIDEO_ADV_DEBUG
32ffa9ae
MI		 3780 struct pvr2_i2c_client *cp;
3781 struct v4l2_register req;
6d98816f
MI		 3782 int stat = 0;
3783 int okFl = 0;
32ffa9ae 3784
201f5c9c
MI		 3785 if (!capable(CAP_SYS_ADMIN)) return -EPERM;
3786
f3d092b8
HV		 3787 req.match_type = match_type;
3788 req.match_chip = match_chip;
32ffa9ae
MI		 3789 req.reg = reg_id;
3790 if (setFl) req.val = *val_ptr;
3791 mutex_lock(&hdw->i2c_list_lock); do {
e77e2c2f 3792 list_for_each_entry(cp, &hdw->i2c_clients, list) {
8481a750
MI		 3793 if (!v4l2_chip_match_i2c_client(
3794 cp->client,
3795 req.match_type, req.match_chip)) {
f3d092b8
HV		 3796 continue;
3797 }
32ffa9ae 3798 stat = pvr2_i2c_client_cmd(
52ebc763
TP		 3799 cp,(setFl ? VIDIOC_DBG_S_REGISTER :
3800 VIDIOC_DBG_G_REGISTER),&req);
32ffa9ae 3801 if (!setFl) *val_ptr = req.val;
6d98816f
MI		 3802 okFl = !0;
3803 break;
32ffa9ae
MI		 3804 }
3805 } while (0); mutex_unlock(&hdw->i2c_list_lock);
6d98816f
MI		 3806 if (okFl) {
3807 return stat;
3808 }
32ffa9ae
MI		 3809 return -EINVAL;
3810#else
3811 return -ENOSYS;
3812#endif
3813}
3814
3815
d855497e
MI		 3816/*
3817 Stuff for Emacs to see, in order to encourage consistent editing style:
3818 *** Local Variables: ***
3819 *** mode: c ***
3820 *** fill-column: 75 ***
3821 *** tab-width: 8 ***
3822 *** c-basic-offset: 8 ***
3823 *** End: ***
3824 */
kernel source for telekom puls (alcatel/mediatek)