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V4L/DVB (11748): pvrusb2: Don't use the internal i2c client list
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / media / video / pvrusb2 / pvrusb2-hdw.c
CommitLineData
d855497e
MI		 1/*
2 *
d855497e
MI		 3 *
4 * Copyright (C) 2005 Mike Isely <isely@pobox.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 *
19 */
20
21#include <linux/errno.h>
22#include <linux/string.h>
23#include <linux/slab.h>
24#include <linux/firmware.h>
d855497e 25#include <linux/videodev2.h>
32ffa9ae 26#include <media/v4l2-common.h>
75212a02 27#include <media/tuner.h>
d855497e
MI		 28#include "pvrusb2.h"
29#include "pvrusb2-std.h"
30#include "pvrusb2-util.h"
31#include "pvrusb2-hdw.h"
32#include "pvrusb2-i2c-core.h"
d855497e
MI		 33#include "pvrusb2-eeprom.h"
34#include "pvrusb2-hdw-internal.h"
35#include "pvrusb2-encoder.h"
36#include "pvrusb2-debug.h"
8d364363 37#include "pvrusb2-fx2-cmd.h"
5f6dae80 38#include "pvrusb2-wm8775.h"
6f956512 39#include "pvrusb2-video-v4l.h"
634ba268 40#include "pvrusb2-cx2584x-v4l.h"
2a6b627f 41#include "pvrusb2-cs53l32a.h"
76891d65 42#include "pvrusb2-audio.h"
d855497e 43
1bde0289
MI		 44#define TV_MIN_FREQ 55250000L
45#define TV_MAX_FREQ 850000000L
25d8527a 46
83ce57aa
MI		 47/* This defines a minimum interval that the decoder must remain quiet
48 before we are allowed to start it running. */
49#define TIME_MSEC_DECODER_WAIT 50
50
51/* This defines a minimum interval that the encoder must remain quiet
fa98e594
MI		 52 before we are allowed to configure it. I had this originally set to
53 50msec, but Martin Dauskardt <martin.dauskardt@gmx.de> reports that
54 things work better when it's set to 100msec. */
55#define TIME_MSEC_ENCODER_WAIT 100
83ce57aa
MI		 56
57/* This defines the minimum interval that the encoder must successfully run
58 before we consider that the encoder has run at least once since its
59 firmware has been loaded. This measurement is in important for cases
60 where we can't do something until we know that the encoder has been run
61 at least once. */
62#define TIME_MSEC_ENCODER_OK 250
63
a0fd1cb1 64static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
8df0c87c 65static DEFINE_MUTEX(pvr2_unit_mtx);
d855497e 66
ff699e6b 67static int ctlchg;
ff699e6b 68static int procreload;
d855497e
MI		 69static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
70static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
71static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
ff699e6b 72static int init_pause_msec;
d855497e
MI		 73
74module_param(ctlchg, int, S_IRUGO|S_IWUSR);
75MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
76module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
77MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
d855497e
MI		 78module_param(procreload, int, S_IRUGO|S_IWUSR);
79MODULE_PARM_DESC(procreload,
80 "Attempt init failure recovery with firmware reload");
81module_param_array(tuner, int, NULL, 0444);
82MODULE_PARM_DESC(tuner,"specify installed tuner type");
83module_param_array(video_std, int, NULL, 0444);
84MODULE_PARM_DESC(video_std,"specify initial video standard");
85module_param_array(tolerance, int, NULL, 0444);
86MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
87
5a4f5da6
MK		 88/* US Broadcast channel 7 (175.25 MHz) */
89static int default_tv_freq = 175250000L;
90/* 104.3 MHz, a usable FM station for my area */
91static int default_radio_freq = 104300000L;
92
93module_param_named(tv_freq, default_tv_freq, int, 0444);
94MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
95module_param_named(radio_freq, default_radio_freq, int, 0444);
96MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
97
d855497e
MI		 98#define PVR2_CTL_WRITE_ENDPOINT 0x01
99#define PVR2_CTL_READ_ENDPOINT 0x81
100
101#define PVR2_GPIO_IN 0x9008
102#define PVR2_GPIO_OUT 0x900c
103#define PVR2_GPIO_DIR 0x9020
104
105#define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
106
107#define PVR2_FIRMWARE_ENDPOINT 0x02
108
109/* size of a firmware chunk */
110#define FIRMWARE_CHUNK_SIZE 0x2000
111
edb9dcb8
MI		 112typedef void (*pvr2_subdev_update_func)(struct pvr2_hdw *,
113 struct v4l2_subdev *);
114
115static const pvr2_subdev_update_func pvr2_module_update_functions[] = {
4ecbc28d 116 [PVR2_CLIENT_ID_WM8775] = pvr2_wm8775_subdev_update,
6f956512 117 [PVR2_CLIENT_ID_SAA7115] = pvr2_saa7115_subdev_update,
76891d65 118 [PVR2_CLIENT_ID_MSP3400] = pvr2_msp3400_subdev_update,
634ba268 119 [PVR2_CLIENT_ID_CX25840] = pvr2_cx25840_subdev_update,
2a6b627f 120 [PVR2_CLIENT_ID_CS53L32A] = pvr2_cs53l32a_subdev_update,
edb9dcb8
MI		 121};
122
e9c64a78
MI		 123static const char *module_names[] = {
124 [PVR2_CLIENT_ID_MSP3400] = "msp3400",
125 [PVR2_CLIENT_ID_CX25840] = "cx25840",
126 [PVR2_CLIENT_ID_SAA7115] = "saa7115",
127 [PVR2_CLIENT_ID_TUNER] = "tuner",
bb65242a 128 [PVR2_CLIENT_ID_DEMOD] = "tuner",
851981a1 129 [PVR2_CLIENT_ID_CS53L32A] = "cs53l32a",
5f6dae80 130 [PVR2_CLIENT_ID_WM8775] = "wm8775",
e9c64a78
MI		 131};
132
133
134static const unsigned char *module_i2c_addresses[] = {
135 [PVR2_CLIENT_ID_TUNER] = "\x60\x61\x62\x63",
bb65242a 136 [PVR2_CLIENT_ID_DEMOD] = "\x43",
1dfe6c77
MI		 137 [PVR2_CLIENT_ID_MSP3400] = "\x40",
138 [PVR2_CLIENT_ID_SAA7115] = "\x21",
ae111f76 139 [PVR2_CLIENT_ID_WM8775] = "\x1b",
0b467014 140 [PVR2_CLIENT_ID_CX25840] = "\x44",
23334a22 141 [PVR2_CLIENT_ID_CS53L32A] = "\x11",
e9c64a78
MI		 142};
143
144
27eab384
MI		 145static const char *ir_scheme_names[] = {
146 [PVR2_IR_SCHEME_NONE] = "none",
147 [PVR2_IR_SCHEME_29XXX] = "29xxx",
148 [PVR2_IR_SCHEME_24XXX] = "24xxx (29xxx emulation)",
149 [PVR2_IR_SCHEME_24XXX_MCE] = "24xxx (MCE device)",
150 [PVR2_IR_SCHEME_ZILOG] = "Zilog",
151};
152
153
b30d2441
MI		 154/* Define the list of additional controls we'll dynamically construct based
155 on query of the cx2341x module. */
156struct pvr2_mpeg_ids {
157 const char *strid;
158 int id;
159};
160static const struct pvr2_mpeg_ids mpeg_ids[] = {
161 {
162 .strid = "audio_layer",
163 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
164 },{
165 .strid = "audio_bitrate",
166 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
167 },{
168 /* Already using audio_mode elsewhere :-( */
169 .strid = "mpeg_audio_mode",
170 .id = V4L2_CID_MPEG_AUDIO_MODE,
171 },{
172 .strid = "mpeg_audio_mode_extension",
173 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
174 },{
175 .strid = "audio_emphasis",
176 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
177 },{
178 .strid = "audio_crc",
179 .id = V4L2_CID_MPEG_AUDIO_CRC,
180 },{
181 .strid = "video_aspect",
182 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
183 },{
184 .strid = "video_b_frames",
185 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
186 },{
187 .strid = "video_gop_size",
188 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
189 },{
190 .strid = "video_gop_closure",
191 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
b30d2441
MI		 192 },{
193 .strid = "video_bitrate_mode",
194 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
195 },{
196 .strid = "video_bitrate",
197 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
198 },{
199 .strid = "video_bitrate_peak",
200 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
201 },{
202 .strid = "video_temporal_decimation",
203 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
204 },{
205 .strid = "stream_type",
206 .id = V4L2_CID_MPEG_STREAM_TYPE,
207 },{
208 .strid = "video_spatial_filter_mode",
209 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
210 },{
211 .strid = "video_spatial_filter",
212 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
213 },{
214 .strid = "video_luma_spatial_filter_type",
215 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
216 },{
217 .strid = "video_chroma_spatial_filter_type",
218 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
219 },{
220 .strid = "video_temporal_filter_mode",
221 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
222 },{
223 .strid = "video_temporal_filter",
224 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
225 },{
226 .strid = "video_median_filter_type",
227 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
228 },{
229 .strid = "video_luma_median_filter_top",
230 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
231 },{
232 .strid = "video_luma_median_filter_bottom",
233 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
234 },{
235 .strid = "video_chroma_median_filter_top",
236 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
237 },{
238 .strid = "video_chroma_median_filter_bottom",
239 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
240 }
241};
eca8ebfc 242#define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
c05c0462 243
434449f4 244
d855497e 245static const char *control_values_srate[] = {
434449f4
MI		 246 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100] = "44.1 kHz",
247 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000] = "48 kHz",
248 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000] = "32 kHz",
d855497e
MI		 249};
250
251
d855497e 252
d855497e
MI		 253static const char *control_values_input[] = {
254 [PVR2_CVAL_INPUT_TV] = "television", /*xawtv needs this name*/
29bf5b1d 255 [PVR2_CVAL_INPUT_DTV] = "dtv",
d855497e
MI		 256 [PVR2_CVAL_INPUT_RADIO] = "radio",
257 [PVR2_CVAL_INPUT_SVIDEO] = "s-video",
258 [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
259};
260
261
262static const char *control_values_audiomode[] = {
263 [V4L2_TUNER_MODE_MONO] = "Mono",
264 [V4L2_TUNER_MODE_STEREO] = "Stereo",
265 [V4L2_TUNER_MODE_LANG1] = "Lang1",
266 [V4L2_TUNER_MODE_LANG2] = "Lang2",
267 [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
268};
269
270
271static const char *control_values_hsm[] = {
272 [PVR2_CVAL_HSM_FAIL] = "Fail",
273 [PVR2_CVAL_HSM_HIGH] = "High",
274 [PVR2_CVAL_HSM_FULL] = "Full",
275};
276
277
681c7399
MI		 278static const char *pvr2_state_names[] = {
279 [PVR2_STATE_NONE] = "none",
280 [PVR2_STATE_DEAD] = "dead",
281 [PVR2_STATE_COLD] = "cold",
282 [PVR2_STATE_WARM] = "warm",
283 [PVR2_STATE_ERROR] = "error",
284 [PVR2_STATE_READY] = "ready",
285 [PVR2_STATE_RUN] = "run",
d855497e
MI		 286};
287
681c7399 288
694dca2b 289struct pvr2_fx2cmd_descdef {
1c9d10d4
MI		 290 unsigned char id;
291 unsigned char *desc;
292};
293
694dca2b 294static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
1c9d10d4
MI		 295 {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
296 {FX2CMD_MEM_READ_DWORD, "read encoder dword"},
31335b13 297 {FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"},
1c9d10d4
MI		 298 {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
299 {FX2CMD_REG_WRITE, "write encoder register"},
300 {FX2CMD_REG_READ, "read encoder register"},
301 {FX2CMD_MEMSEL, "encoder memsel"},
302 {FX2CMD_I2C_WRITE, "i2c write"},
303 {FX2CMD_I2C_READ, "i2c read"},
304 {FX2CMD_GET_USB_SPEED, "get USB speed"},
305 {FX2CMD_STREAMING_ON, "stream on"},
306 {FX2CMD_STREAMING_OFF, "stream off"},
307 {FX2CMD_FWPOST1, "fwpost1"},
308 {FX2CMD_POWER_OFF, "power off"},
309 {FX2CMD_POWER_ON, "power on"},
310 {FX2CMD_DEEP_RESET, "deep reset"},
311 {FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
312 {FX2CMD_GET_IR_CODE, "get IR code"},
313 {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
314 {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
315 {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
316 {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
317 {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
318 {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
319 {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
320};
321
322
1cb03b76 323static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
681c7399
MI		 324static void pvr2_hdw_state_sched(struct pvr2_hdw *);
325static int pvr2_hdw_state_eval(struct pvr2_hdw *);
1bde0289 326static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
681c7399 327static void pvr2_hdw_worker_poll(struct work_struct *work);
681c7399
MI		 328static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
329static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
330static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
07e337ee 331static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
681c7399 332static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
07e337ee 333static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
07e337ee
AB		 334static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
335static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
681c7399
MI		 336static void pvr2_hdw_quiescent_timeout(unsigned long);
337static void pvr2_hdw_encoder_wait_timeout(unsigned long);
d913d630 338static void pvr2_hdw_encoder_run_timeout(unsigned long);
1c9d10d4 339static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
07e337ee
AB		 340static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
341 unsigned int timeout,int probe_fl,
342 void *write_data,unsigned int write_len,
343 void *read_data,unsigned int read_len);
432907f7 344static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw);
d855497e 345
681c7399
MI		 346
347static void trace_stbit(const char *name,int val)
348{
349 pvr2_trace(PVR2_TRACE_STBITS,
350 "State bit %s <-- %s",
351 name,(val ? "true" : "false"));
352}
353
d855497e
MI		 354static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
355{
356 struct pvr2_hdw *hdw = cptr->hdw;
357 if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
358 *vp = hdw->freqTable[hdw->freqProgSlot-1];
359 } else {
360 *vp = 0;
361 }
362 return 0;
363}
364
365static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
366{
367 struct pvr2_hdw *hdw = cptr->hdw;
1bde0289
MI		 368 unsigned int slotId = hdw->freqProgSlot;
369 if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
370 hdw->freqTable[slotId-1] = v;
371 /* Handle side effects correctly - if we're tuned to this
372 slot, then forgot the slot id relation since the stored
373 frequency has been changed. */
374 if (hdw->freqSelector) {
375 if (hdw->freqSlotRadio == slotId) {
376 hdw->freqSlotRadio = 0;
377 }
378 } else {
379 if (hdw->freqSlotTelevision == slotId) {
380 hdw->freqSlotTelevision = 0;
381 }
382 }
d855497e
MI		 383 }
384 return 0;
385}
386
387static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
388{
389 *vp = cptr->hdw->freqProgSlot;
390 return 0;
391}
392
393static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
394{
395 struct pvr2_hdw *hdw = cptr->hdw;
396 if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
397 hdw->freqProgSlot = v;
398 }
399 return 0;
400}
401
402static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
403{
1bde0289
MI		 404 struct pvr2_hdw *hdw = cptr->hdw;
405 *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
d855497e
MI		 406 return 0;
407}
408
1bde0289 409static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
d855497e
MI		 410{
411 unsigned freq = 0;
412 struct pvr2_hdw *hdw = cptr->hdw;
1bde0289
MI		 413 if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
414 if (slotId > 0) {
415 freq = hdw->freqTable[slotId-1];
416 if (!freq) return 0;
417 pvr2_hdw_set_cur_freq(hdw,freq);
d855497e 418 }
1bde0289
MI		 419 if (hdw->freqSelector) {
420 hdw->freqSlotRadio = slotId;
421 } else {
422 hdw->freqSlotTelevision = slotId;
d855497e
MI		 423 }
424 return 0;
425}
426
427static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
428{
1bde0289 429 *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
d855497e
MI		 430 return 0;
431}
432
433static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
434{
435 return cptr->hdw->freqDirty != 0;
436}
437
438static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
439{
440 cptr->hdw->freqDirty = 0;
441}
442
443static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
444{
1bde0289 445 pvr2_hdw_set_cur_freq(cptr->hdw,v);
d855497e
MI		 446 return 0;
447}
448
e784bfb9 449static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left)
450{
432907f7
MI		 451 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
452 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
453 if (stat != 0) {
432907f7 454 return stat;
e784bfb9 455 }
432907f7 456 *left = cap->bounds.left;
e784bfb9 457 return 0;
458}
459
460static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left)
461{
432907f7
MI		 462 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
463 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
464 if (stat != 0) {
432907f7
MI		 465 return stat;
466 }
467 *left = cap->bounds.left;
468 if (cap->bounds.width > cptr->hdw->cropw_val) {
432907f7 469 *left += cap->bounds.width - cptr->hdw->cropw_val;
e784bfb9 470 }
471 return 0;
472}
473
474static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top)
475{
432907f7
MI		 476 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
477 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
478 if (stat != 0) {
432907f7 479 return stat;
e784bfb9 480 }
432907f7 481 *top = cap->bounds.top;
e784bfb9 482 return 0;
483}
484
432907f7 485static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top)
3ad9fc37 486{
432907f7
MI		 487 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
488 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
489 if (stat != 0) {
432907f7
MI		 490 return stat;
491 }
492 *top = cap->bounds.top;
493 if (cap->bounds.height > cptr->hdw->croph_val) {
432907f7 494 *top += cap->bounds.height - cptr->hdw->croph_val;
3ad9fc37
MI		 495 }
496 return 0;
497}
498
432907f7
MI		 499static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *val)
500{
501 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
502 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
503 if (stat != 0) {
432907f7
MI		 504 return stat;
505 }
506 *val = 0;
507 if (cap->bounds.width > cptr->hdw->cropl_val) {
432907f7
MI		 508 *val = cap->bounds.width - cptr->hdw->cropl_val;
509 }
510 return 0;
511}
512
513static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *val)
514{
515 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
516 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
517 if (stat != 0) {
432907f7
MI		 518 return stat;
519 }
520 *val = 0;
521 if (cap->bounds.height > cptr->hdw->cropt_val) {
432907f7
MI		 522 *val = cap->bounds.height - cptr->hdw->cropt_val;
523 }
524 return 0;
525}
526
527static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val)
528{
529 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
530 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
531 if (stat != 0) {
432907f7
MI		 532 return stat;
533 }
534 *val = cap->bounds.left;
535 return 0;
536}
537
538static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val)
539{
540 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
541 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
542 if (stat != 0) {
432907f7
MI		 543 return stat;
544 }
545 *val = cap->bounds.top;
546 return 0;
547}
548
549static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val)
550{
551 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
552 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
553 if (stat != 0) {
432907f7
MI		 554 return stat;
555 }
556 *val = cap->bounds.width;
557 return 0;
558}
559
560static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val)
561{
562 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
563 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
564 if (stat != 0) {
432907f7
MI		 565 return stat;
566 }
567 *val = cap->bounds.height;
568 return 0;
569}
570
571static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val)
572{
573 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
574 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
575 if (stat != 0) {
432907f7
MI		 576 return stat;
577 }
578 *val = cap->defrect.left;
579 return 0;
580}
581
582static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val)
583{
584 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
585 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
586 if (stat != 0) {
432907f7
MI		 587 return stat;
588 }
589 *val = cap->defrect.top;
590 return 0;
591}
592
593static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val)
594{
595 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
596 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
597 if (stat != 0) {
432907f7
MI		 598 return stat;
599 }
600 *val = cap->defrect.width;
601 return 0;
602}
603
604static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val)
605{
606 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
607 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
608 if (stat != 0) {
432907f7
MI		 609 return stat;
610 }
611 *val = cap->defrect.height;
612 return 0;
613}
614
615static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val)
616{
617 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
618 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
619 if (stat != 0) {
432907f7
MI		 620 return stat;
621 }
622 *val = cap->pixelaspect.numerator;
623 return 0;
624}
625
626static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val)
627{
628 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
629 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
630 if (stat != 0) {
432907f7
MI		 631 return stat;
632 }
633 *val = cap->pixelaspect.denominator;
634 return 0;
635}
636
637static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
e784bfb9 638{
432907f7
MI		 639 /* Actual maximum depends on the video standard in effect. */
640 if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
641 *vp = 480;
e784bfb9 642 } else {
432907f7 643 *vp = 576;
e784bfb9 644 }
645 return 0;
646}
647
3ad9fc37
MI		 648static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
649{
989eb154
MI		 650 /* Actual minimum depends on device digitizer type. */
651 if (cptr->hdw->hdw_desc->flag_has_cx25840) {
3ad9fc37
MI		 652 *vp = 75;
653 } else {
654 *vp = 17;
655 }
656 return 0;
657}
658
1bde0289 659static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
5549f54f 660{
1bde0289
MI		 661 *vp = cptr->hdw->input_val;
662 return 0;
663}
664
29bf5b1d
MI		 665static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
666{
1cb03b76 667 return ((1 << v) & cptr->hdw->input_allowed_mask) != 0;
29bf5b1d
MI		 668}
669
1bde0289
MI		 670static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
671{
1cb03b76 672 return pvr2_hdw_set_input(cptr->hdw,v);
1bde0289
MI		 673}
674
675static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
676{
677 return cptr->hdw->input_dirty != 0;
678}
679
680static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
681{
682 cptr->hdw->input_dirty = 0;
683}
684
5549f54f 685
25d8527a
PK		 686static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
687{
644afdb9
MI		 688 unsigned long fv;
689 struct pvr2_hdw *hdw = cptr->hdw;
690 if (hdw->tuner_signal_stale) {
a51f5000 691 pvr2_hdw_status_poll(hdw);
644afdb9
MI		 692 }
693 fv = hdw->tuner_signal_info.rangehigh;
694 if (!fv) {
695 /* Safety fallback */
25d8527a 696 *vp = TV_MAX_FREQ;
644afdb9 697 return 0;
25d8527a 698 }
644afdb9
MI		 699 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
700 fv = (fv * 125) / 2;
701 } else {
702 fv = fv * 62500;
703 }
704 *vp = fv;
25d8527a
PK		 705 return 0;
706}
707
708static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
709{
644afdb9
MI		 710 unsigned long fv;
711 struct pvr2_hdw *hdw = cptr->hdw;
712 if (hdw->tuner_signal_stale) {
a51f5000 713 pvr2_hdw_status_poll(hdw);
644afdb9
MI		 714 }
715 fv = hdw->tuner_signal_info.rangelow;
716 if (!fv) {
717 /* Safety fallback */
25d8527a 718 *vp = TV_MIN_FREQ;
644afdb9
MI		 719 return 0;
720 }
721 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
722 fv = (fv * 125) / 2;
723 } else {
724 fv = fv * 62500;
25d8527a 725 }
644afdb9 726 *vp = fv;
25d8527a
PK		 727 return 0;
728}
729
b30d2441
MI		 730static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
731{
732 return cptr->hdw->enc_stale != 0;
733}
734
735static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
736{
737 cptr->hdw->enc_stale = 0;
681c7399 738 cptr->hdw->enc_unsafe_stale = 0;
b30d2441
MI		 739}
740
741static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
742{
743 int ret;
744 struct v4l2_ext_controls cs;
745 struct v4l2_ext_control c1;
746 memset(&cs,0,sizeof(cs));
747 memset(&c1,0,sizeof(c1));
748 cs.controls = &c1;
749 cs.count = 1;
750 c1.id = cptr->info->v4l_id;
01f1e44f 751 ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
b30d2441
MI		 752 VIDIOC_G_EXT_CTRLS);
753 if (ret) return ret;
754 *vp = c1.value;
755 return 0;
756}
757
758static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
759{
760 int ret;
681c7399 761 struct pvr2_hdw *hdw = cptr->hdw;
b30d2441
MI		 762 struct v4l2_ext_controls cs;
763 struct v4l2_ext_control c1;
764 memset(&cs,0,sizeof(cs));
765 memset(&c1,0,sizeof(c1));
766 cs.controls = &c1;
767 cs.count = 1;
768 c1.id = cptr->info->v4l_id;
769 c1.value = v;
681c7399
MI		 770 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
771 hdw->state_encoder_run, &cs,
b30d2441 772 VIDIOC_S_EXT_CTRLS);
681c7399
MI		 773 if (ret == -EBUSY) {
774 /* Oops. cx2341x is telling us it's not safe to change
775 this control while we're capturing. Make a note of this
776 fact so that the pipeline will be stopped the next time
777 controls are committed. Then go on ahead and store this
778 change anyway. */
779 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
780 0, &cs,
781 VIDIOC_S_EXT_CTRLS);
782 if (!ret) hdw->enc_unsafe_stale = !0;
783 }
b30d2441 784 if (ret) return ret;
681c7399 785 hdw->enc_stale = !0;
b30d2441
MI		 786 return 0;
787}
788
789static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
790{
791 struct v4l2_queryctrl qctrl;
792 struct pvr2_ctl_info *info;
793 qctrl.id = cptr->info->v4l_id;
794 cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
795 /* Strip out the const so we can adjust a function pointer. It's
796 OK to do this here because we know this is a dynamically created
797 control, so the underlying storage for the info pointer is (a)
798 private to us, and (b) not in read-only storage. Either we do
799 this or we significantly complicate the underlying control
800 implementation. */
801 info = (struct pvr2_ctl_info *)(cptr->info);
802 if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
803 if (info->set_value) {
a0fd1cb1 804 info->set_value = NULL;
b30d2441
MI		 805 }
806 } else {
807 if (!(info->set_value)) {
808 info->set_value = ctrl_cx2341x_set;
809 }
810 }
811 return qctrl.flags;
812}
813
d855497e
MI		 814static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
815{
681c7399
MI		 816 *vp = cptr->hdw->state_pipeline_req;
817 return 0;
818}
819
820static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
821{
822 *vp = cptr->hdw->master_state;
d855497e
MI		 823 return 0;
824}
825
826static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
827{
828 int result = pvr2_hdw_is_hsm(cptr->hdw);
829 *vp = PVR2_CVAL_HSM_FULL;
830 if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
831 if (result) *vp = PVR2_CVAL_HSM_HIGH;
832 return 0;
833}
834
835static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
836{
837 *vp = cptr->hdw->std_mask_avail;
838 return 0;
839}
840
841static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
842{
843 struct pvr2_hdw *hdw = cptr->hdw;
844 v4l2_std_id ns;
845 ns = hdw->std_mask_avail;
846 ns = (ns & ~m) | (v & m);
847 if (ns == hdw->std_mask_avail) return 0;
848 hdw->std_mask_avail = ns;
849 pvr2_hdw_internal_set_std_avail(hdw);
850 pvr2_hdw_internal_find_stdenum(hdw);
851 return 0;
852}
853
854static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
855 char *bufPtr,unsigned int bufSize,
856 unsigned int *len)
857{
858 *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
859 return 0;
860}
861
862static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
863 const char *bufPtr,unsigned int bufSize,
864 int *mskp,int *valp)
865{
866 int ret;
867 v4l2_std_id id;
868 ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
869 if (ret < 0) return ret;
870 if (mskp) *mskp = id;
871 if (valp) *valp = id;
872 return 0;
873}
874
875static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
876{
877 *vp = cptr->hdw->std_mask_cur;
878 return 0;
879}
880
881static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
882{
883 struct pvr2_hdw *hdw = cptr->hdw;
884 v4l2_std_id ns;
885 ns = hdw->std_mask_cur;
886 ns = (ns & ~m) | (v & m);
887 if (ns == hdw->std_mask_cur) return 0;
888 hdw->std_mask_cur = ns;
889 hdw->std_dirty = !0;
890 pvr2_hdw_internal_find_stdenum(hdw);
891 return 0;
892}
893
894static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
895{
896 return cptr->hdw->std_dirty != 0;
897}
898
899static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
900{
901 cptr->hdw->std_dirty = 0;
902}
903
904static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
905{
18103c57 906 struct pvr2_hdw *hdw = cptr->hdw;
a51f5000 907 pvr2_hdw_status_poll(hdw);
18103c57
MI		 908 *vp = hdw->tuner_signal_info.signal;
909 return 0;
910}
911
912static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
913{
914 int val = 0;
915 unsigned int subchan;
916 struct pvr2_hdw *hdw = cptr->hdw;
a51f5000 917 pvr2_hdw_status_poll(hdw);
18103c57
MI		 918 subchan = hdw->tuner_signal_info.rxsubchans;
919 if (subchan & V4L2_TUNER_SUB_MONO) {
920 val |= (1 << V4L2_TUNER_MODE_MONO);
921 }
922 if (subchan & V4L2_TUNER_SUB_STEREO) {
923 val |= (1 << V4L2_TUNER_MODE_STEREO);
924 }
925 if (subchan & V4L2_TUNER_SUB_LANG1) {
926 val |= (1 << V4L2_TUNER_MODE_LANG1);
927 }
928 if (subchan & V4L2_TUNER_SUB_LANG2) {
929 val |= (1 << V4L2_TUNER_MODE_LANG2);
930 }
931 *vp = val;
d855497e
MI		 932 return 0;
933}
934
d855497e
MI		 935
936static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
937{
938 struct pvr2_hdw *hdw = cptr->hdw;
939 if (v < 0) return -EINVAL;
940 if (v > hdw->std_enum_cnt) return -EINVAL;
941 hdw->std_enum_cur = v;
942 if (!v) return 0;
943 v--;
944 if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
945 hdw->std_mask_cur = hdw->std_defs[v].id;
946 hdw->std_dirty = !0;
947 return 0;
948}
949
950
951static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
952{
953 *vp = cptr->hdw->std_enum_cur;
954 return 0;
955}
956
957
958static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
959{
960 return cptr->hdw->std_dirty != 0;
961}
962
963
964static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
965{
966 cptr->hdw->std_dirty = 0;
967}
968
969
970#define DEFINT(vmin,vmax) \
971 .type = pvr2_ctl_int, \
972 .def.type_int.min_value = vmin, \
973 .def.type_int.max_value = vmax
974
975#define DEFENUM(tab) \
976 .type = pvr2_ctl_enum, \
27c7b710 977 .def.type_enum.count = ARRAY_SIZE(tab), \
d855497e
MI		 978 .def.type_enum.value_names = tab
979
33213963
MI		 980#define DEFBOOL \
981 .type = pvr2_ctl_bool
982
d855497e
MI		 983#define DEFMASK(msk,tab) \
984 .type = pvr2_ctl_bitmask, \
985 .def.type_bitmask.valid_bits = msk, \
986 .def.type_bitmask.bit_names = tab
987
988#define DEFREF(vname) \
989 .set_value = ctrl_set_##vname, \
990 .get_value = ctrl_get_##vname, \
991 .is_dirty = ctrl_isdirty_##vname, \
992 .clear_dirty = ctrl_cleardirty_##vname
993
994
995#define VCREATE_FUNCS(vname) \
996static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
997{*vp = cptr->hdw->vname##_val; return 0;} \
998static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
999{cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
1000static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
1001{return cptr->hdw->vname##_dirty != 0;} \
1002static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
1003{cptr->hdw->vname##_dirty = 0;}
1004
1005VCREATE_FUNCS(brightness)
1006VCREATE_FUNCS(contrast)
1007VCREATE_FUNCS(saturation)
1008VCREATE_FUNCS(hue)
1009VCREATE_FUNCS(volume)
1010VCREATE_FUNCS(balance)
1011VCREATE_FUNCS(bass)
1012VCREATE_FUNCS(treble)
1013VCREATE_FUNCS(mute)
e784bfb9 1014VCREATE_FUNCS(cropl)
1015VCREATE_FUNCS(cropt)
1016VCREATE_FUNCS(cropw)
1017VCREATE_FUNCS(croph)
c05c0462
MI		 1018VCREATE_FUNCS(audiomode)
1019VCREATE_FUNCS(res_hor)
1020VCREATE_FUNCS(res_ver)
d855497e 1021VCREATE_FUNCS(srate)
d855497e 1022
d855497e
MI		 1023/* Table definition of all controls which can be manipulated */
1024static const struct pvr2_ctl_info control_defs[] = {
1025 {
1026 .v4l_id = V4L2_CID_BRIGHTNESS,
1027 .desc = "Brightness",
1028 .name = "brightness",
1029 .default_value = 128,
1030 DEFREF(brightness),
1031 DEFINT(0,255),
1032 },{
1033 .v4l_id = V4L2_CID_CONTRAST,
1034 .desc = "Contrast",
1035 .name = "contrast",
1036 .default_value = 68,
1037 DEFREF(contrast),
1038 DEFINT(0,127),
1039 },{
1040 .v4l_id = V4L2_CID_SATURATION,
1041 .desc = "Saturation",
1042 .name = "saturation",
1043 .default_value = 64,
1044 DEFREF(saturation),
1045 DEFINT(0,127),
1046 },{
1047 .v4l_id = V4L2_CID_HUE,
1048 .desc = "Hue",
1049 .name = "hue",
1050 .default_value = 0,
1051 DEFREF(hue),
1052 DEFINT(-128,127),
1053 },{
1054 .v4l_id = V4L2_CID_AUDIO_VOLUME,
1055 .desc = "Volume",
1056 .name = "volume",
139eecf9 1057 .default_value = 62000,
d855497e
MI		 1058 DEFREF(volume),
1059 DEFINT(0,65535),
1060 },{
1061 .v4l_id = V4L2_CID_AUDIO_BALANCE,
1062 .desc = "Balance",
1063 .name = "balance",
1064 .default_value = 0,
1065 DEFREF(balance),
1066 DEFINT(-32768,32767),
1067 },{
1068 .v4l_id = V4L2_CID_AUDIO_BASS,
1069 .desc = "Bass",
1070 .name = "bass",
1071 .default_value = 0,
1072 DEFREF(bass),
1073 DEFINT(-32768,32767),
1074 },{
1075 .v4l_id = V4L2_CID_AUDIO_TREBLE,
1076 .desc = "Treble",
1077 .name = "treble",
1078 .default_value = 0,
1079 DEFREF(treble),
1080 DEFINT(-32768,32767),
1081 },{
1082 .v4l_id = V4L2_CID_AUDIO_MUTE,
1083 .desc = "Mute",
1084 .name = "mute",
1085 .default_value = 0,
1086 DEFREF(mute),
33213963 1087 DEFBOOL,
e784bfb9 1088 }, {
432907f7 1089 .desc = "Capture crop left margin",
e784bfb9 1090 .name = "crop_left",
1091 .internal_id = PVR2_CID_CROPL,
1092 .default_value = 0,
1093 DEFREF(cropl),
1094 DEFINT(-129, 340),
1095 .get_min_value = ctrl_cropl_min_get,
1096 .get_max_value = ctrl_cropl_max_get,
432907f7 1097 .get_def_value = ctrl_get_cropcapdl,
e784bfb9 1098 }, {
432907f7 1099 .desc = "Capture crop top margin",
e784bfb9 1100 .name = "crop_top",
1101 .internal_id = PVR2_CID_CROPT,
1102 .default_value = 0,
1103 DEFREF(cropt),
1104 DEFINT(-35, 544),
1105 .get_min_value = ctrl_cropt_min_get,
1106 .get_max_value = ctrl_cropt_max_get,
432907f7 1107 .get_def_value = ctrl_get_cropcapdt,
e784bfb9 1108 }, {
432907f7 1109 .desc = "Capture crop width",
e784bfb9 1110 .name = "crop_width",
1111 .internal_id = PVR2_CID_CROPW,
1112 .default_value = 720,
1113 DEFREF(cropw),
432907f7
MI		 1114 .get_max_value = ctrl_cropw_max_get,
1115 .get_def_value = ctrl_get_cropcapdw,
e784bfb9 1116 }, {
432907f7 1117 .desc = "Capture crop height",
e784bfb9 1118 .name = "crop_height",
1119 .internal_id = PVR2_CID_CROPH,
1120 .default_value = 480,
1121 DEFREF(croph),
432907f7
MI		 1122 .get_max_value = ctrl_croph_max_get,
1123 .get_def_value = ctrl_get_cropcapdh,
1124 }, {
1125 .desc = "Capture capability pixel aspect numerator",
1126 .name = "cropcap_pixel_numerator",
1127 .internal_id = PVR2_CID_CROPCAPPAN,
1128 .get_value = ctrl_get_cropcappan,
1129 }, {
1130 .desc = "Capture capability pixel aspect denominator",
1131 .name = "cropcap_pixel_denominator",
1132 .internal_id = PVR2_CID_CROPCAPPAD,
1133 .get_value = ctrl_get_cropcappad,
1134 }, {
1135 .desc = "Capture capability bounds top",
1136 .name = "cropcap_bounds_top",
1137 .internal_id = PVR2_CID_CROPCAPBT,
1138 .get_value = ctrl_get_cropcapbt,
1139 }, {
1140 .desc = "Capture capability bounds left",
1141 .name = "cropcap_bounds_left",
1142 .internal_id = PVR2_CID_CROPCAPBL,
1143 .get_value = ctrl_get_cropcapbl,
1144 }, {
1145 .desc = "Capture capability bounds width",
1146 .name = "cropcap_bounds_width",
1147 .internal_id = PVR2_CID_CROPCAPBW,
1148 .get_value = ctrl_get_cropcapbw,
1149 }, {
1150 .desc = "Capture capability bounds height",
1151 .name = "cropcap_bounds_height",
1152 .internal_id = PVR2_CID_CROPCAPBH,
1153 .get_value = ctrl_get_cropcapbh,
c05c0462
MI		 1154 },{
1155 .desc = "Video Source",
1156 .name = "input",
1157 .internal_id = PVR2_CID_INPUT,
1158 .default_value = PVR2_CVAL_INPUT_TV,
29bf5b1d 1159 .check_value = ctrl_check_input,
c05c0462
MI		 1160 DEFREF(input),
1161 DEFENUM(control_values_input),
1162 },{
1163 .desc = "Audio Mode",
1164 .name = "audio_mode",
1165 .internal_id = PVR2_CID_AUDIOMODE,
1166 .default_value = V4L2_TUNER_MODE_STEREO,
1167 DEFREF(audiomode),
1168 DEFENUM(control_values_audiomode),
1169 },{
1170 .desc = "Horizontal capture resolution",
1171 .name = "resolution_hor",
1172 .internal_id = PVR2_CID_HRES,
1173 .default_value = 720,
1174 DEFREF(res_hor),
3ad9fc37 1175 DEFINT(19,720),
c05c0462
MI		 1176 },{
1177 .desc = "Vertical capture resolution",
1178 .name = "resolution_ver",
1179 .internal_id = PVR2_CID_VRES,
1180 .default_value = 480,
1181 DEFREF(res_ver),
3ad9fc37
MI		 1182 DEFINT(17,576),
1183 /* Hook in check for video standard and adjust maximum
1184 depending on the standard. */
1185 .get_max_value = ctrl_vres_max_get,
1186 .get_min_value = ctrl_vres_min_get,
d855497e 1187 },{
b30d2441 1188 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
434449f4
MI		 1189 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
1190 .desc = "Audio Sampling Frequency",
d855497e 1191 .name = "srate",
d855497e
MI		 1192 DEFREF(srate),
1193 DEFENUM(control_values_srate),
d855497e
MI		 1194 },{
1195 .desc = "Tuner Frequency (Hz)",
1196 .name = "frequency",
1197 .internal_id = PVR2_CID_FREQUENCY,
1bde0289 1198 .default_value = 0,
d855497e
MI		 1199 .set_value = ctrl_freq_set,
1200 .get_value = ctrl_freq_get,
1201 .is_dirty = ctrl_freq_is_dirty,
1202 .clear_dirty = ctrl_freq_clear_dirty,
644afdb9 1203 DEFINT(0,0),
25d8527a
PK		 1204 /* Hook in check for input value (tv/radio) and adjust
1205 max/min values accordingly */
1206 .get_max_value = ctrl_freq_max_get,
1207 .get_min_value = ctrl_freq_min_get,
d855497e
MI		 1208 },{
1209 .desc = "Channel",
1210 .name = "channel",
1211 .set_value = ctrl_channel_set,
1212 .get_value = ctrl_channel_get,
1213 DEFINT(0,FREQTABLE_SIZE),
1214 },{
1215 .desc = "Channel Program Frequency",
1216 .name = "freq_table_value",
1217 .set_value = ctrl_channelfreq_set,
1218 .get_value = ctrl_channelfreq_get,
644afdb9 1219 DEFINT(0,0),
1bde0289
MI		 1220 /* Hook in check for input value (tv/radio) and adjust
1221 max/min values accordingly */
1bde0289
MI		 1222 .get_max_value = ctrl_freq_max_get,
1223 .get_min_value = ctrl_freq_min_get,
d855497e
MI		 1224 },{
1225 .desc = "Channel Program ID",
1226 .name = "freq_table_channel",
1227 .set_value = ctrl_channelprog_set,
1228 .get_value = ctrl_channelprog_get,
1229 DEFINT(0,FREQTABLE_SIZE),
d855497e
MI		 1230 },{
1231 .desc = "Streaming Enabled",
1232 .name = "streaming_enabled",
1233 .get_value = ctrl_streamingenabled_get,
33213963 1234 DEFBOOL,
d855497e
MI		 1235 },{
1236 .desc = "USB Speed",
1237 .name = "usb_speed",
1238 .get_value = ctrl_hsm_get,
1239 DEFENUM(control_values_hsm),
681c7399
MI		 1240 },{
1241 .desc = "Master State",
1242 .name = "master_state",
1243 .get_value = ctrl_masterstate_get,
1244 DEFENUM(pvr2_state_names),
d855497e
MI		 1245 },{
1246 .desc = "Signal Present",
1247 .name = "signal_present",
1248 .get_value = ctrl_signal_get,
18103c57
MI		 1249 DEFINT(0,65535),
1250 },{
1251 .desc = "Audio Modes Present",
1252 .name = "audio_modes_present",
1253 .get_value = ctrl_audio_modes_present_get,
1254 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
1255 v4l. Nothing outside of this module cares about this,
1256 but I reuse it in order to also reuse the
1257 control_values_audiomode string table. */
1258 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
1259 (1 << V4L2_TUNER_MODE_STEREO)|
1260 (1 << V4L2_TUNER_MODE_LANG1)|
1261 (1 << V4L2_TUNER_MODE_LANG2)),
1262 control_values_audiomode),
d855497e
MI		 1263 },{
1264 .desc = "Video Standards Available Mask",
1265 .name = "video_standard_mask_available",
1266 .internal_id = PVR2_CID_STDAVAIL,
1267 .skip_init = !0,
1268 .get_value = ctrl_stdavail_get,
1269 .set_value = ctrl_stdavail_set,
1270 .val_to_sym = ctrl_std_val_to_sym,
1271 .sym_to_val = ctrl_std_sym_to_val,
1272 .type = pvr2_ctl_bitmask,
1273 },{
1274 .desc = "Video Standards In Use Mask",
1275 .name = "video_standard_mask_active",
1276 .internal_id = PVR2_CID_STDCUR,
1277 .skip_init = !0,
1278 .get_value = ctrl_stdcur_get,
1279 .set_value = ctrl_stdcur_set,
1280 .is_dirty = ctrl_stdcur_is_dirty,
1281 .clear_dirty = ctrl_stdcur_clear_dirty,
1282 .val_to_sym = ctrl_std_val_to_sym,
1283 .sym_to_val = ctrl_std_sym_to_val,
1284 .type = pvr2_ctl_bitmask,
d855497e
MI		 1285 },{
1286 .desc = "Video Standard Name",
1287 .name = "video_standard",
1288 .internal_id = PVR2_CID_STDENUM,
1289 .skip_init = !0,
1290 .get_value = ctrl_stdenumcur_get,
1291 .set_value = ctrl_stdenumcur_set,
1292 .is_dirty = ctrl_stdenumcur_is_dirty,
1293 .clear_dirty = ctrl_stdenumcur_clear_dirty,
1294 .type = pvr2_ctl_enum,
1295 }
1296};
1297
eca8ebfc 1298#define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
d855497e
MI		 1299
1300
1301const char *pvr2_config_get_name(enum pvr2_config cfg)
1302{
1303 switch (cfg) {
1304 case pvr2_config_empty: return "empty";
1305 case pvr2_config_mpeg: return "mpeg";
1306 case pvr2_config_vbi: return "vbi";
16eb40d3
MI		 1307 case pvr2_config_pcm: return "pcm";
1308 case pvr2_config_rawvideo: return "raw video";
d855497e
MI		 1309 }
1310 return "<unknown>";
1311}
1312
1313
1314struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1315{
1316 return hdw->usb_dev;
1317}
1318
1319
1320unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1321{
1322 return hdw->serial_number;
1323}
1324
31a18547
MI		 1325
1326const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1327{
1328 return hdw->bus_info;
1329}
1330
1331
13a88797
MI		 1332const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw)
1333{
1334 return hdw->identifier;
1335}
1336
1337
1bde0289
MI		 1338unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1339{
1340 return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1341}
1342
1343/* Set the currently tuned frequency and account for all possible
1344 driver-core side effects of this action. */
f55a8712 1345static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1bde0289 1346{
7c74e57e 1347 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1bde0289
MI		 1348 if (hdw->freqSelector) {
1349 /* Swing over to radio frequency selection */
1350 hdw->freqSelector = 0;
1351 hdw->freqDirty = !0;
1352 }
1bde0289
MI		 1353 if (hdw->freqValRadio != val) {
1354 hdw->freqValRadio = val;
1355 hdw->freqSlotRadio = 0;
7c74e57e 1356 hdw->freqDirty = !0;
1bde0289 1357 }
7c74e57e 1358 } else {
1bde0289
MI		 1359 if (!(hdw->freqSelector)) {
1360 /* Swing over to television frequency selection */
1361 hdw->freqSelector = 1;
1362 hdw->freqDirty = !0;
1363 }
1bde0289
MI		 1364 if (hdw->freqValTelevision != val) {
1365 hdw->freqValTelevision = val;
1366 hdw->freqSlotTelevision = 0;
7c74e57e 1367 hdw->freqDirty = !0;
1bde0289 1368 }
1bde0289
MI		 1369 }
1370}
1371
d855497e
MI		 1372int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1373{
1374 return hdw->unit_number;
1375}
1376
1377
1378/* Attempt to locate one of the given set of files. Messages are logged
1379 appropriate to what has been found. The return value will be 0 or
1380 greater on success (it will be the index of the file name found) and
1381 fw_entry will be filled in. Otherwise a negative error is returned on
1382 failure. If the return value is -ENOENT then no viable firmware file
1383 could be located. */
1384static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1385 const struct firmware **fw_entry,
1386 const char *fwtypename,
1387 unsigned int fwcount,
1388 const char *fwnames[])
1389{
1390 unsigned int idx;
1391 int ret = -EINVAL;
1392 for (idx = 0; idx < fwcount; idx++) {
1393 ret = request_firmware(fw_entry,
1394 fwnames[idx],
1395 &hdw->usb_dev->dev);
1396 if (!ret) {
1397 trace_firmware("Located %s firmware: %s;"
1398 " uploading...",
1399 fwtypename,
1400 fwnames[idx]);
1401 return idx;
1402 }
1403 if (ret == -ENOENT) continue;
1404 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1405 "request_firmware fatal error with code=%d",ret);
1406 return ret;
1407 }
1408 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1409 "***WARNING***"
1410 " Device %s firmware"
1411 " seems to be missing.",
1412 fwtypename);
1413 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1414 "Did you install the pvrusb2 firmware files"
1415 " in their proper location?");
1416 if (fwcount == 1) {
1417 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1418 "request_firmware unable to locate %s file %s",
1419 fwtypename,fwnames[0]);
1420 } else {
1421 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1422 "request_firmware unable to locate"
1423 " one of the following %s files:",
1424 fwtypename);
1425 for (idx = 0; idx < fwcount; idx++) {
1426 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1427 "request_firmware: Failed to find %s",
1428 fwnames[idx]);
1429 }
1430 }
1431 return ret;
1432}
1433
1434
1435/*
1436 * pvr2_upload_firmware1().
1437 *
1438 * Send the 8051 firmware to the device. After the upload, arrange for
1439 * device to re-enumerate.
1440 *
1441 * NOTE : the pointer to the firmware data given by request_firmware()
1442 * is not suitable for an usb transaction.
1443 *
1444 */
07e337ee 1445static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
d855497e 1446{
a0fd1cb1 1447 const struct firmware *fw_entry = NULL;
d855497e
MI		 1448 void *fw_ptr;
1449 unsigned int pipe;
1450 int ret;
1451 u16 address;
1d643a37 1452
989eb154 1453 if (!hdw->hdw_desc->fx2_firmware.cnt) {
1d643a37 1454 hdw->fw1_state = FW1_STATE_OK;
56dcbfa0
MI		 1455 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1456 "Connected device type defines"
1457 " no firmware to upload; ignoring firmware");
1458 return -ENOTTY;
1d643a37
MI		 1459 }
1460
d855497e
MI		 1461 hdw->fw1_state = FW1_STATE_FAILED; // default result
1462
1463 trace_firmware("pvr2_upload_firmware1");
1464
1465 ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
989eb154
MI		 1466 hdw->hdw_desc->fx2_firmware.cnt,
1467 hdw->hdw_desc->fx2_firmware.lst);
d855497e
MI		 1468 if (ret < 0) {
1469 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1470 return ret;
1471 }
1472
d855497e
MI		 1473 usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1474
1475 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1476
1477 if (fw_entry->size != 0x2000){
1478 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
1479 release_firmware(fw_entry);
1480 return -ENOMEM;
1481 }
1482
1483 fw_ptr = kmalloc(0x800, GFP_KERNEL);
1484 if (fw_ptr == NULL){
1485 release_firmware(fw_entry);
1486 return -ENOMEM;
1487 }
1488
1489 /* We have to hold the CPU during firmware upload. */
1490 pvr2_hdw_cpureset_assert(hdw,1);
1491
1492 /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1493 chunk. */
1494
1495 ret = 0;
1496 for(address = 0; address < fw_entry->size; address += 0x800) {
1497 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1498 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1499 0, fw_ptr, 0x800, HZ);
1500 }
1501
1502 trace_firmware("Upload done, releasing device's CPU");
1503
1504 /* Now release the CPU. It will disconnect and reconnect later. */
1505 pvr2_hdw_cpureset_assert(hdw,0);
1506
1507 kfree(fw_ptr);
1508 release_firmware(fw_entry);
1509
1510 trace_firmware("Upload done (%d bytes sent)",ret);
1511
1512 /* We should have written 8192 bytes */
1513 if (ret == 8192) {
1514 hdw->fw1_state = FW1_STATE_RELOAD;
1515 return 0;
1516 }
1517
1518 return -EIO;
1519}
1520
1521
1522/*
1523 * pvr2_upload_firmware2()
1524 *
1525 * This uploads encoder firmware on endpoint 2.
1526 *
1527 */
1528
1529int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1530{
a0fd1cb1 1531 const struct firmware *fw_entry = NULL;
d855497e 1532 void *fw_ptr;
90060d32 1533 unsigned int pipe, fw_len, fw_done, bcnt, icnt;
d855497e
MI		 1534 int actual_length;
1535 int ret = 0;
1536 int fwidx;
1537 static const char *fw_files[] = {
1538 CX2341X_FIRM_ENC_FILENAME,
1539 };
1540
989eb154 1541 if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1d643a37
MI		 1542 return 0;
1543 }
1544
d855497e
MI		 1545 trace_firmware("pvr2_upload_firmware2");
1546
1547 ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
eca8ebfc 1548 ARRAY_SIZE(fw_files), fw_files);
d855497e
MI		 1549 if (ret < 0) return ret;
1550 fwidx = ret;
1551 ret = 0;
b30d2441
MI		 1552 /* Since we're about to completely reinitialize the encoder,
1553 invalidate our cached copy of its configuration state. Next
1554 time we configure the encoder, then we'll fully configure it. */
1555 hdw->enc_cur_valid = 0;
d855497e 1556
d913d630
MI		 1557 /* Encoder is about to be reset so note that as far as we're
1558 concerned now, the encoder has never been run. */
1559 del_timer_sync(&hdw->encoder_run_timer);
1560 if (hdw->state_encoder_runok) {
1561 hdw->state_encoder_runok = 0;
1562 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1563 }
1564
d855497e
MI		 1565 /* First prepare firmware loading */
1566 ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1567 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1568 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1569 ret |= pvr2_hdw_cmd_deep_reset(hdw);
1570 ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1571 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1572 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1573 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1574 ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1575 ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1576 ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1577 ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1578 ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1579 ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1580 ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1581 ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1c9d10d4
MI		 1582 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1583 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
d855497e
MI		 1584
1585 if (ret) {
1586 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1587 "firmware2 upload prep failed, ret=%d",ret);
1588 release_firmware(fw_entry);
21684ba9 1589 goto done;
d855497e
MI		 1590 }
1591
1592 /* Now send firmware */
1593
1594 fw_len = fw_entry->size;
1595
90060d32 1596 if (fw_len % sizeof(u32)) {
d855497e
MI		 1597 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1598 "size of %s firmware"
48dc30a1 1599 " must be a multiple of %zu bytes",
90060d32 1600 fw_files[fwidx],sizeof(u32));
d855497e 1601 release_firmware(fw_entry);
21684ba9
MI		 1602 ret = -EINVAL;
1603 goto done;
d855497e
MI		 1604 }
1605
1606 fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1607 if (fw_ptr == NULL){
1608 release_firmware(fw_entry);
1609 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1610 "failed to allocate memory for firmware2 upload");
21684ba9
MI		 1611 ret = -ENOMEM;
1612 goto done;
d855497e
MI		 1613 }
1614
1615 pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1616
90060d32
MI		 1617 fw_done = 0;
1618 for (fw_done = 0; fw_done < fw_len;) {
1619 bcnt = fw_len - fw_done;
1620 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1621 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1622 /* Usbsnoop log shows that we must swap bytes... */
5f33df14
MI		 1623 /* Some background info: The data being swapped here is a
1624 firmware image destined for the mpeg encoder chip that
1625 lives at the other end of a USB endpoint. The encoder
1626 chip always talks in 32 bit chunks and its storage is
1627 organized into 32 bit words. However from the file
1628 system to the encoder chip everything is purely a byte
1629 stream. The firmware file's contents are always 32 bit
1630 swapped from what the encoder expects. Thus the need
1631 always exists to swap the bytes regardless of the endian
1632 type of the host processor and therefore swab32() makes
1633 the most sense. */
90060d32 1634 for (icnt = 0; icnt < bcnt/4 ; icnt++)
513edce6 1635 ((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]);
90060d32
MI		 1636
1637 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
d855497e 1638 &actual_length, HZ);
90060d32
MI		 1639 ret |= (actual_length != bcnt);
1640 if (ret) break;
1641 fw_done += bcnt;
d855497e
MI		 1642 }
1643
1644 trace_firmware("upload of %s : %i / %i ",
1645 fw_files[fwidx],fw_done,fw_len);
1646
1647 kfree(fw_ptr);
1648 release_firmware(fw_entry);
1649
1650 if (ret) {
1651 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1652 "firmware2 upload transfer failure");
21684ba9 1653 goto done;
d855497e
MI		 1654 }
1655
1656 /* Finish upload */
1657
1658 ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1659 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1c9d10d4 1660 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
d855497e
MI		 1661
1662 if (ret) {
1663 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1664 "firmware2 upload post-proc failure");
d855497e 1665 }
21684ba9
MI		 1666
1667 done:
1df59f0b
MI		 1668 if (hdw->hdw_desc->signal_routing_scheme ==
1669 PVR2_ROUTING_SCHEME_GOTVIEW) {
1670 /* Ensure that GPIO 11 is set to output for GOTVIEW
1671 hardware. */
1672 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1673 }
d855497e
MI		 1674 return ret;
1675}
1676
1677
681c7399
MI		 1678static const char *pvr2_get_state_name(unsigned int st)
1679{
1680 if (st < ARRAY_SIZE(pvr2_state_names)) {
1681 return pvr2_state_names[st];
d855497e 1682 }
681c7399 1683 return "???";
d855497e
MI		 1684}
1685
681c7399 1686static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
d855497e 1687{
af78e16b
MI		 1688 /* Even though we really only care about the video decoder chip at
1689 this point, we'll broadcast stream on/off to all sub-devices
1690 anyway, just in case somebody else wants to hear the
1691 command... */
e260508d
MI		 1692 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 stream=%s",
1693 (enablefl ? "on" : "off"));
af78e16b
MI		 1694 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_stream, enablefl);
1695 if (hdw->decoder_client_id) {
1696 /* We get here if the encoder has been noticed. Otherwise
1697 we'll issue a warning to the user (which should
1698 normally never happen). */
1699 return 0;
1700 }
1701 if (!hdw->flag_decoder_missed) {
1702 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1703 "WARNING: No decoder present");
1704 hdw->flag_decoder_missed = !0;
1705 trace_stbit("flag_decoder_missed",
1706 hdw->flag_decoder_missed);
1707 }
1708 return -EIO;
d855497e
MI		 1709}
1710
1711
681c7399 1712int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
d855497e 1713{
681c7399 1714 return hdw->master_state;
d855497e
MI		 1715}
1716
1717
681c7399 1718static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
d855497e 1719{
681c7399
MI		 1720 if (!hdw->flag_tripped) return 0;
1721 hdw->flag_tripped = 0;
1722 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1723 "Clearing driver error statuss");
1724 return !0;
d855497e
MI		 1725}
1726
1727
681c7399 1728int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
d855497e 1729{
681c7399 1730 int fl;
d855497e 1731 LOCK_TAKE(hdw->big_lock); do {
681c7399 1732 fl = pvr2_hdw_untrip_unlocked(hdw);
d855497e 1733 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1734 if (fl) pvr2_hdw_state_sched(hdw);
1735 return 0;
d855497e
MI		 1736}
1737
1738
d855497e
MI		 1739
1740
1741int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1742{
681c7399 1743 return hdw->state_pipeline_req != 0;
d855497e
MI		 1744}
1745
1746
1747int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1748{
681c7399 1749 int ret,st;
d855497e 1750 LOCK_TAKE(hdw->big_lock); do {
681c7399
MI		 1751 pvr2_hdw_untrip_unlocked(hdw);
1752 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1753 hdw->state_pipeline_req = enable_flag != 0;
1754 pvr2_trace(PVR2_TRACE_START_STOP,
1755 "/*--TRACE_STREAM--*/ %s",
1756 enable_flag ? "enable" : "disable");
1757 }
1758 pvr2_hdw_state_sched(hdw);
d855497e 1759 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1760 if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1761 if (enable_flag) {
1762 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1763 if (st != PVR2_STATE_READY) return -EIO;
1764 if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1765 }
1766 }
d855497e
MI		 1767 return 0;
1768}
1769
1770
1771int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1772{
681c7399 1773 int fl;
d855497e 1774 LOCK_TAKE(hdw->big_lock);
681c7399
MI		 1775 if ((fl = (hdw->desired_stream_type != config)) != 0) {
1776 hdw->desired_stream_type = config;
1777 hdw->state_pipeline_config = 0;
1778 trace_stbit("state_pipeline_config",
1779 hdw->state_pipeline_config);
1780 pvr2_hdw_state_sched(hdw);
1781 }
d855497e 1782 LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1783 if (fl) return 0;
1784 return pvr2_hdw_wait(hdw,0);
d855497e
MI		 1785}
1786
1787
1788static int get_default_tuner_type(struct pvr2_hdw *hdw)
1789{
1790 int unit_number = hdw->unit_number;
1791 int tp = -1;
1792 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1793 tp = tuner[unit_number];
1794 }
1795 if (tp < 0) return -EINVAL;
1796 hdw->tuner_type = tp;
aaf7884d 1797 hdw->tuner_updated = !0;
d855497e
MI		 1798 return 0;
1799}
1800
1801
1802static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1803{
1804 int unit_number = hdw->unit_number;
1805 int tp = 0;
1806 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1807 tp = video_std[unit_number];
6a540254 1808 if (tp) return tp;
d855497e 1809 }
6a540254 1810 return 0;
d855497e
MI		 1811}
1812
1813
1814static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1815{
1816 int unit_number = hdw->unit_number;
1817 int tp = 0;
1818 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1819 tp = tolerance[unit_number];
1820 }
1821 return tp;
1822}
1823
1824
1825static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1826{
1827 /* Try a harmless request to fetch the eeprom's address over
1828 endpoint 1. See what happens. Only the full FX2 image can
1829 respond to this. If this probe fails then likely the FX2
1830 firmware needs be loaded. */
1831 int result;
1832 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 1833 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
d855497e
MI		 1834 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1835 hdw->cmd_buffer,1,
1836 hdw->cmd_buffer,1);
1837 if (result < 0) break;
1838 } while(0); LOCK_GIVE(hdw->ctl_lock);
1839 if (result) {
1840 pvr2_trace(PVR2_TRACE_INIT,
1841 "Probe of device endpoint 1 result status %d",
1842 result);
1843 } else {
1844 pvr2_trace(PVR2_TRACE_INIT,
1845 "Probe of device endpoint 1 succeeded");
1846 }
1847 return result == 0;
1848}
1849
9f66d4ea
MI		 1850struct pvr2_std_hack {
1851 v4l2_std_id pat; /* Pattern to match */
1852 v4l2_std_id msk; /* Which bits we care about */
1853 v4l2_std_id std; /* What additional standards or default to set */
1854};
1855
1856/* This data structure labels specific combinations of standards from
1857 tveeprom that we'll try to recognize. If we recognize one, then assume
1858 a specified default standard to use. This is here because tveeprom only
1859 tells us about available standards not the intended default standard (if
1860 any) for the device in question. We guess the default based on what has
1861 been reported as available. Note that this is only for guessing a
1862 default - which can always be overridden explicitly - and if the user
1863 has otherwise named a default then that default will always be used in
1864 place of this table. */
ebff0330 1865static const struct pvr2_std_hack std_eeprom_maps[] = {
9f66d4ea
MI		 1866 { /* PAL(B/G) */
1867 .pat = V4L2_STD_B|V4L2_STD_GH,
1868 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1869 },
1870 { /* NTSC(M) */
1871 .pat = V4L2_STD_MN,
1872 .std = V4L2_STD_NTSC_M,
1873 },
1874 { /* PAL(I) */
1875 .pat = V4L2_STD_PAL_I,
1876 .std = V4L2_STD_PAL_I,
1877 },
1878 { /* SECAM(L/L') */
1879 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1880 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1881 },
1882 { /* PAL(D/D1/K) */
1883 .pat = V4L2_STD_DK,
ea2562d9 1884 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
9f66d4ea
MI		 1885 },
1886};
1887
d855497e
MI		 1888static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1889{
1890 char buf[40];
1891 unsigned int bcnt;
3d290bdb 1892 v4l2_std_id std1,std2,std3;
d855497e
MI		 1893
1894 std1 = get_default_standard(hdw);
3d290bdb 1895 std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
d855497e
MI		 1896
1897 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
56585386 1898 pvr2_trace(PVR2_TRACE_STD,
56dcbfa0
MI		 1899 "Supported video standard(s) reported available"
1900 " in hardware: %.*s",
d855497e
MI		 1901 bcnt,buf);
1902
1903 hdw->std_mask_avail = hdw->std_mask_eeprom;
1904
3d290bdb 1905 std2 = (std1|std3) & ~hdw->std_mask_avail;
d855497e
MI		 1906 if (std2) {
1907 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
56585386 1908 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1909 "Expanding supported video standards"
1910 " to include: %.*s",
1911 bcnt,buf);
1912 hdw->std_mask_avail |= std2;
1913 }
1914
1915 pvr2_hdw_internal_set_std_avail(hdw);
1916
1917 if (std1) {
1918 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
56585386 1919 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1920 "Initial video standard forced to %.*s",
1921 bcnt,buf);
1922 hdw->std_mask_cur = std1;
1923 hdw->std_dirty = !0;
1924 pvr2_hdw_internal_find_stdenum(hdw);
1925 return;
1926 }
3d290bdb
MI		 1927 if (std3) {
1928 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1929 pvr2_trace(PVR2_TRACE_STD,
1930 "Initial video standard"
1931 " (determined by device type): %.*s",bcnt,buf);
1932 hdw->std_mask_cur = std3;
1933 hdw->std_dirty = !0;
1934 pvr2_hdw_internal_find_stdenum(hdw);
1935 return;
1936 }
d855497e 1937
9f66d4ea
MI		 1938 {
1939 unsigned int idx;
1940 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1941 if (std_eeprom_maps[idx].msk ?
1942 ((std_eeprom_maps[idx].pat ^
1943 hdw->std_mask_eeprom) &
1944 std_eeprom_maps[idx].msk) :
1945 (std_eeprom_maps[idx].pat !=
1946 hdw->std_mask_eeprom)) continue;
1947 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1948 std_eeprom_maps[idx].std);
56585386 1949 pvr2_trace(PVR2_TRACE_STD,
9f66d4ea
MI		 1950 "Initial video standard guessed as %.*s",
1951 bcnt,buf);
1952 hdw->std_mask_cur = std_eeprom_maps[idx].std;
1953 hdw->std_dirty = !0;
1954 pvr2_hdw_internal_find_stdenum(hdw);
1955 return;
1956 }
1957 }
1958
d855497e
MI		 1959 if (hdw->std_enum_cnt > 1) {
1960 // Autoselect the first listed standard
1961 hdw->std_enum_cur = 1;
1962 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1963 hdw->std_dirty = !0;
56585386 1964 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1965 "Initial video standard auto-selected to %s",
1966 hdw->std_defs[hdw->std_enum_cur-1].name);
1967 return;
1968 }
1969
0885ba1d 1970 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
d855497e
MI		 1971 "Unable to select a viable initial video standard");
1972}
1973
1974
e9c64a78
MI		 1975static unsigned int pvr2_copy_i2c_addr_list(
1976 unsigned short *dst, const unsigned char *src,
1977 unsigned int dst_max)
1978{
3ab8d295 1979 unsigned int cnt = 0;
e9c64a78
MI		 1980 if (!src) return 0;
1981 while (src[cnt] && (cnt + 1) < dst_max) {
1982 dst[cnt] = src[cnt];
1983 cnt++;
1984 }
1985 dst[cnt] = I2C_CLIENT_END;
1986 return cnt;
1987}
1988
1989
1ab5e74f
MI		 1990static int pvr2_hdw_load_subdev(struct pvr2_hdw *hdw,
1991 const struct pvr2_device_client_desc *cd)
e9c64a78
MI		 1992{
1993 const char *fname;
1994 unsigned char mid;
1995 struct v4l2_subdev *sd;
1996 unsigned int i2ccnt;
1997 const unsigned char *p;
1998 /* Arbitrary count - max # i2c addresses we will probe */
1999 unsigned short i2caddr[25];
2000
2001 mid = cd->module_id;
2002 fname = (mid < ARRAY_SIZE(module_names)) ? module_names[mid] : NULL;
2003 if (!fname) {
2004 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1ab5e74f 2005 "Module ID %u for device %s has no name",
e9c64a78
MI		 2006 mid,
2007 hdw->hdw_desc->description);
1ab5e74f 2008 return -EINVAL;
e9c64a78 2009 }
bd14d4f8
MI		 2010 pvr2_trace(PVR2_TRACE_INIT,
2011 "Module ID %u (%s) for device %s being loaded...",
2012 mid, fname,
2013 hdw->hdw_desc->description);
e9c64a78
MI		 2014
2015 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, cd->i2c_address_list,
2016 ARRAY_SIZE(i2caddr));
2017 if (!i2ccnt && ((p = (mid < ARRAY_SIZE(module_i2c_addresses)) ?
2018 module_i2c_addresses[mid] : NULL) != NULL)) {
2019 /* Second chance: Try default i2c address list */
2020 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, p,
2021 ARRAY_SIZE(i2caddr));
bd14d4f8
MI		 2022 if (i2ccnt) {
2023 pvr2_trace(PVR2_TRACE_INIT,
2024 "Module ID %u:"
2025 " Using default i2c address list",
2026 mid);
2027 }
e9c64a78
MI		 2028 }
2029
2030 if (!i2ccnt) {
2031 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1ab5e74f
MI		 2032 "Module ID %u (%s) for device %s:"
2033 " No i2c addresses",
2034 mid, fname, hdw->hdw_desc->description);
2035 return -EINVAL;
e9c64a78
MI		 2036 }
2037
2038 /* Note how the 2nd and 3rd arguments are the same for both
2039 * v4l2_i2c_new_subdev() and v4l2_i2c_new_probed_subdev(). Why?
2040 * Well the 2nd argument is the module name to load, while the 3rd
2041 * argument is documented in the framework as being the "chipid" -
2042 * and every other place where I can find examples of this, the
2043 * "chipid" appears to just be the module name again. So here we
2044 * just do the same thing. */
2045 if (i2ccnt == 1) {
bd14d4f8
MI		 2046 pvr2_trace(PVR2_TRACE_INIT,
2047 "Module ID %u:"
2048 " Setting up with specified i2c address 0x%x",
2049 mid, i2caddr[0]);
e6574f2f 2050 sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
e9c64a78
MI		 2051 fname, fname,
2052 i2caddr[0]);
2053 } else {
bd14d4f8
MI		 2054 pvr2_trace(PVR2_TRACE_INIT,
2055 "Module ID %u:"
2056 " Setting up with address probe list",
2057 mid);
e6574f2f 2058 sd = v4l2_i2c_new_probed_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
e9c64a78
MI		 2059 fname, fname,
2060 i2caddr);
2061 }
2062
446dfdc6
MI		 2063 if (!sd) {
2064 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1ab5e74f
MI		 2065 "Module ID %u (%s) for device %s failed to load",
2066 mid, fname, hdw->hdw_desc->description);
2067 return -EIO;
446dfdc6
MI		 2068 }
2069
2070 /* Tag this sub-device instance with the module ID we know about.
2071 In other places we'll use that tag to determine if the instance
2072 requires special handling. */
2073 sd->grp_id = mid;
2074
bd14d4f8 2075 pvr2_trace(PVR2_TRACE_INFO, "Attached sub-driver %s", fname);
a932f507 2076
e9c64a78 2077
00e5f736
MI		 2078 /* client-specific setup... */
2079 switch (mid) {
2080 case PVR2_CLIENT_ID_CX25840:
2081 hdw->decoder_client_id = mid;
2082 {
2083 /*
2084 Mike Isely <isely@pobox.com> 19-Nov-2006 - This
2085 bit of nuttiness for cx25840 causes that module
2086 to correctly set up its video scaling. This is
2087 really a problem in the cx25840 module itself,
2088 but we work around it here. The problem has not
2089 been seen in ivtv because there VBI is supported
2090 and set up. We don't do VBI here (at least not
2091 yet) and thus we never attempted to even set it
2092 up.
2093 */
2094 struct v4l2_format fmt;
bd14d4f8
MI		 2095 pvr2_trace(PVR2_TRACE_INIT,
2096 "Module ID %u:"
2097 " Executing cx25840 VBI hack",
2098 mid);
00e5f736
MI		 2099 memset(&fmt, 0, sizeof(fmt));
2100 fmt.type = V4L2_BUF_TYPE_SLICED_VBI_CAPTURE;
2101 v4l2_device_call_all(&hdw->v4l2_dev, mid,
2102 video, s_fmt, &fmt);
2103 }
2104 break;
2105 case PVR2_CLIENT_ID_SAA7115:
2106 hdw->decoder_client_id = mid;
2107 break;
2108 default: break;
2109 }
1ab5e74f
MI		 2110
2111 return 0;
e9c64a78
MI		 2112}
2113
2114
2115static void pvr2_hdw_load_modules(struct pvr2_hdw *hdw)
2116{
2117 unsigned int idx;
2118 const struct pvr2_string_table *cm;
2119 const struct pvr2_device_client_table *ct;
1ab5e74f 2120 int okFl = !0;
e9c64a78
MI		 2121
2122 cm = &hdw->hdw_desc->client_modules;
2123 for (idx = 0; idx < cm->cnt; idx++) {
2124 request_module(cm->lst[idx]);
2125 }
2126
2127 ct = &hdw->hdw_desc->client_table;
2128 for (idx = 0; idx < ct->cnt; idx++) {
bd14d4f8 2129 if (pvr2_hdw_load_subdev(hdw, &ct->lst[idx]) < 0) okFl = 0;
e9c64a78 2130 }
1ab5e74f 2131 if (!okFl) pvr2_hdw_render_useless(hdw);
e9c64a78
MI		 2132}
2133
2134
d855497e
MI		 2135static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
2136{
2137 int ret;
2138 unsigned int idx;
2139 struct pvr2_ctrl *cptr;
2140 int reloadFl = 0;
989eb154 2141 if (hdw->hdw_desc->fx2_firmware.cnt) {
1d643a37
MI		 2142 if (!reloadFl) {
2143 reloadFl =
2144 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
2145 == 0);
2146 if (reloadFl) {
2147 pvr2_trace(PVR2_TRACE_INIT,
2148 "USB endpoint config looks strange"
2149 "; possibly firmware needs to be"
2150 " loaded");
2151 }
d855497e 2152 }
1d643a37
MI		 2153 if (!reloadFl) {
2154 reloadFl = !pvr2_hdw_check_firmware(hdw);
2155 if (reloadFl) {
2156 pvr2_trace(PVR2_TRACE_INIT,
2157 "Check for FX2 firmware failed"
2158 "; possibly firmware needs to be"
2159 " loaded");
2160 }
d855497e 2161 }
1d643a37
MI		 2162 if (reloadFl) {
2163 if (pvr2_upload_firmware1(hdw) != 0) {
2164 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2165 "Failure uploading firmware1");
2166 }
2167 return;
d855497e 2168 }
d855497e
MI		 2169 }
2170 hdw->fw1_state = FW1_STATE_OK;
2171
d855497e
MI		 2172 if (!pvr2_hdw_dev_ok(hdw)) return;
2173
27764726
MI		 2174 hdw->force_dirty = !0;
2175
989eb154 2176 if (!hdw->hdw_desc->flag_no_powerup) {
1d643a37
MI		 2177 pvr2_hdw_cmd_powerup(hdw);
2178 if (!pvr2_hdw_dev_ok(hdw)) return;
d855497e
MI		 2179 }
2180
31335b13 2181 /* Take the IR chip out of reset, if appropriate */
27eab384 2182 if (hdw->ir_scheme_active == PVR2_IR_SCHEME_ZILOG) {
31335b13
MI		 2183 pvr2_issue_simple_cmd(hdw,
2184 FX2CMD_HCW_ZILOG_RESET |
2185 (1 << 8) |
2186 ((0) << 16));
2187 }
2188
d855497e
MI		 2189 // This step MUST happen after the earlier powerup step.
2190 pvr2_i2c_core_init(hdw);
2191 if (!pvr2_hdw_dev_ok(hdw)) return;
2192
e9c64a78 2193 pvr2_hdw_load_modules(hdw);
1ab5e74f 2194 if (!pvr2_hdw_dev_ok(hdw)) return;
e9c64a78 2195
cc26b076 2196 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, load_fw);
5c6cb4e2 2197
c05c0462 2198 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
d855497e
MI		 2199 cptr = hdw->controls + idx;
2200 if (cptr->info->skip_init) continue;
2201 if (!cptr->info->set_value) continue;
2202 cptr->info->set_value(cptr,~0,cptr->info->default_value);
2203 }
2204
1bde0289
MI		 2205 /* Set up special default values for the television and radio
2206 frequencies here. It's not really important what these defaults
2207 are, but I set them to something usable in the Chicago area just
2208 to make driver testing a little easier. */
2209
5a4f5da6
MK		 2210 hdw->freqValTelevision = default_tv_freq;
2211 hdw->freqValRadio = default_radio_freq;
1bde0289 2212
d855497e
MI		 2213 // Do not use pvr2_reset_ctl_endpoints() here. It is not
2214 // thread-safe against the normal pvr2_send_request() mechanism.
2215 // (We should make it thread safe).
2216
aaf7884d
MI		 2217 if (hdw->hdw_desc->flag_has_hauppauge_rom) {
2218 ret = pvr2_hdw_get_eeprom_addr(hdw);
d855497e 2219 if (!pvr2_hdw_dev_ok(hdw)) return;
aaf7884d
MI		 2220 if (ret < 0) {
2221 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2222 "Unable to determine location of eeprom,"
2223 " skipping");
2224 } else {
2225 hdw->eeprom_addr = ret;
2226 pvr2_eeprom_analyze(hdw);
2227 if (!pvr2_hdw_dev_ok(hdw)) return;
2228 }
2229 } else {
2230 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
2231 hdw->tuner_updated = !0;
2232 hdw->std_mask_eeprom = V4L2_STD_ALL;
d855497e
MI		 2233 }
2234
13a88797
MI		 2235 if (hdw->serial_number) {
2236 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2237 "sn-%lu", hdw->serial_number);
2238 } else if (hdw->unit_number >= 0) {
2239 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2240 "unit-%c",
2241 hdw->unit_number + 'a');
2242 } else {
2243 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2244 "unit-??");
2245 }
2246 hdw->identifier[idx] = 0;
2247
d855497e
MI		 2248 pvr2_hdw_setup_std(hdw);
2249
2250 if (!get_default_tuner_type(hdw)) {
2251 pvr2_trace(PVR2_TRACE_INIT,
2252 "pvr2_hdw_setup: Tuner type overridden to %d",
2253 hdw->tuner_type);
2254 }
2255
d855497e
MI		 2256
2257 if (!pvr2_hdw_dev_ok(hdw)) return;
2258
1df59f0b
MI		 2259 if (hdw->hdw_desc->signal_routing_scheme ==
2260 PVR2_ROUTING_SCHEME_GOTVIEW) {
2261 /* Ensure that GPIO 11 is set to output for GOTVIEW
2262 hardware. */
2263 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
2264 }
2265
681c7399 2266 pvr2_hdw_commit_setup(hdw);
d855497e
MI		 2267
2268 hdw->vid_stream = pvr2_stream_create();
2269 if (!pvr2_hdw_dev_ok(hdw)) return;
2270 pvr2_trace(PVR2_TRACE_INIT,
2271 "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
2272 if (hdw->vid_stream) {
2273 idx = get_default_error_tolerance(hdw);
2274 if (idx) {
2275 pvr2_trace(PVR2_TRACE_INIT,
2276 "pvr2_hdw_setup: video stream %p"
2277 " setting tolerance %u",
2278 hdw->vid_stream,idx);
2279 }
2280 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
2281 PVR2_VID_ENDPOINT,idx);
2282 }
2283
2284 if (!pvr2_hdw_dev_ok(hdw)) return;
2285
d855497e 2286 hdw->flag_init_ok = !0;
681c7399
MI		 2287
2288 pvr2_hdw_state_sched(hdw);
d855497e
MI		 2289}
2290
2291
681c7399
MI		 2292/* Set up the structure and attempt to put the device into a usable state.
2293 This can be a time-consuming operation, which is why it is not done
2294 internally as part of the create() step. */
2295static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
d855497e
MI		 2296{
2297 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
681c7399 2298 do {
d855497e
MI		 2299 pvr2_hdw_setup_low(hdw);
2300 pvr2_trace(PVR2_TRACE_INIT,
2301 "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
681c7399 2302 hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
d855497e 2303 if (pvr2_hdw_dev_ok(hdw)) {
681c7399 2304 if (hdw->flag_init_ok) {
d855497e
MI		 2305 pvr2_trace(
2306 PVR2_TRACE_INFO,
2307 "Device initialization"
2308 " completed successfully.");
2309 break;
2310 }
2311 if (hdw->fw1_state == FW1_STATE_RELOAD) {
2312 pvr2_trace(
2313 PVR2_TRACE_INFO,
2314 "Device microcontroller firmware"
2315 " (re)loaded; it should now reset"
2316 " and reconnect.");
2317 break;
2318 }
2319 pvr2_trace(
2320 PVR2_TRACE_ERROR_LEGS,
2321 "Device initialization was not successful.");
2322 if (hdw->fw1_state == FW1_STATE_MISSING) {
2323 pvr2_trace(
2324 PVR2_TRACE_ERROR_LEGS,
2325 "Giving up since device"
2326 " microcontroller firmware"
2327 " appears to be missing.");
2328 break;
2329 }
2330 }
2331 if (procreload) {
2332 pvr2_trace(
2333 PVR2_TRACE_ERROR_LEGS,
2334 "Attempting pvrusb2 recovery by reloading"
2335 " primary firmware.");
2336 pvr2_trace(
2337 PVR2_TRACE_ERROR_LEGS,
2338 "If this works, device should disconnect"
2339 " and reconnect in a sane state.");
2340 hdw->fw1_state = FW1_STATE_UNKNOWN;
2341 pvr2_upload_firmware1(hdw);
2342 } else {
2343 pvr2_trace(
2344 PVR2_TRACE_ERROR_LEGS,
2345 "***WARNING*** pvrusb2 device hardware"
2346 " appears to be jammed"
2347 " and I can't clear it.");
2348 pvr2_trace(
2349 PVR2_TRACE_ERROR_LEGS,
2350 "You might need to power cycle"
2351 " the pvrusb2 device"
2352 " in order to recover.");
2353 }
681c7399 2354 } while (0);
d855497e 2355 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
d855497e
MI		 2356}
2357
2358
c4a8828d
MI		 2359/* Perform second stage initialization. Set callback pointer first so that
2360 we can avoid a possible initialization race (if the kernel thread runs
2361 before the callback has been set). */
794b1607
MI		 2362int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
2363 void (*callback_func)(void *),
2364 void *callback_data)
c4a8828d
MI		 2365{
2366 LOCK_TAKE(hdw->big_lock); do {
97f26ff6
MI		 2367 if (hdw->flag_disconnected) {
2368 /* Handle a race here: If we're already
2369 disconnected by this point, then give up. If we
2370 get past this then we'll remain connected for
2371 the duration of initialization since the entire
2372 initialization sequence is now protected by the
2373 big_lock. */
2374 break;
2375 }
c4a8828d
MI		 2376 hdw->state_data = callback_data;
2377 hdw->state_func = callback_func;
97f26ff6 2378 pvr2_hdw_setup(hdw);
c4a8828d 2379 } while (0); LOCK_GIVE(hdw->big_lock);
794b1607 2380 return hdw->flag_init_ok;
c4a8828d
MI		 2381}
2382
2383
2384/* Create, set up, and return a structure for interacting with the
2385 underlying hardware. */
d855497e
MI		 2386struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
2387 const struct usb_device_id *devid)
2388{
7fb20fa3 2389 unsigned int idx,cnt1,cnt2,m;
fe15f136 2390 struct pvr2_hdw *hdw = NULL;
d855497e
MI		 2391 int valid_std_mask;
2392 struct pvr2_ctrl *cptr;
b72b7bf5 2393 struct usb_device *usb_dev;
989eb154 2394 const struct pvr2_device_desc *hdw_desc;
d855497e 2395 __u8 ifnum;
b30d2441
MI		 2396 struct v4l2_queryctrl qctrl;
2397 struct pvr2_ctl_info *ciptr;
d855497e 2398
b72b7bf5
MI		 2399 usb_dev = interface_to_usbdev(intf);
2400
d130fa8a 2401 hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
d855497e 2402
fe15f136
MI		 2403 if (hdw_desc == NULL) {
2404 pvr2_trace(PVR2_TRACE_INIT, "pvr2_hdw_create:"
2405 " No device description pointer,"
2406 " unable to continue.");
2407 pvr2_trace(PVR2_TRACE_INIT, "If you have a new device type,"
2408 " please contact Mike Isely <isely@pobox.com>"
2409 " to get it included in the driver\n");
2410 goto fail;
2411 }
2412
ca545f7c 2413 hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
d855497e 2414 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
989eb154 2415 hdw,hdw_desc->description);
d855497e 2416 if (!hdw) goto fail;
681c7399
MI		 2417
2418 init_timer(&hdw->quiescent_timer);
2419 hdw->quiescent_timer.data = (unsigned long)hdw;
2420 hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
2421
2422 init_timer(&hdw->encoder_wait_timer);
2423 hdw->encoder_wait_timer.data = (unsigned long)hdw;
2424 hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
2425
d913d630
MI		 2426 init_timer(&hdw->encoder_run_timer);
2427 hdw->encoder_run_timer.data = (unsigned long)hdw;
2428 hdw->encoder_run_timer.function = pvr2_hdw_encoder_run_timeout;
2429
681c7399
MI		 2430 hdw->master_state = PVR2_STATE_DEAD;
2431
2432 init_waitqueue_head(&hdw->state_wait_data);
2433
18103c57 2434 hdw->tuner_signal_stale = !0;
b30d2441 2435 cx2341x_fill_defaults(&hdw->enc_ctl_state);
d855497e 2436
7fb20fa3
MI		 2437 /* Calculate which inputs are OK */
2438 m = 0;
2439 if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
e8f5bacf
MI		 2440 if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
2441 m |= 1 << PVR2_CVAL_INPUT_DTV;
2442 }
7fb20fa3
MI		 2443 if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
2444 if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
2445 if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
2446 hdw->input_avail_mask = m;
1cb03b76 2447 hdw->input_allowed_mask = hdw->input_avail_mask;
7fb20fa3 2448
62433e31
MI		 2449 /* If not a hybrid device, pathway_state never changes. So
2450 initialize it here to what it should forever be. */
2451 if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
2452 hdw->pathway_state = PVR2_PATHWAY_ANALOG;
2453 } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
2454 hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
2455 }
2456
c05c0462 2457 hdw->control_cnt = CTRLDEF_COUNT;
b30d2441 2458 hdw->control_cnt += MPEGDEF_COUNT;
ca545f7c 2459 hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
d855497e
MI		 2460 GFP_KERNEL);
2461 if (!hdw->controls) goto fail;
989eb154 2462 hdw->hdw_desc = hdw_desc;
27eab384 2463 hdw->ir_scheme_active = hdw->hdw_desc->ir_scheme;
c05c0462
MI		 2464 for (idx = 0; idx < hdw->control_cnt; idx++) {
2465 cptr = hdw->controls + idx;
2466 cptr->hdw = hdw;
2467 }
d855497e
MI		 2468 for (idx = 0; idx < 32; idx++) {
2469 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
2470 }
c05c0462 2471 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
d855497e 2472 cptr = hdw->controls + idx;
d855497e
MI		 2473 cptr->info = control_defs+idx;
2474 }
dbc40a0e
MI		 2475
2476 /* Ensure that default input choice is a valid one. */
2477 m = hdw->input_avail_mask;
2478 if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
2479 if (!((1 << idx) & m)) continue;
2480 hdw->input_val = idx;
2481 break;
2482 }
2483
b30d2441 2484 /* Define and configure additional controls from cx2341x module. */
ca545f7c 2485 hdw->mpeg_ctrl_info = kzalloc(
b30d2441
MI		 2486 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
2487 if (!hdw->mpeg_ctrl_info) goto fail;
b30d2441
MI		 2488 for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
2489 cptr = hdw->controls + idx + CTRLDEF_COUNT;
2490 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
2491 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
2492 ciptr->name = mpeg_ids[idx].strid;
2493 ciptr->v4l_id = mpeg_ids[idx].id;
2494 ciptr->skip_init = !0;
2495 ciptr->get_value = ctrl_cx2341x_get;
2496 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
2497 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
2498 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
2499 qctrl.id = ciptr->v4l_id;
2500 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
2501 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
2502 ciptr->set_value = ctrl_cx2341x_set;
2503 }
2504 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
2505 PVR2_CTLD_INFO_DESC_SIZE);
2506 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
2507 ciptr->default_value = qctrl.default_value;
2508 switch (qctrl.type) {
2509 default:
2510 case V4L2_CTRL_TYPE_INTEGER:
2511 ciptr->type = pvr2_ctl_int;
2512 ciptr->def.type_int.min_value = qctrl.minimum;
2513 ciptr->def.type_int.max_value = qctrl.maximum;
2514 break;
2515 case V4L2_CTRL_TYPE_BOOLEAN:
2516 ciptr->type = pvr2_ctl_bool;
2517 break;
2518 case V4L2_CTRL_TYPE_MENU:
2519 ciptr->type = pvr2_ctl_enum;
2520 ciptr->def.type_enum.value_names =
e0e31cdb
HV		 2521 cx2341x_ctrl_get_menu(&hdw->enc_ctl_state,
2522 ciptr->v4l_id);
b30d2441
MI		 2523 for (cnt1 = 0;
2524 ciptr->def.type_enum.value_names[cnt1] != NULL;
2525 cnt1++) { }
2526 ciptr->def.type_enum.count = cnt1;
2527 break;
2528 }
2529 cptr->info = ciptr;
2530 }
d855497e
MI		 2531
2532 // Initialize video standard enum dynamic control
2533 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
2534 if (cptr) {
2535 memcpy(&hdw->std_info_enum,cptr->info,
2536 sizeof(hdw->std_info_enum));
2537 cptr->info = &hdw->std_info_enum;
2538
2539 }
2540 // Initialize control data regarding video standard masks
2541 valid_std_mask = pvr2_std_get_usable();
2542 for (idx = 0; idx < 32; idx++) {
2543 if (!(valid_std_mask & (1 << idx))) continue;
2544 cnt1 = pvr2_std_id_to_str(
2545 hdw->std_mask_names[idx],
2546 sizeof(hdw->std_mask_names[idx])-1,
2547 1 << idx);
2548 hdw->std_mask_names[idx][cnt1] = 0;
2549 }
2550 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2551 if (cptr) {
2552 memcpy(&hdw->std_info_avail,cptr->info,
2553 sizeof(hdw->std_info_avail));
2554 cptr->info = &hdw->std_info_avail;
2555 hdw->std_info_avail.def.type_bitmask.bit_names =
2556 hdw->std_mask_ptrs;
2557 hdw->std_info_avail.def.type_bitmask.valid_bits =
2558 valid_std_mask;
2559 }
2560 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2561 if (cptr) {
2562 memcpy(&hdw->std_info_cur,cptr->info,
2563 sizeof(hdw->std_info_cur));
2564 cptr->info = &hdw->std_info_cur;
2565 hdw->std_info_cur.def.type_bitmask.bit_names =
2566 hdw->std_mask_ptrs;
2567 hdw->std_info_avail.def.type_bitmask.valid_bits =
2568 valid_std_mask;
2569 }
2570
432907f7 2571 hdw->cropcap_stale = !0;
d855497e
MI		 2572 hdw->eeprom_addr = -1;
2573 hdw->unit_number = -1;
8079384e
MI		 2574 hdw->v4l_minor_number_video = -1;
2575 hdw->v4l_minor_number_vbi = -1;
fd5a75fe 2576 hdw->v4l_minor_number_radio = -1;
d855497e
MI		 2577 hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2578 if (!hdw->ctl_write_buffer) goto fail;
2579 hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2580 if (!hdw->ctl_read_buffer) goto fail;
2581 hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2582 if (!hdw->ctl_write_urb) goto fail;
2583 hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2584 if (!hdw->ctl_read_urb) goto fail;
2585
70ad6383 2586 if (v4l2_device_register(&intf->dev, &hdw->v4l2_dev) != 0) {
b72b7bf5
MI		 2587 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2588 "Error registering with v4l core, giving up");
2589 goto fail;
2590 }
8df0c87c 2591 mutex_lock(&pvr2_unit_mtx); do {
d855497e
MI		 2592 for (idx = 0; idx < PVR_NUM; idx++) {
2593 if (unit_pointers[idx]) continue;
2594 hdw->unit_number = idx;
2595 unit_pointers[idx] = hdw;
2596 break;
2597 }
8df0c87c 2598 } while (0); mutex_unlock(&pvr2_unit_mtx);
d855497e
MI		 2599
2600 cnt1 = 0;
2601 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2602 cnt1 += cnt2;
2603 if (hdw->unit_number >= 0) {
2604 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2605 ('a' + hdw->unit_number));
2606 cnt1 += cnt2;
2607 }
2608 if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2609 hdw->name[cnt1] = 0;
2610
681c7399
MI		 2611 hdw->workqueue = create_singlethread_workqueue(hdw->name);
2612 INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
681c7399 2613
d855497e
MI		 2614 pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2615 hdw->unit_number,hdw->name);
2616
2617 hdw->tuner_type = -1;
2618 hdw->flag_ok = !0;
d855497e
MI		 2619
2620 hdw->usb_intf = intf;
b72b7bf5 2621 hdw->usb_dev = usb_dev;
d855497e 2622
87e3495c 2623 usb_make_path(hdw->usb_dev, hdw->bus_info, sizeof(hdw->bus_info));
31a18547 2624
d855497e
MI		 2625 ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2626 usb_set_interface(hdw->usb_dev,ifnum,0);
2627
2628 mutex_init(&hdw->ctl_lock_mutex);
2629 mutex_init(&hdw->big_lock_mutex);
2630
2631 return hdw;
2632 fail:
2633 if (hdw) {
681c7399 2634 del_timer_sync(&hdw->quiescent_timer);
d913d630 2635 del_timer_sync(&hdw->encoder_run_timer);
681c7399
MI		 2636 del_timer_sync(&hdw->encoder_wait_timer);
2637 if (hdw->workqueue) {
2638 flush_workqueue(hdw->workqueue);
2639 destroy_workqueue(hdw->workqueue);
2640 hdw->workqueue = NULL;
2641 }
5e55d2ce
MK		 2642 usb_free_urb(hdw->ctl_read_urb);
2643 usb_free_urb(hdw->ctl_write_urb);
22071a42
MK		 2644 kfree(hdw->ctl_read_buffer);
2645 kfree(hdw->ctl_write_buffer);
2646 kfree(hdw->controls);
2647 kfree(hdw->mpeg_ctrl_info);
681c7399
MI		 2648 kfree(hdw->std_defs);
2649 kfree(hdw->std_enum_names);
d855497e
MI		 2650 kfree(hdw);
2651 }
a0fd1cb1 2652 return NULL;
d855497e
MI		 2653}
2654
2655
2656/* Remove _all_ associations between this driver and the underlying USB
2657 layer. */
07e337ee 2658static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
d855497e
MI		 2659{
2660 if (hdw->flag_disconnected) return;
2661 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2662 if (hdw->ctl_read_urb) {
2663 usb_kill_urb(hdw->ctl_read_urb);
2664 usb_free_urb(hdw->ctl_read_urb);
a0fd1cb1 2665 hdw->ctl_read_urb = NULL;
d855497e
MI		 2666 }
2667 if (hdw->ctl_write_urb) {
2668 usb_kill_urb(hdw->ctl_write_urb);
2669 usb_free_urb(hdw->ctl_write_urb);
a0fd1cb1 2670 hdw->ctl_write_urb = NULL;
d855497e
MI		 2671 }
2672 if (hdw->ctl_read_buffer) {
2673 kfree(hdw->ctl_read_buffer);
a0fd1cb1 2674 hdw->ctl_read_buffer = NULL;
d855497e
MI		 2675 }
2676 if (hdw->ctl_write_buffer) {
2677 kfree(hdw->ctl_write_buffer);
a0fd1cb1 2678 hdw->ctl_write_buffer = NULL;
d855497e 2679 }
d855497e 2680 hdw->flag_disconnected = !0;
b72b7bf5
MI		 2681 /* If we don't do this, then there will be a dangling struct device
2682 reference to our disappearing device persisting inside the V4L
2683 core... */
dc070bcc 2684 v4l2_device_disconnect(&hdw->v4l2_dev);
a0fd1cb1
MI		 2685 hdw->usb_dev = NULL;
2686 hdw->usb_intf = NULL;
681c7399 2687 pvr2_hdw_render_useless(hdw);
d855497e
MI		 2688}
2689
2690
2691/* Destroy hardware interaction structure */
2692void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2693{
401c27ce 2694 if (!hdw) return;
d855497e 2695 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
681c7399
MI		 2696 if (hdw->workqueue) {
2697 flush_workqueue(hdw->workqueue);
2698 destroy_workqueue(hdw->workqueue);
2699 hdw->workqueue = NULL;
2700 }
8f59100a 2701 del_timer_sync(&hdw->quiescent_timer);
d913d630 2702 del_timer_sync(&hdw->encoder_run_timer);
8f59100a 2703 del_timer_sync(&hdw->encoder_wait_timer);
d855497e
MI		 2704 if (hdw->fw_buffer) {
2705 kfree(hdw->fw_buffer);
a0fd1cb1 2706 hdw->fw_buffer = NULL;
d855497e
MI		 2707 }
2708 if (hdw->vid_stream) {
2709 pvr2_stream_destroy(hdw->vid_stream);
a0fd1cb1 2710 hdw->vid_stream = NULL;
d855497e 2711 }
d855497e 2712 pvr2_i2c_core_done(hdw);
b72b7bf5 2713 v4l2_device_unregister(&hdw->v4l2_dev);
d855497e 2714 pvr2_hdw_remove_usb_stuff(hdw);
8df0c87c 2715 mutex_lock(&pvr2_unit_mtx); do {
d855497e
MI		 2716 if ((hdw->unit_number >= 0) &&
2717 (hdw->unit_number < PVR_NUM) &&
2718 (unit_pointers[hdw->unit_number] == hdw)) {
a0fd1cb1 2719 unit_pointers[hdw->unit_number] = NULL;
d855497e 2720 }
8df0c87c 2721 } while (0); mutex_unlock(&pvr2_unit_mtx);
22071a42
MK		 2722 kfree(hdw->controls);
2723 kfree(hdw->mpeg_ctrl_info);
2724 kfree(hdw->std_defs);
2725 kfree(hdw->std_enum_names);
d855497e
MI		 2726 kfree(hdw);
2727}
2728
2729
d855497e
MI		 2730int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2731{
2732 return (hdw && hdw->flag_ok);
2733}
2734
2735
2736/* Called when hardware has been unplugged */
2737void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2738{
2739 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2740 LOCK_TAKE(hdw->big_lock);
2741 LOCK_TAKE(hdw->ctl_lock);
2742 pvr2_hdw_remove_usb_stuff(hdw);
2743 LOCK_GIVE(hdw->ctl_lock);
2744 LOCK_GIVE(hdw->big_lock);
2745}
2746
2747
2748// Attempt to autoselect an appropriate value for std_enum_cur given
2749// whatever is currently in std_mask_cur
07e337ee 2750static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
d855497e
MI		 2751{
2752 unsigned int idx;
2753 for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2754 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2755 hdw->std_enum_cur = idx;
2756 return;
2757 }
2758 }
2759 hdw->std_enum_cur = 0;
2760}
2761
2762
2763// Calculate correct set of enumerated standards based on currently known
2764// set of available standards bits.
07e337ee 2765static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
d855497e
MI		 2766{
2767 struct v4l2_standard *newstd;
2768 unsigned int std_cnt;
2769 unsigned int idx;
2770
2771 newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2772
2773 if (hdw->std_defs) {
2774 kfree(hdw->std_defs);
a0fd1cb1 2775 hdw->std_defs = NULL;
d855497e
MI		 2776 }
2777 hdw->std_enum_cnt = 0;
2778 if (hdw->std_enum_names) {
2779 kfree(hdw->std_enum_names);
a0fd1cb1 2780 hdw->std_enum_names = NULL;
d855497e
MI		 2781 }
2782
2783 if (!std_cnt) {
2784 pvr2_trace(
2785 PVR2_TRACE_ERROR_LEGS,
2786 "WARNING: Failed to identify any viable standards");
2787 }
2788 hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2789 hdw->std_enum_names[0] = "none";
2790 for (idx = 0; idx < std_cnt; idx++) {
2791 hdw->std_enum_names[idx+1] =
2792 newstd[idx].name;
2793 }
2794 // Set up the dynamic control for this standard
2795 hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2796 hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2797 hdw->std_defs = newstd;
2798 hdw->std_enum_cnt = std_cnt+1;
2799 hdw->std_enum_cur = 0;
2800 hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2801}
2802
2803
2804int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2805 struct v4l2_standard *std,
2806 unsigned int idx)
2807{
2808 int ret = -EINVAL;
2809 if (!idx) return ret;
2810 LOCK_TAKE(hdw->big_lock); do {
2811 if (idx >= hdw->std_enum_cnt) break;
2812 idx--;
2813 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2814 ret = 0;
2815 } while (0); LOCK_GIVE(hdw->big_lock);
2816 return ret;
2817}
2818
2819
2820/* Get the number of defined controls */
2821unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2822{
c05c0462 2823 return hdw->control_cnt;
d855497e
MI		 2824}
2825
2826
2827/* Retrieve a control handle given its index (0..count-1) */
2828struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2829 unsigned int idx)
2830{
a0fd1cb1 2831 if (idx >= hdw->control_cnt) return NULL;
d855497e
MI		 2832 return hdw->controls + idx;
2833}
2834
2835
2836/* Retrieve a control handle given its index (0..count-1) */
2837struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2838 unsigned int ctl_id)
2839{
2840 struct pvr2_ctrl *cptr;
2841 unsigned int idx;
2842 int i;
2843
2844 /* This could be made a lot more efficient, but for now... */
c05c0462 2845 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2846 cptr = hdw->controls + idx;
2847 i = cptr->info->internal_id;
2848 if (i && (i == ctl_id)) return cptr;
2849 }
a0fd1cb1 2850 return NULL;
d855497e
MI		 2851}
2852
2853
a761f431 2854/* Given a V4L ID, retrieve the control structure associated with it. */
d855497e
MI		 2855struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2856{
2857 struct pvr2_ctrl *cptr;
2858 unsigned int idx;
2859 int i;
2860
2861 /* This could be made a lot more efficient, but for now... */
c05c0462 2862 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2863 cptr = hdw->controls + idx;
2864 i = cptr->info->v4l_id;
2865 if (i && (i == ctl_id)) return cptr;
2866 }
a0fd1cb1 2867 return NULL;
d855497e
MI		 2868}
2869
2870
a761f431
MI		 2871/* Given a V4L ID for its immediate predecessor, retrieve the control
2872 structure associated with it. */
2873struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2874 unsigned int ctl_id)
2875{
2876 struct pvr2_ctrl *cptr,*cp2;
2877 unsigned int idx;
2878 int i;
2879
2880 /* This could be made a lot more efficient, but for now... */
a0fd1cb1 2881 cp2 = NULL;
a761f431
MI		 2882 for (idx = 0; idx < hdw->control_cnt; idx++) {
2883 cptr = hdw->controls + idx;
2884 i = cptr->info->v4l_id;
2885 if (!i) continue;
2886 if (i <= ctl_id) continue;
2887 if (cp2 && (cp2->info->v4l_id < i)) continue;
2888 cp2 = cptr;
2889 }
2890 return cp2;
a0fd1cb1 2891 return NULL;
a761f431
MI		 2892}
2893
2894
d855497e
MI		 2895static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2896{
2897 switch (tp) {
2898 case pvr2_ctl_int: return "integer";
2899 case pvr2_ctl_enum: return "enum";
33213963 2900 case pvr2_ctl_bool: return "boolean";
d855497e
MI		 2901 case pvr2_ctl_bitmask: return "bitmask";
2902 }
2903 return "";
2904}
2905
2906
2641df36
MI		 2907static void pvr2_subdev_set_control(struct pvr2_hdw *hdw, int id,
2908 const char *name, int val)
2909{
2910 struct v4l2_control ctrl;
2911 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 %s=%d", name, val);
2912 memset(&ctrl, 0, sizeof(ctrl));
2913 ctrl.id = id;
2914 ctrl.value = val;
2915 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, s_ctrl, &ctrl);
2916}
2917
2918#define PVR2_SUBDEV_SET_CONTROL(hdw, id, lab) \
27764726 2919 if ((hdw)->lab##_dirty || (hdw)->force_dirty) { \
2641df36
MI		 2920 pvr2_subdev_set_control(hdw, id, #lab, (hdw)->lab##_val); \
2921 }
2922
5ceaad14 2923/* Execute whatever commands are required to update the state of all the
2641df36 2924 sub-devices so that they match our current control values. */
5ceaad14
MI		 2925static void pvr2_subdev_update(struct pvr2_hdw *hdw)
2926{
edb9dcb8
MI		 2927 struct v4l2_subdev *sd;
2928 unsigned int id;
2929 pvr2_subdev_update_func fp;
2930
75212a02
MI		 2931 pvr2_trace(PVR2_TRACE_CHIPS, "subdev update...");
2932
27764726 2933 if (hdw->tuner_updated || hdw->force_dirty) {
75212a02
MI		 2934 struct tuner_setup setup;
2935 pvr2_trace(PVR2_TRACE_CHIPS, "subdev tuner set_type(%d)",
2936 hdw->tuner_type);
2937 if (((int)(hdw->tuner_type)) >= 0) {
fcd62cf7 2938 memset(&setup, 0, sizeof(setup));
75212a02
MI		 2939 setup.addr = ADDR_UNSET;
2940 setup.type = hdw->tuner_type;
2941 setup.mode_mask = T_RADIO | T_ANALOG_TV;
2942 v4l2_device_call_all(&hdw->v4l2_dev, 0,
2943 tuner, s_type_addr, &setup);
2944 }
2945 }
2946
27764726 2947 if (hdw->input_dirty || hdw->std_dirty || hdw->force_dirty) {
b481880b 2948 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_standard");
2641df36
MI		 2949 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2950 v4l2_device_call_all(&hdw->v4l2_dev, 0,
2951 tuner, s_radio);
2952 } else {
2953 v4l2_std_id vs;
2954 vs = hdw->std_mask_cur;
2955 v4l2_device_call_all(&hdw->v4l2_dev, 0,
f41737ec 2956 core, s_std, vs);
2641df36
MI		 2957 }
2958 hdw->tuner_signal_stale = !0;
2959 hdw->cropcap_stale = !0;
2960 }
2961
2962 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_BRIGHTNESS, brightness);
2963 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_CONTRAST, contrast);
2964 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_SATURATION, saturation);
2965 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_HUE, hue);
2966 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_MUTE, mute);
2967 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_VOLUME, volume);
2968 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BALANCE, balance);
2969 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BASS, bass);
2970 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_TREBLE, treble);
2971
27764726 2972 if (hdw->input_dirty || hdw->audiomode_dirty || hdw->force_dirty) {
2641df36
MI		 2973 struct v4l2_tuner vt;
2974 memset(&vt, 0, sizeof(vt));
2975 vt.audmode = hdw->audiomode_val;
2976 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, s_tuner, &vt);
2977 }
2978
27764726 2979 if (hdw->freqDirty || hdw->force_dirty) {
2641df36
MI		 2980 unsigned long fv;
2981 struct v4l2_frequency freq;
2982 fv = pvr2_hdw_get_cur_freq(hdw);
2983 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_freq(%lu)", fv);
2984 if (hdw->tuner_signal_stale) pvr2_hdw_status_poll(hdw);
2985 memset(&freq, 0, sizeof(freq));
2986 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
2987 /* ((fv * 1000) / 62500) */
2988 freq.frequency = (fv * 2) / 125;
2989 } else {
2990 freq.frequency = fv / 62500;
2991 }
2992 /* tuner-core currently doesn't seem to care about this, but
2993 let's set it anyway for completeness. */
2994 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2995 freq.type = V4L2_TUNER_RADIO;
2996 } else {
2997 freq.type = V4L2_TUNER_ANALOG_TV;
2998 }
2999 freq.tuner = 0;
3000 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner,
3001 s_frequency, &freq);
3002 }
3003
27764726 3004 if (hdw->res_hor_dirty || hdw->res_ver_dirty || hdw->force_dirty) {
2641df36
MI		 3005 struct v4l2_format fmt;
3006 memset(&fmt, 0, sizeof(fmt));
3007 fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
3008 fmt.fmt.pix.width = hdw->res_hor_val;
3009 fmt.fmt.pix.height = hdw->res_ver_val;
7dfdf1ee 3010 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_size(%dx%d)",
2641df36
MI		 3011 fmt.fmt.pix.width, fmt.fmt.pix.height);
3012 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_fmt, &fmt);
3013 }
3014
27764726 3015 if (hdw->srate_dirty || hdw->force_dirty) {
01c59df8
MI		 3016 u32 val;
3017 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_audio %d",
3018 hdw->srate_val);
3019 switch (hdw->srate_val) {
3020 default:
3021 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000:
3022 val = 48000;
3023 break;
3024 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100:
3025 val = 44100;
3026 break;
3027 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000:
3028 val = 32000;
3029 break;
3030 }
3031 v4l2_device_call_all(&hdw->v4l2_dev, 0,
3032 audio, s_clock_freq, val);
3033 }
3034
2641df36
MI		 3035 /* Unable to set crop parameters; there is apparently no equivalent
3036 for VIDIOC_S_CROP */
3037
edb9dcb8
MI		 3038 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
3039 id = sd->grp_id;
3040 if (id >= ARRAY_SIZE(pvr2_module_update_functions)) continue;
3041 fp = pvr2_module_update_functions[id];
3042 if (!fp) continue;
3043 (*fp)(hdw, sd);
3044 }
2641df36 3045
27764726 3046 if (hdw->tuner_signal_stale || hdw->cropcap_stale) {
2641df36
MI		 3047 pvr2_hdw_status_poll(hdw);
3048 }
5ceaad14
MI		 3049}
3050
3051
681c7399
MI		 3052/* Figure out if we need to commit control changes. If so, mark internal
3053 state flags to indicate this fact and return true. Otherwise do nothing
3054 else and return false. */
3055static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
d855497e 3056{
d855497e
MI		 3057 unsigned int idx;
3058 struct pvr2_ctrl *cptr;
3059 int value;
27764726 3060 int commit_flag = hdw->force_dirty;
d855497e
MI		 3061 char buf[100];
3062 unsigned int bcnt,ccnt;
3063
c05c0462 3064 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e 3065 cptr = hdw->controls + idx;
5fa1247a 3066 if (!cptr->info->is_dirty) continue;
d855497e 3067 if (!cptr->info->is_dirty(cptr)) continue;
fe23a280 3068 commit_flag = !0;
d855497e 3069
fe23a280 3070 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
d855497e
MI		 3071 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
3072 cptr->info->name);
3073 value = 0;
3074 cptr->info->get_value(cptr,&value);
3075 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
3076 buf+bcnt,
3077 sizeof(buf)-bcnt,&ccnt);
3078 bcnt += ccnt;
3079 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
3080 get_ctrl_typename(cptr->info->type));
3081 pvr2_trace(PVR2_TRACE_CTL,
3082 "/*--TRACE_COMMIT--*/ %.*s",
3083 bcnt,buf);
3084 }
3085
3086 if (!commit_flag) {
3087 /* Nothing has changed */
3088 return 0;
3089 }
3090
681c7399
MI		 3091 hdw->state_pipeline_config = 0;
3092 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3093 pvr2_hdw_state_sched(hdw);
3094
3095 return !0;
3096}
3097
3098
3099/* Perform all operations needed to commit all control changes. This must
3100 be performed in synchronization with the pipeline state and is thus
3101 expected to be called as part of the driver's worker thread. Return
3102 true if commit successful, otherwise return false to indicate that
3103 commit isn't possible at this time. */
3104static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
3105{
3106 unsigned int idx;
3107 struct pvr2_ctrl *cptr;
3108 int disruptive_change;
3109
ab062fe3
MI		 3110 /* Handle some required side effects when the video standard is
3111 changed.... */
d855497e 3112 if (hdw->std_dirty) {
d855497e 3113 int nvres;
00528d9c 3114 int gop_size;
d855497e
MI		 3115 if (hdw->std_mask_cur & V4L2_STD_525_60) {
3116 nvres = 480;
00528d9c 3117 gop_size = 15;
d855497e
MI		 3118 } else {
3119 nvres = 576;
00528d9c 3120 gop_size = 12;
d855497e 3121 }
00528d9c
MI		 3122 /* Rewrite the vertical resolution to be appropriate to the
3123 video standard that has been selected. */
d855497e
MI		 3124 if (nvres != hdw->res_ver_val) {
3125 hdw->res_ver_val = nvres;
3126 hdw->res_ver_dirty = !0;
3127 }
00528d9c
MI		 3128 /* Rewrite the GOP size to be appropriate to the video
3129 standard that has been selected. */
3130 if (gop_size != hdw->enc_ctl_state.video_gop_size) {
3131 struct v4l2_ext_controls cs;
3132 struct v4l2_ext_control c1;
3133 memset(&cs, 0, sizeof(cs));
3134 memset(&c1, 0, sizeof(c1));
3135 cs.controls = &c1;
3136 cs.count = 1;
3137 c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE;
3138 c1.value = gop_size;
3139 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,
3140 VIDIOC_S_EXT_CTRLS);
3141 }
d855497e
MI		 3142 }
3143
38d9a2cf 3144 if (hdw->input_dirty && hdw->state_pathway_ok &&
62433e31
MI		 3145 (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
3146 PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
3147 hdw->pathway_state)) {
3148 /* Change of mode being asked for... */
3149 hdw->state_pathway_ok = 0;
e9db1ff2 3150 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
62433e31
MI		 3151 }
3152 if (!hdw->state_pathway_ok) {
3153 /* Can't commit anything until pathway is ok. */
3154 return 0;
3155 }
e784bfb9 3156 /* The broadcast decoder can only scale down, so if
3157 * res_*_dirty && crop window < output format ==> enlarge crop.
3158 *
3159 * The mpeg encoder receives fields of res_hor_val dots and
3160 * res_ver_val halflines. Limits: hor<=720, ver<=576.
3161 */
3162 if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) {
3163 hdw->cropw_val = hdw->res_hor_val;
3164 hdw->cropw_dirty = !0;
3165 } else if (hdw->cropw_dirty) {
3166 hdw->res_hor_dirty = !0; /* must rescale */
3167 hdw->res_hor_val = min(720, hdw->cropw_val);
3168 }
3169 if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) {
3170 hdw->croph_val = hdw->res_ver_val;
3171 hdw->croph_dirty = !0;
3172 } else if (hdw->croph_dirty) {
3173 int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576;
3174 hdw->res_ver_dirty = !0;
3175 hdw->res_ver_val = min(nvres, hdw->croph_val);
3176 }
3177
681c7399
MI		 3178 /* If any of the below has changed, then we can't do the update
3179 while the pipeline is running. Pipeline must be paused first
3180 and decoder -> encoder connection be made quiescent before we
3181 can proceed. */
3182 disruptive_change =
3183 (hdw->std_dirty ||
3184 hdw->enc_unsafe_stale ||
3185 hdw->srate_dirty ||
3186 hdw->res_ver_dirty ||
3187 hdw->res_hor_dirty ||
755879c6
MI		 3188 hdw->cropw_dirty ||
3189 hdw->croph_dirty ||
681c7399
MI		 3190 hdw->input_dirty ||
3191 (hdw->active_stream_type != hdw->desired_stream_type));
3192 if (disruptive_change && !hdw->state_pipeline_idle) {
3193 /* Pipeline is not idle; we can't proceed. Arrange to
3194 cause pipeline to stop so that we can try this again
3195 later.... */
3196 hdw->state_pipeline_pause = !0;
3197 return 0;
275b2e28
PK		 3198 }
3199
b30d2441
MI		 3200 if (hdw->srate_dirty) {
3201 /* Write new sample rate into control structure since
3202 * the master copy is stale. We must track srate
3203 * separate from the mpeg control structure because
3204 * other logic also uses this value. */
3205 struct v4l2_ext_controls cs;
3206 struct v4l2_ext_control c1;
3207 memset(&cs,0,sizeof(cs));
3208 memset(&c1,0,sizeof(c1));
3209 cs.controls = &c1;
3210 cs.count = 1;
3211 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
3212 c1.value = hdw->srate_val;
01f1e44f 3213 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
b30d2441 3214 }
c05c0462 3215
681c7399
MI		 3216 if (hdw->active_stream_type != hdw->desired_stream_type) {
3217 /* Handle any side effects of stream config here */
3218 hdw->active_stream_type = hdw->desired_stream_type;
3219 }
3220
1df59f0b
MI		 3221 if (hdw->hdw_desc->signal_routing_scheme ==
3222 PVR2_ROUTING_SCHEME_GOTVIEW) {
3223 u32 b;
3224 /* Handle GOTVIEW audio switching */
3225 pvr2_hdw_gpio_get_out(hdw,&b);
3226 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3227 /* Set GPIO 11 */
3228 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0);
3229 } else {
3230 /* Clear GPIO 11 */
3231 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0);
3232 }
3233 }
3234
e68a619a
MI		 3235 /* Check and update state for all sub-devices. */
3236 pvr2_subdev_update(hdw);
3237
75212a02 3238 hdw->tuner_updated = 0;
27764726 3239 hdw->force_dirty = 0;
5ceaad14
MI		 3240 for (idx = 0; idx < hdw->control_cnt; idx++) {
3241 cptr = hdw->controls + idx;
3242 if (!cptr->info->clear_dirty) continue;
3243 cptr->info->clear_dirty(cptr);
3244 }
3245
62433e31
MI		 3246 if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
3247 hdw->state_encoder_run) {
3248 /* If encoder isn't running or it can't be touched, then
3249 this will get worked out later when we start the
3250 encoder. */
681c7399
MI		 3251 if (pvr2_encoder_adjust(hdw) < 0) return !0;
3252 }
d855497e 3253
681c7399 3254 hdw->state_pipeline_config = !0;
432907f7
MI		 3255 /* Hardware state may have changed in a way to cause the cropping
3256 capabilities to have changed. So mark it stale, which will
3257 cause a later re-fetch. */
681c7399
MI		 3258 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3259 return !0;
d855497e
MI		 3260}
3261
3262
3263int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
3264{
681c7399
MI		 3265 int fl;
3266 LOCK_TAKE(hdw->big_lock);
3267 fl = pvr2_hdw_commit_setup(hdw);
3268 LOCK_GIVE(hdw->big_lock);
3269 if (!fl) return 0;
3270 return pvr2_hdw_wait(hdw,0);
3271}
3272
3273
681c7399 3274static void pvr2_hdw_worker_poll(struct work_struct *work)
d855497e 3275{
681c7399
MI		 3276 int fl = 0;
3277 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
d855497e 3278 LOCK_TAKE(hdw->big_lock); do {
681c7399 3279 fl = pvr2_hdw_state_eval(hdw);
d855497e 3280 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 3281 if (fl && hdw->state_func) {
3282 hdw->state_func(hdw->state_data);
3283 }
d855497e
MI		 3284}
3285
3286
681c7399 3287static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
d855497e 3288{
681c7399
MI		 3289 return wait_event_interruptible(
3290 hdw->state_wait_data,
3291 (hdw->state_stale == 0) &&
3292 (!state || (hdw->master_state != state)));
3293}
3294
3295
d855497e
MI		 3296/* Return name for this driver instance */
3297const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
3298{
3299 return hdw->name;
3300}
3301
3302
78a47101
MI		 3303const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
3304{
3305 return hdw->hdw_desc->description;
3306}
3307
3308
3309const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
3310{
3311 return hdw->hdw_desc->shortname;
3312}
3313
3314
d855497e
MI		 3315int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
3316{
3317 int result;
3318 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 3319 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
d855497e
MI		 3320 result = pvr2_send_request(hdw,
3321 hdw->cmd_buffer,1,
3322 hdw->cmd_buffer,1);
3323 if (result < 0) break;
3324 result = (hdw->cmd_buffer[0] != 0);
3325 } while(0); LOCK_GIVE(hdw->ctl_lock);
3326 return result;
3327}
3328
3329
18103c57
MI		 3330/* Execute poll of tuner status */
3331void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
d855497e 3332{
d855497e 3333 LOCK_TAKE(hdw->big_lock); do {
a51f5000 3334 pvr2_hdw_status_poll(hdw);
d855497e 3335 } while (0); LOCK_GIVE(hdw->big_lock);
18103c57
MI		 3336}
3337
3338
432907f7
MI		 3339static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw)
3340{
3341 if (!hdw->cropcap_stale) {
432907f7
MI		 3342 return 0;
3343 }
a51f5000 3344 pvr2_hdw_status_poll(hdw);
432907f7 3345 if (hdw->cropcap_stale) {
432907f7
MI		 3346 return -EIO;
3347 }
3348 return 0;
3349}
3350
3351
3352/* Return information about cropping capabilities */
3353int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp)
3354{
3355 int stat = 0;
3356 LOCK_TAKE(hdw->big_lock);
3357 stat = pvr2_hdw_check_cropcap(hdw);
3358 if (!stat) {
432907f7
MI		 3359 memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info));
3360 }
3361 LOCK_GIVE(hdw->big_lock);
3362 return stat;
3363}
3364
3365
18103c57
MI		 3366/* Return information about the tuner */
3367int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
3368{
3369 LOCK_TAKE(hdw->big_lock); do {
3370 if (hdw->tuner_signal_stale) {
a51f5000 3371 pvr2_hdw_status_poll(hdw);
18103c57
MI		 3372 }
3373 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
3374 } while (0); LOCK_GIVE(hdw->big_lock);
3375 return 0;
d855497e
MI		 3376}
3377
3378
3379/* Get handle to video output stream */
3380struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
3381{
3382 return hp->vid_stream;
3383}
3384
3385
3386void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
3387{
4f1a3e5b 3388 int nr = pvr2_hdw_get_unit_number(hdw);
d855497e 3389 LOCK_TAKE(hdw->big_lock); do {
4f1a3e5b 3390 printk(KERN_INFO "pvrusb2: ================= START STATUS CARD #%d =================\n", nr);
ed3261a8 3391 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, log_status);
b30d2441 3392 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
99eb44fe 3393 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
681c7399 3394 pvr2_hdw_state_log_state(hdw);
4f1a3e5b 3395 printk(KERN_INFO "pvrusb2: ================== END STATUS CARD #%d ==================\n", nr);
d855497e
MI		 3396 } while (0); LOCK_GIVE(hdw->big_lock);
3397}
3398
4db666cc
MI		 3399
3400/* Grab EEPROM contents, needed for direct method. */
3401#define EEPROM_SIZE 8192
3402#define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
3403static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
3404{
3405 struct i2c_msg msg[2];
3406 u8 *eeprom;
3407 u8 iadd[2];
3408 u8 addr;
3409 u16 eepromSize;
3410 unsigned int offs;
3411 int ret;
3412 int mode16 = 0;
3413 unsigned pcnt,tcnt;
3414 eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
3415 if (!eeprom) {
3416 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3417 "Failed to allocate memory"
3418 " required to read eeprom");
3419 return NULL;
3420 }
3421
3422 trace_eeprom("Value for eeprom addr from controller was 0x%x",
3423 hdw->eeprom_addr);
3424 addr = hdw->eeprom_addr;
3425 /* Seems that if the high bit is set, then the *real* eeprom
3426 address is shifted right now bit position (noticed this in
3427 newer PVR USB2 hardware) */
3428 if (addr & 0x80) addr >>= 1;
3429
3430 /* FX2 documentation states that a 16bit-addressed eeprom is
3431 expected if the I2C address is an odd number (yeah, this is
3432 strange but it's what they do) */
3433 mode16 = (addr & 1);
3434 eepromSize = (mode16 ? EEPROM_SIZE : 256);
3435 trace_eeprom("Examining %d byte eeprom at location 0x%x"
3436 " using %d bit addressing",eepromSize,addr,
3437 mode16 ? 16 : 8);
3438
3439 msg[0].addr = addr;
3440 msg[0].flags = 0;
3441 msg[0].len = mode16 ? 2 : 1;
3442 msg[0].buf = iadd;
3443 msg[1].addr = addr;
3444 msg[1].flags = I2C_M_RD;
3445
3446 /* We have to do the actual eeprom data fetch ourselves, because
3447 (1) we're only fetching part of the eeprom, and (2) if we were
3448 getting the whole thing our I2C driver can't grab it in one
3449 pass - which is what tveeprom is otherwise going to attempt */
3450 memset(eeprom,0,EEPROM_SIZE);
3451 for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
3452 pcnt = 16;
3453 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
3454 offs = tcnt + (eepromSize - EEPROM_SIZE);
3455 if (mode16) {
3456 iadd[0] = offs >> 8;
3457 iadd[1] = offs;
3458 } else {
3459 iadd[0] = offs;
3460 }
3461 msg[1].len = pcnt;
3462 msg[1].buf = eeprom+tcnt;
3463 if ((ret = i2c_transfer(&hdw->i2c_adap,
3464 msg,ARRAY_SIZE(msg))) != 2) {
3465 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3466 "eeprom fetch set offs err=%d",ret);
3467 kfree(eeprom);
3468 return NULL;
3469 }
3470 }
3471 return eeprom;
3472}
3473
3474
3475void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
3476 int prom_flag,
3477 int enable_flag)
d855497e
MI		 3478{
3479 int ret;
3480 u16 address;
3481 unsigned int pipe;
3482 LOCK_TAKE(hdw->big_lock); do {
5fa1247a 3483 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
d855497e
MI		 3484
3485 if (!enable_flag) {
3486 pvr2_trace(PVR2_TRACE_FIRMWARE,
3487 "Cleaning up after CPU firmware fetch");
3488 kfree(hdw->fw_buffer);
a0fd1cb1 3489 hdw->fw_buffer = NULL;
d855497e 3490 hdw->fw_size = 0;
4db666cc
MI		 3491 if (hdw->fw_cpu_flag) {
3492 /* Now release the CPU. It will disconnect
3493 and reconnect later. */
3494 pvr2_hdw_cpureset_assert(hdw,0);
3495 }
d855497e
MI		 3496 break;
3497 }
3498
4db666cc
MI		 3499 hdw->fw_cpu_flag = (prom_flag == 0);
3500 if (hdw->fw_cpu_flag) {
3501 pvr2_trace(PVR2_TRACE_FIRMWARE,
3502 "Preparing to suck out CPU firmware");
3503 hdw->fw_size = 0x2000;
3504 hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
3505 if (!hdw->fw_buffer) {
3506 hdw->fw_size = 0;
3507 break;
3508 }
d855497e 3509
4db666cc
MI		 3510 /* We have to hold the CPU during firmware upload. */
3511 pvr2_hdw_cpureset_assert(hdw,1);
d855497e 3512
4db666cc
MI		 3513 /* download the firmware from address 0000-1fff in 2048
3514 (=0x800) bytes chunk. */
d855497e 3515
4db666cc
MI		 3516 pvr2_trace(PVR2_TRACE_FIRMWARE,
3517 "Grabbing CPU firmware");
3518 pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
3519 for(address = 0; address < hdw->fw_size;
3520 address += 0x800) {
3521 ret = usb_control_msg(hdw->usb_dev,pipe,
3522 0xa0,0xc0,
3523 address,0,
3524 hdw->fw_buffer+address,
3525 0x800,HZ);
3526 if (ret < 0) break;
3527 }
d855497e 3528
4db666cc
MI		 3529 pvr2_trace(PVR2_TRACE_FIRMWARE,
3530 "Done grabbing CPU firmware");
3531 } else {
3532 pvr2_trace(PVR2_TRACE_FIRMWARE,
3533 "Sucking down EEPROM contents");
3534 hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
3535 if (!hdw->fw_buffer) {
3536 pvr2_trace(PVR2_TRACE_FIRMWARE,
3537 "EEPROM content suck failed.");
3538 break;
3539 }
3540 hdw->fw_size = EEPROM_SIZE;
3541 pvr2_trace(PVR2_TRACE_FIRMWARE,
3542 "Done sucking down EEPROM contents");
3543 }
d855497e
MI		 3544
3545 } while (0); LOCK_GIVE(hdw->big_lock);
3546}
3547
3548
3549/* Return true if we're in a mode for retrieval CPU firmware */
3550int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
3551{
5fa1247a 3552 return hdw->fw_buffer != NULL;
d855497e
MI		 3553}
3554
3555
3556int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
3557 char *buf,unsigned int cnt)
3558{
3559 int ret = -EINVAL;
3560 LOCK_TAKE(hdw->big_lock); do {
3561 if (!buf) break;
3562 if (!cnt) break;
3563
3564 if (!hdw->fw_buffer) {
3565 ret = -EIO;
3566 break;
3567 }
3568
3569 if (offs >= hdw->fw_size) {
3570 pvr2_trace(PVR2_TRACE_FIRMWARE,
3571 "Read firmware data offs=%d EOF",
3572 offs);
3573 ret = 0;
3574 break;
3575 }
3576
3577 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
3578
3579 memcpy(buf,hdw->fw_buffer+offs,cnt);
3580
3581 pvr2_trace(PVR2_TRACE_FIRMWARE,
3582 "Read firmware data offs=%d cnt=%d",
3583 offs,cnt);
3584 ret = cnt;
3585 } while (0); LOCK_GIVE(hdw->big_lock);
3586
3587 return ret;
3588}
3589
3590
fd5a75fe 3591int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
8079384e 3592 enum pvr2_v4l_type index)
d855497e 3593{
fd5a75fe 3594 switch (index) {
8079384e
MI		 3595 case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
3596 case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
3597 case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
fd5a75fe
MI		 3598 default: return -1;
3599 }
d855497e
MI		 3600}
3601
3602
2fdf3d9c 3603/* Store a v4l minor device number */
fd5a75fe 3604void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
8079384e 3605 enum pvr2_v4l_type index,int v)
d855497e 3606{
fd5a75fe 3607 switch (index) {
8079384e
MI		 3608 case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
3609 case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
3610 case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
fd5a75fe
MI		 3611 default: break;
3612 }
d855497e
MI		 3613}
3614
3615
7d12e780 3616static void pvr2_ctl_write_complete(struct urb *urb)
d855497e
MI		 3617{
3618 struct pvr2_hdw *hdw = urb->context;
3619 hdw->ctl_write_pend_flag = 0;
3620 if (hdw->ctl_read_pend_flag) return;
3621 complete(&hdw->ctl_done);
3622}
3623
3624
7d12e780 3625static void pvr2_ctl_read_complete(struct urb *urb)
d855497e
MI		 3626{
3627 struct pvr2_hdw *hdw = urb->context;
3628 hdw->ctl_read_pend_flag = 0;
3629 if (hdw->ctl_write_pend_flag) return;
3630 complete(&hdw->ctl_done);
3631}
3632
3633
3634static void pvr2_ctl_timeout(unsigned long data)
3635{
3636 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3637 if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3638 hdw->ctl_timeout_flag = !0;
5e55d2ce 3639 if (hdw->ctl_write_pend_flag)
d855497e 3640 usb_unlink_urb(hdw->ctl_write_urb);
5e55d2ce 3641 if (hdw->ctl_read_pend_flag)
d855497e 3642 usb_unlink_urb(hdw->ctl_read_urb);
d855497e
MI		 3643 }
3644}
3645
3646
e61b6fc5
MI		 3647/* Issue a command and get a response from the device. This extended
3648 version includes a probe flag (which if set means that device errors
3649 should not be logged or treated as fatal) and a timeout in jiffies.
3650 This can be used to non-lethally probe the health of endpoint 1. */
07e337ee
AB		 3651static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
3652 unsigned int timeout,int probe_fl,
3653 void *write_data,unsigned int write_len,
3654 void *read_data,unsigned int read_len)
d855497e
MI		 3655{
3656 unsigned int idx;
3657 int status = 0;
3658 struct timer_list timer;
3659 if (!hdw->ctl_lock_held) {
3660 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3661 "Attempted to execute control transfer"
3662 " without lock!!");
3663 return -EDEADLK;
3664 }
681c7399 3665 if (!hdw->flag_ok && !probe_fl) {
d855497e
MI		 3666 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3667 "Attempted to execute control transfer"
3668 " when device not ok");
3669 return -EIO;
3670 }
3671 if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
3672 if (!probe_fl) {
3673 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3674 "Attempted to execute control transfer"
3675 " when USB is disconnected");
3676 }
3677 return -ENOTTY;
3678 }
3679
3680 /* Ensure that we have sane parameters */
3681 if (!write_data) write_len = 0;
3682 if (!read_data) read_len = 0;
3683 if (write_len > PVR2_CTL_BUFFSIZE) {
3684 pvr2_trace(
3685 PVR2_TRACE_ERROR_LEGS,
3686 "Attempted to execute %d byte"
3687 " control-write transfer (limit=%d)",
3688 write_len,PVR2_CTL_BUFFSIZE);
3689 return -EINVAL;
3690 }
3691 if (read_len > PVR2_CTL_BUFFSIZE) {
3692 pvr2_trace(
3693 PVR2_TRACE_ERROR_LEGS,
3694 "Attempted to execute %d byte"
3695 " control-read transfer (limit=%d)",
3696 write_len,PVR2_CTL_BUFFSIZE);
3697 return -EINVAL;
3698 }
3699 if ((!write_len) && (!read_len)) {
3700 pvr2_trace(
3701 PVR2_TRACE_ERROR_LEGS,
3702 "Attempted to execute null control transfer?");
3703 return -EINVAL;
3704 }
3705
3706
3707 hdw->cmd_debug_state = 1;
3708 if (write_len) {
3709 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
3710 } else {
3711 hdw->cmd_debug_code = 0;
3712 }
3713 hdw->cmd_debug_write_len = write_len;
3714 hdw->cmd_debug_read_len = read_len;
3715
3716 /* Initialize common stuff */
3717 init_completion(&hdw->ctl_done);
3718 hdw->ctl_timeout_flag = 0;
3719 hdw->ctl_write_pend_flag = 0;
3720 hdw->ctl_read_pend_flag = 0;
3721 init_timer(&timer);
3722 timer.expires = jiffies + timeout;
3723 timer.data = (unsigned long)hdw;
3724 timer.function = pvr2_ctl_timeout;
3725
3726 if (write_len) {
3727 hdw->cmd_debug_state = 2;
3728 /* Transfer write data to internal buffer */
3729 for (idx = 0; idx < write_len; idx++) {
3730 hdw->ctl_write_buffer[idx] =
3731 ((unsigned char *)write_data)[idx];
3732 }
3733 /* Initiate a write request */
3734 usb_fill_bulk_urb(hdw->ctl_write_urb,
3735 hdw->usb_dev,
3736 usb_sndbulkpipe(hdw->usb_dev,
3737 PVR2_CTL_WRITE_ENDPOINT),
3738 hdw->ctl_write_buffer,
3739 write_len,
3740 pvr2_ctl_write_complete,
3741 hdw);
3742 hdw->ctl_write_urb->actual_length = 0;
3743 hdw->ctl_write_pend_flag = !0;
3744 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
3745 if (status < 0) {
3746 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3747 "Failed to submit write-control"
3748 " URB status=%d",status);
3749 hdw->ctl_write_pend_flag = 0;
3750 goto done;
3751 }
3752 }
3753
3754 if (read_len) {
3755 hdw->cmd_debug_state = 3;
3756 memset(hdw->ctl_read_buffer,0x43,read_len);
3757 /* Initiate a read request */
3758 usb_fill_bulk_urb(hdw->ctl_read_urb,
3759 hdw->usb_dev,
3760 usb_rcvbulkpipe(hdw->usb_dev,
3761 PVR2_CTL_READ_ENDPOINT),
3762 hdw->ctl_read_buffer,
3763 read_len,
3764 pvr2_ctl_read_complete,
3765 hdw);
3766 hdw->ctl_read_urb->actual_length = 0;
3767 hdw->ctl_read_pend_flag = !0;
3768 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3769 if (status < 0) {
3770 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3771 "Failed to submit read-control"
3772 " URB status=%d",status);
3773 hdw->ctl_read_pend_flag = 0;
3774 goto done;
3775 }
3776 }
3777
3778 /* Start timer */
3779 add_timer(&timer);
3780
3781 /* Now wait for all I/O to complete */
3782 hdw->cmd_debug_state = 4;
3783 while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3784 wait_for_completion(&hdw->ctl_done);
3785 }
3786 hdw->cmd_debug_state = 5;
3787
3788 /* Stop timer */
3789 del_timer_sync(&timer);
3790
3791 hdw->cmd_debug_state = 6;
3792 status = 0;
3793
3794 if (hdw->ctl_timeout_flag) {
3795 status = -ETIMEDOUT;
3796 if (!probe_fl) {
3797 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3798 "Timed out control-write");
3799 }
3800 goto done;
3801 }
3802
3803 if (write_len) {
3804 /* Validate results of write request */
3805 if ((hdw->ctl_write_urb->status != 0) &&
3806 (hdw->ctl_write_urb->status != -ENOENT) &&
3807 (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3808 (hdw->ctl_write_urb->status != -ECONNRESET)) {
3809 /* USB subsystem is reporting some kind of failure
3810 on the write */
3811 status = hdw->ctl_write_urb->status;
3812 if (!probe_fl) {
3813 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3814 "control-write URB failure,"
3815 " status=%d",
3816 status);
3817 }
3818 goto done;
3819 }
3820 if (hdw->ctl_write_urb->actual_length < write_len) {
3821 /* Failed to write enough data */
3822 status = -EIO;
3823 if (!probe_fl) {
3824 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3825 "control-write URB short,"
3826 " expected=%d got=%d",
3827 write_len,
3828 hdw->ctl_write_urb->actual_length);
3829 }
3830 goto done;
3831 }
3832 }
3833 if (read_len) {
3834 /* Validate results of read request */
3835 if ((hdw->ctl_read_urb->status != 0) &&
3836 (hdw->ctl_read_urb->status != -ENOENT) &&
3837 (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3838 (hdw->ctl_read_urb->status != -ECONNRESET)) {
3839 /* USB subsystem is reporting some kind of failure
3840 on the read */
3841 status = hdw->ctl_read_urb->status;
3842 if (!probe_fl) {
3843 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3844 "control-read URB failure,"
3845 " status=%d",
3846 status);
3847 }
3848 goto done;
3849 }
3850 if (hdw->ctl_read_urb->actual_length < read_len) {
3851 /* Failed to read enough data */
3852 status = -EIO;
3853 if (!probe_fl) {
3854 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3855 "control-read URB short,"
3856 " expected=%d got=%d",
3857 read_len,
3858 hdw->ctl_read_urb->actual_length);
3859 }
3860 goto done;
3861 }
3862 /* Transfer retrieved data out from internal buffer */
3863 for (idx = 0; idx < read_len; idx++) {
3864 ((unsigned char *)read_data)[idx] =
3865 hdw->ctl_read_buffer[idx];
3866 }
3867 }
3868
3869 done:
3870
3871 hdw->cmd_debug_state = 0;
3872 if ((status < 0) && (!probe_fl)) {
681c7399 3873 pvr2_hdw_render_useless(hdw);
d855497e
MI		 3874 }
3875 return status;
3876}
3877
3878
3879int pvr2_send_request(struct pvr2_hdw *hdw,
3880 void *write_data,unsigned int write_len,
3881 void *read_data,unsigned int read_len)
3882{
3883 return pvr2_send_request_ex(hdw,HZ*4,0,
3884 write_data,write_len,
3885 read_data,read_len);
3886}
3887
1c9d10d4
MI		 3888
3889static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3890{
3891 int ret;
3892 unsigned int cnt = 1;
3893 unsigned int args = 0;
3894 LOCK_TAKE(hdw->ctl_lock);
3895 hdw->cmd_buffer[0] = cmdcode & 0xffu;
3896 args = (cmdcode >> 8) & 0xffu;
3897 args = (args > 2) ? 2 : args;
3898 if (args) {
3899 cnt += args;
3900 hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3901 if (args > 1) {
3902 hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3903 }
3904 }
3905 if (pvrusb2_debug & PVR2_TRACE_INIT) {
3906 unsigned int idx;
3907 unsigned int ccnt,bcnt;
3908 char tbuf[50];
3909 cmdcode &= 0xffu;
3910 bcnt = 0;
3911 ccnt = scnprintf(tbuf+bcnt,
3912 sizeof(tbuf)-bcnt,
3913 "Sending FX2 command 0x%x",cmdcode);
3914 bcnt += ccnt;
3915 for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
3916 if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
3917 ccnt = scnprintf(tbuf+bcnt,
3918 sizeof(tbuf)-bcnt,
3919 " \"%s\"",
3920 pvr2_fx2cmd_desc[idx].desc);
3921 bcnt += ccnt;
3922 break;
3923 }
3924 }
3925 if (args) {
3926 ccnt = scnprintf(tbuf+bcnt,
3927 sizeof(tbuf)-bcnt,
3928 " (%u",hdw->cmd_buffer[1]);
3929 bcnt += ccnt;
3930 if (args > 1) {
3931 ccnt = scnprintf(tbuf+bcnt,
3932 sizeof(tbuf)-bcnt,
3933 ",%u",hdw->cmd_buffer[2]);
3934 bcnt += ccnt;
3935 }
3936 ccnt = scnprintf(tbuf+bcnt,
3937 sizeof(tbuf)-bcnt,
3938 ")");
3939 bcnt += ccnt;
3940 }
3941 pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
3942 }
3943 ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
3944 LOCK_GIVE(hdw->ctl_lock);
3945 return ret;
3946}
3947
3948
d855497e
MI		 3949int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3950{
3951 int ret;
3952
3953 LOCK_TAKE(hdw->ctl_lock);
3954
8d364363 3955 hdw->cmd_buffer[0] = FX2CMD_REG_WRITE; /* write register prefix */
d855497e
MI		 3956 PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
3957 hdw->cmd_buffer[5] = 0;
3958 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3959 hdw->cmd_buffer[7] = reg & 0xff;
3960
3961
3962 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
3963
3964 LOCK_GIVE(hdw->ctl_lock);
3965
3966 return ret;
3967}
3968
3969
07e337ee 3970static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
d855497e
MI		 3971{
3972 int ret = 0;
3973
3974 LOCK_TAKE(hdw->ctl_lock);
3975
8d364363 3976 hdw->cmd_buffer[0] = FX2CMD_REG_READ; /* read register prefix */
d855497e
MI		 3977 hdw->cmd_buffer[1] = 0;
3978 hdw->cmd_buffer[2] = 0;
3979 hdw->cmd_buffer[3] = 0;
3980 hdw->cmd_buffer[4] = 0;
3981 hdw->cmd_buffer[5] = 0;
3982 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3983 hdw->cmd_buffer[7] = reg & 0xff;
3984
3985 ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
3986 *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
3987
3988 LOCK_GIVE(hdw->ctl_lock);
3989
3990 return ret;
3991}
3992
3993
681c7399 3994void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
d855497e
MI		 3995{
3996 if (!hdw->flag_ok) return;
681c7399
MI		 3997 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3998 "Device being rendered inoperable");
d855497e 3999 if (hdw->vid_stream) {
a0fd1cb1 4000 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
d855497e 4001 }
681c7399
MI		 4002 hdw->flag_ok = 0;
4003 trace_stbit("flag_ok",hdw->flag_ok);
4004 pvr2_hdw_state_sched(hdw);
d855497e
MI		 4005}
4006
4007
4008void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
4009{
4010 int ret;
4011 pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
a0fd1cb1 4012 ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
011b15df 4013 if (ret == 0) {
d855497e
MI		 4014 ret = usb_reset_device(hdw->usb_dev);
4015 usb_unlock_device(hdw->usb_dev);
4016 } else {
4017 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4018 "Failed to lock USB device ret=%d",ret);
4019 }
4020 if (init_pause_msec) {
4021 pvr2_trace(PVR2_TRACE_INFO,
4022 "Waiting %u msec for hardware to settle",
4023 init_pause_msec);
4024 msleep(init_pause_msec);
4025 }
4026
4027}
4028
4029
4030void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
4031{
4032 char da[1];
4033 unsigned int pipe;
4034 int ret;
4035
4036 if (!hdw->usb_dev) return;
4037
4038 pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
4039
4040 da[0] = val ? 0x01 : 0x00;
4041
4042 /* Write the CPUCS register on the 8051. The lsb of the register
4043 is the reset bit; a 1 asserts reset while a 0 clears it. */
4044 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
4045 ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
4046 if (ret < 0) {
4047 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4048 "cpureset_assert(%d) error=%d",val,ret);
4049 pvr2_hdw_render_useless(hdw);
4050 }
4051}
4052
4053
4054int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
4055{
1c9d10d4 4056 return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
d855497e
MI		 4057}
4058
4059
e1edb19a
MK		 4060int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
4061{
1c9d10d4 4062 return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
e1edb19a
MK		 4063}
4064
1c9d10d4 4065
e1edb19a
MK		 4066int pvr2_hdw_cmd_powerdown(struct pvr2_hdw *hdw)
4067{
1c9d10d4 4068 return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_OFF);
e1edb19a
MK		 4069}
4070
d855497e
MI		 4071
4072int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
4073{
af78e16b
MI		 4074 pvr2_trace(PVR2_TRACE_INIT,
4075 "Requesting decoder reset");
af78e16b
MI		 4076 if (hdw->decoder_client_id) {
4077 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
4078 core, reset, 0);
4079 return 0;
d855497e 4080 }
d855497e 4081 pvr2_trace(PVR2_TRACE_INIT,
af78e16b
MI		 4082 "Unable to reset decoder: nothing attached");
4083 return -ENOTTY;
d855497e
MI		 4084}
4085
4086
62433e31 4087static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
84147f3d 4088{
1c9d10d4
MI		 4089 hdw->flag_ok = !0;
4090 return pvr2_issue_simple_cmd(hdw,
4091 FX2CMD_HCW_DEMOD_RESETIN |
4092 (1 << 8) |
4093 ((onoff ? 1 : 0) << 16));
84147f3d
MI		 4094}
4095
84147f3d 4096
62433e31 4097static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
84147f3d 4098{
1c9d10d4
MI		 4099 hdw->flag_ok = !0;
4100 return pvr2_issue_simple_cmd(hdw,(onoff ?
4101 FX2CMD_ONAIR_DTV_POWER_ON :
4102 FX2CMD_ONAIR_DTV_POWER_OFF));
84147f3d
MI		 4103}
4104
62433e31
MI		 4105
4106static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
4107 int onoff)
84147f3d 4108{
1c9d10d4
MI		 4109 return pvr2_issue_simple_cmd(hdw,(onoff ?
4110 FX2CMD_ONAIR_DTV_STREAMING_ON :
4111 FX2CMD_ONAIR_DTV_STREAMING_OFF));
84147f3d
MI		 4112}
4113
62433e31
MI		 4114
4115static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
4116{
4117 int cmode;
4118 /* Compare digital/analog desired setting with current setting. If
4119 they don't match, fix it... */
4120 cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
4121 if (cmode == hdw->pathway_state) {
4122 /* They match; nothing to do */
4123 return;
4124 }
4125
4126 switch (hdw->hdw_desc->digital_control_scheme) {
4127 case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4128 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
4129 if (cmode == PVR2_PATHWAY_ANALOG) {
4130 /* If moving to analog mode, also force the decoder
4131 to reset. If no decoder is attached, then it's
4132 ok to ignore this because if/when the decoder
4133 attaches, it will reset itself at that time. */
4134 pvr2_hdw_cmd_decoder_reset(hdw);
4135 }
4136 break;
4137 case PVR2_DIGITAL_SCHEME_ONAIR:
4138 /* Supposedly we should always have the power on whether in
4139 digital or analog mode. But for now do what appears to
4140 work... */
bb0c2fe0 4141 pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
62433e31
MI		 4142 break;
4143 default: break;
4144 }
4145
1b9c18c5 4146 pvr2_hdw_untrip_unlocked(hdw);
62433e31
MI		 4147 hdw->pathway_state = cmode;
4148}
4149
4150
e9b59f6e 4151static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
c55a97d7
MI		 4152{
4153 /* change some GPIO data
4154 *
4155 * note: bit d7 of dir appears to control the LED,
4156 * so we shut it off here.
4157 *
c55a97d7 4158 */
40381cb0 4159 if (onoff) {
c55a97d7 4160 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
40381cb0 4161 } else {
c55a97d7 4162 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
40381cb0 4163 }
c55a97d7 4164 pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
40381cb0 4165}
c55a97d7 4166
40381cb0
MI		 4167
4168typedef void (*led_method_func)(struct pvr2_hdw *,int);
4169
4170static led_method_func led_methods[] = {
4171 [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
4172};
4173
4174
4175/* Toggle LED */
4176static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
4177{
4178 unsigned int scheme_id;
4179 led_method_func fp;
4180
4181 if ((!onoff) == (!hdw->led_on)) return;
4182
4183 hdw->led_on = onoff != 0;
4184
4185 scheme_id = hdw->hdw_desc->led_scheme;
4186 if (scheme_id < ARRAY_SIZE(led_methods)) {
4187 fp = led_methods[scheme_id];
4188 } else {
4189 fp = NULL;
4190 }
4191
4192 if (fp) (*fp)(hdw,onoff);
c55a97d7
MI		 4193}
4194
4195
e61b6fc5 4196/* Stop / start video stream transport */
07e337ee 4197static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
d855497e 4198{
bb0c2fe0
MI		 4199 int ret;
4200
4201 /* If we're in analog mode, then just issue the usual analog
4202 command. */
4203 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4204 return pvr2_issue_simple_cmd(hdw,
4205 (runFl ?
4206 FX2CMD_STREAMING_ON :
4207 FX2CMD_STREAMING_OFF));
4208 /*Note: Not reached */
4209 }
4210
4211 if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
4212 /* Whoops, we don't know what mode we're in... */
4213 return -EINVAL;
4214 }
4215
4216 /* To get here we have to be in digital mode. The mechanism here
4217 is unfortunately different for different vendors. So we switch
4218 on the device's digital scheme attribute in order to figure out
4219 what to do. */
4220 switch (hdw->hdw_desc->digital_control_scheme) {
4221 case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4222 return pvr2_issue_simple_cmd(hdw,
4223 (runFl ?
4224 FX2CMD_HCW_DTV_STREAMING_ON :
4225 FX2CMD_HCW_DTV_STREAMING_OFF));
4226 case PVR2_DIGITAL_SCHEME_ONAIR:
4227 ret = pvr2_issue_simple_cmd(hdw,
4228 (runFl ?
4229 FX2CMD_STREAMING_ON :
4230 FX2CMD_STREAMING_OFF));
4231 if (ret) return ret;
4232 return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
4233 default:
4234 return -EINVAL;
62433e31 4235 }
d855497e
MI		 4236}
4237
4238
62433e31
MI		 4239/* Evaluate whether or not state_pathway_ok can change */
4240static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
4241{
4242 if (hdw->state_pathway_ok) {
4243 /* Nothing to do if pathway is already ok */
4244 return 0;
4245 }
4246 if (!hdw->state_pipeline_idle) {
4247 /* Not allowed to change anything if pipeline is not idle */
4248 return 0;
4249 }
4250 pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
4251 hdw->state_pathway_ok = !0;
e9db1ff2 4252 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
62433e31
MI		 4253 return !0;
4254}
4255
4256
681c7399
MI		 4257/* Evaluate whether or not state_encoder_ok can change */
4258static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
4259{
4260 if (hdw->state_encoder_ok) return 0;
4261 if (hdw->flag_tripped) return 0;
4262 if (hdw->state_encoder_run) return 0;
4263 if (hdw->state_encoder_config) return 0;
4264 if (hdw->state_decoder_run) return 0;
4265 if (hdw->state_usbstream_run) return 0;
72998b71
MI		 4266 if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
4267 if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
4268 } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
4269 return 0;
4270 }
4271
681c7399
MI		 4272 if (pvr2_upload_firmware2(hdw) < 0) {
4273 hdw->flag_tripped = !0;
4274 trace_stbit("flag_tripped",hdw->flag_tripped);
4275 return !0;
4276 }
4277 hdw->state_encoder_ok = !0;
4278 trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
4279 return !0;
4280}
4281
4282
4283/* Evaluate whether or not state_encoder_config can change */
4284static int state_eval_encoder_config(struct pvr2_hdw *hdw)
4285{
4286 if (hdw->state_encoder_config) {
4287 if (hdw->state_encoder_ok) {
4288 if (hdw->state_pipeline_req &&
4289 !hdw->state_pipeline_pause) return 0;
4290 }
4291 hdw->state_encoder_config = 0;
4292 hdw->state_encoder_waitok = 0;
4293 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4294 /* paranoia - solve race if timer just completed */
4295 del_timer_sync(&hdw->encoder_wait_timer);
4296 } else {
62433e31
MI		 4297 if (!hdw->state_pathway_ok ||
4298 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4299 !hdw->state_encoder_ok ||
681c7399
MI		 4300 !hdw->state_pipeline_idle ||
4301 hdw->state_pipeline_pause ||
4302 !hdw->state_pipeline_req ||
4303 !hdw->state_pipeline_config) {
4304 /* We must reset the enforced wait interval if
4305 anything has happened that might have disturbed
4306 the encoder. This should be a rare case. */
4307 if (timer_pending(&hdw->encoder_wait_timer)) {
4308 del_timer_sync(&hdw->encoder_wait_timer);
4309 }
4310 if (hdw->state_encoder_waitok) {
4311 /* Must clear the state - therefore we did
4312 something to a state bit and must also
4313 return true. */
4314 hdw->state_encoder_waitok = 0;
4315 trace_stbit("state_encoder_waitok",
4316 hdw->state_encoder_waitok);
4317 return !0;
4318 }
4319 return 0;
4320 }
4321 if (!hdw->state_encoder_waitok) {
4322 if (!timer_pending(&hdw->encoder_wait_timer)) {
4323 /* waitok flag wasn't set and timer isn't
4324 running. Check flag once more to avoid
4325 a race then start the timer. This is
4326 the point when we measure out a minimal
4327 quiet interval before doing something to
4328 the encoder. */
4329 if (!hdw->state_encoder_waitok) {
4330 hdw->encoder_wait_timer.expires =
83ce57aa
MI		 4331 jiffies +
4332 (HZ * TIME_MSEC_ENCODER_WAIT
4333 / 1000);
681c7399
MI		 4334 add_timer(&hdw->encoder_wait_timer);
4335 }
4336 }
4337 /* We can't continue until we know we have been
4338 quiet for the interval measured by this
4339 timer. */
4340 return 0;
4341 }
4342 pvr2_encoder_configure(hdw);
4343 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
4344 }
4345 trace_stbit("state_encoder_config",hdw->state_encoder_config);
4346 return !0;
4347}
4348
4349
d913d630
MI		 4350/* Return true if the encoder should not be running. */
4351static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
4352{
4353 if (!hdw->state_encoder_ok) {
4354 /* Encoder isn't healthy at the moment, so stop it. */
4355 return !0;
4356 }
4357 if (!hdw->state_pathway_ok) {
4358 /* Mode is not understood at the moment (i.e. it wants to
4359 change), so encoder must be stopped. */
4360 return !0;
4361 }
4362
4363 switch (hdw->pathway_state) {
4364 case PVR2_PATHWAY_ANALOG:
4365 if (!hdw->state_decoder_run) {
4366 /* We're in analog mode and the decoder is not
4367 running; thus the encoder should be stopped as
4368 well. */
4369 return !0;
4370 }
4371 break;
4372 case PVR2_PATHWAY_DIGITAL:
4373 if (hdw->state_encoder_runok) {
4374 /* This is a funny case. We're in digital mode so
4375 really the encoder should be stopped. However
4376 if it really is running, only kill it after
4377 runok has been set. This gives a chance for the
4378 onair quirk to function (encoder must run
4379 briefly first, at least once, before onair
4380 digital streaming can work). */
4381 return !0;
4382 }
4383 break;
4384 default:
4385 /* Unknown mode; so encoder should be stopped. */
4386 return !0;
4387 }
4388
4389 /* If we get here, we haven't found a reason to stop the
4390 encoder. */
4391 return 0;
4392}
4393
4394
4395/* Return true if the encoder should be running. */
4396static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
4397{
4398 if (!hdw->state_encoder_ok) {
4399 /* Don't run the encoder if it isn't healthy... */
4400 return 0;
4401 }
4402 if (!hdw->state_pathway_ok) {
4403 /* Don't run the encoder if we don't (yet) know what mode
4404 we need to be in... */
4405 return 0;
4406 }
4407
4408 switch (hdw->pathway_state) {
4409 case PVR2_PATHWAY_ANALOG:
4410 if (hdw->state_decoder_run) {
4411 /* In analog mode, if the decoder is running, then
4412 run the encoder. */
4413 return !0;
4414 }
4415 break;
4416 case PVR2_PATHWAY_DIGITAL:
4417 if ((hdw->hdw_desc->digital_control_scheme ==
4418 PVR2_DIGITAL_SCHEME_ONAIR) &&
4419 !hdw->state_encoder_runok) {
4420 /* This is a quirk. OnAir hardware won't stream
4421 digital until the encoder has been run at least
4422 once, for a minimal period of time (empiricially
4423 measured to be 1/4 second). So if we're on
4424 OnAir hardware and the encoder has never been
4425 run at all, then start the encoder. Normal
4426 state machine logic in the driver will
4427 automatically handle the remaining bits. */
4428 return !0;
4429 }
4430 break;
4431 default:
4432 /* For completeness (unknown mode; encoder won't run ever) */
4433 break;
4434 }
4435 /* If we get here, then we haven't found any reason to run the
4436 encoder, so don't run it. */
4437 return 0;
4438}
4439
4440
681c7399
MI		 4441/* Evaluate whether or not state_encoder_run can change */
4442static int state_eval_encoder_run(struct pvr2_hdw *hdw)
4443{
4444 if (hdw->state_encoder_run) {
d913d630 4445 if (!state_check_disable_encoder_run(hdw)) return 0;
681c7399 4446 if (hdw->state_encoder_ok) {
d913d630 4447 del_timer_sync(&hdw->encoder_run_timer);
681c7399
MI		 4448 if (pvr2_encoder_stop(hdw) < 0) return !0;
4449 }
4450 hdw->state_encoder_run = 0;
4451 } else {
d913d630 4452 if (!state_check_enable_encoder_run(hdw)) return 0;
681c7399
MI		 4453 if (pvr2_encoder_start(hdw) < 0) return !0;
4454 hdw->state_encoder_run = !0;
d913d630
MI		 4455 if (!hdw->state_encoder_runok) {
4456 hdw->encoder_run_timer.expires =
83ce57aa 4457 jiffies + (HZ * TIME_MSEC_ENCODER_OK / 1000);
d913d630
MI		 4458 add_timer(&hdw->encoder_run_timer);
4459 }
681c7399
MI		 4460 }
4461 trace_stbit("state_encoder_run",hdw->state_encoder_run);
4462 return !0;
4463}
4464
4465
4466/* Timeout function for quiescent timer. */
4467static void pvr2_hdw_quiescent_timeout(unsigned long data)
4468{
4469 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4470 hdw->state_decoder_quiescent = !0;
4471 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4472 hdw->state_stale = !0;
4473 queue_work(hdw->workqueue,&hdw->workpoll);
4474}
4475
4476
4477/* Timeout function for encoder wait timer. */
4478static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
4479{
4480 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4481 hdw->state_encoder_waitok = !0;
4482 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4483 hdw->state_stale = !0;
4484 queue_work(hdw->workqueue,&hdw->workpoll);
4485}
4486
4487
d913d630
MI		 4488/* Timeout function for encoder run timer. */
4489static void pvr2_hdw_encoder_run_timeout(unsigned long data)
4490{
4491 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4492 if (!hdw->state_encoder_runok) {
4493 hdw->state_encoder_runok = !0;
4494 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
4495 hdw->state_stale = !0;
4496 queue_work(hdw->workqueue,&hdw->workpoll);
4497 }
4498}
4499
4500
681c7399
MI		 4501/* Evaluate whether or not state_decoder_run can change */
4502static int state_eval_decoder_run(struct pvr2_hdw *hdw)
4503{
4504 if (hdw->state_decoder_run) {
4505 if (hdw->state_encoder_ok) {
4506 if (hdw->state_pipeline_req &&
62433e31
MI		 4507 !hdw->state_pipeline_pause &&
4508 hdw->state_pathway_ok) return 0;
681c7399
MI		 4509 }
4510 if (!hdw->flag_decoder_missed) {
4511 pvr2_decoder_enable(hdw,0);
4512 }
4513 hdw->state_decoder_quiescent = 0;
4514 hdw->state_decoder_run = 0;
4515 /* paranoia - solve race if timer just completed */
4516 del_timer_sync(&hdw->quiescent_timer);
4517 } else {
4518 if (!hdw->state_decoder_quiescent) {
4519 if (!timer_pending(&hdw->quiescent_timer)) {
4520 /* We don't do something about the
4521 quiescent timer until right here because
4522 we also want to catch cases where the
4523 decoder was already not running (like
4524 after initialization) as opposed to
4525 knowing that we had just stopped it.
4526 The second flag check is here to cover a
4527 race - the timer could have run and set
4528 this flag just after the previous check
4529 but before we did the pending check. */
4530 if (!hdw->state_decoder_quiescent) {
4531 hdw->quiescent_timer.expires =
83ce57aa
MI		 4532 jiffies +
4533 (HZ * TIME_MSEC_DECODER_WAIT
4534 / 1000);
681c7399
MI		 4535 add_timer(&hdw->quiescent_timer);
4536 }
4537 }
4538 /* Don't allow decoder to start again until it has
4539 been quiesced first. This little detail should
4540 hopefully further stabilize the encoder. */
4541 return 0;
4542 }
62433e31
MI		 4543 if (!hdw->state_pathway_ok ||
4544 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4545 !hdw->state_pipeline_req ||
681c7399
MI		 4546 hdw->state_pipeline_pause ||
4547 !hdw->state_pipeline_config ||
4548 !hdw->state_encoder_config ||
4549 !hdw->state_encoder_ok) return 0;
4550 del_timer_sync(&hdw->quiescent_timer);
4551 if (hdw->flag_decoder_missed) return 0;
4552 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
4553 hdw->state_decoder_quiescent = 0;
4554 hdw->state_decoder_run = !0;
4555 }
4556 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4557 trace_stbit("state_decoder_run",hdw->state_decoder_run);
4558 return !0;
4559}
4560
4561
4562/* Evaluate whether or not state_usbstream_run can change */
4563static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
4564{
4565 if (hdw->state_usbstream_run) {
72998b71 4566 int fl = !0;
62433e31 4567 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
72998b71
MI		 4568 fl = (hdw->state_encoder_ok &&
4569 hdw->state_encoder_run);
4570 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4571 (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4572 fl = hdw->state_encoder_ok;
4573 }
4574 if (fl &&
4575 hdw->state_pipeline_req &&
4576 !hdw->state_pipeline_pause &&
4577 hdw->state_pathway_ok) {
4578 return 0;
681c7399
MI		 4579 }
4580 pvr2_hdw_cmd_usbstream(hdw,0);
4581 hdw->state_usbstream_run = 0;
4582 } else {
62433e31
MI		 4583 if (!hdw->state_pipeline_req ||
4584 hdw->state_pipeline_pause ||
4585 !hdw->state_pathway_ok) return 0;
4586 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4587 if (!hdw->state_encoder_ok ||
4588 !hdw->state_encoder_run) return 0;
72998b71
MI		 4589 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4590 (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4591 if (!hdw->state_encoder_ok) return 0;
d913d630
MI		 4592 if (hdw->state_encoder_run) return 0;
4593 if (hdw->hdw_desc->digital_control_scheme ==
4594 PVR2_DIGITAL_SCHEME_ONAIR) {
4595 /* OnAir digital receivers won't stream
4596 unless the analog encoder has run first.
4597 Why? I have no idea. But don't even
4598 try until we know the analog side is
4599 known to have run. */
4600 if (!hdw->state_encoder_runok) return 0;
4601 }
62433e31 4602 }
681c7399
MI		 4603 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
4604 hdw->state_usbstream_run = !0;
4605 }
4606 trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
4607 return !0;
4608}
4609
4610
4611/* Attempt to configure pipeline, if needed */
4612static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
4613{
4614 if (hdw->state_pipeline_config ||
4615 hdw->state_pipeline_pause) return 0;
4616 pvr2_hdw_commit_execute(hdw);
4617 return !0;
4618}
4619
4620
4621/* Update pipeline idle and pipeline pause tracking states based on other
4622 inputs. This must be called whenever the other relevant inputs have
4623 changed. */
4624static int state_update_pipeline_state(struct pvr2_hdw *hdw)
4625{
4626 unsigned int st;
4627 int updatedFl = 0;
4628 /* Update pipeline state */
4629 st = !(hdw->state_encoder_run ||
4630 hdw->state_decoder_run ||
4631 hdw->state_usbstream_run ||
4632 (!hdw->state_decoder_quiescent));
4633 if (!st != !hdw->state_pipeline_idle) {
4634 hdw->state_pipeline_idle = st;
4635 updatedFl = !0;
4636 }
4637 if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
4638 hdw->state_pipeline_pause = 0;
4639 updatedFl = !0;
4640 }
4641 return updatedFl;
4642}
4643
4644
4645typedef int (*state_eval_func)(struct pvr2_hdw *);
4646
4647/* Set of functions to be run to evaluate various states in the driver. */
ebff0330 4648static const state_eval_func eval_funcs[] = {
62433e31 4649 state_eval_pathway_ok,
681c7399
MI		 4650 state_eval_pipeline_config,
4651 state_eval_encoder_ok,
4652 state_eval_encoder_config,
4653 state_eval_decoder_run,
4654 state_eval_encoder_run,
4655 state_eval_usbstream_run,
4656};
4657
4658
4659/* Process various states and return true if we did anything interesting. */
4660static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
4661{
4662 unsigned int i;
4663 int state_updated = 0;
4664 int check_flag;
4665
4666 if (!hdw->state_stale) return 0;
4667 if ((hdw->fw1_state != FW1_STATE_OK) ||
4668 !hdw->flag_ok) {
4669 hdw->state_stale = 0;
4670 return !0;
4671 }
4672 /* This loop is the heart of the entire driver. It keeps trying to
4673 evaluate various bits of driver state until nothing changes for
4674 one full iteration. Each "bit of state" tracks some global
4675 aspect of the driver, e.g. whether decoder should run, if
4676 pipeline is configured, usb streaming is on, etc. We separately
4677 evaluate each of those questions based on other driver state to
4678 arrive at the correct running configuration. */
4679 do {
4680 check_flag = 0;
4681 state_update_pipeline_state(hdw);
4682 /* Iterate over each bit of state */
4683 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
4684 if ((*eval_funcs[i])(hdw)) {
4685 check_flag = !0;
4686 state_updated = !0;
4687 state_update_pipeline_state(hdw);
4688 }
4689 }
4690 } while (check_flag && hdw->flag_ok);
4691 hdw->state_stale = 0;
4692 trace_stbit("state_stale",hdw->state_stale);
4693 return state_updated;
4694}
4695
4696
1cb03b76
MI		 4697static unsigned int print_input_mask(unsigned int msk,
4698 char *buf,unsigned int acnt)
4699{
4700 unsigned int idx,ccnt;
4701 unsigned int tcnt = 0;
4702 for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) {
4703 if (!((1 << idx) & msk)) continue;
4704 ccnt = scnprintf(buf+tcnt,
4705 acnt-tcnt,
4706 "%s%s",
4707 (tcnt ? ", " : ""),
4708 control_values_input[idx]);
4709 tcnt += ccnt;
4710 }
4711 return tcnt;
4712}
4713
4714
62433e31
MI		 4715static const char *pvr2_pathway_state_name(int id)
4716{
4717 switch (id) {
4718 case PVR2_PATHWAY_ANALOG: return "analog";
4719 case PVR2_PATHWAY_DIGITAL: return "digital";
4720 default: return "unknown";
4721 }
4722}
4723
4724
681c7399
MI		 4725static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
4726 char *buf,unsigned int acnt)
4727{
4728 switch (which) {
4729 case 0:
4730 return scnprintf(
4731 buf,acnt,
e9db1ff2 4732 "driver:%s%s%s%s%s <mode=%s>",
681c7399
MI		 4733 (hdw->flag_ok ? " <ok>" : " <fail>"),
4734 (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
4735 (hdw->flag_disconnected ? " <disconnected>" :
4736 " <connected>"),
4737 (hdw->flag_tripped ? " <tripped>" : ""),
62433e31
MI		 4738 (hdw->flag_decoder_missed ? " <no decoder>" : ""),
4739 pvr2_pathway_state_name(hdw->pathway_state));
4740
681c7399
MI		 4741 case 1:
4742 return scnprintf(
4743 buf,acnt,
4744 "pipeline:%s%s%s%s",
4745 (hdw->state_pipeline_idle ? " <idle>" : ""),
4746 (hdw->state_pipeline_config ?
4747 " <configok>" : " <stale>"),
4748 (hdw->state_pipeline_req ? " <req>" : ""),
4749 (hdw->state_pipeline_pause ? " <pause>" : ""));
4750 case 2:
4751 return scnprintf(
4752 buf,acnt,
62433e31 4753 "worker:%s%s%s%s%s%s%s",
681c7399
MI		 4754 (hdw->state_decoder_run ?
4755 " <decode:run>" :
4756 (hdw->state_decoder_quiescent ?
4757 "" : " <decode:stop>")),
4758 (hdw->state_decoder_quiescent ?
4759 " <decode:quiescent>" : ""),
4760 (hdw->state_encoder_ok ?
4761 "" : " <encode:init>"),
4762 (hdw->state_encoder_run ?
d913d630
MI		 4763 (hdw->state_encoder_runok ?
4764 " <encode:run>" :
4765 " <encode:firstrun>") :
4766 (hdw->state_encoder_runok ?
4767 " <encode:stop>" :
4768 " <encode:virgin>")),
681c7399
MI		 4769 (hdw->state_encoder_config ?
4770 " <encode:configok>" :
4771 (hdw->state_encoder_waitok ?
b9a37d91 4772 "" : " <encode:waitok>")),
681c7399 4773 (hdw->state_usbstream_run ?
62433e31
MI		 4774 " <usb:run>" : " <usb:stop>"),
4775 (hdw->state_pathway_ok ?
e9db1ff2 4776 " <pathway:ok>" : ""));
681c7399
MI		 4777 case 3:
4778 return scnprintf(
4779 buf,acnt,
4780 "state: %s",
4781 pvr2_get_state_name(hdw->master_state));
ad0992e9 4782 case 4: {
1cb03b76
MI		 4783 unsigned int tcnt = 0;
4784 unsigned int ccnt;
4785
4786 ccnt = scnprintf(buf,
4787 acnt,
4788 "Hardware supported inputs: ");
4789 tcnt += ccnt;
4790 tcnt += print_input_mask(hdw->input_avail_mask,
4791 buf+tcnt,
4792 acnt-tcnt);
4793 if (hdw->input_avail_mask != hdw->input_allowed_mask) {
4794 ccnt = scnprintf(buf+tcnt,
4795 acnt-tcnt,
4796 "; allowed inputs: ");
4797 tcnt += ccnt;
4798 tcnt += print_input_mask(hdw->input_allowed_mask,
4799 buf+tcnt,
4800 acnt-tcnt);
4801 }
4802 return tcnt;
4803 }
4804 case 5: {
ad0992e9
MI		 4805 struct pvr2_stream_stats stats;
4806 if (!hdw->vid_stream) break;
4807 pvr2_stream_get_stats(hdw->vid_stream,
4808 &stats,
4809 0);
4810 return scnprintf(
4811 buf,acnt,
4812 "Bytes streamed=%u"
4813 " URBs: queued=%u idle=%u ready=%u"
4814 " processed=%u failed=%u",
4815 stats.bytes_processed,
4816 stats.buffers_in_queue,
4817 stats.buffers_in_idle,
4818 stats.buffers_in_ready,
4819 stats.buffers_processed,
4820 stats.buffers_failed);
4821 }
27eab384
MI		 4822 case 6: {
4823 unsigned int id = hdw->ir_scheme_active;
4824 return scnprintf(buf, acnt, "ir scheme: id=%d %s", id,
4825 (id >= ARRAY_SIZE(ir_scheme_names) ?
4826 "?" : ir_scheme_names[id]));
4827 }
2eb563b7
MI		 4828 default: break;
4829 }
4830 return 0;
4831}
4832
4833
4834/* Generate report containing info about attached sub-devices and attached
4835 i2c clients, including an indication of which attached i2c clients are
4836 actually sub-devices. */
4837static unsigned int pvr2_hdw_report_clients(struct pvr2_hdw *hdw,
4838 char *buf, unsigned int acnt)
4839{
4840 struct v4l2_subdev *sd;
4841 unsigned int tcnt = 0;
4842 unsigned int ccnt;
4843 struct i2c_client *client;
2eb563b7
MI		 4844 const char *p;
4845 unsigned int id;
4846
fa7ce764 4847 ccnt = scnprintf(buf, acnt, "Associated v4l2-subdev drivers and I2C clients:\n");
2eb563b7
MI		 4848 tcnt += ccnt;
4849 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
4850 id = sd->grp_id;
4851 p = NULL;
4852 if (id < ARRAY_SIZE(module_names)) p = module_names[id];
4853 if (p) {
fa7ce764 4854 ccnt = scnprintf(buf + tcnt, acnt - tcnt, " %s:", p);
2eb563b7
MI		 4855 tcnt += ccnt;
4856 } else {
4857 ccnt = scnprintf(buf + tcnt, acnt - tcnt,
fa7ce764 4858 " (unknown id=%u):", id);
2eb563b7
MI		 4859 tcnt += ccnt;
4860 }
fa7ce764
JD		 4861 client = v4l2_get_subdevdata(sd);
4862 if (client) {
4863 ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4864 " %s @ %02x\n", client->name,
4865 client->addr);
4866 tcnt += ccnt;
4867 } else {
4868 ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4869 " no i2c client\n");
4870 tcnt += ccnt;
858f910e 4871 }
681c7399 4872 }
2eb563b7 4873 return tcnt;
681c7399
MI		 4874}
4875
4876
4877unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
4878 char *buf,unsigned int acnt)
4879{
4880 unsigned int bcnt,ccnt,idx;
4881 bcnt = 0;
4882 LOCK_TAKE(hdw->big_lock);
4883 for (idx = 0; ; idx++) {
4884 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
4885 if (!ccnt) break;
4886 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4887 if (!acnt) break;
4888 buf[0] = '\n'; ccnt = 1;
4889 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4890 }
2eb563b7
MI		 4891 ccnt = pvr2_hdw_report_clients(hdw, buf, acnt);
4892 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
681c7399
MI		 4893 LOCK_GIVE(hdw->big_lock);
4894 return bcnt;
4895}
4896
4897
4898static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
4899{
2eb563b7
MI		 4900 char buf[256];
4901 unsigned int idx, ccnt;
4902 unsigned int lcnt, ucnt;
681c7399
MI		 4903
4904 for (idx = 0; ; idx++) {
4905 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
4906 if (!ccnt) break;
4907 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
4908 }
2eb563b7
MI		 4909 ccnt = pvr2_hdw_report_clients(hdw, buf, sizeof(buf));
4910 ucnt = 0;
4911 while (ucnt < ccnt) {
4912 lcnt = 0;
4913 while ((lcnt + ucnt < ccnt) && (buf[lcnt + ucnt] != '\n')) {
4914 lcnt++;
4915 }
4916 printk(KERN_INFO "%s %.*s\n", hdw->name, lcnt, buf + ucnt);
4917 ucnt += lcnt + 1;
4918 }
681c7399
MI		 4919}
4920
4921
4922/* Evaluate and update the driver's current state, taking various actions
4923 as appropriate for the update. */
4924static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
4925{
4926 unsigned int st;
4927 int state_updated = 0;
4928 int callback_flag = 0;
1b9c18c5 4929 int analog_mode;
681c7399
MI		 4930
4931 pvr2_trace(PVR2_TRACE_STBITS,
4932 "Drive state check START");
4933 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4934 pvr2_hdw_state_log_state(hdw);
4935 }
4936
4937 /* Process all state and get back over disposition */
4938 state_updated = pvr2_hdw_state_update(hdw);
4939
1b9c18c5
MI		 4940 analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
4941
681c7399
MI		 4942 /* Update master state based upon all other states. */
4943 if (!hdw->flag_ok) {
4944 st = PVR2_STATE_DEAD;
4945 } else if (hdw->fw1_state != FW1_STATE_OK) {
4946 st = PVR2_STATE_COLD;
72998b71
MI		 4947 } else if ((analog_mode ||
4948 hdw->hdw_desc->flag_digital_requires_cx23416) &&
4949 !hdw->state_encoder_ok) {
681c7399 4950 st = PVR2_STATE_WARM;
1b9c18c5
MI		 4951 } else if (hdw->flag_tripped ||
4952 (analog_mode && hdw->flag_decoder_missed)) {
681c7399 4953 st = PVR2_STATE_ERROR;
62433e31 4954 } else if (hdw->state_usbstream_run &&
1b9c18c5 4955 (!analog_mode ||
62433e31 4956 (hdw->state_encoder_run && hdw->state_decoder_run))) {
681c7399
MI		 4957 st = PVR2_STATE_RUN;
4958 } else {
4959 st = PVR2_STATE_READY;
4960 }
4961 if (hdw->master_state != st) {
4962 pvr2_trace(PVR2_TRACE_STATE,
4963 "Device state change from %s to %s",
4964 pvr2_get_state_name(hdw->master_state),
4965 pvr2_get_state_name(st));
40381cb0 4966 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
681c7399
MI		 4967 hdw->master_state = st;
4968 state_updated = !0;
4969 callback_flag = !0;
4970 }
4971 if (state_updated) {
4972 /* Trigger anyone waiting on any state changes here. */
4973 wake_up(&hdw->state_wait_data);
4974 }
4975
4976 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4977 pvr2_hdw_state_log_state(hdw);
4978 }
4979 pvr2_trace(PVR2_TRACE_STBITS,
4980 "Drive state check DONE callback=%d",callback_flag);
4981
4982 return callback_flag;
4983}
4984
4985
4986/* Cause kernel thread to check / update driver state */
4987static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
4988{
4989 if (hdw->state_stale) return;
4990 hdw->state_stale = !0;
4991 trace_stbit("state_stale",hdw->state_stale);
4992 queue_work(hdw->workqueue,&hdw->workpoll);
4993}
4994
4995
d855497e
MI		 4996int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
4997{
4998 return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
4999}
5000
5001
5002int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
5003{
5004 return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
5005}
5006
5007
5008int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
5009{
5010 return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
5011}
5012
5013
5014int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
5015{
5016 u32 cval,nval;
5017 int ret;
5018 if (~msk) {
5019 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
5020 if (ret) return ret;
5021 nval = (cval & ~msk) | (val & msk);
5022 pvr2_trace(PVR2_TRACE_GPIO,
5023 "GPIO direction changing 0x%x:0x%x"
5024 " from 0x%x to 0x%x",
5025 msk,val,cval,nval);
5026 } else {
5027 nval = val;
5028 pvr2_trace(PVR2_TRACE_GPIO,
5029 "GPIO direction changing to 0x%x",nval);
5030 }
5031 return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
5032}
5033
5034
5035int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
5036{
5037 u32 cval,nval;
5038 int ret;
5039 if (~msk) {
5040 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
5041 if (ret) return ret;
5042 nval = (cval & ~msk) | (val & msk);
5043 pvr2_trace(PVR2_TRACE_GPIO,
5044 "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
5045 msk,val,cval,nval);
5046 } else {
5047 nval = val;
5048 pvr2_trace(PVR2_TRACE_GPIO,
5049 "GPIO output changing to 0x%x",nval);
5050 }
5051 return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
5052}
5053
5054
a51f5000
MI		 5055void pvr2_hdw_status_poll(struct pvr2_hdw *hdw)
5056{
40f07111
MI		 5057 struct v4l2_tuner *vtp = &hdw->tuner_signal_info;
5058 memset(vtp, 0, sizeof(*vtp));
2641df36 5059 hdw->tuner_signal_stale = 0;
40f07111
MI		 5060 /* Note: There apparently is no replacement for VIDIOC_CROPCAP
5061 using v4l2-subdev - therefore we can't support that AT ALL right
5062 now. (Of course, no sub-drivers seem to implement it either.
5063 But now it's a a chicken and egg problem...) */
5064 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, g_tuner,
5065 &hdw->tuner_signal_info);
2641df36 5066 pvr2_trace(PVR2_TRACE_CHIPS, "subdev status poll"
40f07111
MI		 5067 " type=%u strength=%u audio=0x%x cap=0x%x"
5068 " low=%u hi=%u",
5069 vtp->type,
5070 vtp->signal, vtp->rxsubchans, vtp->capability,
5071 vtp->rangelow, vtp->rangehigh);
2641df36
MI		 5072
5073 /* We have to do this to avoid getting into constant polling if
5074 there's nobody to answer a poll of cropcap info. */
5075 hdw->cropcap_stale = 0;
a51f5000
MI		 5076}
5077
5078
7fb20fa3
MI		 5079unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
5080{
5081 return hdw->input_avail_mask;
5082}
5083
5084
1cb03b76
MI		 5085unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
5086{
5087 return hdw->input_allowed_mask;
5088}
5089
5090
5091static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
5092{
5093 if (hdw->input_val != v) {
5094 hdw->input_val = v;
5095 hdw->input_dirty = !0;
5096 }
5097
5098 /* Handle side effects - if we switch to a mode that needs the RF
5099 tuner, then select the right frequency choice as well and mark
5100 it dirty. */
5101 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
5102 hdw->freqSelector = 0;
5103 hdw->freqDirty = !0;
5104 } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
5105 (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
5106 hdw->freqSelector = 1;
5107 hdw->freqDirty = !0;
5108 }
5109 return 0;
5110}
5111
5112
5113int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
5114 unsigned int change_mask,
5115 unsigned int change_val)
5116{
5117 int ret = 0;
5118 unsigned int nv,m,idx;
5119 LOCK_TAKE(hdw->big_lock);
5120 do {
5121 nv = hdw->input_allowed_mask & ~change_mask;
5122 nv |= (change_val & change_mask);
5123 nv &= hdw->input_avail_mask;
5124 if (!nv) {
5125 /* No legal modes left; return error instead. */
5126 ret = -EPERM;
5127 break;
5128 }
5129 hdw->input_allowed_mask = nv;
5130 if ((1 << hdw->input_val) & hdw->input_allowed_mask) {
5131 /* Current mode is still in the allowed mask, so
5132 we're done. */
5133 break;
5134 }
5135 /* Select and switch to a mode that is still in the allowed
5136 mask */
5137 if (!hdw->input_allowed_mask) {
5138 /* Nothing legal; give up */
5139 break;
5140 }
5141 m = hdw->input_allowed_mask;
5142 for (idx = 0; idx < (sizeof(m) << 3); idx++) {
5143 if (!((1 << idx) & m)) continue;
5144 pvr2_hdw_set_input(hdw,idx);
5145 break;
5146 }
5147 } while (0);
5148 LOCK_GIVE(hdw->big_lock);
5149 return ret;
5150}
5151
5152
e61b6fc5 5153/* Find I2C address of eeprom */
07e337ee 5154static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
d855497e
MI		 5155{
5156 int result;
5157 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 5158 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
d855497e
MI		 5159 result = pvr2_send_request(hdw,
5160 hdw->cmd_buffer,1,
5161 hdw->cmd_buffer,1);
5162 if (result < 0) break;
5163 result = hdw->cmd_buffer[0];
5164 } while(0); LOCK_GIVE(hdw->ctl_lock);
5165 return result;
5166}
5167
5168
32ffa9ae 5169int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
aecde8b5
HV		 5170 struct v4l2_dbg_match *match, u64 reg_id,
5171 int setFl, u64 *val_ptr)
32ffa9ae
MI		 5172{
5173#ifdef CONFIG_VIDEO_ADV_DEBUG
aecde8b5 5174 struct v4l2_dbg_register req;
6d98816f
MI		 5175 int stat = 0;
5176 int okFl = 0;
32ffa9ae 5177
201f5c9c
MI		 5178 if (!capable(CAP_SYS_ADMIN)) return -EPERM;
5179
aecde8b5 5180 req.match = *match;
32ffa9ae
MI		 5181 req.reg = reg_id;
5182 if (setFl) req.val = *val_ptr;
d8f5b9ba
MI		 5183 /* It would be nice to know if a sub-device answered the request */
5184 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, g_register, &req);
5185 if (!setFl) *val_ptr = req.val;
6d98816f
MI		 5186 if (okFl) {
5187 return stat;
5188 }
32ffa9ae
MI		 5189 return -EINVAL;
5190#else
5191 return -ENOSYS;
5192#endif
5193}
5194
5195
d855497e
MI		 5196/*
5197 Stuff for Emacs to see, in order to encourage consistent editing style:
5198 *** Local Variables: ***
5199 *** mode: c ***
5200 *** fill-column: 75 ***
5201 *** tab-width: 8 ***
5202 *** c-basic-offset: 8 ***
5203 *** End: ***
5204 */
kernel source for telekom puls (alcatel/mediatek)