[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / media / video / omap3isp / isp.h

/*
 * isp.h
 *
 * TI OMAP3 ISP - Core
 *
 * Copyright (C) 2009-2010 Nokia Corporation
 * Copyright (C) 2009 Texas Instruments, Inc.
 *
 * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
 *	     Sakari Ailus <sakari.ailus@iki.fi>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 */

#ifndef OMAP3_ISP_CORE_H
#define OMAP3_ISP_CORE_H

#include <media/omap3isp.h>
#include <media/v4l2-device.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/wait.h>
#include <linux/iommu.h>
#include <plat/iommu.h>
#include <plat/iovmm.h>

#include "ispstat.h"
#include "ispccdc.h"
#include "ispreg.h"
#include "ispresizer.h"
#include "isppreview.h"
#include "ispcsiphy.h"
#include "ispcsi2.h"
#include "ispccp2.h"

#define IOMMU_FLAG (IOVMF_ENDIAN_LITTLE | IOVMF_ELSZ_8)

#define ISP_TOK_TERM		0xFFFFFFFF	/*
						 * terminating token for ISP
						 * modules reg list
						 */
#define to_isp_device(ptr_module)				\
	container_of(ptr_module, struct isp_device, isp_##ptr_module)
#define to_device(ptr_module)						\
	(to_isp_device(ptr_module)->dev)

enum isp_mem_resources {
	OMAP3_ISP_IOMEM_MAIN,
	OMAP3_ISP_IOMEM_CCP2,
	OMAP3_ISP_IOMEM_CCDC,
	OMAP3_ISP_IOMEM_HIST,
	OMAP3_ISP_IOMEM_H3A,
	OMAP3_ISP_IOMEM_PREV,
	OMAP3_ISP_IOMEM_RESZ,
	OMAP3_ISP_IOMEM_SBL,
	OMAP3_ISP_IOMEM_CSI2A_REGS1,
	OMAP3_ISP_IOMEM_CSIPHY2,
	OMAP3_ISP_IOMEM_CSI2A_REGS2,
	OMAP3_ISP_IOMEM_CSI2C_REGS1,
	OMAP3_ISP_IOMEM_CSIPHY1,
	OMAP3_ISP_IOMEM_CSI2C_REGS2,
	OMAP3_ISP_IOMEM_LAST
};

enum isp_sbl_resource {
	OMAP3_ISP_SBL_CSI1_READ		= 0x1,
	OMAP3_ISP_SBL_CSI1_WRITE	= 0x2,
	OMAP3_ISP_SBL_CSI2A_WRITE	= 0x4,
	OMAP3_ISP_SBL_CSI2C_WRITE	= 0x8,
	OMAP3_ISP_SBL_CCDC_LSC_READ	= 0x10,
	OMAP3_ISP_SBL_CCDC_WRITE	= 0x20,
	OMAP3_ISP_SBL_PREVIEW_READ	= 0x40,
	OMAP3_ISP_SBL_PREVIEW_WRITE	= 0x80,
	OMAP3_ISP_SBL_RESIZER_READ	= 0x100,
	OMAP3_ISP_SBL_RESIZER_WRITE	= 0x200,
};

enum isp_subclk_resource {
	OMAP3_ISP_SUBCLK_CCDC		= (1 << 0),
	OMAP3_ISP_SUBCLK_H3A		= (1 << 1),
	OMAP3_ISP_SUBCLK_HIST		= (1 << 2),
	OMAP3_ISP_SUBCLK_PREVIEW	= (1 << 3),
	OMAP3_ISP_SUBCLK_RESIZER	= (1 << 4),
};

/* ISP: OMAP 34xx ES 1.0 */
#define ISP_REVISION_1_0		0x10
/* ISP2: OMAP 34xx ES 2.0, 2.1 and 3.0 */
#define ISP_REVISION_2_0		0x20
/* ISP2P: OMAP 36xx */
#define ISP_REVISION_15_0		0xF0

/*
 * struct isp_res_mapping - Map ISP io resources to ISP revision.
 * @isp_rev: ISP_REVISION_x_x
 * @map: bitmap for enum isp_mem_resources
 */
struct isp_res_mapping {
	u32 isp_rev;
	u32 map;
};

/*
 * struct isp_reg - Structure for ISP register values.
 * @reg: 32-bit Register address.
 * @val: 32-bit Register value.
 */
struct isp_reg {
	enum isp_mem_resources mmio_range;
	u32 reg;
	u32 val;
};

struct isp_platform_callback {
	u32 (*set_xclk)(struct isp_device *isp, u32 xclk, u8 xclksel);
	int (*csiphy_config)(struct isp_csiphy *phy,
			     struct isp_csiphy_dphy_cfg *dphy,
			     struct isp_csiphy_lanes_cfg *lanes);
	void (*set_pixel_clock)(struct isp_device *isp, unsigned int pixelclk);
};

/*
 * struct isp_device - ISP device structure.
 * @dev: Device pointer specific to the OMAP3 ISP.
 * @revision: Stores current ISP module revision.
 * @irq_num: Currently used IRQ number.
 * @mmio_base: Array with kernel base addresses for ioremapped ISP register
 *             regions.
 * @mmio_base_phys: Array with physical L4 bus addresses for ISP register
 *                  regions.
 * @mmio_size: Array with ISP register regions size in bytes.
 * @raw_dmamask: Raw DMA mask
 * @stat_lock: Spinlock for handling statistics
 * @isp_mutex: Mutex for serializing requests to ISP.
 * @crashed: Bitmask of crashed entities (indexed by entity ID)
 * @has_context: Context has been saved at least once and can be restored.
 * @ref_count: Reference count for handling multiple ISP requests.
 * @cam_ick: Pointer to camera interface clock structure.
 * @cam_mclk: Pointer to camera functional clock structure.
 * @dpll4_m5_ck: Pointer to DPLL4 M5 clock structure.
 * @csi2_fck: Pointer to camera CSI2 complexIO clock structure.
 * @l3_ick: Pointer to OMAP3 L3 bus interface clock.
 * @irq: Currently attached ISP ISR callbacks information structure.
 * @isp_af: Pointer to current settings for ISP AutoFocus SCM.
 * @isp_hist: Pointer to current settings for ISP Histogram SCM.
 * @isp_h3a: Pointer to current settings for ISP Auto Exposure and
 *           White Balance SCM.
 * @isp_res: Pointer to current settings for ISP Resizer.
 * @isp_prev: Pointer to current settings for ISP Preview.
 * @isp_ccdc: Pointer to current settings for ISP CCDC.
 * @iommu: Pointer to requested IOMMU instance for ISP.
 * @platform_cb: ISP driver callback function pointers for platform code
 *
 * This structure is used to store the OMAP ISP Information.
 */
struct isp_device {
	struct v4l2_device v4l2_dev;
	struct media_device media_dev;
	struct device *dev;
	u32 revision;

	/* platform HW resources */
	struct isp_platform_data *pdata;
	unsigned int irq_num;

	void __iomem *mmio_base[OMAP3_ISP_IOMEM_LAST];
	unsigned long mmio_base_phys[OMAP3_ISP_IOMEM_LAST];
	resource_size_t mmio_size[OMAP3_ISP_IOMEM_LAST];

	u64 raw_dmamask;

	/* ISP Obj */
	spinlock_t stat_lock;	/* common lock for statistic drivers */
	struct mutex isp_mutex;	/* For handling ref_count field */
	u32 crashed;
	int has_context;
	int ref_count;
	unsigned int autoidle;
	u32 xclk_divisor[2];	/* Two clocks, a and b. */
#define ISP_CLK_CAM_ICK		0
#define ISP_CLK_CAM_MCLK	1
#define ISP_CLK_DPLL4_M5_CK	2
#define ISP_CLK_CSI2_FCK	3
#define ISP_CLK_L3_ICK		4
	struct clk *clock[5];

	/* ISP modules */
	struct ispstat isp_af;
	struct ispstat isp_aewb;
	struct ispstat isp_hist;
	struct isp_res_device isp_res;
	struct isp_prev_device isp_prev;
	struct isp_ccdc_device isp_ccdc;
	struct isp_csi2_device isp_csi2a;
	struct isp_csi2_device isp_csi2c;
	struct isp_ccp2_device isp_ccp2;
	struct isp_csiphy isp_csiphy1;
	struct isp_csiphy isp_csiphy2;

	unsigned int sbl_resources;
	unsigned int subclk_resources;

	struct iommu_domain *domain;

	struct isp_platform_callback platform_cb;
};

#define v4l2_dev_to_isp_device(dev) \
	container_of(dev, struct isp_device, v4l2_dev)

void omap3isp_hist_dma_done(struct isp_device *isp);

void omap3isp_flush(struct isp_device *isp);

int omap3isp_module_sync_idle(struct media_entity *me, wait_queue_head_t *wait,
			      atomic_t *stopping);

int omap3isp_module_sync_is_stopping(wait_queue_head_t *wait,
				     atomic_t *stopping);

int omap3isp_pipeline_set_stream(struct isp_pipeline *pipe,
				 enum isp_pipeline_stream_state state);
void omap3isp_configure_bridge(struct isp_device *isp,
			       enum ccdc_input_entity input,
			       const struct isp_parallel_platform_data *pdata,
			       unsigned int shift);

#define ISP_XCLK_NONE			0
#define ISP_XCLK_A			1
#define ISP_XCLK_B			2

struct isp_device *omap3isp_get(struct isp_device *isp);
void omap3isp_put(struct isp_device *isp);

void omap3isp_print_status(struct isp_device *isp);

void omap3isp_sbl_enable(struct isp_device *isp, enum isp_sbl_resource res);
void omap3isp_sbl_disable(struct isp_device *isp, enum isp_sbl_resource res);

void omap3isp_subclk_enable(struct isp_device *isp,
			    enum isp_subclk_resource res);
void omap3isp_subclk_disable(struct isp_device *isp,
			     enum isp_subclk_resource res);

int omap3isp_pipeline_pm_use(struct media_entity *entity, int use);

int omap3isp_register_entities(struct platform_device *pdev,
			       struct v4l2_device *v4l2_dev);
void omap3isp_unregister_entities(struct platform_device *pdev);

/*
 * isp_reg_readl - Read value of an OMAP3 ISP register
 * @dev: Device pointer specific to the OMAP3 ISP.
 * @isp_mmio_range: Range to which the register offset refers to.
 * @reg_offset: Register offset to read from.
 *
 * Returns an unsigned 32 bit value with the required register contents.
 */
static inline
u32 isp_reg_readl(struct isp_device *isp, enum isp_mem_resources isp_mmio_range,
		  u32 reg_offset)
{
	return __raw_readl(isp->mmio_base[isp_mmio_range] + reg_offset);
}

/*
 * isp_reg_writel - Write value to an OMAP3 ISP register
 * @dev: Device pointer specific to the OMAP3 ISP.
 * @reg_value: 32 bit value to write to the register.
 * @isp_mmio_range: Range to which the register offset refers to.
 * @reg_offset: Register offset to write into.
 */
static inline
void isp_reg_writel(struct isp_device *isp, u32 reg_value,
		    enum isp_mem_resources isp_mmio_range, u32 reg_offset)
{
	__raw_writel(reg_value, isp->mmio_base[isp_mmio_range] + reg_offset);
}

/*
 * isp_reg_and - Clear individual bits in an OMAP3 ISP register
 * @dev: Device pointer specific to the OMAP3 ISP.
 * @mmio_range: Range to which the register offset refers to.
 * @reg: Register offset to work on.
 * @clr_bits: 32 bit value which would be cleared in the register.
 */
static inline
void isp_reg_clr(struct isp_device *isp, enum isp_mem_resources mmio_range,
		 u32 reg, u32 clr_bits)
{
	u32 v = isp_reg_readl(isp, mmio_range, reg);

	isp_reg_writel(isp, v & ~clr_bits, mmio_range, reg);
}

/*
 * isp_reg_set - Set individual bits in an OMAP3 ISP register
 * @dev: Device pointer specific to the OMAP3 ISP.
 * @mmio_range: Range to which the register offset refers to.
 * @reg: Register offset to work on.
 * @set_bits: 32 bit value which would be set in the register.
 */
static inline
void isp_reg_set(struct isp_device *isp, enum isp_mem_resources mmio_range,
		 u32 reg, u32 set_bits)
{
	u32 v = isp_reg_readl(isp, mmio_range, reg);

	isp_reg_writel(isp, v | set_bits, mmio_range, reg);
}

/*
 * isp_reg_clr_set - Clear and set invidial bits in an OMAP3 ISP register
 * @dev: Device pointer specific to the OMAP3 ISP.
 * @mmio_range: Range to which the register offset refers to.
 * @reg: Register offset to work on.
 * @clr_bits: 32 bit value which would be cleared in the register.
 * @set_bits: 32 bit value which would be set in the register.
 *
 * The clear operation is done first, and then the set operation.
 */
static inline
void isp_reg_clr_set(struct isp_device *isp, enum isp_mem_resources mmio_range,
		     u32 reg, u32 clr_bits, u32 set_bits)
{
	u32 v = isp_reg_readl(isp, mmio_range, reg);

	isp_reg_writel(isp, (v & ~clr_bits) | set_bits, mmio_range, reg);
}

static inline enum v4l2_buf_type
isp_pad_buffer_type(const struct v4l2_subdev *subdev, int pad)
{
	if (pad >= subdev->entity.num_pads)
		return 0;

	if (subdev->entity.pads[pad].flags & MEDIA_PAD_FL_SINK)
		return V4L2_BUF_TYPE_VIDEO_OUTPUT;
	else
		return V4L2_BUF_TYPE_VIDEO_CAPTURE;
}

#endif	/* OMAP3_ISP_CORE_H */
Commit	Line	Data
448de7e7 SA	1	/*
	2	* isp.h
	3	*
	4	* TI OMAP3 ISP - Core
	5	*
	6	* Copyright (C) 2009-2010 Nokia Corporation
	7	* Copyright (C) 2009 Texas Instruments, Inc.
	8	*
	9	* Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
	10	* Sakari Ailus <sakari.ailus@iki.fi>
	11	*
	12	* This program is free software; you can redistribute it and/or modify
	13	* it under the terms of the GNU General Public License version 2 as
	14	* published by the Free Software Foundation.
	15	*
	16	* This program is distributed in the hope that it will be useful, but
	17	* WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	19	* General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	24	* 02110-1301 USA
	25	*/
	26
	27	#ifndef OMAP3_ISP_CORE_H
	28	#define OMAP3_ISP_CORE_H
	29
b98d32f7	30	#include <media/omap3isp.h>
448de7e7 SA	31	#include <media/v4l2-device.h>
	32	#include <linux/device.h>
	33	#include <linux/io.h>
	34	#include <linux/platform_device.h>
	35	#include <linux/wait.h>
f626b52d	36	#include <linux/iommu.h>
448de7e7 SA	37	#include <plat/iommu.h>
	38	#include <plat/iovmm.h>
	39
	40	#include "ispstat.h"
	41	#include "ispccdc.h"
	42	#include "ispreg.h"
	43	#include "ispresizer.h"
	44	#include "isppreview.h"
	45	#include "ispcsiphy.h"
	46	#include "ispcsi2.h"
	47	#include "ispccp2.h"
	48
	49	#define IOMMU_FLAG (IOVMF_ENDIAN_LITTLE \| IOVMF_ELSZ_8)
	50
	51	#define ISP_TOK_TERM 0xFFFFFFFF /*
	52	* terminating token for ISP
	53	* modules reg list
	54	*/
	55	#define to_isp_device(ptr_module) \
	56	container_of(ptr_module, struct isp_device, isp_##ptr_module)
	57	#define to_device(ptr_module) \
	58	(to_isp_device(ptr_module)->dev)
	59
	60	enum isp_mem_resources {
	61	OMAP3_ISP_IOMEM_MAIN,
	62	OMAP3_ISP_IOMEM_CCP2,
	63	OMAP3_ISP_IOMEM_CCDC,
	64	OMAP3_ISP_IOMEM_HIST,
	65	OMAP3_ISP_IOMEM_H3A,
	66	OMAP3_ISP_IOMEM_PREV,
	67	OMAP3_ISP_IOMEM_RESZ,
	68	OMAP3_ISP_IOMEM_SBL,
	69	OMAP3_ISP_IOMEM_CSI2A_REGS1,
	70	OMAP3_ISP_IOMEM_CSIPHY2,
	71	OMAP3_ISP_IOMEM_CSI2A_REGS2,
	72	OMAP3_ISP_IOMEM_CSI2C_REGS1,
	73	OMAP3_ISP_IOMEM_CSIPHY1,
	74	OMAP3_ISP_IOMEM_CSI2C_REGS2,
	75	OMAP3_ISP_IOMEM_LAST
	76	};
	77
	78	enum isp_sbl_resource {
	79	OMAP3_ISP_SBL_CSI1_READ = 0x1,
	80	OMAP3_ISP_SBL_CSI1_WRITE = 0x2,
	81	OMAP3_ISP_SBL_CSI2A_WRITE = 0x4,
	82	OMAP3_ISP_SBL_CSI2C_WRITE = 0x8,
	83	OMAP3_ISP_SBL_CCDC_LSC_READ = 0x10,
	84	OMAP3_ISP_SBL_CCDC_WRITE = 0x20,
	85	OMAP3_ISP_SBL_PREVIEW_READ = 0x40,
	86	OMAP3_ISP_SBL_PREVIEW_WRITE = 0x80,
	87	OMAP3_ISP_SBL_RESIZER_READ = 0x100,
	88	OMAP3_ISP_SBL_RESIZER_WRITE = 0x200,
	89	};
	90
	91	enum isp_subclk_resource {
	92	OMAP3_ISP_SUBCLK_CCDC = (1 << 0),
	93	OMAP3_ISP_SUBCLK_H3A = (1 << 1),
	94	OMAP3_ISP_SUBCLK_HIST = (1 << 2),
	95	OMAP3_ISP_SUBCLK_PREVIEW = (1 << 3),
	96	OMAP3_ISP_SUBCLK_RESIZER = (1 << 4),
	97	};
	98
448de7e7 SA	99	/* ISP: OMAP 34xx ES 1.0 */
	100	#define ISP_REVISION_1_0 0x10
	101	/* ISP2: OMAP 34xx ES 2.0, 2.1 and 3.0 */
	102	#define ISP_REVISION_2_0 0x20
	103	/* ISP2P: OMAP 36xx */
	104	#define ISP_REVISION_15_0 0xF0
	105
	106	/*
	107	* struct isp_res_mapping - Map ISP io resources to ISP revision.
	108	* @isp_rev: ISP_REVISION_x_x
	109	* @map: bitmap for enum isp_mem_resources
	110	*/
	111	struct isp_res_mapping {
	112	u32 isp_rev;
	113	u32 map;
	114	};
	115
	116	/*
	117	* struct isp_reg - Structure for ISP register values.
	118	* @reg: 32-bit Register address.
	119	* @val: 32-bit Register value.
	120	*/
	121	struct isp_reg {
	122	enum isp_mem_resources mmio_range;
	123	u32 reg;
	124	u32 val;
	125	};
	126
448de7e7 SA	127	struct isp_platform_callback {
	128	u32 (set_xclk)(struct isp_device isp, u32 xclk, u8 xclksel);
	129	int (csiphy_config)(struct isp_csiphy phy,
	130	struct isp_csiphy_dphy_cfg *dphy,
	131	struct isp_csiphy_lanes_cfg *lanes);
	132	void (set_pixel_clock)(struct isp_device isp, unsigned int pixelclk);
	133	};
	134
	135	/*
	136	* struct isp_device - ISP device structure.
	137	* @dev: Device pointer specific to the OMAP3 ISP.
	138	* @revision: Stores current ISP module revision.
	139	* @irq_num: Currently used IRQ number.
	140	* @mmio_base: Array with kernel base addresses for ioremapped ISP register
	141	* regions.
	142	* @mmio_base_phys: Array with physical L4 bus addresses for ISP register
	143	* regions.
	144	* @mmio_size: Array with ISP register regions size in bytes.
	145	* @raw_dmamask: Raw DMA mask
	146	* @stat_lock: Spinlock for handling statistics
	147	* @isp_mutex: Mutex for serializing requests to ISP.
1567bb7d	148	* @crashed: Bitmask of crashed entities (indexed by entity ID)
448de7e7 SA	149	* @has_context: Context has been saved at least once and can be restored.
	150	* @ref_count: Reference count for handling multiple ISP requests.
	151	* @cam_ick: Pointer to camera interface clock structure.
	152	* @cam_mclk: Pointer to camera functional clock structure.
	153	* @dpll4_m5_ck: Pointer to DPLL4 M5 clock structure.
	154	* @csi2_fck: Pointer to camera CSI2 complexIO clock structure.
	155	* @l3_ick: Pointer to OMAP3 L3 bus interface clock.
	156	* @irq: Currently attached ISP ISR callbacks information structure.
	157	* @isp_af: Pointer to current settings for ISP AutoFocus SCM.
	158	* @isp_hist: Pointer to current settings for ISP Histogram SCM.
	159	* @isp_h3a: Pointer to current settings for ISP Auto Exposure and
	160	* White Balance SCM.
	161	* @isp_res: Pointer to current settings for ISP Resizer.
	162	* @isp_prev: Pointer to current settings for ISP Preview.
	163	* @isp_ccdc: Pointer to current settings for ISP CCDC.
	164	* @iommu: Pointer to requested IOMMU instance for ISP.
	165	* @platform_cb: ISP driver callback function pointers for platform code
	166	*
	167	* This structure is used to store the OMAP ISP Information.
	168	*/
	169	struct isp_device {
	170	struct v4l2_device v4l2_dev;
	171	struct media_device media_dev;
	172	struct device *dev;
	173	u32 revision;
	174
	175	/* platform HW resources */
	176	struct isp_platform_data *pdata;
	177	unsigned int irq_num;
	178
	179	void __iomem *mmio_base[OMAP3_ISP_IOMEM_LAST];
	180	unsigned long mmio_base_phys[OMAP3_ISP_IOMEM_LAST];
	181	resource_size_t mmio_size[OMAP3_ISP_IOMEM_LAST];
	182
	183	u64 raw_dmamask;
	184
	185	/* ISP Obj */
	186	spinlock_t stat_lock; /* common lock for statistic drivers */
	187	struct mutex isp_mutex; /* For handling ref_count field */
1567bb7d	188	u32 crashed;
448de7e7 SA	189	int has_context;
	190	int ref_count;
	191	unsigned int autoidle;
	192	u32 xclk_divisor[2]; /* Two clocks, a and b. */
	193	#define ISP_CLK_CAM_ICK 0
	194	#define ISP_CLK_CAM_MCLK 1
	195	#define ISP_CLK_DPLL4_M5_CK 2
	196	#define ISP_CLK_CSI2_FCK 3
	197	#define ISP_CLK_L3_ICK 4
	198	struct clk *clock[5];
	199
	200	/* ISP modules */
	201	struct ispstat isp_af;
	202	struct ispstat isp_aewb;
	203	struct ispstat isp_hist;
	204	struct isp_res_device isp_res;
	205	struct isp_prev_device isp_prev;
	206	struct isp_ccdc_device isp_ccdc;
	207	struct isp_csi2_device isp_csi2a;
	208	struct isp_csi2_device isp_csi2c;
	209	struct isp_ccp2_device isp_ccp2;
	210	struct isp_csiphy isp_csiphy1;
	211	struct isp_csiphy isp_csiphy2;
	212
	213	unsigned int sbl_resources;
	214	unsigned int subclk_resources;
	215
f626b52d	216	struct iommu_domain *domain;
448de7e7 SA	217
	218	struct isp_platform_callback platform_cb;
	219	};
	220
	221	#define v4l2_dev_to_isp_device(dev) \
	222	container_of(dev, struct isp_device, v4l2_dev)
	223
	224	void omap3isp_hist_dma_done(struct isp_device *isp);
	225
	226	void omap3isp_flush(struct isp_device *isp);
	227
	228	int omap3isp_module_sync_idle(struct media_entity me, wait_queue_head_t wait,
	229	atomic_t *stopping);
	230
	231	int omap3isp_module_sync_is_stopping(wait_queue_head_t *wait,
	232	atomic_t *stopping);
	233
	234	int omap3isp_pipeline_set_stream(struct isp_pipeline *pipe,
	235	enum isp_pipeline_stream_state state);
	236	void omap3isp_configure_bridge(struct isp_device *isp,
	237	enum ccdc_input_entity input,
c09af044 MJ	238	const struct isp_parallel_platform_data *pdata,
c09af044 MJ	239	unsigned int shift);
448de7e7	240
7c2c8f42 SV	241	#define ISP_XCLK_NONE 0
	242	#define ISP_XCLK_A 1
	243	#define ISP_XCLK_B 2
448de7e7 SA	244
	245	struct isp_device omap3isp_get(struct isp_device isp);
	246	void omap3isp_put(struct isp_device *isp);
	247
	248	void omap3isp_print_status(struct isp_device *isp);
	249
	250	void omap3isp_sbl_enable(struct isp_device *isp, enum isp_sbl_resource res);
	251	void omap3isp_sbl_disable(struct isp_device *isp, enum isp_sbl_resource res);
	252
	253	void omap3isp_subclk_enable(struct isp_device *isp,
	254	enum isp_subclk_resource res);
	255	void omap3isp_subclk_disable(struct isp_device *isp,
	256	enum isp_subclk_resource res);
	257
	258	int omap3isp_pipeline_pm_use(struct media_entity *entity, int use);
	259
	260	int omap3isp_register_entities(struct platform_device *pdev,
	261	struct v4l2_device *v4l2_dev);
	262	void omap3isp_unregister_entities(struct platform_device *pdev);
	263
	264	/*
	265	* isp_reg_readl - Read value of an OMAP3 ISP register
	266	* @dev: Device pointer specific to the OMAP3 ISP.
	267	* @isp_mmio_range: Range to which the register offset refers to.
	268	* @reg_offset: Register offset to read from.
	269	*
	270	* Returns an unsigned 32 bit value with the required register contents.
	271	*/
	272	static inline
	273	u32 isp_reg_readl(struct isp_device *isp, enum isp_mem_resources isp_mmio_range,
	274	u32 reg_offset)
	275	{
	276	return __raw_readl(isp->mmio_base[isp_mmio_range] + reg_offset);
	277	}
	278
	279	/*
	280	* isp_reg_writel - Write value to an OMAP3 ISP register
	281	* @dev: Device pointer specific to the OMAP3 ISP.
	282	* @reg_value: 32 bit value to write to the register.
	283	* @isp_mmio_range: Range to which the register offset refers to.
	284	* @reg_offset: Register offset to write into.
	285	*/
	286	static inline
	287	void isp_reg_writel(struct isp_device *isp, u32 reg_value,
	288	enum isp_mem_resources isp_mmio_range, u32 reg_offset)
	289	{
	290	__raw_writel(reg_value, isp->mmio_base[isp_mmio_range] + reg_offset);
	291	}
	292
	293	/*
	294	* isp_reg_and - Clear individual bits in an OMAP3 ISP register
	295	* @dev: Device pointer specific to the OMAP3 ISP.
	296	* @mmio_range: Range to which the register offset refers to.
	297	* @reg: Register offset to work on.
	298	* @clr_bits: 32 bit value which would be cleared in the register.
	299	*/
	300	static inline
	301	void isp_reg_clr(struct isp_device *isp, enum isp_mem_resources mmio_range,
	302	u32 reg, u32 clr_bits)
	303	{
	304	u32 v = isp_reg_readl(isp, mmio_range, reg);
	305
	306	isp_reg_writel(isp, v & ~clr_bits, mmio_range, reg);
	307	}
308
309	/*
310	* isp_reg_set - Set individual bits in an OMAP3 ISP register
311	* @dev: Device pointer specific to the OMAP3 ISP.
312	* @mmio_range: Range to which the register offset refers to.
313	* @reg: Register offset to work on.
314	* @set_bits: 32 bit value which would be set in the register.
315	*/
316	static inline
317	void isp_reg_set(struct isp_device *isp, enum isp_mem_resources mmio_range,
318	u32 reg, u32 set_bits)
319	{
320	u32 v = isp_reg_readl(isp, mmio_range, reg);
321
322	isp_reg_writel(isp, v \| set_bits, mmio_range, reg);
323	}
324
325	/*
326	* isp_reg_clr_set - Clear and set invidial bits in an OMAP3 ISP register
327	* @dev: Device pointer specific to the OMAP3 ISP.
328	* @mmio_range: Range to which the register offset refers to.
329	* @reg: Register offset to work on.
330	* @clr_bits: 32 bit value which would be cleared in the register.
331	* @set_bits: 32 bit value which would be set in the register.
332	*
333	* The clear operation is done first, and then the set operation.
334	*/
335	static inline
336	void isp_reg_clr_set(struct isp_device *isp, enum isp_mem_resources mmio_range,
337	u32 reg, u32 clr_bits, u32 set_bits)
338	{
339	u32 v = isp_reg_readl(isp, mmio_range, reg);
340
341	isp_reg_writel(isp, (v & ~clr_bits) \| set_bits, mmio_range, reg);
342	}
343
344	static inline enum v4l2_buf_type
345	isp_pad_buffer_type(const struct v4l2_subdev *subdev, int pad)
346	{
347	if (pad >= subdev->entity.num_pads)
348	return 0;
349
350	if (subdev->entity.pads[pad].flags & MEDIA_PAD_FL_SINK)
351	return V4L2_BUF_TYPE_VIDEO_OUTPUT;
352	else
353	return V4L2_BUF_TYPE_VIDEO_CAPTURE;
354	}
355
356	#endif /* OMAP3_ISP_CORE_H */