[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / media / video / omap3isp / isp.h

/*
 * isp.h
 *
 * TI OMAP3 ISP - Core
 *
 * Copyright (C) 2009-2010 Nokia Corporation
 * Copyright (C) 2009 Texas Instruments, Inc.
 *
 * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
 *	     Sakari Ailus <sakari.ailus@iki.fi>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 */

#ifndef OMAP3_ISP_CORE_H
#define OMAP3_ISP_CORE_H

#include <media/v4l2-device.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/wait.h>
#include <plat/iommu.h>
#include <plat/iovmm.h>

#include "ispstat.h"
#include "ispccdc.h"
#include "ispreg.h"
#include "ispresizer.h"
#include "isppreview.h"
#include "ispcsiphy.h"
#include "ispcsi2.h"
#include "ispccp2.h"

#define IOMMU_FLAG (IOVMF_ENDIAN_LITTLE | IOVMF_ELSZ_8)

#define ISP_TOK_TERM		0xFFFFFFFF	/*
						 * terminating token for ISP
						 * modules reg list
						 */
#define to_isp_device(ptr_module)				\
	container_of(ptr_module, struct isp_device, isp_##ptr_module)
#define to_device(ptr_module)						\
	(to_isp_device(ptr_module)->dev)

enum isp_mem_resources {
	OMAP3_ISP_IOMEM_MAIN,
	OMAP3_ISP_IOMEM_CCP2,
	OMAP3_ISP_IOMEM_CCDC,
	OMAP3_ISP_IOMEM_HIST,
	OMAP3_ISP_IOMEM_H3A,
	OMAP3_ISP_IOMEM_PREV,
	OMAP3_ISP_IOMEM_RESZ,
	OMAP3_ISP_IOMEM_SBL,
	OMAP3_ISP_IOMEM_CSI2A_REGS1,
	OMAP3_ISP_IOMEM_CSIPHY2,
	OMAP3_ISP_IOMEM_CSI2A_REGS2,
	OMAP3_ISP_IOMEM_CSI2C_REGS1,
	OMAP3_ISP_IOMEM_CSIPHY1,
	OMAP3_ISP_IOMEM_CSI2C_REGS2,
	OMAP3_ISP_IOMEM_LAST
};

enum isp_sbl_resource {
	OMAP3_ISP_SBL_CSI1_READ		= 0x1,
	OMAP3_ISP_SBL_CSI1_WRITE	= 0x2,
	OMAP3_ISP_SBL_CSI2A_WRITE	= 0x4,
	OMAP3_ISP_SBL_CSI2C_WRITE	= 0x8,
	OMAP3_ISP_SBL_CCDC_LSC_READ	= 0x10,
	OMAP3_ISP_SBL_CCDC_WRITE	= 0x20,
	OMAP3_ISP_SBL_PREVIEW_READ	= 0x40,
	OMAP3_ISP_SBL_PREVIEW_WRITE	= 0x80,
	OMAP3_ISP_SBL_RESIZER_READ	= 0x100,
	OMAP3_ISP_SBL_RESIZER_WRITE	= 0x200,
};

enum isp_subclk_resource {
	OMAP3_ISP_SUBCLK_CCDC		= (1 << 0),
	OMAP3_ISP_SUBCLK_H3A		= (1 << 1),
	OMAP3_ISP_SUBCLK_HIST		= (1 << 2),
	OMAP3_ISP_SUBCLK_PREVIEW	= (1 << 3),
	OMAP3_ISP_SUBCLK_RESIZER	= (1 << 4),
};

enum isp_interface_type {
	ISP_INTERFACE_PARALLEL,
	ISP_INTERFACE_CSI2A_PHY2,
	ISP_INTERFACE_CCP2B_PHY1,
	ISP_INTERFACE_CCP2B_PHY2,
	ISP_INTERFACE_CSI2C_PHY1,
};

/* ISP: OMAP 34xx ES 1.0 */
#define ISP_REVISION_1_0		0x10
/* ISP2: OMAP 34xx ES 2.0, 2.1 and 3.0 */
#define ISP_REVISION_2_0		0x20
/* ISP2P: OMAP 36xx */
#define ISP_REVISION_15_0		0xF0

/*
 * struct isp_res_mapping - Map ISP io resources to ISP revision.
 * @isp_rev: ISP_REVISION_x_x
 * @map: bitmap for enum isp_mem_resources
 */
struct isp_res_mapping {
	u32 isp_rev;
	u32 map;
};

/*
 * struct isp_reg - Structure for ISP register values.
 * @reg: 32-bit Register address.
 * @val: 32-bit Register value.
 */
struct isp_reg {
	enum isp_mem_resources mmio_range;
	u32 reg;
	u32 val;
};

/**
 * struct isp_parallel_platform_data - Parallel interface platform data
 * @data_lane_shift: Data lane shifter
 *		0 - CAMEXT[13:0] -> CAM[13:0]
 *		1 - CAMEXT[13:2] -> CAM[11:0]
 *		2 - CAMEXT[13:4] -> CAM[9:0]
 *		3 - CAMEXT[13:6] -> CAM[7:0]
 * @clk_pol: Pixel clock polarity
 *		0 - Non Inverted, 1 - Inverted
 * @bridge: CCDC Bridge input control
 *		ISPCTRL_PAR_BRIDGE_DISABLE - Disable
 *		ISPCTRL_PAR_BRIDGE_LENDIAN - Little endian
 *		ISPCTRL_PAR_BRIDGE_BENDIAN - Big endian
 */
struct isp_parallel_platform_data {
	unsigned int data_lane_shift:2;
	unsigned int clk_pol:1;
	unsigned int bridge:4;
};

/**
 * struct isp_ccp2_platform_data - CCP2 interface platform data
 * @strobe_clk_pol: Strobe/clock polarity
 *		0 - Non Inverted, 1 - Inverted
 * @crc: Enable the cyclic redundancy check
 * @ccp2_mode: Enable CCP2 compatibility mode
 *		0 - MIPI-CSI1 mode, 1 - CCP2 mode
 * @phy_layer: Physical layer selection
 *		ISPCCP2_CTRL_PHY_SEL_CLOCK - Data/clock physical layer
 *		ISPCCP2_CTRL_PHY_SEL_STROBE - Data/strobe physical layer
 * @vpclk_div: Video port output clock control
 */
struct isp_ccp2_platform_data {
	unsigned int strobe_clk_pol:1;
	unsigned int crc:1;
	unsigned int ccp2_mode:1;
	unsigned int phy_layer:1;
	unsigned int vpclk_div:2;
};

/**
 * struct isp_csi2_platform_data - CSI2 interface platform data
 * @crc: Enable the cyclic redundancy check
 * @vpclk_div: Video port output clock control
 */
struct isp_csi2_platform_data {
	unsigned crc:1;
	unsigned vpclk_div:2;
};

struct isp_subdev_i2c_board_info {
	struct i2c_board_info *board_info;
	int i2c_adapter_id;
};

struct isp_v4l2_subdevs_group {
	struct isp_subdev_i2c_board_info *subdevs;
	enum isp_interface_type interface;
	union {
		struct isp_parallel_platform_data parallel;
		struct isp_ccp2_platform_data ccp2;
		struct isp_csi2_platform_data csi2;
	} bus; /* gcc < 4.6.0 chokes on anonymous union initializers */
};

struct isp_platform_data {
	struct isp_v4l2_subdevs_group *subdevs;
	void (*set_constraints)(struct isp_device *isp, bool enable);
};

struct isp_platform_callback {
	u32 (*set_xclk)(struct isp_device *isp, u32 xclk, u8 xclksel);
	int (*csiphy_config)(struct isp_csiphy *phy,
			     struct isp_csiphy_dphy_cfg *dphy,
			     struct isp_csiphy_lanes_cfg *lanes);
	void (*set_pixel_clock)(struct isp_device *isp, unsigned int pixelclk);
};

/*
 * struct isp_device - ISP device structure.
 * @dev: Device pointer specific to the OMAP3 ISP.
 * @revision: Stores current ISP module revision.
 * @irq_num: Currently used IRQ number.
 * @mmio_base: Array with kernel base addresses for ioremapped ISP register
 *             regions.
 * @mmio_base_phys: Array with physical L4 bus addresses for ISP register
 *                  regions.
 * @mmio_size: Array with ISP register regions size in bytes.
 * @raw_dmamask: Raw DMA mask
 * @stat_lock: Spinlock for handling statistics
 * @isp_mutex: Mutex for serializing requests to ISP.
 * @has_context: Context has been saved at least once and can be restored.
 * @ref_count: Reference count for handling multiple ISP requests.
 * @cam_ick: Pointer to camera interface clock structure.
 * @cam_mclk: Pointer to camera functional clock structure.
 * @dpll4_m5_ck: Pointer to DPLL4 M5 clock structure.
 * @csi2_fck: Pointer to camera CSI2 complexIO clock structure.
 * @l3_ick: Pointer to OMAP3 L3 bus interface clock.
 * @irq: Currently attached ISP ISR callbacks information structure.
 * @isp_af: Pointer to current settings for ISP AutoFocus SCM.
 * @isp_hist: Pointer to current settings for ISP Histogram SCM.
 * @isp_h3a: Pointer to current settings for ISP Auto Exposure and
 *           White Balance SCM.
 * @isp_res: Pointer to current settings for ISP Resizer.
 * @isp_prev: Pointer to current settings for ISP Preview.
 * @isp_ccdc: Pointer to current settings for ISP CCDC.
 * @iommu: Pointer to requested IOMMU instance for ISP.
 * @platform_cb: ISP driver callback function pointers for platform code
 *
 * This structure is used to store the OMAP ISP Information.
 */
struct isp_device {
	struct v4l2_device v4l2_dev;
	struct media_device media_dev;
	struct device *dev;
	u32 revision;

	/* platform HW resources */
	struct isp_platform_data *pdata;
	unsigned int irq_num;

	void __iomem *mmio_base[OMAP3_ISP_IOMEM_LAST];
	unsigned long mmio_base_phys[OMAP3_ISP_IOMEM_LAST];
	resource_size_t mmio_size[OMAP3_ISP_IOMEM_LAST];

	u64 raw_dmamask;

	/* ISP Obj */
	spinlock_t stat_lock;	/* common lock for statistic drivers */
	struct mutex isp_mutex;	/* For handling ref_count field */
	bool needs_reset;
	int has_context;
	int ref_count;
	unsigned int autoidle;
	u32 xclk_divisor[2];	/* Two clocks, a and b. */
#define ISP_CLK_CAM_ICK		0
#define ISP_CLK_CAM_MCLK	1
#define ISP_CLK_DPLL4_M5_CK	2
#define ISP_CLK_CSI2_FCK	3
#define ISP_CLK_L3_ICK		4
	struct clk *clock[5];

	/* ISP modules */
	struct ispstat isp_af;
	struct ispstat isp_aewb;
	struct ispstat isp_hist;
	struct isp_res_device isp_res;
	struct isp_prev_device isp_prev;
	struct isp_ccdc_device isp_ccdc;
	struct isp_csi2_device isp_csi2a;
	struct isp_csi2_device isp_csi2c;
	struct isp_ccp2_device isp_ccp2;
	struct isp_csiphy isp_csiphy1;
	struct isp_csiphy isp_csiphy2;

	unsigned int sbl_resources;
	unsigned int subclk_resources;

	struct iommu *iommu;

	struct isp_platform_callback platform_cb;
};

#define v4l2_dev_to_isp_device(dev) \
	container_of(dev, struct isp_device, v4l2_dev)

void omap3isp_hist_dma_done(struct isp_device *isp);

void omap3isp_flush(struct isp_device *isp);

int omap3isp_module_sync_idle(struct media_entity *me, wait_queue_head_t *wait,
			      atomic_t *stopping);

int omap3isp_module_sync_is_stopping(wait_queue_head_t *wait,
				     atomic_t *stopping);

int omap3isp_pipeline_set_stream(struct isp_pipeline *pipe,
				 enum isp_pipeline_stream_state state);
void omap3isp_configure_bridge(struct isp_device *isp,
			       enum ccdc_input_entity input,
			       const struct isp_parallel_platform_data *pdata,
			       unsigned int shift);

#define ISP_XCLK_NONE			0
#define ISP_XCLK_A			1
#define ISP_XCLK_B			2

struct isp_device *omap3isp_get(struct isp_device *isp);
void omap3isp_put(struct isp_device *isp);

void omap3isp_print_status(struct isp_device *isp);

void omap3isp_sbl_enable(struct isp_device *isp, enum isp_sbl_resource res);
void omap3isp_sbl_disable(struct isp_device *isp, enum isp_sbl_resource res);

void omap3isp_subclk_enable(struct isp_device *isp,
			    enum isp_subclk_resource res);
void omap3isp_subclk_disable(struct isp_device *isp,
			     enum isp_subclk_resource res);

int omap3isp_pipeline_pm_use(struct media_entity *entity, int use);

int omap3isp_register_entities(struct platform_device *pdev,
			       struct v4l2_device *v4l2_dev);
void omap3isp_unregister_entities(struct platform_device *pdev);

/*
 * isp_reg_readl - Read value of an OMAP3 ISP register
 * @dev: Device pointer specific to the OMAP3 ISP.
 * @isp_mmio_range: Range to which the register offset refers to.
 * @reg_offset: Register offset to read from.
 *
 * Returns an unsigned 32 bit value with the required register contents.
 */
static inline
u32 isp_reg_readl(struct isp_device *isp, enum isp_mem_resources isp_mmio_range,
		  u32 reg_offset)
{
	return __raw_readl(isp->mmio_base[isp_mmio_range] + reg_offset);
}

/*
 * isp_reg_writel - Write value to an OMAP3 ISP register
 * @dev: Device pointer specific to the OMAP3 ISP.
 * @reg_value: 32 bit value to write to the register.
 * @isp_mmio_range: Range to which the register offset refers to.
 * @reg_offset: Register offset to write into.
 */
static inline
void isp_reg_writel(struct isp_device *isp, u32 reg_value,
		    enum isp_mem_resources isp_mmio_range, u32 reg_offset)
{
	__raw_writel(reg_value, isp->mmio_base[isp_mmio_range] + reg_offset);
}

/*
 * isp_reg_and - Clear individual bits in an OMAP3 ISP register
 * @dev: Device pointer specific to the OMAP3 ISP.
 * @mmio_range: Range to which the register offset refers to.
 * @reg: Register offset to work on.
 * @clr_bits: 32 bit value which would be cleared in the register.
 */
static inline
void isp_reg_clr(struct isp_device *isp, enum isp_mem_resources mmio_range,
		 u32 reg, u32 clr_bits)
{
	u32 v = isp_reg_readl(isp, mmio_range, reg);

	isp_reg_writel(isp, v & ~clr_bits, mmio_range, reg);
}

/*
 * isp_reg_set - Set individual bits in an OMAP3 ISP register
 * @dev: Device pointer specific to the OMAP3 ISP.
 * @mmio_range: Range to which the register offset refers to.
 * @reg: Register offset to work on.
 * @set_bits: 32 bit value which would be set in the register.
 */
static inline
void isp_reg_set(struct isp_device *isp, enum isp_mem_resources mmio_range,
		 u32 reg, u32 set_bits)
{
	u32 v = isp_reg_readl(isp, mmio_range, reg);

	isp_reg_writel(isp, v | set_bits, mmio_range, reg);
}

/*
 * isp_reg_clr_set - Clear and set invidial bits in an OMAP3 ISP register
 * @dev: Device pointer specific to the OMAP3 ISP.
 * @mmio_range: Range to which the register offset refers to.
 * @reg: Register offset to work on.
 * @clr_bits: 32 bit value which would be cleared in the register.
 * @set_bits: 32 bit value which would be set in the register.
 *
 * The clear operation is done first, and then the set operation.
 */
static inline
void isp_reg_clr_set(struct isp_device *isp, enum isp_mem_resources mmio_range,
		     u32 reg, u32 clr_bits, u32 set_bits)
{
	u32 v = isp_reg_readl(isp, mmio_range, reg);

	isp_reg_writel(isp, (v & ~clr_bits) | set_bits, mmio_range, reg);
}

static inline enum v4l2_buf_type
isp_pad_buffer_type(const struct v4l2_subdev *subdev, int pad)
{
	if (pad >= subdev->entity.num_pads)
		return 0;

	if (subdev->entity.pads[pad].flags & MEDIA_PAD_FL_SINK)
		return V4L2_BUF_TYPE_VIDEO_OUTPUT;
	else
		return V4L2_BUF_TYPE_VIDEO_CAPTURE;
}

#endif	/* OMAP3_ISP_CORE_H */
Commit	Line	Data
448de7e7 SA	1	/*
	2	* isp.h
	3	*
	4	* TI OMAP3 ISP - Core
	5	*
	6	* Copyright (C) 2009-2010 Nokia Corporation
	7	* Copyright (C) 2009 Texas Instruments, Inc.
	8	*
	9	* Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
	10	* Sakari Ailus <sakari.ailus@iki.fi>
	11	*
	12	* This program is free software; you can redistribute it and/or modify
	13	* it under the terms of the GNU General Public License version 2 as
	14	* published by the Free Software Foundation.
	15	*
	16	* This program is distributed in the hope that it will be useful, but
	17	* WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	19	* General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	24	* 02110-1301 USA
	25	*/
	26
	27	#ifndef OMAP3_ISP_CORE_H
	28	#define OMAP3_ISP_CORE_H
	29
	30	#include <media/v4l2-device.h>
	31	#include <linux/device.h>
	32	#include <linux/io.h>
	33	#include <linux/platform_device.h>
	34	#include <linux/wait.h>
	35	#include <plat/iommu.h>
	36	#include <plat/iovmm.h>
	37
	38	#include "ispstat.h"
	39	#include "ispccdc.h"
	40	#include "ispreg.h"
	41	#include "ispresizer.h"
	42	#include "isppreview.h"
	43	#include "ispcsiphy.h"
	44	#include "ispcsi2.h"
	45	#include "ispccp2.h"
	46
	47	#define IOMMU_FLAG (IOVMF_ENDIAN_LITTLE \| IOVMF_ELSZ_8)
	48
	49	#define ISP_TOK_TERM 0xFFFFFFFF /*
	50	* terminating token for ISP
	51	* modules reg list
	52	*/
	53	#define to_isp_device(ptr_module) \
	54	container_of(ptr_module, struct isp_device, isp_##ptr_module)
	55	#define to_device(ptr_module) \
	56	(to_isp_device(ptr_module)->dev)
	57
	58	enum isp_mem_resources {
	59	OMAP3_ISP_IOMEM_MAIN,
	60	OMAP3_ISP_IOMEM_CCP2,
	61	OMAP3_ISP_IOMEM_CCDC,
	62	OMAP3_ISP_IOMEM_HIST,
	63	OMAP3_ISP_IOMEM_H3A,
	64	OMAP3_ISP_IOMEM_PREV,
65	OMAP3_ISP_IOMEM_RESZ,
66	OMAP3_ISP_IOMEM_SBL,
67	OMAP3_ISP_IOMEM_CSI2A_REGS1,
68	OMAP3_ISP_IOMEM_CSIPHY2,
69	OMAP3_ISP_IOMEM_CSI2A_REGS2,
70	OMAP3_ISP_IOMEM_CSI2C_REGS1,
71	OMAP3_ISP_IOMEM_CSIPHY1,
72	OMAP3_ISP_IOMEM_CSI2C_REGS2,
73	OMAP3_ISP_IOMEM_LAST
74	};
75
76	enum isp_sbl_resource {
77	OMAP3_ISP_SBL_CSI1_READ = 0x1,
78	OMAP3_ISP_SBL_CSI1_WRITE = 0x2,
79	OMAP3_ISP_SBL_CSI2A_WRITE = 0x4,
80	OMAP3_ISP_SBL_CSI2C_WRITE = 0x8,
81	OMAP3_ISP_SBL_CCDC_LSC_READ = 0x10,
82	OMAP3_ISP_SBL_CCDC_WRITE = 0x20,
83	OMAP3_ISP_SBL_PREVIEW_READ = 0x40,
84	OMAP3_ISP_SBL_PREVIEW_WRITE = 0x80,
85	OMAP3_ISP_SBL_RESIZER_READ = 0x100,
86	OMAP3_ISP_SBL_RESIZER_WRITE = 0x200,
87	};
88
89	enum isp_subclk_resource {
90	OMAP3_ISP_SUBCLK_CCDC = (1 << 0),
91	OMAP3_ISP_SUBCLK_H3A = (1 << 1),
92	OMAP3_ISP_SUBCLK_HIST = (1 << 2),
93	OMAP3_ISP_SUBCLK_PREVIEW = (1 << 3),
94	OMAP3_ISP_SUBCLK_RESIZER = (1 << 4),
95	};
96
97	enum isp_interface_type {
98	ISP_INTERFACE_PARALLEL,
99	ISP_INTERFACE_CSI2A_PHY2,
100	ISP_INTERFACE_CCP2B_PHY1,
101	ISP_INTERFACE_CCP2B_PHY2,
102	ISP_INTERFACE_CSI2C_PHY1,
103	};
104
105	/* ISP: OMAP 34xx ES 1.0 */
106	#define ISP_REVISION_1_0 0x10
107	/* ISP2: OMAP 34xx ES 2.0, 2.1 and 3.0 */
108	#define ISP_REVISION_2_0 0x20
109	/* ISP2P: OMAP 36xx */
110	#define ISP_REVISION_15_0 0xF0
111
112	/*
113	* struct isp_res_mapping - Map ISP io resources to ISP revision.
114	* @isp_rev: ISP_REVISION_x_x
115	* @map: bitmap for enum isp_mem_resources
116	*/
117	struct isp_res_mapping {
118	u32 isp_rev;
119	u32 map;
120	};
121
122	/*
123	* struct isp_reg - Structure for ISP register values.
124	* @reg: 32-bit Register address.
125	* @val: 32-bit Register value.
126	*/
127	struct isp_reg {
128	enum isp_mem_resources mmio_range;
129	u32 reg;
130	u32 val;
131	};
132
133	/**
134	* struct isp_parallel_platform_data - Parallel interface platform data
448de7e7 SA	135	* @data_lane_shift: Data lane shifter
	136	* 0 - CAMEXT[13:0] -> CAM[13:0]
	137	* 1 - CAMEXT[13:2] -> CAM[11:0]
	138	* 2 - CAMEXT[13:4] -> CAM[9:0]
	139	* 3 - CAMEXT[13:6] -> CAM[7:0]
	140	* @clk_pol: Pixel clock polarity
	141	* 0 - Non Inverted, 1 - Inverted
	142	* @bridge: CCDC Bridge input control
	143	* ISPCTRL_PAR_BRIDGE_DISABLE - Disable
	144	* ISPCTRL_PAR_BRIDGE_LENDIAN - Little endian
	145	* ISPCTRL_PAR_BRIDGE_BENDIAN - Big endian
	146	*/
	147	struct isp_parallel_platform_data {
448de7e7 SA	148	unsigned int data_lane_shift:2;
	149	unsigned int clk_pol:1;
	150	unsigned int bridge:4;
	151	};
	152
	153	/**
	154	* struct isp_ccp2_platform_data - CCP2 interface platform data
	155	* @strobe_clk_pol: Strobe/clock polarity
	156	* 0 - Non Inverted, 1 - Inverted
	157	* @crc: Enable the cyclic redundancy check
	158	* @ccp2_mode: Enable CCP2 compatibility mode
	159	* 0 - MIPI-CSI1 mode, 1 - CCP2 mode
	160	* @phy_layer: Physical layer selection
	161	* ISPCCP2_CTRL_PHY_SEL_CLOCK - Data/clock physical layer
	162	* ISPCCP2_CTRL_PHY_SEL_STROBE - Data/strobe physical layer
	163	* @vpclk_div: Video port output clock control
	164	*/
	165	struct isp_ccp2_platform_data {
	166	unsigned int strobe_clk_pol:1;
	167	unsigned int crc:1;
	168	unsigned int ccp2_mode:1;
	169	unsigned int phy_layer:1;
	170	unsigned int vpclk_div:2;
	171	};
	172
	173	/**
	174	* struct isp_csi2_platform_data - CSI2 interface platform data
	175	* @crc: Enable the cyclic redundancy check
	176	* @vpclk_div: Video port output clock control
	177	*/
	178	struct isp_csi2_platform_data {
	179	unsigned crc:1;
	180	unsigned vpclk_div:2;
	181	};
	182
	183	struct isp_subdev_i2c_board_info {
	184	struct i2c_board_info *board_info;
	185	int i2c_adapter_id;
	186	};
	187
	188	struct isp_v4l2_subdevs_group {
	189	struct isp_subdev_i2c_board_info *subdevs;
	190	enum isp_interface_type interface;
	191	union {
	192	struct isp_parallel_platform_data parallel;
	193	struct isp_ccp2_platform_data ccp2;
	194	struct isp_csi2_platform_data csi2;
	195	} bus; /* gcc < 4.6.0 chokes on anonymous union initializers */
	196	};
	197
	198	struct isp_platform_data {
	199	struct isp_v4l2_subdevs_group *subdevs;
4b0ec19e	200	void (set_constraints)(struct isp_device isp, bool enable);
448de7e7 SA	201	};
	202
	203	struct isp_platform_callback {
	204	u32 (set_xclk)(struct isp_device isp, u32 xclk, u8 xclksel);
	205	int (csiphy_config)(struct isp_csiphy phy,
	206	struct isp_csiphy_dphy_cfg *dphy,
	207	struct isp_csiphy_lanes_cfg *lanes);
	208	void (set_pixel_clock)(struct isp_device isp, unsigned int pixelclk);
	209	};
	210
	211	/*
	212	* struct isp_device - ISP device structure.
	213	* @dev: Device pointer specific to the OMAP3 ISP.
	214	* @revision: Stores current ISP module revision.
	215	* @irq_num: Currently used IRQ number.
	216	* @mmio_base: Array with kernel base addresses for ioremapped ISP register
	217	* regions.
	218	* @mmio_base_phys: Array with physical L4 bus addresses for ISP register
	219	* regions.
	220	* @mmio_size: Array with ISP register regions size in bytes.
	221	* @raw_dmamask: Raw DMA mask
	222	* @stat_lock: Spinlock for handling statistics
	223	* @isp_mutex: Mutex for serializing requests to ISP.
	224	* @has_context: Context has been saved at least once and can be restored.
	225	* @ref_count: Reference count for handling multiple ISP requests.
	226	* @cam_ick: Pointer to camera interface clock structure.
	227	* @cam_mclk: Pointer to camera functional clock structure.
	228	* @dpll4_m5_ck: Pointer to DPLL4 M5 clock structure.
	229	* @csi2_fck: Pointer to camera CSI2 complexIO clock structure.
	230	* @l3_ick: Pointer to OMAP3 L3 bus interface clock.
	231	* @irq: Currently attached ISP ISR callbacks information structure.
	232	* @isp_af: Pointer to current settings for ISP AutoFocus SCM.
	233	* @isp_hist: Pointer to current settings for ISP Histogram SCM.
	234	* @isp_h3a: Pointer to current settings for ISP Auto Exposure and
	235	* White Balance SCM.
	236	* @isp_res: Pointer to current settings for ISP Resizer.
	237	* @isp_prev: Pointer to current settings for ISP Preview.
	238	* @isp_ccdc: Pointer to current settings for ISP CCDC.
	239	* @iommu: Pointer to requested IOMMU instance for ISP.
	240	* @platform_cb: ISP driver callback function pointers for platform code
	241	*
	242	* This structure is used to store the OMAP ISP Information.
	243	*/
	244	struct isp_device {
	245	struct v4l2_device v4l2_dev;
	246	struct media_device media_dev;
	247	struct device *dev;
	248	u32 revision;
	249
	250	/* platform HW resources */
	251	struct isp_platform_data *pdata;
	252	unsigned int irq_num;
	253
	254	void __iomem *mmio_base[OMAP3_ISP_IOMEM_LAST];
	255	unsigned long mmio_base_phys[OMAP3_ISP_IOMEM_LAST];
	256	resource_size_t mmio_size[OMAP3_ISP_IOMEM_LAST];
	257
	258	u64 raw_dmamask;
	259
	260	/* ISP Obj */
	261	spinlock_t stat_lock; /* common lock for statistic drivers */
	262	struct mutex isp_mutex; /* For handling ref_count field */
994d5375	263	bool needs_reset;
448de7e7 SA	264	int has_context;
	265	int ref_count;
	266	unsigned int autoidle;
	267	u32 xclk_divisor[2]; /* Two clocks, a and b. */
	268	#define ISP_CLK_CAM_ICK 0
	269	#define ISP_CLK_CAM_MCLK 1
	270	#define ISP_CLK_DPLL4_M5_CK 2
	271	#define ISP_CLK_CSI2_FCK 3
	272	#define ISP_CLK_L3_ICK 4
	273	struct clk *clock[5];
	274
	275	/* ISP modules */
	276	struct ispstat isp_af;
	277	struct ispstat isp_aewb;
	278	struct ispstat isp_hist;
	279	struct isp_res_device isp_res;
	280	struct isp_prev_device isp_prev;
	281	struct isp_ccdc_device isp_ccdc;
	282	struct isp_csi2_device isp_csi2a;
	283	struct isp_csi2_device isp_csi2c;
	284	struct isp_ccp2_device isp_ccp2;
	285	struct isp_csiphy isp_csiphy1;
	286	struct isp_csiphy isp_csiphy2;
	287
	288	unsigned int sbl_resources;
	289	unsigned int subclk_resources;
	290
	291	struct iommu *iommu;
	292
	293	struct isp_platform_callback platform_cb;
	294	};
	295
	296	#define v4l2_dev_to_isp_device(dev) \
	297	container_of(dev, struct isp_device, v4l2_dev)
	298
	299	void omap3isp_hist_dma_done(struct isp_device *isp);
	300
	301	void omap3isp_flush(struct isp_device *isp);
	302
	303	int omap3isp_module_sync_idle(struct media_entity me, wait_queue_head_t wait,
	304	atomic_t *stopping);
	305
	306	int omap3isp_module_sync_is_stopping(wait_queue_head_t *wait,
	307	atomic_t *stopping);
	308
	309	int omap3isp_pipeline_set_stream(struct isp_pipeline *pipe,
	310	enum isp_pipeline_stream_state state);
	311	void omap3isp_configure_bridge(struct isp_device *isp,
	312	enum ccdc_input_entity input,
c09af044 MJ	313	const struct isp_parallel_platform_data *pdata,
c09af044 MJ	314	unsigned int shift);
448de7e7	315
7c2c8f42 SV	316	#define ISP_XCLK_NONE 0
	317	#define ISP_XCLK_A 1
	318	#define ISP_XCLK_B 2
448de7e7 SA	319
	320	struct isp_device omap3isp_get(struct isp_device isp);
	321	void omap3isp_put(struct isp_device *isp);
	322
	323	void omap3isp_print_status(struct isp_device *isp);
	324
	325	void omap3isp_sbl_enable(struct isp_device *isp, enum isp_sbl_resource res);
	326	void omap3isp_sbl_disable(struct isp_device *isp, enum isp_sbl_resource res);
	327
	328	void omap3isp_subclk_enable(struct isp_device *isp,
	329	enum isp_subclk_resource res);
	330	void omap3isp_subclk_disable(struct isp_device *isp,
	331	enum isp_subclk_resource res);
	332
	333	int omap3isp_pipeline_pm_use(struct media_entity *entity, int use);
	334
	335	int omap3isp_register_entities(struct platform_device *pdev,
	336	struct v4l2_device *v4l2_dev);
	337	void omap3isp_unregister_entities(struct platform_device *pdev);
	338
	339	/*
	340	* isp_reg_readl - Read value of an OMAP3 ISP register
	341	* @dev: Device pointer specific to the OMAP3 ISP.
	342	* @isp_mmio_range: Range to which the register offset refers to.
	343	* @reg_offset: Register offset to read from.
	344	*
	345	* Returns an unsigned 32 bit value with the required register contents.
	346	*/
	347	static inline
	348	u32 isp_reg_readl(struct isp_device *isp, enum isp_mem_resources isp_mmio_range,
	349	u32 reg_offset)
	350	{
	351	return __raw_readl(isp->mmio_base[isp_mmio_range] + reg_offset);
	352	}
	353
	354	/*
	355	* isp_reg_writel - Write value to an OMAP3 ISP register
	356	* @dev: Device pointer specific to the OMAP3 ISP.
	357	* @reg_value: 32 bit value to write to the register.
	358	* @isp_mmio_range: Range to which the register offset refers to.
	359	* @reg_offset: Register offset to write into.
	360	*/
	361	static inline
	362	void isp_reg_writel(struct isp_device *isp, u32 reg_value,
	363	enum isp_mem_resources isp_mmio_range, u32 reg_offset)
	364	{
	365	__raw_writel(reg_value, isp->mmio_base[isp_mmio_range] + reg_offset);
	366	}
	367
	368	/*
	369	* isp_reg_and - Clear individual bits in an OMAP3 ISP register
	370	* @dev: Device pointer specific to the OMAP3 ISP.
	371	* @mmio_range: Range to which the register offset refers to.
	372	* @reg: Register offset to work on.
	373	* @clr_bits: 32 bit value which would be cleared in the register.
	374	*/
	375	static inline
	376	void isp_reg_clr(struct isp_device *isp, enum isp_mem_resources mmio_range,
	377	u32 reg, u32 clr_bits)
	378	{
	379	u32 v = isp_reg_readl(isp, mmio_range, reg);
	380
	381	isp_reg_writel(isp, v & ~clr_bits, mmio_range, reg);
	382	}
383
384	/*
385	* isp_reg_set - Set individual bits in an OMAP3 ISP register
386	* @dev: Device pointer specific to the OMAP3 ISP.
387	* @mmio_range: Range to which the register offset refers to.
388	* @reg: Register offset to work on.
389	* @set_bits: 32 bit value which would be set in the register.
390	*/
391	static inline
392	void isp_reg_set(struct isp_device *isp, enum isp_mem_resources mmio_range,
393	u32 reg, u32 set_bits)
394	{
395	u32 v = isp_reg_readl(isp, mmio_range, reg);
396
397	isp_reg_writel(isp, v \| set_bits, mmio_range, reg);
398	}
399
400	/*
401	* isp_reg_clr_set - Clear and set invidial bits in an OMAP3 ISP register
402	* @dev: Device pointer specific to the OMAP3 ISP.
403	* @mmio_range: Range to which the register offset refers to.
404	* @reg: Register offset to work on.
405	* @clr_bits: 32 bit value which would be cleared in the register.
406	* @set_bits: 32 bit value which would be set in the register.
407	*
408	* The clear operation is done first, and then the set operation.
409	*/
410	static inline
411	void isp_reg_clr_set(struct isp_device *isp, enum isp_mem_resources mmio_range,
412	u32 reg, u32 clr_bits, u32 set_bits)
413	{
414	u32 v = isp_reg_readl(isp, mmio_range, reg);
415
416	isp_reg_writel(isp, (v & ~clr_bits) \| set_bits, mmio_range, reg);
417	}
418
419	static inline enum v4l2_buf_type
420	isp_pad_buffer_type(const struct v4l2_subdev *subdev, int pad)
421	{
422	if (pad >= subdev->entity.num_pads)
423	return 0;
424
425	if (subdev->entity.pads[pad].flags & MEDIA_PAD_FL_SINK)
426	return V4L2_BUF_TYPE_VIDEO_OUTPUT;
427	else
428	return V4L2_BUF_TYPE_VIDEO_CAPTURE;
429	}
430
431	#endif /* OMAP3_ISP_CORE_H */