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Merge branch 'topic/hda' into for-linus
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / media / video / omap3isp / isp.c
CommitLineData
448de7e7
SA		 1/*
2 * isp.c
3 *
4 * TI OMAP3 ISP - Core
5 *
6 * Copyright (C) 2006-2010 Nokia Corporation
7 * Copyright (C) 2007-2009 Texas Instruments, Inc.
8 *
9 * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10 * Sakari Ailus <sakari.ailus@iki.fi>
11 *
12 * Contributors:
13 * Laurent Pinchart <laurent.pinchart@ideasonboard.com>
14 * Sakari Ailus <sakari.ailus@iki.fi>
15 * David Cohen <dacohen@gmail.com>
16 * Stanimir Varbanov <svarbanov@mm-sol.com>
17 * Vimarsh Zutshi <vimarsh.zutshi@gmail.com>
18 * Tuukka Toivonen <tuukkat76@gmail.com>
19 * Sergio Aguirre <saaguirre@ti.com>
20 * Antti Koskipaa <akoskipa@gmail.com>
21 * Ivan T. Ivanov <iivanov@mm-sol.com>
22 * RaniSuneela <r-m@ti.com>
23 * Atanas Filipov <afilipov@mm-sol.com>
24 * Gjorgji Rosikopulos <grosikopulos@mm-sol.com>
25 * Hiroshi DOYU <hiroshi.doyu@nokia.com>
26 * Nayden Kanchev <nkanchev@mm-sol.com>
27 * Phil Carmody <ext-phil.2.carmody@nokia.com>
28 * Artem Bityutskiy <artem.bityutskiy@nokia.com>
29 * Dominic Curran <dcurran@ti.com>
30 * Ilkka Myllyperkio <ilkka.myllyperkio@sofica.fi>
31 * Pallavi Kulkarni <p-kulkarni@ti.com>
32 * Vaibhav Hiremath <hvaibhav@ti.com>
33 * Mohit Jalori <mjalori@ti.com>
34 * Sameer Venkatraman <sameerv@ti.com>
35 * Senthilvadivu Guruswamy <svadivu@ti.com>
36 * Thara Gopinath <thara@ti.com>
37 * Toni Leinonen <toni.leinonen@nokia.com>
38 * Troy Laramy <t-laramy@ti.com>
39 *
40 * This program is free software; you can redistribute it and/or modify
41 * it under the terms of the GNU General Public License version 2 as
42 * published by the Free Software Foundation.
43 *
44 * This program is distributed in the hope that it will be useful, but
45 * WITHOUT ANY WARRANTY; without even the implied warranty of
46 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
47 * General Public License for more details.
48 *
49 * You should have received a copy of the GNU General Public License
50 * along with this program; if not, write to the Free Software
51 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
52 * 02110-1301 USA
53 */
54
55#include <asm/cacheflush.h>
56
57#include <linux/clk.h>
58#include <linux/delay.h>
59#include <linux/device.h>
60#include <linux/dma-mapping.h>
61#include <linux/i2c.h>
62#include <linux/interrupt.h>
63#include <linux/module.h>
64#include <linux/platform_device.h>
65#include <linux/regulator/consumer.h>
66#include <linux/slab.h>
67#include <linux/sched.h>
68#include <linux/vmalloc.h>
69
70#include <media/v4l2-common.h>
71#include <media/v4l2-device.h>
72
73#include "isp.h"
74#include "ispreg.h"
75#include "ispccdc.h"
76#include "isppreview.h"
77#include "ispresizer.h"
78#include "ispcsi2.h"
79#include "ispccp2.h"
80#include "isph3a.h"
81#include "isphist.h"
82
83static unsigned int autoidle;
84module_param(autoidle, int, 0444);
85MODULE_PARM_DESC(autoidle, "Enable OMAP3ISP AUTOIDLE support");
86
87static void isp_save_ctx(struct isp_device *isp);
88
89static void isp_restore_ctx(struct isp_device *isp);
90
91static const struct isp_res_mapping isp_res_maps[] = {
92 {
93 .isp_rev = ISP_REVISION_2_0,
94 .map = 1 << OMAP3_ISP_IOMEM_MAIN |
95 1 << OMAP3_ISP_IOMEM_CCP2 |
96 1 << OMAP3_ISP_IOMEM_CCDC |
97 1 << OMAP3_ISP_IOMEM_HIST |
98 1 << OMAP3_ISP_IOMEM_H3A |
99 1 << OMAP3_ISP_IOMEM_PREV |
100 1 << OMAP3_ISP_IOMEM_RESZ |
101 1 << OMAP3_ISP_IOMEM_SBL |
102 1 << OMAP3_ISP_IOMEM_CSI2A_REGS1 |
103 1 << OMAP3_ISP_IOMEM_CSIPHY2,
104 },
105 {
106 .isp_rev = ISP_REVISION_15_0,
107 .map = 1 << OMAP3_ISP_IOMEM_MAIN |
108 1 << OMAP3_ISP_IOMEM_CCP2 |
109 1 << OMAP3_ISP_IOMEM_CCDC |
110 1 << OMAP3_ISP_IOMEM_HIST |
111 1 << OMAP3_ISP_IOMEM_H3A |
112 1 << OMAP3_ISP_IOMEM_PREV |
113 1 << OMAP3_ISP_IOMEM_RESZ |
114 1 << OMAP3_ISP_IOMEM_SBL |
115 1 << OMAP3_ISP_IOMEM_CSI2A_REGS1 |
116 1 << OMAP3_ISP_IOMEM_CSIPHY2 |
117 1 << OMAP3_ISP_IOMEM_CSI2A_REGS2 |
118 1 << OMAP3_ISP_IOMEM_CSI2C_REGS1 |
119 1 << OMAP3_ISP_IOMEM_CSIPHY1 |
120 1 << OMAP3_ISP_IOMEM_CSI2C_REGS2,
121 },
122};
123
124/* Structure for saving/restoring ISP module registers */
125static struct isp_reg isp_reg_list[] = {
126 {OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG, 0},
127 {OMAP3_ISP_IOMEM_MAIN, ISP_CTRL, 0},
128 {OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_CTRL, 0},
129 {0, ISP_TOK_TERM, 0}
130};
131
132/*
133 * omap3isp_flush - Post pending L3 bus writes by doing a register readback
134 * @isp: OMAP3 ISP device
135 *
136 * In order to force posting of pending writes, we need to write and
137 * readback the same register, in this case the revision register.
138 *
139 * See this link for reference:
140 * http://www.mail-archive.com/linux-omap@vger.kernel.org/msg08149.html
141 */
142void omap3isp_flush(struct isp_device *isp)
143{
144 isp_reg_writel(isp, 0, OMAP3_ISP_IOMEM_MAIN, ISP_REVISION);
145 isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_REVISION);
146}
147
148/*
149 * isp_enable_interrupts - Enable ISP interrupts.
150 * @isp: OMAP3 ISP device
151 */
152static void isp_enable_interrupts(struct isp_device *isp)
153{
154 static const u32 irq = IRQ0ENABLE_CSIA_IRQ
155 | IRQ0ENABLE_CSIB_IRQ
156 | IRQ0ENABLE_CCDC_LSC_PREF_ERR_IRQ
157 | IRQ0ENABLE_CCDC_LSC_DONE_IRQ
158 | IRQ0ENABLE_CCDC_VD0_IRQ
159 | IRQ0ENABLE_CCDC_VD1_IRQ
160 | IRQ0ENABLE_HS_VS_IRQ
161 | IRQ0ENABLE_HIST_DONE_IRQ
162 | IRQ0ENABLE_H3A_AWB_DONE_IRQ
163 | IRQ0ENABLE_H3A_AF_DONE_IRQ
164 | IRQ0ENABLE_PRV_DONE_IRQ
165 | IRQ0ENABLE_RSZ_DONE_IRQ;
166
167 isp_reg_writel(isp, irq, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
168 isp_reg_writel(isp, irq, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE);
169}
170
171/*
172 * isp_disable_interrupts - Disable ISP interrupts.
173 * @isp: OMAP3 ISP device
174 */
175static void isp_disable_interrupts(struct isp_device *isp)
176{
177 isp_reg_writel(isp, 0, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE);
178}
179
180/**
181 * isp_set_xclk - Configures the specified cam_xclk to the desired frequency.
182 * @isp: OMAP3 ISP device
183 * @xclk: Desired frequency of the clock in Hz. 0 = stable low, 1 is stable high
184 * @xclksel: XCLK to configure (0 = A, 1 = B).
185 *
186 * Configures the specified MCLK divisor in the ISP timing control register
187 * (TCTRL_CTRL) to generate the desired xclk clock value.
188 *
189 * Divisor = cam_mclk_hz / xclk
190 *
191 * Returns the final frequency that is actually being generated
192 **/
193static u32 isp_set_xclk(struct isp_device *isp, u32 xclk, u8 xclksel)
194{
195 u32 divisor;
196 u32 currentxclk;
197 unsigned long mclk_hz;
198
199 if (!omap3isp_get(isp))
200 return 0;
201
202 mclk_hz = clk_get_rate(isp->clock[ISP_CLK_CAM_MCLK]);
203
204 if (xclk >= mclk_hz) {
205 divisor = ISPTCTRL_CTRL_DIV_BYPASS;
206 currentxclk = mclk_hz;
207 } else if (xclk >= 2) {
208 divisor = mclk_hz / xclk;
209 if (divisor >= ISPTCTRL_CTRL_DIV_BYPASS)
210 divisor = ISPTCTRL_CTRL_DIV_BYPASS - 1;
211 currentxclk = mclk_hz / divisor;
212 } else {
213 divisor = xclk;
214 currentxclk = 0;
215 }
216
217 switch (xclksel) {
7c2c8f42 218 case ISP_XCLK_A:
448de7e7
SA		 219 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_CTRL,
220 ISPTCTRL_CTRL_DIVA_MASK,
221 divisor << ISPTCTRL_CTRL_DIVA_SHIFT);
222 dev_dbg(isp->dev, "isp_set_xclk(): cam_xclka set to %d Hz\n",
223 currentxclk);
224 break;
7c2c8f42 225 case ISP_XCLK_B:
448de7e7
SA		 226 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_CTRL,
227 ISPTCTRL_CTRL_DIVB_MASK,
228 divisor << ISPTCTRL_CTRL_DIVB_SHIFT);
229 dev_dbg(isp->dev, "isp_set_xclk(): cam_xclkb set to %d Hz\n",
230 currentxclk);
231 break;
7c2c8f42 232 case ISP_XCLK_NONE:
448de7e7
SA		 233 default:
234 omap3isp_put(isp);
235 dev_dbg(isp->dev, "ISP_ERR: isp_set_xclk(): Invalid requested "
236 "xclk. Must be 0 (A) or 1 (B).\n");
237 return -EINVAL;
238 }
239
240 /* Do we go from stable whatever to clock? */
7c2c8f42 241 if (divisor >= 2 && isp->xclk_divisor[xclksel - 1] < 2)
448de7e7
SA		 242 omap3isp_get(isp);
243 /* Stopping the clock. */
7c2c8f42 244 else if (divisor < 2 && isp->xclk_divisor[xclksel - 1] >= 2)
448de7e7
SA		 245 omap3isp_put(isp);
246
7c2c8f42 247 isp->xclk_divisor[xclksel - 1] = divisor;
448de7e7
SA		 248
249 omap3isp_put(isp);
250
251 return currentxclk;
252}
253
254/*
255 * isp_power_settings - Sysconfig settings, for Power Management.
256 * @isp: OMAP3 ISP device
257 * @idle: Consider idle state.
258 *
259 * Sets the power settings for the ISP, and SBL bus.
260 */
261static void isp_power_settings(struct isp_device *isp, int idle)
262{
263 isp_reg_writel(isp,
264 ((idle ? ISP_SYSCONFIG_MIDLEMODE_SMARTSTANDBY :
265 ISP_SYSCONFIG_MIDLEMODE_FORCESTANDBY) <<
266 ISP_SYSCONFIG_MIDLEMODE_SHIFT) |
267 ((isp->revision == ISP_REVISION_15_0) ?
268 ISP_SYSCONFIG_AUTOIDLE : 0),
269 OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG);
270
271 if (isp->autoidle)
272 isp_reg_writel(isp, ISPCTRL_SBL_AUTOIDLE, OMAP3_ISP_IOMEM_MAIN,
273 ISP_CTRL);
274}
275
276/*
277 * Configure the bridge and lane shifter. Valid inputs are
278 *
279 * CCDC_INPUT_PARALLEL: Parallel interface
280 * CCDC_INPUT_CSI2A: CSI2a receiver
281 * CCDC_INPUT_CCP2B: CCP2b receiver
282 * CCDC_INPUT_CSI2C: CSI2c receiver
283 *
284 * The bridge and lane shifter are configured according to the selected input
285 * and the ISP platform data.
286 */
287void omap3isp_configure_bridge(struct isp_device *isp,
288 enum ccdc_input_entity input,
c09af044
MJ		 289 const struct isp_parallel_platform_data *pdata,
290 unsigned int shift)
448de7e7
SA		 291{
292 u32 ispctrl_val;
293
294 ispctrl_val = isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL);
295 ispctrl_val &= ~ISPCTRL_SHIFT_MASK;
296 ispctrl_val &= ~ISPCTRL_PAR_CLK_POL_INV;
297 ispctrl_val &= ~ISPCTRL_PAR_SER_CLK_SEL_MASK;
298 ispctrl_val &= ~ISPCTRL_PAR_BRIDGE_MASK;
299
300 switch (input) {
301 case CCDC_INPUT_PARALLEL:
302 ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_PARALLEL;
448de7e7
SA		 303 ispctrl_val |= pdata->clk_pol << ISPCTRL_PAR_CLK_POL_SHIFT;
304 ispctrl_val |= pdata->bridge << ISPCTRL_PAR_BRIDGE_SHIFT;
c09af044 305 shift += pdata->data_lane_shift * 2;
448de7e7
SA		 306 break;
307
308 case CCDC_INPUT_CSI2A:
309 ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_CSIA;
310 break;
311
312 case CCDC_INPUT_CCP2B:
313 ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_CSIB;
314 break;
315
316 case CCDC_INPUT_CSI2C:
317 ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_CSIC;
318 break;
319
320 default:
321 return;
322 }
323
c09af044
MJ		 324 ispctrl_val |= ((shift/2) << ISPCTRL_SHIFT_SHIFT) & ISPCTRL_SHIFT_MASK;
325
448de7e7
SA		 326 ispctrl_val &= ~ISPCTRL_SYNC_DETECT_MASK;
327 ispctrl_val |= ISPCTRL_SYNC_DETECT_VSRISE;
328
329 isp_reg_writel(isp, ispctrl_val, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL);
330}
331
332/**
333 * isp_set_pixel_clock - Configures the ISP pixel clock
334 * @isp: OMAP3 ISP device
335 * @pixelclk: Average pixel clock in Hz
336 *
337 * Set the average pixel clock required by the sensor. The ISP will use the
338 * lowest possible memory bandwidth settings compatible with the clock.
339 **/
340static void isp_set_pixel_clock(struct isp_device *isp, unsigned int pixelclk)
341{
342 isp->isp_ccdc.vpcfg.pixelclk = pixelclk;
343}
344
345void omap3isp_hist_dma_done(struct isp_device *isp)
346{
347 if (omap3isp_ccdc_busy(&isp->isp_ccdc) ||
348 omap3isp_stat_pcr_busy(&isp->isp_hist)) {
349 /* Histogram cannot be enabled in this frame anymore */
350 atomic_set(&isp->isp_hist.buf_err, 1);
351 dev_dbg(isp->dev, "hist: Out of synchronization with "
352 "CCDC. Ignoring next buffer.\n");
353 }
354}
355
356static inline void isp_isr_dbg(struct isp_device *isp, u32 irqstatus)
357{
358 static const char *name[] = {
359 "CSIA_IRQ",
360 "res1",
361 "res2",
362 "CSIB_LCM_IRQ",
363 "CSIB_IRQ",
364 "res5",
365 "res6",
366 "res7",
367 "CCDC_VD0_IRQ",
368 "CCDC_VD1_IRQ",
369 "CCDC_VD2_IRQ",
370 "CCDC_ERR_IRQ",
371 "H3A_AF_DONE_IRQ",
372 "H3A_AWB_DONE_IRQ",
373 "res14",
374 "res15",
375 "HIST_DONE_IRQ",
376 "CCDC_LSC_DONE",
377 "CCDC_LSC_PREFETCH_COMPLETED",
378 "CCDC_LSC_PREFETCH_ERROR",
379 "PRV_DONE_IRQ",
380 "CBUFF_IRQ",
381 "res22",
382 "res23",
383 "RSZ_DONE_IRQ",
384 "OVF_IRQ",
385 "res26",
386 "res27",
387 "MMU_ERR_IRQ",
388 "OCP_ERR_IRQ",
389 "SEC_ERR_IRQ",
390 "HS_VS_IRQ",
391 };
392 int i;
393
394 dev_dbg(isp->dev, "");
395
396 for (i = 0; i < ARRAY_SIZE(name); i++) {
397 if ((1 << i) & irqstatus)
398 printk(KERN_CONT "%s ", name[i]);
399 }
400 printk(KERN_CONT "\n");
401}
402
403static void isp_isr_sbl(struct isp_device *isp)
404{
405 struct device *dev = isp->dev;
406 u32 sbl_pcr;
407
408 /*
409 * Handle shared buffer logic overflows for video buffers.
410 * ISPSBL_PCR_CCDCPRV_2_RSZ_OVF can be safely ignored.
411 */
412 sbl_pcr = isp_reg_readl(isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_PCR);
413 isp_reg_writel(isp, sbl_pcr, OMAP3_ISP_IOMEM_SBL, ISPSBL_PCR);
414 sbl_pcr &= ~ISPSBL_PCR_CCDCPRV_2_RSZ_OVF;
415
416 if (sbl_pcr)
417 dev_dbg(dev, "SBL overflow (PCR = 0x%08x)\n", sbl_pcr);
418
419 if (sbl_pcr & (ISPSBL_PCR_CCDC_WBL_OVF | ISPSBL_PCR_CSIA_WBL_OVF
420 | ISPSBL_PCR_CSIB_WBL_OVF)) {
421 isp->isp_ccdc.error = 1;
422 if (isp->isp_ccdc.output & CCDC_OUTPUT_PREVIEW)
423 isp->isp_prev.error = 1;
424 if (isp->isp_ccdc.output & CCDC_OUTPUT_RESIZER)
425 isp->isp_res.error = 1;
426 }
427
428 if (sbl_pcr & ISPSBL_PCR_PRV_WBL_OVF) {
429 isp->isp_prev.error = 1;
430 if (isp->isp_res.input == RESIZER_INPUT_VP &&
431 !(isp->isp_ccdc.output & CCDC_OUTPUT_RESIZER))
432 isp->isp_res.error = 1;
433 }
434
435 if (sbl_pcr & (ISPSBL_PCR_RSZ1_WBL_OVF
436 | ISPSBL_PCR_RSZ2_WBL_OVF
437 | ISPSBL_PCR_RSZ3_WBL_OVF
438 | ISPSBL_PCR_RSZ4_WBL_OVF))
439 isp->isp_res.error = 1;
440
441 if (sbl_pcr & ISPSBL_PCR_H3A_AF_WBL_OVF)
442 omap3isp_stat_sbl_overflow(&isp->isp_af);
443
444 if (sbl_pcr & ISPSBL_PCR_H3A_AEAWB_WBL_OVF)
445 omap3isp_stat_sbl_overflow(&isp->isp_aewb);
446}
447
448/*
449 * isp_isr - Interrupt Service Routine for Camera ISP module.
450 * @irq: Not used currently.
451 * @_isp: Pointer to the OMAP3 ISP device
452 *
453 * Handles the corresponding callback if plugged in.
454 *
455 * Returns IRQ_HANDLED when IRQ was correctly handled, or IRQ_NONE when the
456 * IRQ wasn't handled.
457 */
458static irqreturn_t isp_isr(int irq, void *_isp)
459{
460 static const u32 ccdc_events = IRQ0STATUS_CCDC_LSC_PREF_ERR_IRQ |
461 IRQ0STATUS_CCDC_LSC_DONE_IRQ |
462 IRQ0STATUS_CCDC_VD0_IRQ |
463 IRQ0STATUS_CCDC_VD1_IRQ |
464 IRQ0STATUS_HS_VS_IRQ;
465 struct isp_device *isp = _isp;
466 u32 irqstatus;
467 int ret;
468
469 irqstatus = isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
470 isp_reg_writel(isp, irqstatus, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
471
472 isp_isr_sbl(isp);
473
474 if (irqstatus & IRQ0STATUS_CSIA_IRQ) {
475 ret = omap3isp_csi2_isr(&isp->isp_csi2a);
476 if (ret)
477 isp->isp_ccdc.error = 1;
478 }
479
480 if (irqstatus & IRQ0STATUS_CSIB_IRQ) {
481 ret = omap3isp_ccp2_isr(&isp->isp_ccp2);
482 if (ret)
483 isp->isp_ccdc.error = 1;
484 }
485
486 if (irqstatus & IRQ0STATUS_CCDC_VD0_IRQ) {
487 if (isp->isp_ccdc.output & CCDC_OUTPUT_PREVIEW)
488 omap3isp_preview_isr_frame_sync(&isp->isp_prev);
489 if (isp->isp_ccdc.output & CCDC_OUTPUT_RESIZER)
490 omap3isp_resizer_isr_frame_sync(&isp->isp_res);
491 omap3isp_stat_isr_frame_sync(&isp->isp_aewb);
492 omap3isp_stat_isr_frame_sync(&isp->isp_af);
493 omap3isp_stat_isr_frame_sync(&isp->isp_hist);
494 }
495
496 if (irqstatus & ccdc_events)
497 omap3isp_ccdc_isr(&isp->isp_ccdc, irqstatus & ccdc_events);
498
499 if (irqstatus & IRQ0STATUS_PRV_DONE_IRQ) {
500 if (isp->isp_prev.output & PREVIEW_OUTPUT_RESIZER)
501 omap3isp_resizer_isr_frame_sync(&isp->isp_res);
502 omap3isp_preview_isr(&isp->isp_prev);
503 }
504
505 if (irqstatus & IRQ0STATUS_RSZ_DONE_IRQ)
506 omap3isp_resizer_isr(&isp->isp_res);
507
508 if (irqstatus & IRQ0STATUS_H3A_AWB_DONE_IRQ)
509 omap3isp_stat_isr(&isp->isp_aewb);
510
511 if (irqstatus & IRQ0STATUS_H3A_AF_DONE_IRQ)
512 omap3isp_stat_isr(&isp->isp_af);
513
514 if (irqstatus & IRQ0STATUS_HIST_DONE_IRQ)
515 omap3isp_stat_isr(&isp->isp_hist);
516
517 omap3isp_flush(isp);
518
519#if defined(DEBUG) && defined(ISP_ISR_DEBUG)
520 isp_isr_dbg(isp, irqstatus);
521#endif
522
523 return IRQ_HANDLED;
524}
525
526/* -----------------------------------------------------------------------------
527 * Pipeline power management
528 *
529 * Entities must be powered up when part of a pipeline that contains at least
530 * one open video device node.
531 *
532 * To achieve this use the entity use_count field to track the number of users.
533 * For entities corresponding to video device nodes the use_count field stores
534 * the users count of the node. For entities corresponding to subdevs the
535 * use_count field stores the total number of users of all video device nodes
536 * in the pipeline.
537 *
538 * The omap3isp_pipeline_pm_use() function must be called in the open() and
539 * close() handlers of video device nodes. It increments or decrements the use
540 * count of all subdev entities in the pipeline.
541 *
542 * To react to link management on powered pipelines, the link setup notification
543 * callback updates the use count of all entities in the source and sink sides
544 * of the link.
545 */
546
547/*
548 * isp_pipeline_pm_use_count - Count the number of users of a pipeline
549 * @entity: The entity
550 *
551 * Return the total number of users of all video device nodes in the pipeline.
552 */
553static int isp_pipeline_pm_use_count(struct media_entity *entity)
554{
555 struct media_entity_graph graph;
556 int use = 0;
557
558 media_entity_graph_walk_start(&graph, entity);
559
560 while ((entity = media_entity_graph_walk_next(&graph))) {
561 if (media_entity_type(entity) == MEDIA_ENT_T_DEVNODE)
562 use += entity->use_count;
563 }
564
565 return use;
566}
567
568/*
569 * isp_pipeline_pm_power_one - Apply power change to an entity
570 * @entity: The entity
571 * @change: Use count change
572 *
573 * Change the entity use count by @change. If the entity is a subdev update its
574 * power state by calling the core::s_power operation when the use count goes
575 * from 0 to != 0 or from != 0 to 0.
576 *
577 * Return 0 on success or a negative error code on failure.
578 */
579static int isp_pipeline_pm_power_one(struct media_entity *entity, int change)
580{
581 struct v4l2_subdev *subdev;
582 int ret;
583
584 subdev = media_entity_type(entity) == MEDIA_ENT_T_V4L2_SUBDEV
585 ? media_entity_to_v4l2_subdev(entity) : NULL;
586
587 if (entity->use_count == 0 && change > 0 && subdev != NULL) {
588 ret = v4l2_subdev_call(subdev, core, s_power, 1);
589 if (ret < 0 && ret != -ENOIOCTLCMD)
590 return ret;
591 }
592
593 entity->use_count += change;
594 WARN_ON(entity->use_count < 0);
595
596 if (entity->use_count == 0 && change < 0 && subdev != NULL)
597 v4l2_subdev_call(subdev, core, s_power, 0);
598
599 return 0;
600}
601
602/*
603 * isp_pipeline_pm_power - Apply power change to all entities in a pipeline
604 * @entity: The entity
605 * @change: Use count change
606 *
607 * Walk the pipeline to update the use count and the power state of all non-node
608 * entities.
609 *
610 * Return 0 on success or a negative error code on failure.
611 */
612static int isp_pipeline_pm_power(struct media_entity *entity, int change)
613{
614 struct media_entity_graph graph;
615 struct media_entity *first = entity;
616 int ret = 0;
617
618 if (!change)
619 return 0;
620
621 media_entity_graph_walk_start(&graph, entity);
622
623 while (!ret && (entity = media_entity_graph_walk_next(&graph)))
624 if (media_entity_type(entity) != MEDIA_ENT_T_DEVNODE)
625 ret = isp_pipeline_pm_power_one(entity, change);
626
627 if (!ret)
628 return 0;
629
630 media_entity_graph_walk_start(&graph, first);
631
632 while ((first = media_entity_graph_walk_next(&graph))
633 && first != entity)
634 if (media_entity_type(first) != MEDIA_ENT_T_DEVNODE)
635 isp_pipeline_pm_power_one(first, -change);
636
637 return ret;
638}
639
640/*
641 * omap3isp_pipeline_pm_use - Update the use count of an entity
642 * @entity: The entity
643 * @use: Use (1) or stop using (0) the entity
644 *
645 * Update the use count of all entities in the pipeline and power entities on or
646 * off accordingly.
647 *
648 * Return 0 on success or a negative error code on failure. Powering entities
649 * off is assumed to never fail. No failure can occur when the use parameter is
650 * set to 0.
651 */
652int omap3isp_pipeline_pm_use(struct media_entity *entity, int use)
653{
654 int change = use ? 1 : -1;
655 int ret;
656
657 mutex_lock(&entity->parent->graph_mutex);
658
659 /* Apply use count to node. */
660 entity->use_count += change;
661 WARN_ON(entity->use_count < 0);
662
663 /* Apply power change to connected non-nodes. */
664 ret = isp_pipeline_pm_power(entity, change);
e2241531
LP		 665 if (ret < 0)
666 entity->use_count -= change;
448de7e7
SA		 667
668 mutex_unlock(&entity->parent->graph_mutex);
669
670 return ret;
671}
672
673/*
674 * isp_pipeline_link_notify - Link management notification callback
675 * @source: Pad at the start of the link
676 * @sink: Pad at the end of the link
677 * @flags: New link flags that will be applied
678 *
679 * React to link management on powered pipelines by updating the use count of
680 * all entities in the source and sink sides of the link. Entities are powered
681 * on or off accordingly.
682 *
683 * Return 0 on success or a negative error code on failure. Powering entities
684 * off is assumed to never fail. This function will not fail for disconnection
685 * events.
686 */
687static int isp_pipeline_link_notify(struct media_pad *source,
688 struct media_pad *sink, u32 flags)
689{
690 int source_use = isp_pipeline_pm_use_count(source->entity);
691 int sink_use = isp_pipeline_pm_use_count(sink->entity);
692 int ret;
693
694 if (!(flags & MEDIA_LNK_FL_ENABLED)) {
695 /* Powering off entities is assumed to never fail. */
696 isp_pipeline_pm_power(source->entity, -sink_use);
697 isp_pipeline_pm_power(sink->entity, -source_use);
698 return 0;
699 }
700
701 ret = isp_pipeline_pm_power(source->entity, sink_use);
702 if (ret < 0)
703 return ret;
704
705 ret = isp_pipeline_pm_power(sink->entity, source_use);
706 if (ret < 0)
707 isp_pipeline_pm_power(source->entity, -sink_use);
708
709 return ret;
710}
711
712/* -----------------------------------------------------------------------------
713 * Pipeline stream management
714 */
715
716/*
717 * isp_pipeline_enable - Enable streaming on a pipeline
718 * @pipe: ISP pipeline
719 * @mode: Stream mode (single shot or continuous)
720 *
721 * Walk the entities chain starting at the pipeline output video node and start
722 * all modules in the chain in the given mode.
723 *
25985edc 724 * Return 0 if successful, or the return value of the failed video::s_stream
448de7e7
SA		 725 * operation otherwise.
726 */
727static int isp_pipeline_enable(struct isp_pipeline *pipe,
728 enum isp_pipeline_stream_state mode)
729{
730 struct isp_device *isp = pipe->output->isp;
731 struct media_entity *entity;
732 struct media_pad *pad;
733 struct v4l2_subdev *subdev;
734 unsigned long flags;
735 int ret = 0;
736
737 spin_lock_irqsave(&pipe->lock, flags);
738 pipe->state &= ~(ISP_PIPELINE_IDLE_INPUT | ISP_PIPELINE_IDLE_OUTPUT);
739 spin_unlock_irqrestore(&pipe->lock, flags);
740
741 pipe->do_propagation = false;
742
743 entity = &pipe->output->video.entity;
744 while (1) {
745 pad = &entity->pads[0];
746 if (!(pad->flags & MEDIA_PAD_FL_SINK))
747 break;
748
749 pad = media_entity_remote_source(pad);
750 if (pad == NULL ||
751 media_entity_type(pad->entity) != MEDIA_ENT_T_V4L2_SUBDEV)
752 break;
753
754 entity = pad->entity;
755 subdev = media_entity_to_v4l2_subdev(entity);
756
757 ret = v4l2_subdev_call(subdev, video, s_stream, mode);
758 if (ret < 0 && ret != -ENOIOCTLCMD)
759 break;
760
761 if (subdev == &isp->isp_ccdc.subdev) {
762 v4l2_subdev_call(&isp->isp_aewb.subdev, video,
763 s_stream, mode);
764 v4l2_subdev_call(&isp->isp_af.subdev, video,
765 s_stream, mode);
766 v4l2_subdev_call(&isp->isp_hist.subdev, video,
767 s_stream, mode);
768 pipe->do_propagation = true;
769 }
770 }
771
772 /* Frame number propagation. In continuous streaming mode the number
773 * is incremented in the frame start ISR. In mem-to-mem mode
774 * singleshot is used and frame start IRQs are not available.
775 * Thus we have to increment the number here.
776 */
777 if (pipe->do_propagation && mode == ISP_PIPELINE_STREAM_SINGLESHOT)
778 atomic_inc(&pipe->frame_number);
779
780 return ret;
781}
782
783static int isp_pipeline_wait_resizer(struct isp_device *isp)
784{
785 return omap3isp_resizer_busy(&isp->isp_res);
786}
787
788static int isp_pipeline_wait_preview(struct isp_device *isp)
789{
790 return omap3isp_preview_busy(&isp->isp_prev);
791}
792
793static int isp_pipeline_wait_ccdc(struct isp_device *isp)
794{
795 return omap3isp_stat_busy(&isp->isp_af)
796 || omap3isp_stat_busy(&isp->isp_aewb)
797 || omap3isp_stat_busy(&isp->isp_hist)
798 || omap3isp_ccdc_busy(&isp->isp_ccdc);
799}
800
801#define ISP_STOP_TIMEOUT msecs_to_jiffies(1000)
802
803static int isp_pipeline_wait(struct isp_device *isp,
804 int(*busy)(struct isp_device *isp))
805{
806 unsigned long timeout = jiffies + ISP_STOP_TIMEOUT;
807
808 while (!time_after(jiffies, timeout)) {
809 if (!busy(isp))
810 return 0;
811 }
812
813 return 1;
814}
815
816/*
817 * isp_pipeline_disable - Disable streaming on a pipeline
818 * @pipe: ISP pipeline
819 *
820 * Walk the entities chain starting at the pipeline output video node and stop
821 * all modules in the chain. Wait synchronously for the modules to be stopped if
822 * necessary.
823 *
824 * Return 0 if all modules have been properly stopped, or -ETIMEDOUT if a module
825 * can't be stopped (in which case a software reset of the ISP is probably
826 * necessary).
827 */
828static int isp_pipeline_disable(struct isp_pipeline *pipe)
829{
830 struct isp_device *isp = pipe->output->isp;
831 struct media_entity *entity;
832 struct media_pad *pad;
833 struct v4l2_subdev *subdev;
834 int failure = 0;
835 int ret;
836
837 /*
838 * We need to stop all the modules after CCDC first or they'll
839 * never stop since they may not get a full frame from CCDC.
840 */
841 entity = &pipe->output->video.entity;
842 while (1) {
843 pad = &entity->pads[0];
844 if (!(pad->flags & MEDIA_PAD_FL_SINK))
845 break;
846
847 pad = media_entity_remote_source(pad);
848 if (pad == NULL ||
849 media_entity_type(pad->entity) != MEDIA_ENT_T_V4L2_SUBDEV)
850 break;
851
852 entity = pad->entity;
853 subdev = media_entity_to_v4l2_subdev(entity);
854
855 if (subdev == &isp->isp_ccdc.subdev) {
856 v4l2_subdev_call(&isp->isp_aewb.subdev,
857 video, s_stream, 0);
858 v4l2_subdev_call(&isp->isp_af.subdev,
859 video, s_stream, 0);
860 v4l2_subdev_call(&isp->isp_hist.subdev,
861 video, s_stream, 0);
862 }
863
864 v4l2_subdev_call(subdev, video, s_stream, 0);
865
866 if (subdev == &isp->isp_res.subdev)
867 ret = isp_pipeline_wait(isp, isp_pipeline_wait_resizer);
868 else if (subdev == &isp->isp_prev.subdev)
869 ret = isp_pipeline_wait(isp, isp_pipeline_wait_preview);
870 else if (subdev == &isp->isp_ccdc.subdev)
871 ret = isp_pipeline_wait(isp, isp_pipeline_wait_ccdc);
872 else
873 ret = 0;
874
875 if (ret) {
876 dev_info(isp->dev, "Unable to stop %s\n", subdev->name);
877 failure = -ETIMEDOUT;
878 }
879 }
880
994d5375
LP		 881 if (failure < 0)
882 isp->needs_reset = true;
883
448de7e7
SA		 884 return failure;
885}
886
887/*
888 * omap3isp_pipeline_set_stream - Enable/disable streaming on a pipeline
889 * @pipe: ISP pipeline
890 * @state: Stream state (stopped, single shot or continuous)
891 *
892 * Set the pipeline to the given stream state. Pipelines can be started in
893 * single-shot or continuous mode.
894 *
25985edc 895 * Return 0 if successful, or the return value of the failed video::s_stream
994d5375
LP		 896 * operation otherwise. The pipeline state is not updated when the operation
897 * fails, except when stopping the pipeline.
448de7e7
SA		 898 */
899int omap3isp_pipeline_set_stream(struct isp_pipeline *pipe,
900 enum isp_pipeline_stream_state state)
901{
902 int ret;
903
904 if (state == ISP_PIPELINE_STREAM_STOPPED)
905 ret = isp_pipeline_disable(pipe);
906 else
907 ret = isp_pipeline_enable(pipe, state);
994d5375
LP		 908
909 if (ret == 0 || state == ISP_PIPELINE_STREAM_STOPPED)
910 pipe->stream_state = state;
448de7e7
SA		 911
912 return ret;
913}
914
915/*
916 * isp_pipeline_resume - Resume streaming on a pipeline
917 * @pipe: ISP pipeline
918 *
919 * Resume video output and input and re-enable pipeline.
920 */
921static void isp_pipeline_resume(struct isp_pipeline *pipe)
922{
923 int singleshot = pipe->stream_state == ISP_PIPELINE_STREAM_SINGLESHOT;
924
925 omap3isp_video_resume(pipe->output, !singleshot);
926 if (singleshot)
927 omap3isp_video_resume(pipe->input, 0);
928 isp_pipeline_enable(pipe, pipe->stream_state);
929}
930
931/*
932 * isp_pipeline_suspend - Suspend streaming on a pipeline
933 * @pipe: ISP pipeline
934 *
935 * Suspend pipeline.
936 */
937static void isp_pipeline_suspend(struct isp_pipeline *pipe)
938{
939 isp_pipeline_disable(pipe);
940}
941
942/*
943 * isp_pipeline_is_last - Verify if entity has an enabled link to the output
944 * video node
945 * @me: ISP module's media entity
946 *
947 * Returns 1 if the entity has an enabled link to the output video node or 0
948 * otherwise. It's true only while pipeline can have no more than one output
949 * node.
950 */
951static int isp_pipeline_is_last(struct media_entity *me)
952{
953 struct isp_pipeline *pipe;
954 struct media_pad *pad;
955
956 if (!me->pipe)
957 return 0;
958 pipe = to_isp_pipeline(me);
959 if (pipe->stream_state == ISP_PIPELINE_STREAM_STOPPED)
960 return 0;
961 pad = media_entity_remote_source(&pipe->output->pad);
962 return pad->entity == me;
963}
964
965/*
966 * isp_suspend_module_pipeline - Suspend pipeline to which belongs the module
967 * @me: ISP module's media entity
968 *
969 * Suspend the whole pipeline if module's entity has an enabled link to the
970 * output video node. It works only while pipeline can have no more than one
971 * output node.
972 */
973static void isp_suspend_module_pipeline(struct media_entity *me)
974{
975 if (isp_pipeline_is_last(me))
976 isp_pipeline_suspend(to_isp_pipeline(me));
977}
978
979/*
980 * isp_resume_module_pipeline - Resume pipeline to which belongs the module
981 * @me: ISP module's media entity
982 *
983 * Resume the whole pipeline if module's entity has an enabled link to the
984 * output video node. It works only while pipeline can have no more than one
985 * output node.
986 */
987static void isp_resume_module_pipeline(struct media_entity *me)
988{
989 if (isp_pipeline_is_last(me))
990 isp_pipeline_resume(to_isp_pipeline(me));
991}
992
993/*
994 * isp_suspend_modules - Suspend ISP submodules.
995 * @isp: OMAP3 ISP device
996 *
997 * Returns 0 if suspend left in idle state all the submodules properly,
998 * or returns 1 if a general Reset is required to suspend the submodules.
999 */
1000static int isp_suspend_modules(struct isp_device *isp)
1001{
1002 unsigned long timeout;
1003
1004 omap3isp_stat_suspend(&isp->isp_aewb);
1005 omap3isp_stat_suspend(&isp->isp_af);
1006 omap3isp_stat_suspend(&isp->isp_hist);
1007 isp_suspend_module_pipeline(&isp->isp_res.subdev.entity);
1008 isp_suspend_module_pipeline(&isp->isp_prev.subdev.entity);
1009 isp_suspend_module_pipeline(&isp->isp_ccdc.subdev.entity);
1010 isp_suspend_module_pipeline(&isp->isp_csi2a.subdev.entity);
1011 isp_suspend_module_pipeline(&isp->isp_ccp2.subdev.entity);
1012
1013 timeout = jiffies + ISP_STOP_TIMEOUT;
1014 while (omap3isp_stat_busy(&isp->isp_af)
1015 || omap3isp_stat_busy(&isp->isp_aewb)
1016 || omap3isp_stat_busy(&isp->isp_hist)
1017 || omap3isp_preview_busy(&isp->isp_prev)
1018 || omap3isp_resizer_busy(&isp->isp_res)
1019 || omap3isp_ccdc_busy(&isp->isp_ccdc)) {
1020 if (time_after(jiffies, timeout)) {
1021 dev_info(isp->dev, "can't stop modules.\n");
1022 return 1;
1023 }
1024 msleep(1);
1025 }
1026
1027 return 0;
1028}
1029
1030/*
1031 * isp_resume_modules - Resume ISP submodules.
1032 * @isp: OMAP3 ISP device
1033 */
1034static void isp_resume_modules(struct isp_device *isp)
1035{
1036 omap3isp_stat_resume(&isp->isp_aewb);
1037 omap3isp_stat_resume(&isp->isp_af);
1038 omap3isp_stat_resume(&isp->isp_hist);
1039 isp_resume_module_pipeline(&isp->isp_res.subdev.entity);
1040 isp_resume_module_pipeline(&isp->isp_prev.subdev.entity);
1041 isp_resume_module_pipeline(&isp->isp_ccdc.subdev.entity);
1042 isp_resume_module_pipeline(&isp->isp_csi2a.subdev.entity);
1043 isp_resume_module_pipeline(&isp->isp_ccp2.subdev.entity);
1044}
1045
1046/*
1047 * isp_reset - Reset ISP with a timeout wait for idle.
1048 * @isp: OMAP3 ISP device
1049 */
1050static int isp_reset(struct isp_device *isp)
1051{
1052 unsigned long timeout = 0;
1053
1054 isp_reg_writel(isp,
1055 isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG)
1056 | ISP_SYSCONFIG_SOFTRESET,
1057 OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG);
1058 while (!(isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN,
1059 ISP_SYSSTATUS) & 0x1)) {
1060 if (timeout++ > 10000) {
1061 dev_alert(isp->dev, "cannot reset ISP\n");
1062 return -ETIMEDOUT;
1063 }
1064 udelay(1);
1065 }
1066
1067 return 0;
1068}
1069
1070/*
1071 * isp_save_context - Saves the values of the ISP module registers.
1072 * @isp: OMAP3 ISP device
1073 * @reg_list: Structure containing pairs of register address and value to
1074 * modify on OMAP.
1075 */
1076static void
1077isp_save_context(struct isp_device *isp, struct isp_reg *reg_list)
1078{
1079 struct isp_reg *next = reg_list;
1080
1081 for (; next->reg != ISP_TOK_TERM; next++)
1082 next->val = isp_reg_readl(isp, next->mmio_range, next->reg);
1083}
1084
1085/*
1086 * isp_restore_context - Restores the values of the ISP module registers.
1087 * @isp: OMAP3 ISP device
1088 * @reg_list: Structure containing pairs of register address and value to
1089 * modify on OMAP.
1090 */
1091static void
1092isp_restore_context(struct isp_device *isp, struct isp_reg *reg_list)
1093{
1094 struct isp_reg *next = reg_list;
1095
1096 for (; next->reg != ISP_TOK_TERM; next++)
1097 isp_reg_writel(isp, next->val, next->mmio_range, next->reg);
1098}
1099
1100/*
1101 * isp_save_ctx - Saves ISP, CCDC, HIST, H3A, PREV, RESZ & MMU context.
1102 * @isp: OMAP3 ISP device
1103 *
1104 * Routine for saving the context of each module in the ISP.
1105 * CCDC, HIST, H3A, PREV, RESZ and MMU.
1106 */
1107static void isp_save_ctx(struct isp_device *isp)
1108{
1109 isp_save_context(isp, isp_reg_list);
1110 if (isp->iommu)
1111 iommu_save_ctx(isp->iommu);
1112}
1113
1114/*
1115 * isp_restore_ctx - Restores ISP, CCDC, HIST, H3A, PREV, RESZ & MMU context.
1116 * @isp: OMAP3 ISP device
1117 *
1118 * Routine for restoring the context of each module in the ISP.
1119 * CCDC, HIST, H3A, PREV, RESZ and MMU.
1120 */
1121static void isp_restore_ctx(struct isp_device *isp)
1122{
1123 isp_restore_context(isp, isp_reg_list);
1124 if (isp->iommu)
1125 iommu_restore_ctx(isp->iommu);
1126 omap3isp_ccdc_restore_context(isp);
1127 omap3isp_preview_restore_context(isp);
1128}
1129
1130/* -----------------------------------------------------------------------------
1131 * SBL resources management
1132 */
1133#define OMAP3_ISP_SBL_READ (OMAP3_ISP_SBL_CSI1_READ | \
1134 OMAP3_ISP_SBL_CCDC_LSC_READ | \
1135 OMAP3_ISP_SBL_PREVIEW_READ | \
1136 OMAP3_ISP_SBL_RESIZER_READ)
1137#define OMAP3_ISP_SBL_WRITE (OMAP3_ISP_SBL_CSI1_WRITE | \
1138 OMAP3_ISP_SBL_CSI2A_WRITE | \
1139 OMAP3_ISP_SBL_CSI2C_WRITE | \
1140 OMAP3_ISP_SBL_CCDC_WRITE | \
1141 OMAP3_ISP_SBL_PREVIEW_WRITE)
1142
1143void omap3isp_sbl_enable(struct isp_device *isp, enum isp_sbl_resource res)
1144{
1145 u32 sbl = 0;
1146
1147 isp->sbl_resources |= res;
1148
1149 if (isp->sbl_resources & OMAP3_ISP_SBL_CSI1_READ)
1150 sbl |= ISPCTRL_SBL_SHARED_RPORTA;
1151
1152 if (isp->sbl_resources & OMAP3_ISP_SBL_CCDC_LSC_READ)
1153 sbl |= ISPCTRL_SBL_SHARED_RPORTB;
1154
1155 if (isp->sbl_resources & OMAP3_ISP_SBL_CSI2C_WRITE)
1156 sbl |= ISPCTRL_SBL_SHARED_WPORTC;
1157
1158 if (isp->sbl_resources & OMAP3_ISP_SBL_RESIZER_WRITE)
1159 sbl |= ISPCTRL_SBL_WR0_RAM_EN;
1160
1161 if (isp->sbl_resources & OMAP3_ISP_SBL_WRITE)
1162 sbl |= ISPCTRL_SBL_WR1_RAM_EN;
1163
1164 if (isp->sbl_resources & OMAP3_ISP_SBL_READ)
1165 sbl |= ISPCTRL_SBL_RD_RAM_EN;
1166
1167 isp_reg_set(isp, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL, sbl);
1168}
1169
1170void omap3isp_sbl_disable(struct isp_device *isp, enum isp_sbl_resource res)
1171{
1172 u32 sbl = 0;
1173
1174 isp->sbl_resources &= ~res;
1175
1176 if (!(isp->sbl_resources & OMAP3_ISP_SBL_CSI1_READ))
1177 sbl |= ISPCTRL_SBL_SHARED_RPORTA;
1178
1179 if (!(isp->sbl_resources & OMAP3_ISP_SBL_CCDC_LSC_READ))
1180 sbl |= ISPCTRL_SBL_SHARED_RPORTB;
1181
1182 if (!(isp->sbl_resources & OMAP3_ISP_SBL_CSI2C_WRITE))
1183 sbl |= ISPCTRL_SBL_SHARED_WPORTC;
1184
1185 if (!(isp->sbl_resources & OMAP3_ISP_SBL_RESIZER_WRITE))
1186 sbl |= ISPCTRL_SBL_WR0_RAM_EN;
1187
1188 if (!(isp->sbl_resources & OMAP3_ISP_SBL_WRITE))
1189 sbl |= ISPCTRL_SBL_WR1_RAM_EN;
1190
1191 if (!(isp->sbl_resources & OMAP3_ISP_SBL_READ))
1192 sbl |= ISPCTRL_SBL_RD_RAM_EN;
1193
1194 isp_reg_clr(isp, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL, sbl);
1195}
1196
1197/*
1198 * isp_module_sync_idle - Helper to sync module with its idle state
1199 * @me: ISP submodule's media entity
1200 * @wait: ISP submodule's wait queue for streamoff/interrupt synchronization
1201 * @stopping: flag which tells module wants to stop
1202 *
1203 * This function checks if ISP submodule needs to wait for next interrupt. If
1204 * yes, makes the caller to sleep while waiting for such event.
1205 */
1206int omap3isp_module_sync_idle(struct media_entity *me, wait_queue_head_t *wait,
1207 atomic_t *stopping)
1208{
1209 struct isp_pipeline *pipe = to_isp_pipeline(me);
1210
1211 if (pipe->stream_state == ISP_PIPELINE_STREAM_STOPPED ||
1212 (pipe->stream_state == ISP_PIPELINE_STREAM_SINGLESHOT &&
1213 !isp_pipeline_ready(pipe)))
1214 return 0;
1215
1216 /*
1217 * atomic_set() doesn't include memory barrier on ARM platform for SMP
1218 * scenario. We'll call it here to avoid race conditions.
1219 */
1220 atomic_set(stopping, 1);
1221 smp_mb();
1222
1223 /*
1224 * If module is the last one, it's writing to memory. In this case,
1225 * it's necessary to check if the module is already paused due to
1226 * DMA queue underrun or if it has to wait for next interrupt to be
1227 * idle.
1228 * If it isn't the last one, the function won't sleep but *stopping
1229 * will still be set to warn next submodule caller's interrupt the
1230 * module wants to be idle.
1231 */
1232 if (isp_pipeline_is_last(me)) {
1233 struct isp_video *video = pipe->output;
1234 unsigned long flags;
1235 spin_lock_irqsave(&video->queue->irqlock, flags);
1236 if (video->dmaqueue_flags & ISP_VIDEO_DMAQUEUE_UNDERRUN) {
1237 spin_unlock_irqrestore(&video->queue->irqlock, flags);
1238 atomic_set(stopping, 0);
1239 smp_mb();
1240 return 0;
1241 }
1242 spin_unlock_irqrestore(&video->queue->irqlock, flags);
1243 if (!wait_event_timeout(*wait, !atomic_read(stopping),
1244 msecs_to_jiffies(1000))) {
1245 atomic_set(stopping, 0);
1246 smp_mb();
1247 return -ETIMEDOUT;
1248 }
1249 }
1250
1251 return 0;
1252}
1253
1254/*
1255 * omap3isp_module_sync_is_stopped - Helper to verify if module was stopping
1256 * @wait: ISP submodule's wait queue for streamoff/interrupt synchronization
1257 * @stopping: flag which tells module wants to stop
1258 *
1259 * This function checks if ISP submodule was stopping. In case of yes, it
1260 * notices the caller by setting stopping to 0 and waking up the wait queue.
1261 * Returns 1 if it was stopping or 0 otherwise.
1262 */
1263int omap3isp_module_sync_is_stopping(wait_queue_head_t *wait,
1264 atomic_t *stopping)
1265{
1266 if (atomic_cmpxchg(stopping, 1, 0)) {
1267 wake_up(wait);
1268 return 1;
1269 }
1270
1271 return 0;
1272}
1273
1274/* --------------------------------------------------------------------------
1275 * Clock management
1276 */
1277
1278#define ISPCTRL_CLKS_MASK (ISPCTRL_H3A_CLK_EN | \
1279 ISPCTRL_HIST_CLK_EN | \
1280 ISPCTRL_RSZ_CLK_EN | \
1281 (ISPCTRL_CCDC_CLK_EN | ISPCTRL_CCDC_RAM_EN) | \
1282 (ISPCTRL_PREV_CLK_EN | ISPCTRL_PREV_RAM_EN))
1283
1284static void __isp_subclk_update(struct isp_device *isp)
1285{
1286 u32 clk = 0;
1287
1288 if (isp->subclk_resources & OMAP3_ISP_SUBCLK_H3A)
1289 clk |= ISPCTRL_H3A_CLK_EN;
1290
1291 if (isp->subclk_resources & OMAP3_ISP_SUBCLK_HIST)
1292 clk |= ISPCTRL_HIST_CLK_EN;
1293
1294 if (isp->subclk_resources & OMAP3_ISP_SUBCLK_RESIZER)
1295 clk |= ISPCTRL_RSZ_CLK_EN;
1296
1297 /* NOTE: For CCDC & Preview submodules, we need to affect internal
25985edc 1298 * RAM as well.
448de7e7
SA		 1299 */
1300 if (isp->subclk_resources & OMAP3_ISP_SUBCLK_CCDC)
1301 clk |= ISPCTRL_CCDC_CLK_EN | ISPCTRL_CCDC_RAM_EN;
1302
1303 if (isp->subclk_resources & OMAP3_ISP_SUBCLK_PREVIEW)
1304 clk |= ISPCTRL_PREV_CLK_EN | ISPCTRL_PREV_RAM_EN;
1305
1306 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL,
1307 ISPCTRL_CLKS_MASK, clk);
1308}
1309
1310void omap3isp_subclk_enable(struct isp_device *isp,
1311 enum isp_subclk_resource res)
1312{
1313 isp->subclk_resources |= res;
1314
1315 __isp_subclk_update(isp);
1316}
1317
1318void omap3isp_subclk_disable(struct isp_device *isp,
1319 enum isp_subclk_resource res)
1320{
1321 isp->subclk_resources &= ~res;
1322
1323 __isp_subclk_update(isp);
1324}
1325
1326/*
1327 * isp_enable_clocks - Enable ISP clocks
1328 * @isp: OMAP3 ISP device
1329 *
1330 * Return 0 if successful, or clk_enable return value if any of tthem fails.
1331 */
1332static int isp_enable_clocks(struct isp_device *isp)
1333{
1334 int r;
1335 unsigned long rate;
1336 int divisor;
1337
1338 /*
1339 * cam_mclk clock chain:
1340 * dpll4 -> dpll4_m5 -> dpll4_m5x2 -> cam_mclk
1341 *
1342 * In OMAP3630 dpll4_m5x2 != 2 x dpll4_m5 but both are
1343 * set to the same value. Hence the rate set for dpll4_m5
1344 * has to be twice of what is set on OMAP3430 to get
1345 * the required value for cam_mclk
1346 */
1347 if (cpu_is_omap3630())
1348 divisor = 1;
1349 else
1350 divisor = 2;
1351
1352 r = clk_enable(isp->clock[ISP_CLK_CAM_ICK]);
1353 if (r) {
1354 dev_err(isp->dev, "clk_enable cam_ick failed\n");
1355 goto out_clk_enable_ick;
1356 }
1357 r = clk_set_rate(isp->clock[ISP_CLK_DPLL4_M5_CK],
1358 CM_CAM_MCLK_HZ/divisor);
1359 if (r) {
1360 dev_err(isp->dev, "clk_set_rate for dpll4_m5_ck failed\n");
1361 goto out_clk_enable_mclk;
1362 }
1363 r = clk_enable(isp->clock[ISP_CLK_CAM_MCLK]);
1364 if (r) {
1365 dev_err(isp->dev, "clk_enable cam_mclk failed\n");
1366 goto out_clk_enable_mclk;
1367 }
1368 rate = clk_get_rate(isp->clock[ISP_CLK_CAM_MCLK]);
1369 if (rate != CM_CAM_MCLK_HZ)
1370 dev_warn(isp->dev, "unexpected cam_mclk rate:\n"
1371 " expected : %d\n"
1372 " actual : %ld\n", CM_CAM_MCLK_HZ, rate);
1373 r = clk_enable(isp->clock[ISP_CLK_CSI2_FCK]);
1374 if (r) {
1375 dev_err(isp->dev, "clk_enable csi2_fck failed\n");
1376 goto out_clk_enable_csi2_fclk;
1377 }
1378 return 0;
1379
1380out_clk_enable_csi2_fclk:
1381 clk_disable(isp->clock[ISP_CLK_CAM_MCLK]);
1382out_clk_enable_mclk:
1383 clk_disable(isp->clock[ISP_CLK_CAM_ICK]);
1384out_clk_enable_ick:
1385 return r;
1386}
1387
1388/*
1389 * isp_disable_clocks - Disable ISP clocks
1390 * @isp: OMAP3 ISP device
1391 */
1392static void isp_disable_clocks(struct isp_device *isp)
1393{
1394 clk_disable(isp->clock[ISP_CLK_CAM_ICK]);
1395 clk_disable(isp->clock[ISP_CLK_CAM_MCLK]);
1396 clk_disable(isp->clock[ISP_CLK_CSI2_FCK]);
1397}
1398
1399static const char *isp_clocks[] = {
1400 "cam_ick",
1401 "cam_mclk",
1402 "dpll4_m5_ck",
1403 "csi2_96m_fck",
1404 "l3_ick",
1405};
1406
1407static void isp_put_clocks(struct isp_device *isp)
1408{
1409 unsigned int i;
1410
1411 for (i = 0; i < ARRAY_SIZE(isp_clocks); ++i) {
1412 if (isp->clock[i]) {
1413 clk_put(isp->clock[i]);
1414 isp->clock[i] = NULL;
1415 }
1416 }
1417}
1418
1419static int isp_get_clocks(struct isp_device *isp)
1420{
1421 struct clk *clk;
1422 unsigned int i;
1423
1424 for (i = 0; i < ARRAY_SIZE(isp_clocks); ++i) {
1425 clk = clk_get(isp->dev, isp_clocks[i]);
1426 if (IS_ERR(clk)) {
1427 dev_err(isp->dev, "clk_get %s failed\n", isp_clocks[i]);
1428 isp_put_clocks(isp);
1429 return PTR_ERR(clk);
1430 }
1431
1432 isp->clock[i] = clk;
1433 }
1434
1435 return 0;
1436}
1437
1438/*
1439 * omap3isp_get - Acquire the ISP resource.
1440 *
1441 * Initializes the clocks for the first acquire.
1442 *
1443 * Increment the reference count on the ISP. If the first reference is taken,
1444 * enable clocks and power-up all submodules.
1445 *
25985edc 1446 * Return a pointer to the ISP device structure, or NULL if an error occurred.
448de7e7
SA		 1447 */
1448struct isp_device *omap3isp_get(struct isp_device *isp)
1449{
1450 struct isp_device *__isp = isp;
1451
1452 if (isp == NULL)
1453 return NULL;
1454
1455 mutex_lock(&isp->isp_mutex);
1456 if (isp->ref_count > 0)
1457 goto out;
1458
1459 if (isp_enable_clocks(isp) < 0) {
1460 __isp = NULL;
1461 goto out;
1462 }
1463
1464 /* We don't want to restore context before saving it! */
1465 if (isp->has_context)
1466 isp_restore_ctx(isp);
1467 else
1468 isp->has_context = 1;
1469
1470 isp_enable_interrupts(isp);
1471
1472out:
1473 if (__isp != NULL)
1474 isp->ref_count++;
1475 mutex_unlock(&isp->isp_mutex);
1476
1477 return __isp;
1478}
1479
1480/*
1481 * omap3isp_put - Release the ISP
1482 *
1483 * Decrement the reference count on the ISP. If the last reference is released,
1484 * power-down all submodules, disable clocks and free temporary buffers.
1485 */
1486void omap3isp_put(struct isp_device *isp)
1487{
1488 if (isp == NULL)
1489 return;
1490
1491 mutex_lock(&isp->isp_mutex);
1492 BUG_ON(isp->ref_count == 0);
1493 if (--isp->ref_count == 0) {
1494 isp_disable_interrupts(isp);
1495 isp_save_ctx(isp);
994d5375
LP		 1496 if (isp->needs_reset) {
1497 isp_reset(isp);
1498 isp->needs_reset = false;
1499 }
448de7e7
SA		 1500 isp_disable_clocks(isp);
1501 }
1502 mutex_unlock(&isp->isp_mutex);
1503}
1504
1505/* --------------------------------------------------------------------------
1506 * Platform device driver
1507 */
1508
1509/*
1510 * omap3isp_print_status - Prints the values of the ISP Control Module registers
1511 * @isp: OMAP3 ISP device
1512 */
1513#define ISP_PRINT_REGISTER(isp, name)\
1514 dev_dbg(isp->dev, "###ISP " #name "=0x%08x\n", \
1515 isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_##name))
1516#define SBL_PRINT_REGISTER(isp, name)\
1517 dev_dbg(isp->dev, "###SBL " #name "=0x%08x\n", \
1518 isp_reg_readl(isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_##name))
1519
1520void omap3isp_print_status(struct isp_device *isp)
1521{
1522 dev_dbg(isp->dev, "-------------ISP Register dump--------------\n");
1523
1524 ISP_PRINT_REGISTER(isp, SYSCONFIG);
1525 ISP_PRINT_REGISTER(isp, SYSSTATUS);
1526 ISP_PRINT_REGISTER(isp, IRQ0ENABLE);
1527 ISP_PRINT_REGISTER(isp, IRQ0STATUS);
1528 ISP_PRINT_REGISTER(isp, TCTRL_GRESET_LENGTH);
1529 ISP_PRINT_REGISTER(isp, TCTRL_PSTRB_REPLAY);
1530 ISP_PRINT_REGISTER(isp, CTRL);
1531 ISP_PRINT_REGISTER(isp, TCTRL_CTRL);
1532 ISP_PRINT_REGISTER(isp, TCTRL_FRAME);
1533 ISP_PRINT_REGISTER(isp, TCTRL_PSTRB_DELAY);
1534 ISP_PRINT_REGISTER(isp, TCTRL_STRB_DELAY);
1535 ISP_PRINT_REGISTER(isp, TCTRL_SHUT_DELAY);
1536 ISP_PRINT_REGISTER(isp, TCTRL_PSTRB_LENGTH);
1537 ISP_PRINT_REGISTER(isp, TCTRL_STRB_LENGTH);
1538 ISP_PRINT_REGISTER(isp, TCTRL_SHUT_LENGTH);
1539
1540 SBL_PRINT_REGISTER(isp, PCR);
1541 SBL_PRINT_REGISTER(isp, SDR_REQ_EXP);
1542
1543 dev_dbg(isp->dev, "--------------------------------------------\n");
1544}
1545
1546#ifdef CONFIG_PM
1547
1548/*
1549 * Power management support.
1550 *
1551 * As the ISP can't properly handle an input video stream interruption on a non
1552 * frame boundary, the ISP pipelines need to be stopped before sensors get
1553 * suspended. However, as suspending the sensors can require a running clock,
1554 * which can be provided by the ISP, the ISP can't be completely suspended
1555 * before the sensor.
1556 *
1557 * To solve this problem power management support is split into prepare/complete
1558 * and suspend/resume operations. The pipelines are stopped in prepare() and the
1559 * ISP clocks get disabled in suspend(). Similarly, the clocks are reenabled in
1560 * resume(), and the the pipelines are restarted in complete().
1561 *
1562 * TODO: PM dependencies between the ISP and sensors are not modeled explicitly
1563 * yet.
1564 */
1565static int isp_pm_prepare(struct device *dev)
1566{
1567 struct isp_device *isp = dev_get_drvdata(dev);
1568 int reset;
1569
1570 WARN_ON(mutex_is_locked(&isp->isp_mutex));
1571
1572 if (isp->ref_count == 0)
1573 return 0;
1574
1575 reset = isp_suspend_modules(isp);
1576 isp_disable_interrupts(isp);
1577 isp_save_ctx(isp);
1578 if (reset)
1579 isp_reset(isp);
1580
1581 return 0;
1582}
1583
1584static int isp_pm_suspend(struct device *dev)
1585{
1586 struct isp_device *isp = dev_get_drvdata(dev);
1587
1588 WARN_ON(mutex_is_locked(&isp->isp_mutex));
1589
1590 if (isp->ref_count)
1591 isp_disable_clocks(isp);
1592
1593 return 0;
1594}
1595
1596static int isp_pm_resume(struct device *dev)
1597{
1598 struct isp_device *isp = dev_get_drvdata(dev);
1599
1600 if (isp->ref_count == 0)
1601 return 0;
1602
1603 return isp_enable_clocks(isp);
1604}
1605
1606static void isp_pm_complete(struct device *dev)
1607{
1608 struct isp_device *isp = dev_get_drvdata(dev);
1609
1610 if (isp->ref_count == 0)
1611 return;
1612
1613 isp_restore_ctx(isp);
1614 isp_enable_interrupts(isp);
1615 isp_resume_modules(isp);
1616}
1617
1618#else
1619
1620#define isp_pm_prepare NULL
1621#define isp_pm_suspend NULL
1622#define isp_pm_resume NULL
1623#define isp_pm_complete NULL
1624
1625#endif /* CONFIG_PM */
1626
1627static void isp_unregister_entities(struct isp_device *isp)
1628{
1629 omap3isp_csi2_unregister_entities(&isp->isp_csi2a);
1630 omap3isp_ccp2_unregister_entities(&isp->isp_ccp2);
1631 omap3isp_ccdc_unregister_entities(&isp->isp_ccdc);
1632 omap3isp_preview_unregister_entities(&isp->isp_prev);
1633 omap3isp_resizer_unregister_entities(&isp->isp_res);
1634 omap3isp_stat_unregister_entities(&isp->isp_aewb);
1635 omap3isp_stat_unregister_entities(&isp->isp_af);
1636 omap3isp_stat_unregister_entities(&isp->isp_hist);
1637
1638 v4l2_device_unregister(&isp->v4l2_dev);
1639 media_device_unregister(&isp->media_dev);
1640}
1641
1642/*
1643 * isp_register_subdev_group - Register a group of subdevices
1644 * @isp: OMAP3 ISP device
1645 * @board_info: I2C subdevs board information array
1646 *
1647 * Register all I2C subdevices in the board_info array. The array must be
1648 * terminated by a NULL entry, and the first entry must be the sensor.
1649 *
1650 * Return a pointer to the sensor media entity if it has been successfully
1651 * registered, or NULL otherwise.
1652 */
1653static struct v4l2_subdev *
1654isp_register_subdev_group(struct isp_device *isp,
1655 struct isp_subdev_i2c_board_info *board_info)
1656{
1657 struct v4l2_subdev *sensor = NULL;
1658 unsigned int first;
1659
1660 if (board_info->board_info == NULL)
1661 return NULL;
1662
1663 for (first = 1; board_info->board_info; ++board_info, first = 0) {
1664 struct v4l2_subdev *subdev;
1665 struct i2c_adapter *adapter;
1666
1667 adapter = i2c_get_adapter(board_info->i2c_adapter_id);
1668 if (adapter == NULL) {
1669 printk(KERN_ERR "%s: Unable to get I2C adapter %d for "
1670 "device %s\n", __func__,
1671 board_info->i2c_adapter_id,
1672 board_info->board_info->type);
1673 continue;
1674 }
1675
1676 subdev = v4l2_i2c_new_subdev_board(&isp->v4l2_dev, adapter,
1677 board_info->board_info, NULL);
1678 if (subdev == NULL) {
1679 printk(KERN_ERR "%s: Unable to register subdev %s\n",
1680 __func__, board_info->board_info->type);
1681 continue;
1682 }
1683
1684 if (first)
1685 sensor = subdev;
1686 }
1687
1688 return sensor;
1689}
1690
1691static int isp_register_entities(struct isp_device *isp)
1692{
1693 struct isp_platform_data *pdata = isp->pdata;
1694 struct isp_v4l2_subdevs_group *subdevs;
1695 int ret;
1696
1697 isp->media_dev.dev = isp->dev;
1698 strlcpy(isp->media_dev.model, "TI OMAP3 ISP",
1699 sizeof(isp->media_dev.model));
1700 isp->media_dev.link_notify = isp_pipeline_link_notify;
1701 ret = media_device_register(&isp->media_dev);
1702 if (ret < 0) {
1703 printk(KERN_ERR "%s: Media device registration failed (%d)\n",
1704 __func__, ret);
1705 return ret;
1706 }
1707
1708 isp->v4l2_dev.mdev = &isp->media_dev;
1709 ret = v4l2_device_register(isp->dev, &isp->v4l2_dev);
1710 if (ret < 0) {
1711 printk(KERN_ERR "%s: V4L2 device registration failed (%d)\n",
1712 __func__, ret);
1713 goto done;
1714 }
1715
1716 /* Register internal entities */
1717 ret = omap3isp_ccp2_register_entities(&isp->isp_ccp2, &isp->v4l2_dev);
1718 if (ret < 0)
1719 goto done;
1720
1721 ret = omap3isp_csi2_register_entities(&isp->isp_csi2a, &isp->v4l2_dev);
1722 if (ret < 0)
1723 goto done;
1724
1725 ret = omap3isp_ccdc_register_entities(&isp->isp_ccdc, &isp->v4l2_dev);
1726 if (ret < 0)
1727 goto done;
1728
1729 ret = omap3isp_preview_register_entities(&isp->isp_prev,
1730 &isp->v4l2_dev);
1731 if (ret < 0)
1732 goto done;
1733
1734 ret = omap3isp_resizer_register_entities(&isp->isp_res, &isp->v4l2_dev);
1735 if (ret < 0)
1736 goto done;
1737
1738 ret = omap3isp_stat_register_entities(&isp->isp_aewb, &isp->v4l2_dev);
1739 if (ret < 0)
1740 goto done;
1741
1742 ret = omap3isp_stat_register_entities(&isp->isp_af, &isp->v4l2_dev);
1743 if (ret < 0)
1744 goto done;
1745
1746 ret = omap3isp_stat_register_entities(&isp->isp_hist, &isp->v4l2_dev);
1747 if (ret < 0)
1748 goto done;
1749
1750 /* Register external entities */
1751 for (subdevs = pdata->subdevs; subdevs->subdevs; ++subdevs) {
1752 struct v4l2_subdev *sensor;
1753 struct media_entity *input;
1754 unsigned int flags;
1755 unsigned int pad;
1756
1757 sensor = isp_register_subdev_group(isp, subdevs->subdevs);
1758 if (sensor == NULL)
1759 continue;
1760
1761 sensor->host_priv = subdevs;
1762
1763 /* Connect the sensor to the correct interface module. Parallel
1764 * sensors are connected directly to the CCDC, while serial
1765 * sensors are connected to the CSI2a, CCP2b or CSI2c receiver
1766 * through CSIPHY1 or CSIPHY2.
1767 */
1768 switch (subdevs->interface) {
1769 case ISP_INTERFACE_PARALLEL:
1770 input = &isp->isp_ccdc.subdev.entity;
1771 pad = CCDC_PAD_SINK;
1772 flags = 0;
1773 break;
1774
1775 case ISP_INTERFACE_CSI2A_PHY2:
1776 input = &isp->isp_csi2a.subdev.entity;
1777 pad = CSI2_PAD_SINK;
1778 flags = MEDIA_LNK_FL_IMMUTABLE
1779 | MEDIA_LNK_FL_ENABLED;
1780 break;
1781
1782 case ISP_INTERFACE_CCP2B_PHY1:
1783 case ISP_INTERFACE_CCP2B_PHY2:
1784 input = &isp->isp_ccp2.subdev.entity;
1785 pad = CCP2_PAD_SINK;
1786 flags = 0;
1787 break;
1788
1789 case ISP_INTERFACE_CSI2C_PHY1:
1790 input = &isp->isp_csi2c.subdev.entity;
1791 pad = CSI2_PAD_SINK;
1792 flags = MEDIA_LNK_FL_IMMUTABLE
1793 | MEDIA_LNK_FL_ENABLED;
1794 break;
1795
1796 default:
1797 printk(KERN_ERR "%s: invalid interface type %u\n",
1798 __func__, subdevs->interface);
1799 ret = -EINVAL;
1800 goto done;
1801 }
1802
1803 ret = media_entity_create_link(&sensor->entity, 0, input, pad,
1804 flags);
1805 if (ret < 0)
1806 goto done;
1807 }
1808
1809 ret = v4l2_device_register_subdev_nodes(&isp->v4l2_dev);
1810
1811done:
1812 if (ret < 0)
1813 isp_unregister_entities(isp);
1814
1815 return ret;
1816}
1817
1818static void isp_cleanup_modules(struct isp_device *isp)
1819{
1820 omap3isp_h3a_aewb_cleanup(isp);
1821 omap3isp_h3a_af_cleanup(isp);
1822 omap3isp_hist_cleanup(isp);
1823 omap3isp_resizer_cleanup(isp);
1824 omap3isp_preview_cleanup(isp);
1825 omap3isp_ccdc_cleanup(isp);
1826 omap3isp_ccp2_cleanup(isp);
1827 omap3isp_csi2_cleanup(isp);
1828}
1829
1830static int isp_initialize_modules(struct isp_device *isp)
1831{
1832 int ret;
1833
1834 ret = omap3isp_csiphy_init(isp);
1835 if (ret < 0) {
1836 dev_err(isp->dev, "CSI PHY initialization failed\n");
1837 goto error_csiphy;
1838 }
1839
1840 ret = omap3isp_csi2_init(isp);
1841 if (ret < 0) {
1842 dev_err(isp->dev, "CSI2 initialization failed\n");
1843 goto error_csi2;
1844 }
1845
1846 ret = omap3isp_ccp2_init(isp);
1847 if (ret < 0) {
1848 dev_err(isp->dev, "CCP2 initialization failed\n");
1849 goto error_ccp2;
1850 }
1851
1852 ret = omap3isp_ccdc_init(isp);
1853 if (ret < 0) {
1854 dev_err(isp->dev, "CCDC initialization failed\n");
1855 goto error_ccdc;
1856 }
1857
1858 ret = omap3isp_preview_init(isp);
1859 if (ret < 0) {
1860 dev_err(isp->dev, "Preview initialization failed\n");
1861 goto error_preview;
1862 }
1863
1864 ret = omap3isp_resizer_init(isp);
1865 if (ret < 0) {
1866 dev_err(isp->dev, "Resizer initialization failed\n");
1867 goto error_resizer;
1868 }
1869
1870 ret = omap3isp_hist_init(isp);
1871 if (ret < 0) {
1872 dev_err(isp->dev, "Histogram initialization failed\n");
1873 goto error_hist;
1874 }
1875
1876 ret = omap3isp_h3a_aewb_init(isp);
1877 if (ret < 0) {
1878 dev_err(isp->dev, "H3A AEWB initialization failed\n");
1879 goto error_h3a_aewb;
1880 }
1881
1882 ret = omap3isp_h3a_af_init(isp);
1883 if (ret < 0) {
1884 dev_err(isp->dev, "H3A AF initialization failed\n");
1885 goto error_h3a_af;
1886 }
1887
1888 /* Connect the submodules. */
1889 ret = media_entity_create_link(
1890 &isp->isp_csi2a.subdev.entity, CSI2_PAD_SOURCE,
1891 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SINK, 0);
1892 if (ret < 0)
1893 goto error_link;
1894
1895 ret = media_entity_create_link(
1896 &isp->isp_ccp2.subdev.entity, CCP2_PAD_SOURCE,
1897 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SINK, 0);
1898 if (ret < 0)
1899 goto error_link;
1900
1901 ret = media_entity_create_link(
1902 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_VP,
1903 &isp->isp_prev.subdev.entity, PREV_PAD_SINK, 0);
1904 if (ret < 0)
1905 goto error_link;
1906
1907 ret = media_entity_create_link(
1908 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_OF,
1909 &isp->isp_res.subdev.entity, RESZ_PAD_SINK, 0);
1910 if (ret < 0)
1911 goto error_link;
1912
1913 ret = media_entity_create_link(
1914 &isp->isp_prev.subdev.entity, PREV_PAD_SOURCE,
1915 &isp->isp_res.subdev.entity, RESZ_PAD_SINK, 0);
1916 if (ret < 0)
1917 goto error_link;
1918
1919 ret = media_entity_create_link(
1920 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_VP,
1921 &isp->isp_aewb.subdev.entity, 0,
1922 MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE);
1923 if (ret < 0)
1924 goto error_link;
1925
1926 ret = media_entity_create_link(
1927 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_VP,
1928 &isp->isp_af.subdev.entity, 0,
1929 MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE);
1930 if (ret < 0)
1931 goto error_link;
1932
1933 ret = media_entity_create_link(
1934 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_VP,
1935 &isp->isp_hist.subdev.entity, 0,
1936 MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE);
1937 if (ret < 0)
1938 goto error_link;
1939
1940 return 0;
1941
1942error_link:
1943 omap3isp_h3a_af_cleanup(isp);
1944error_h3a_af:
1945 omap3isp_h3a_aewb_cleanup(isp);
1946error_h3a_aewb:
1947 omap3isp_hist_cleanup(isp);
1948error_hist:
1949 omap3isp_resizer_cleanup(isp);
1950error_resizer:
1951 omap3isp_preview_cleanup(isp);
1952error_preview:
1953 omap3isp_ccdc_cleanup(isp);
1954error_ccdc:
1955 omap3isp_ccp2_cleanup(isp);
1956error_ccp2:
1957 omap3isp_csi2_cleanup(isp);
1958error_csi2:
1959error_csiphy:
1960 return ret;
1961}
1962
1963/*
1964 * isp_remove - Remove ISP platform device
1965 * @pdev: Pointer to ISP platform device
1966 *
1967 * Always returns 0.
1968 */
1969static int isp_remove(struct platform_device *pdev)
1970{
1971 struct isp_device *isp = platform_get_drvdata(pdev);
1972 int i;
1973
1974 isp_unregister_entities(isp);
1975 isp_cleanup_modules(isp);
1976
1977 omap3isp_get(isp);
1978 iommu_put(isp->iommu);
1979 omap3isp_put(isp);
1980
1981 free_irq(isp->irq_num, isp);
1982 isp_put_clocks(isp);
1983
1984 for (i = 0; i < OMAP3_ISP_IOMEM_LAST; i++) {
1985 if (isp->mmio_base[i]) {
1986 iounmap(isp->mmio_base[i]);
1987 isp->mmio_base[i] = NULL;
1988 }
1989
1990 if (isp->mmio_base_phys[i]) {
1991 release_mem_region(isp->mmio_base_phys[i],
1992 isp->mmio_size[i]);
1993 isp->mmio_base_phys[i] = 0;
1994 }
1995 }
1996
1997 regulator_put(isp->isp_csiphy1.vdd);
1998 regulator_put(isp->isp_csiphy2.vdd);
1999 kfree(isp);
2000
2001 return 0;
2002}
2003
2004static int isp_map_mem_resource(struct platform_device *pdev,
2005 struct isp_device *isp,
2006 enum isp_mem_resources res)
2007{
2008 struct resource *mem;
2009
2010 /* request the mem region for the camera registers */
2011
2012 mem = platform_get_resource(pdev, IORESOURCE_MEM, res);
2013 if (!mem) {
2014 dev_err(isp->dev, "no mem resource?\n");
2015 return -ENODEV;
2016 }
2017
2018 if (!request_mem_region(mem->start, resource_size(mem), pdev->name)) {
2019 dev_err(isp->dev,
2020 "cannot reserve camera register I/O region\n");
2021 return -ENODEV;
2022 }
2023 isp->mmio_base_phys[res] = mem->start;
2024 isp->mmio_size[res] = resource_size(mem);
2025
2026 /* map the region */
2027 isp->mmio_base[res] = ioremap_nocache(isp->mmio_base_phys[res],
2028 isp->mmio_size[res]);
2029 if (!isp->mmio_base[res]) {
2030 dev_err(isp->dev, "cannot map camera register I/O region\n");
2031 return -ENODEV;
2032 }
2033
2034 return 0;
2035}
2036
2037/*
2038 * isp_probe - Probe ISP platform device
2039 * @pdev: Pointer to ISP platform device
2040 *
2041 * Returns 0 if successful,
2042 * -ENOMEM if no memory available,
2043 * -ENODEV if no platform device resources found
2044 * or no space for remapping registers,
2045 * -EINVAL if couldn't install ISR,
2046 * or clk_get return error value.
2047 */
2048static int isp_probe(struct platform_device *pdev)
2049{
2050 struct isp_platform_data *pdata = pdev->dev.platform_data;
2051 struct isp_device *isp;
2052 int ret;
2053 int i, m;
2054
2055 if (pdata == NULL)
2056 return -EINVAL;
2057
2058 isp = kzalloc(sizeof(*isp), GFP_KERNEL);
2059 if (!isp) {
2060 dev_err(&pdev->dev, "could not allocate memory\n");
2061 return -ENOMEM;
2062 }
2063
2064 isp->autoidle = autoidle;
2065 isp->platform_cb.set_xclk = isp_set_xclk;
2066 isp->platform_cb.set_pixel_clock = isp_set_pixel_clock;
2067
2068 mutex_init(&isp->isp_mutex);
2069 spin_lock_init(&isp->stat_lock);
2070
2071 isp->dev = &pdev->dev;
2072 isp->pdata = pdata;
2073 isp->ref_count = 0;
2074
2075 isp->raw_dmamask = DMA_BIT_MASK(32);
2076 isp->dev->dma_mask = &isp->raw_dmamask;
2077 isp->dev->coherent_dma_mask = DMA_BIT_MASK(32);
2078
2079 platform_set_drvdata(pdev, isp);
2080
2081 /* Regulators */
2082 isp->isp_csiphy1.vdd = regulator_get(&pdev->dev, "VDD_CSIPHY1");
2083 isp->isp_csiphy2.vdd = regulator_get(&pdev->dev, "VDD_CSIPHY2");
2084
2085 /* Clocks */
2086 ret = isp_map_mem_resource(pdev, isp, OMAP3_ISP_IOMEM_MAIN);
2087 if (ret < 0)
2088 goto error;
2089
2090 ret = isp_get_clocks(isp);
2091 if (ret < 0)
2092 goto error;
2093
2094 if (omap3isp_get(isp) == NULL)
2095 goto error;
2096
2097 ret = isp_reset(isp);
2098 if (ret < 0)
2099 goto error_isp;
2100
2101 /* Memory resources */
2102 isp->revision = isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_REVISION);
2103 dev_info(isp->dev, "Revision %d.%d found\n",
2104 (isp->revision & 0xf0) >> 4, isp->revision & 0x0f);
2105
2106 for (m = 0; m < ARRAY_SIZE(isp_res_maps); m++)
2107 if (isp->revision == isp_res_maps[m].isp_rev)
2108 break;
2109
2110 if (m == ARRAY_SIZE(isp_res_maps)) {
2111 dev_err(isp->dev, "No resource map found for ISP rev %d.%d\n",
2112 (isp->revision & 0xf0) >> 4, isp->revision & 0xf);
2113 ret = -ENODEV;
2114 goto error_isp;
2115 }
2116
2117 for (i = 1; i < OMAP3_ISP_IOMEM_LAST; i++) {
2118 if (isp_res_maps[m].map & 1 << i) {
2119 ret = isp_map_mem_resource(pdev, isp, i);
2120 if (ret)
2121 goto error_isp;
2122 }
2123 }
2124
2125 /* IOMMU */
2126 isp->iommu = iommu_get("isp");
2127 if (IS_ERR_OR_NULL(isp->iommu)) {
2128 isp->iommu = NULL;
2129 ret = -ENODEV;
2130 goto error_isp;
2131 }
2132
2133 /* Interrupt */
2134 isp->irq_num = platform_get_irq(pdev, 0);
2135 if (isp->irq_num <= 0) {
2136 dev_err(isp->dev, "No IRQ resource\n");
2137 ret = -ENODEV;
2138 goto error_isp;
2139 }
2140
2141 if (request_irq(isp->irq_num, isp_isr, IRQF_SHARED, "OMAP3 ISP", isp)) {
2142 dev_err(isp->dev, "Unable to request IRQ\n");
2143 ret = -EINVAL;
2144 goto error_isp;
2145 }
2146
2147 /* Entities */
2148 ret = isp_initialize_modules(isp);
2149 if (ret < 0)
2150 goto error_irq;
2151
2152 ret = isp_register_entities(isp);
2153 if (ret < 0)
2154 goto error_modules;
2155
2156 isp_power_settings(isp, 1);
2157 omap3isp_put(isp);
2158
2159 return 0;
2160
2161error_modules:
2162 isp_cleanup_modules(isp);
2163error_irq:
2164 free_irq(isp->irq_num, isp);
2165error_isp:
2166 iommu_put(isp->iommu);
2167 omap3isp_put(isp);
2168error:
2169 isp_put_clocks(isp);
2170
2171 for (i = 0; i < OMAP3_ISP_IOMEM_LAST; i++) {
2172 if (isp->mmio_base[i]) {
2173 iounmap(isp->mmio_base[i]);
2174 isp->mmio_base[i] = NULL;
2175 }
2176
2177 if (isp->mmio_base_phys[i]) {
2178 release_mem_region(isp->mmio_base_phys[i],
2179 isp->mmio_size[i]);
2180 isp->mmio_base_phys[i] = 0;
2181 }
2182 }
2183 regulator_put(isp->isp_csiphy2.vdd);
2184 regulator_put(isp->isp_csiphy1.vdd);
2185 platform_set_drvdata(pdev, NULL);
2186 kfree(isp);
2187
2188 return ret;
2189}
2190
2191static const struct dev_pm_ops omap3isp_pm_ops = {
2192 .prepare = isp_pm_prepare,
2193 .suspend = isp_pm_suspend,
2194 .resume = isp_pm_resume,
2195 .complete = isp_pm_complete,
2196};
2197
2198static struct platform_device_id omap3isp_id_table[] = {
2199 { "omap3isp", 0 },
2200 { },
2201};
2202MODULE_DEVICE_TABLE(platform, omap3isp_id_table);
2203
2204static struct platform_driver omap3isp_driver = {
2205 .probe = isp_probe,
2206 .remove = isp_remove,
2207 .id_table = omap3isp_id_table,
2208 .driver = {
2209 .owner = THIS_MODULE,
2210 .name = "omap3isp",
2211 .pm = &omap3isp_pm_ops,
2212 },
2213};
2214
2215/*
2216 * isp_init - ISP module initialization.
2217 */
2218static int __init isp_init(void)
2219{
2220 return platform_driver_register(&omap3isp_driver);
2221}
2222
2223/*
2224 * isp_cleanup - ISP module cleanup.
2225 */
2226static void __exit isp_cleanup(void)
2227{
2228 platform_driver_unregister(&omap3isp_driver);
2229}
2230
2231module_init(isp_init);
2232module_exit(isp_cleanup);
2233
2234MODULE_AUTHOR("Nokia Corporation");
2235MODULE_DESCRIPTION("TI OMAP3 ISP driver");
2236MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)