Commit | Line | Data |
---|---|---|
6acc81c3 PZ |
1 | /* |
2 | * V4L2 Driver for i.MXL/i.MXL camera (CSI) host | |
3 | * | |
4 | * Copyright (C) 2008, Paulius Zaleckas <paulius.zaleckas@teltonika.lt> | |
5 | * Copyright (C) 2009, Darius Augulis <augulis.darius@gmail.com> | |
6 | * | |
7 | * Based on PXA SoC camera driver | |
8 | * Copyright (C) 2006, Sascha Hauer, Pengutronix | |
9 | * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
16 | #include <linux/clk.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/device.h> | |
19 | #include <linux/dma-mapping.h> | |
20 | #include <linux/errno.h> | |
21 | #include <linux/fs.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/io.h> | |
25 | #include <linux/kernel.h> | |
26 | #include <linux/mm.h> | |
27 | #include <linux/module.h> | |
28 | #include <linux/moduleparam.h> | |
29 | #include <linux/mutex.h> | |
30 | #include <linux/platform_device.h> | |
31 | #include <linux/time.h> | |
32 | #include <linux/version.h> | |
33 | #include <linux/videodev2.h> | |
34 | ||
35 | #include <media/soc_camera.h> | |
36 | #include <media/v4l2-common.h> | |
37 | #include <media/v4l2-dev.h> | |
38 | #include <media/videobuf-dma-contig.h> | |
39 | ||
40 | #include <asm/dma.h> | |
41 | #include <asm/fiq.h> | |
42 | #include <mach/dma-mx1-mx2.h> | |
43 | #include <mach/hardware.h> | |
44 | #include <mach/mx1_camera.h> | |
45 | ||
46 | /* | |
47 | * CSI registers | |
48 | */ | |
49 | #define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */ | |
50 | #define DMA_DIMR 0x08 /* Interrupt mask Register */ | |
51 | #define CSICR1 0x00 /* CSI Control Register 1 */ | |
52 | #define CSISR 0x08 /* CSI Status Register */ | |
53 | #define CSIRXR 0x10 /* CSI RxFIFO Register */ | |
54 | ||
55 | #define CSICR1_RXFF_LEVEL(x) (((x) & 0x3) << 19) | |
56 | #define CSICR1_SOF_POL (1 << 17) | |
57 | #define CSICR1_SOF_INTEN (1 << 16) | |
58 | #define CSICR1_MCLKDIV(x) (((x) & 0xf) << 12) | |
59 | #define CSICR1_MCLKEN (1 << 9) | |
60 | #define CSICR1_FCC (1 << 8) | |
61 | #define CSICR1_BIG_ENDIAN (1 << 7) | |
62 | #define CSICR1_CLR_RXFIFO (1 << 5) | |
63 | #define CSICR1_GCLK_MODE (1 << 4) | |
64 | #define CSICR1_DATA_POL (1 << 2) | |
65 | #define CSICR1_REDGE (1 << 1) | |
66 | #define CSICR1_EN (1 << 0) | |
67 | ||
68 | #define CSISR_SFF_OR_INT (1 << 25) | |
69 | #define CSISR_RFF_OR_INT (1 << 24) | |
70 | #define CSISR_STATFF_INT (1 << 21) | |
71 | #define CSISR_RXFF_INT (1 << 18) | |
72 | #define CSISR_SOF_INT (1 << 16) | |
73 | #define CSISR_DRDY (1 << 0) | |
74 | ||
75 | #define VERSION_CODE KERNEL_VERSION(0, 0, 1) | |
76 | #define DRIVER_NAME "mx1-camera" | |
77 | ||
78 | #define CSI_IRQ_MASK (CSISR_SFF_OR_INT | CSISR_RFF_OR_INT | \ | |
79 | CSISR_STATFF_INT | CSISR_RXFF_INT | CSISR_SOF_INT) | |
80 | ||
81 | #define CSI_BUS_FLAGS (SOCAM_MASTER | SOCAM_HSYNC_ACTIVE_HIGH | \ | |
82 | SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_VSYNC_ACTIVE_LOW | \ | |
83 | SOCAM_PCLK_SAMPLE_RISING | SOCAM_PCLK_SAMPLE_FALLING | \ | |
84 | SOCAM_DATA_ACTIVE_HIGH | SOCAM_DATA_ACTIVE_LOW | \ | |
85 | SOCAM_DATAWIDTH_8) | |
86 | ||
87 | #define MAX_VIDEO_MEM 16 /* Video memory limit in megabytes */ | |
88 | ||
89 | /* | |
90 | * Structures | |
91 | */ | |
92 | ||
93 | /* buffer for one video frame */ | |
94 | struct mx1_buffer { | |
95 | /* common v4l buffer stuff -- must be first */ | |
96 | struct videobuf_buffer vb; | |
97 | const struct soc_camera_data_format *fmt; | |
98 | int inwork; | |
99 | }; | |
100 | ||
101 | /* i.MX1/i.MXL is only supposed to handle one camera on its Camera Sensor | |
102 | * Interface. If anyone ever builds hardware to enable more than | |
103 | * one camera, they will have to modify this driver too */ | |
104 | struct mx1_camera_dev { | |
eb6c8558 | 105 | struct soc_camera_host soc_host; |
6acc81c3 PZ |
106 | struct soc_camera_device *icd; |
107 | struct mx1_camera_pdata *pdata; | |
108 | struct mx1_buffer *active; | |
6acc81c3 PZ |
109 | struct resource *res; |
110 | struct clk *clk; | |
111 | struct list_head capture; | |
112 | ||
113 | void __iomem *base; | |
114 | int dma_chan; | |
115 | unsigned int irq; | |
116 | unsigned long mclk; | |
117 | ||
118 | spinlock_t lock; | |
119 | }; | |
120 | ||
121 | /* | |
122 | * Videobuf operations | |
123 | */ | |
124 | static int mx1_videobuf_setup(struct videobuf_queue *vq, unsigned int *count, | |
125 | unsigned int *size) | |
126 | { | |
127 | struct soc_camera_device *icd = vq->priv_data; | |
128 | ||
129 | *size = icd->width * icd->height * | |
130 | ((icd->current_fmt->depth + 7) >> 3); | |
131 | ||
132 | if (!*count) | |
133 | *count = 32; | |
134 | ||
135 | while (*size * *count > MAX_VIDEO_MEM * 1024 * 1024) | |
136 | (*count)--; | |
137 | ||
138 | dev_dbg(&icd->dev, "count=%d, size=%d\n", *count, *size); | |
139 | ||
140 | return 0; | |
141 | } | |
142 | ||
143 | static void free_buffer(struct videobuf_queue *vq, struct mx1_buffer *buf) | |
144 | { | |
145 | struct soc_camera_device *icd = vq->priv_data; | |
146 | struct videobuf_buffer *vb = &buf->vb; | |
147 | ||
148 | BUG_ON(in_interrupt()); | |
149 | ||
150 | dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, | |
151 | vb, vb->baddr, vb->bsize); | |
152 | ||
153 | /* This waits until this buffer is out of danger, i.e., until it is no | |
154 | * longer in STATE_QUEUED or STATE_ACTIVE */ | |
155 | videobuf_waiton(vb, 0, 0); | |
156 | videobuf_dma_contig_free(vq, vb); | |
157 | ||
158 | vb->state = VIDEOBUF_NEEDS_INIT; | |
159 | } | |
160 | ||
161 | static int mx1_videobuf_prepare(struct videobuf_queue *vq, | |
162 | struct videobuf_buffer *vb, enum v4l2_field field) | |
163 | { | |
164 | struct soc_camera_device *icd = vq->priv_data; | |
165 | struct mx1_buffer *buf = container_of(vb, struct mx1_buffer, vb); | |
166 | int ret; | |
167 | ||
168 | dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, | |
169 | vb, vb->baddr, vb->bsize); | |
170 | ||
171 | /* Added list head initialization on alloc */ | |
172 | WARN_ON(!list_empty(&vb->queue)); | |
173 | ||
174 | BUG_ON(NULL == icd->current_fmt); | |
175 | ||
176 | /* I think, in buf_prepare you only have to protect global data, | |
177 | * the actual buffer is yours */ | |
178 | buf->inwork = 1; | |
179 | ||
180 | if (buf->fmt != icd->current_fmt || | |
181 | vb->width != icd->width || | |
182 | vb->height != icd->height || | |
183 | vb->field != field) { | |
184 | buf->fmt = icd->current_fmt; | |
185 | vb->width = icd->width; | |
186 | vb->height = icd->height; | |
187 | vb->field = field; | |
188 | vb->state = VIDEOBUF_NEEDS_INIT; | |
189 | } | |
190 | ||
191 | vb->size = vb->width * vb->height * ((buf->fmt->depth + 7) >> 3); | |
192 | if (0 != vb->baddr && vb->bsize < vb->size) { | |
193 | ret = -EINVAL; | |
194 | goto out; | |
195 | } | |
196 | ||
197 | if (vb->state == VIDEOBUF_NEEDS_INIT) { | |
198 | ret = videobuf_iolock(vq, vb, NULL); | |
199 | if (ret) | |
200 | goto fail; | |
201 | ||
202 | vb->state = VIDEOBUF_PREPARED; | |
203 | } | |
204 | ||
205 | buf->inwork = 0; | |
206 | ||
207 | return 0; | |
208 | ||
209 | fail: | |
210 | free_buffer(vq, buf); | |
211 | out: | |
212 | buf->inwork = 0; | |
213 | return ret; | |
214 | } | |
215 | ||
216 | static int mx1_camera_setup_dma(struct mx1_camera_dev *pcdev) | |
217 | { | |
218 | struct videobuf_buffer *vbuf = &pcdev->active->vb; | |
219 | int ret; | |
220 | ||
221 | if (unlikely(!pcdev->active)) { | |
eff505fa | 222 | dev_err(pcdev->soc_host.dev, "DMA End IRQ with no active buffer\n"); |
6acc81c3 PZ |
223 | return -EFAULT; |
224 | } | |
225 | ||
226 | /* setup sg list for future DMA */ | |
227 | ret = imx_dma_setup_single(pcdev->dma_chan, | |
228 | videobuf_to_dma_contig(vbuf), | |
229 | vbuf->size, pcdev->res->start + | |
230 | CSIRXR, DMA_MODE_READ); | |
231 | if (unlikely(ret)) | |
eff505fa | 232 | dev_err(pcdev->soc_host.dev, "Failed to setup DMA sg list\n"); |
6acc81c3 PZ |
233 | |
234 | return ret; | |
235 | } | |
236 | ||
237 | static void mx1_videobuf_queue(struct videobuf_queue *vq, | |
238 | struct videobuf_buffer *vb) | |
239 | { | |
240 | struct soc_camera_device *icd = vq->priv_data; | |
241 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); | |
242 | struct mx1_camera_dev *pcdev = ici->priv; | |
243 | struct mx1_buffer *buf = container_of(vb, struct mx1_buffer, vb); | |
244 | unsigned long flags; | |
245 | ||
246 | dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, | |
247 | vb, vb->baddr, vb->bsize); | |
248 | ||
249 | spin_lock_irqsave(&pcdev->lock, flags); | |
250 | ||
251 | list_add_tail(&vb->queue, &pcdev->capture); | |
252 | ||
253 | vb->state = VIDEOBUF_ACTIVE; | |
254 | ||
255 | if (!pcdev->active) { | |
256 | pcdev->active = buf; | |
257 | ||
258 | /* setup sg list for future DMA */ | |
259 | if (!mx1_camera_setup_dma(pcdev)) { | |
260 | unsigned int temp; | |
261 | /* enable SOF irq */ | |
262 | temp = __raw_readl(pcdev->base + CSICR1) | | |
263 | CSICR1_SOF_INTEN; | |
264 | __raw_writel(temp, pcdev->base + CSICR1); | |
265 | } | |
266 | } | |
267 | ||
268 | spin_unlock_irqrestore(&pcdev->lock, flags); | |
269 | } | |
270 | ||
271 | static void mx1_videobuf_release(struct videobuf_queue *vq, | |
272 | struct videobuf_buffer *vb) | |
273 | { | |
274 | struct mx1_buffer *buf = container_of(vb, struct mx1_buffer, vb); | |
275 | #ifdef DEBUG | |
276 | struct soc_camera_device *icd = vq->priv_data; | |
277 | ||
278 | dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, | |
279 | vb, vb->baddr, vb->bsize); | |
280 | ||
281 | switch (vb->state) { | |
282 | case VIDEOBUF_ACTIVE: | |
283 | dev_dbg(&icd->dev, "%s (active)\n", __func__); | |
284 | break; | |
285 | case VIDEOBUF_QUEUED: | |
286 | dev_dbg(&icd->dev, "%s (queued)\n", __func__); | |
287 | break; | |
288 | case VIDEOBUF_PREPARED: | |
289 | dev_dbg(&icd->dev, "%s (prepared)\n", __func__); | |
290 | break; | |
291 | default: | |
292 | dev_dbg(&icd->dev, "%s (unknown)\n", __func__); | |
293 | break; | |
294 | } | |
295 | #endif | |
296 | ||
297 | free_buffer(vq, buf); | |
298 | } | |
299 | ||
300 | static void mx1_camera_wakeup(struct mx1_camera_dev *pcdev, | |
301 | struct videobuf_buffer *vb, | |
302 | struct mx1_buffer *buf) | |
303 | { | |
304 | /* _init is used to debug races, see comment in mx1_camera_reqbufs() */ | |
305 | list_del_init(&vb->queue); | |
306 | vb->state = VIDEOBUF_DONE; | |
307 | do_gettimeofday(&vb->ts); | |
308 | vb->field_count++; | |
309 | wake_up(&vb->done); | |
310 | ||
311 | if (list_empty(&pcdev->capture)) { | |
312 | pcdev->active = NULL; | |
313 | return; | |
314 | } | |
315 | ||
316 | pcdev->active = list_entry(pcdev->capture.next, | |
317 | struct mx1_buffer, vb.queue); | |
318 | ||
319 | /* setup sg list for future DMA */ | |
320 | if (likely(!mx1_camera_setup_dma(pcdev))) { | |
321 | unsigned int temp; | |
322 | ||
323 | /* enable SOF irq */ | |
324 | temp = __raw_readl(pcdev->base + CSICR1) | CSICR1_SOF_INTEN; | |
325 | __raw_writel(temp, pcdev->base + CSICR1); | |
326 | } | |
327 | } | |
328 | ||
329 | static void mx1_camera_dma_irq(int channel, void *data) | |
330 | { | |
331 | struct mx1_camera_dev *pcdev = data; | |
332 | struct mx1_buffer *buf; | |
333 | struct videobuf_buffer *vb; | |
334 | unsigned long flags; | |
335 | ||
336 | spin_lock_irqsave(&pcdev->lock, flags); | |
337 | ||
338 | imx_dma_disable(channel); | |
339 | ||
340 | if (unlikely(!pcdev->active)) { | |
eff505fa | 341 | dev_err(pcdev->soc_host.dev, "DMA End IRQ with no active buffer\n"); |
6acc81c3 PZ |
342 | goto out; |
343 | } | |
344 | ||
345 | vb = &pcdev->active->vb; | |
346 | buf = container_of(vb, struct mx1_buffer, vb); | |
347 | WARN_ON(buf->inwork || list_empty(&vb->queue)); | |
eff505fa | 348 | dev_dbg(pcdev->soc_host.dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, |
6acc81c3 PZ |
349 | vb, vb->baddr, vb->bsize); |
350 | ||
351 | mx1_camera_wakeup(pcdev, vb, buf); | |
352 | out: | |
353 | spin_unlock_irqrestore(&pcdev->lock, flags); | |
354 | } | |
355 | ||
356 | static struct videobuf_queue_ops mx1_videobuf_ops = { | |
357 | .buf_setup = mx1_videobuf_setup, | |
358 | .buf_prepare = mx1_videobuf_prepare, | |
359 | .buf_queue = mx1_videobuf_queue, | |
360 | .buf_release = mx1_videobuf_release, | |
361 | }; | |
362 | ||
363 | static void mx1_camera_init_videobuf(struct videobuf_queue *q, | |
364 | struct soc_camera_device *icd) | |
365 | { | |
366 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); | |
367 | struct mx1_camera_dev *pcdev = ici->priv; | |
368 | ||
eff505fa | 369 | videobuf_queue_dma_contig_init(q, &mx1_videobuf_ops, ici->dev, |
6acc81c3 PZ |
370 | &pcdev->lock, |
371 | V4L2_BUF_TYPE_VIDEO_CAPTURE, | |
372 | V4L2_FIELD_NONE, | |
373 | sizeof(struct mx1_buffer), icd); | |
374 | } | |
375 | ||
376 | static int mclk_get_divisor(struct mx1_camera_dev *pcdev) | |
377 | { | |
378 | unsigned int mclk = pcdev->mclk; | |
379 | unsigned long div; | |
380 | unsigned long lcdclk; | |
381 | ||
382 | lcdclk = clk_get_rate(pcdev->clk); | |
383 | ||
384 | /* We verify platform_mclk_10khz != 0, so if anyone breaks it, here | |
385 | * they get a nice Oops */ | |
386 | div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1; | |
387 | ||
eff505fa | 388 | dev_dbg(pcdev->soc_host.dev, "System clock %lukHz, target freq %dkHz, " |
6acc81c3 PZ |
389 | "divisor %lu\n", lcdclk / 1000, mclk / 1000, div); |
390 | ||
391 | return div; | |
392 | } | |
393 | ||
394 | static void mx1_camera_activate(struct mx1_camera_dev *pcdev) | |
395 | { | |
396 | unsigned int csicr1 = CSICR1_EN; | |
397 | ||
eff505fa | 398 | dev_dbg(pcdev->soc_host.dev, "Activate device\n"); |
6acc81c3 PZ |
399 | |
400 | clk_enable(pcdev->clk); | |
401 | ||
402 | /* enable CSI before doing anything else */ | |
403 | __raw_writel(csicr1, pcdev->base + CSICR1); | |
404 | ||
405 | csicr1 |= CSICR1_MCLKEN | CSICR1_FCC | CSICR1_GCLK_MODE; | |
406 | csicr1 |= CSICR1_MCLKDIV(mclk_get_divisor(pcdev)); | |
407 | csicr1 |= CSICR1_RXFF_LEVEL(2); /* 16 words */ | |
408 | ||
409 | __raw_writel(csicr1, pcdev->base + CSICR1); | |
410 | } | |
411 | ||
412 | static void mx1_camera_deactivate(struct mx1_camera_dev *pcdev) | |
413 | { | |
eff505fa | 414 | dev_dbg(pcdev->soc_host.dev, "Deactivate device\n"); |
6acc81c3 PZ |
415 | |
416 | /* Disable all CSI interface */ | |
417 | __raw_writel(0x00, pcdev->base + CSICR1); | |
418 | ||
419 | clk_disable(pcdev->clk); | |
420 | } | |
421 | ||
422 | /* The following two functions absolutely depend on the fact, that | |
423 | * there can be only one camera on i.MX1/i.MXL camera sensor interface */ | |
424 | static int mx1_camera_add_device(struct soc_camera_device *icd) | |
425 | { | |
426 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); | |
427 | struct mx1_camera_dev *pcdev = ici->priv; | |
428 | int ret; | |
429 | ||
430 | if (pcdev->icd) { | |
431 | ret = -EBUSY; | |
432 | goto ebusy; | |
433 | } | |
434 | ||
435 | dev_info(&icd->dev, "MX1 Camera driver attached to camera %d\n", | |
436 | icd->devnum); | |
437 | ||
438 | mx1_camera_activate(pcdev); | |
439 | ret = icd->ops->init(icd); | |
440 | ||
441 | if (!ret) | |
442 | pcdev->icd = icd; | |
443 | ||
444 | ebusy: | |
445 | return ret; | |
446 | } | |
447 | ||
448 | static void mx1_camera_remove_device(struct soc_camera_device *icd) | |
449 | { | |
450 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); | |
451 | struct mx1_camera_dev *pcdev = ici->priv; | |
452 | unsigned int csicr1; | |
453 | ||
454 | BUG_ON(icd != pcdev->icd); | |
455 | ||
456 | /* disable interrupts */ | |
457 | csicr1 = __raw_readl(pcdev->base + CSICR1) & ~CSI_IRQ_MASK; | |
458 | __raw_writel(csicr1, pcdev->base + CSICR1); | |
459 | ||
460 | /* Stop DMA engine */ | |
461 | imx_dma_disable(pcdev->dma_chan); | |
462 | ||
463 | dev_info(&icd->dev, "MX1 Camera driver detached from camera %d\n", | |
464 | icd->devnum); | |
465 | ||
466 | icd->ops->release(icd); | |
467 | ||
468 | mx1_camera_deactivate(pcdev); | |
469 | ||
470 | pcdev->icd = NULL; | |
471 | } | |
472 | ||
473 | static int mx1_camera_set_crop(struct soc_camera_device *icd, | |
474 | struct v4l2_rect *rect) | |
475 | { | |
476 | return icd->ops->set_crop(icd, rect); | |
477 | } | |
478 | ||
479 | static int mx1_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt) | |
480 | { | |
481 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); | |
482 | struct mx1_camera_dev *pcdev = ici->priv; | |
483 | unsigned long camera_flags, common_flags; | |
484 | unsigned int csicr1; | |
485 | int ret; | |
486 | ||
487 | camera_flags = icd->ops->query_bus_param(icd); | |
488 | ||
489 | /* MX1 supports only 8bit buswidth */ | |
490 | common_flags = soc_camera_bus_param_compatible(camera_flags, | |
491 | CSI_BUS_FLAGS); | |
492 | if (!common_flags) | |
493 | return -EINVAL; | |
494 | ||
495 | icd->buswidth = 8; | |
496 | ||
497 | /* Make choises, based on platform choice */ | |
498 | if ((common_flags & SOCAM_VSYNC_ACTIVE_HIGH) && | |
499 | (common_flags & SOCAM_VSYNC_ACTIVE_LOW)) { | |
500 | if (!pcdev->pdata || | |
501 | pcdev->pdata->flags & MX1_CAMERA_VSYNC_HIGH) | |
502 | common_flags &= ~SOCAM_VSYNC_ACTIVE_LOW; | |
503 | else | |
504 | common_flags &= ~SOCAM_VSYNC_ACTIVE_HIGH; | |
505 | } | |
506 | ||
507 | if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) && | |
508 | (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) { | |
509 | if (!pcdev->pdata || | |
510 | pcdev->pdata->flags & MX1_CAMERA_PCLK_RISING) | |
511 | common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING; | |
512 | else | |
513 | common_flags &= ~SOCAM_PCLK_SAMPLE_RISING; | |
514 | } | |
515 | ||
516 | if ((common_flags & SOCAM_DATA_ACTIVE_HIGH) && | |
517 | (common_flags & SOCAM_DATA_ACTIVE_LOW)) { | |
518 | if (!pcdev->pdata || | |
519 | pcdev->pdata->flags & MX1_CAMERA_DATA_HIGH) | |
520 | common_flags &= ~SOCAM_DATA_ACTIVE_LOW; | |
521 | else | |
522 | common_flags &= ~SOCAM_DATA_ACTIVE_HIGH; | |
523 | } | |
524 | ||
525 | ret = icd->ops->set_bus_param(icd, common_flags); | |
526 | if (ret < 0) | |
527 | return ret; | |
528 | ||
529 | csicr1 = __raw_readl(pcdev->base + CSICR1); | |
530 | ||
531 | if (common_flags & SOCAM_PCLK_SAMPLE_RISING) | |
532 | csicr1 |= CSICR1_REDGE; | |
533 | if (common_flags & SOCAM_VSYNC_ACTIVE_HIGH) | |
534 | csicr1 |= CSICR1_SOF_POL; | |
535 | if (common_flags & SOCAM_DATA_ACTIVE_LOW) | |
536 | csicr1 |= CSICR1_DATA_POL; | |
537 | ||
538 | __raw_writel(csicr1, pcdev->base + CSICR1); | |
539 | ||
540 | return 0; | |
541 | } | |
542 | ||
543 | static int mx1_camera_set_fmt(struct soc_camera_device *icd, | |
544 | struct v4l2_format *f) | |
545 | { | |
546 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); | |
547 | const struct soc_camera_format_xlate *xlate; | |
548 | struct v4l2_pix_format *pix = &f->fmt.pix; | |
549 | int ret; | |
550 | ||
551 | xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat); | |
552 | if (!xlate) { | |
eff505fa | 553 | dev_warn(ici->dev, "Format %x not found\n", pix->pixelformat); |
6acc81c3 PZ |
554 | return -EINVAL; |
555 | } | |
556 | ||
557 | ret = icd->ops->set_fmt(icd, f); | |
558 | if (!ret) { | |
559 | icd->buswidth = xlate->buswidth; | |
560 | icd->current_fmt = xlate->host_fmt; | |
561 | } | |
562 | ||
563 | return ret; | |
564 | } | |
565 | ||
566 | static int mx1_camera_try_fmt(struct soc_camera_device *icd, | |
567 | struct v4l2_format *f) | |
568 | { | |
569 | /* TODO: limit to mx1 hardware capabilities */ | |
570 | ||
571 | /* limit to sensor capabilities */ | |
572 | return icd->ops->try_fmt(icd, f); | |
573 | } | |
574 | ||
575 | static int mx1_camera_reqbufs(struct soc_camera_file *icf, | |
576 | struct v4l2_requestbuffers *p) | |
577 | { | |
578 | int i; | |
579 | ||
580 | /* This is for locking debugging only. I removed spinlocks and now I | |
581 | * check whether .prepare is ever called on a linked buffer, or whether | |
582 | * a dma IRQ can occur for an in-work or unlinked buffer. Until now | |
583 | * it hadn't triggered */ | |
584 | for (i = 0; i < p->count; i++) { | |
585 | struct mx1_buffer *buf = container_of(icf->vb_vidq.bufs[i], | |
586 | struct mx1_buffer, vb); | |
587 | buf->inwork = 0; | |
588 | INIT_LIST_HEAD(&buf->vb.queue); | |
589 | } | |
590 | ||
591 | return 0; | |
592 | } | |
593 | ||
594 | static unsigned int mx1_camera_poll(struct file *file, poll_table *pt) | |
595 | { | |
596 | struct soc_camera_file *icf = file->private_data; | |
597 | struct mx1_buffer *buf; | |
598 | ||
599 | buf = list_entry(icf->vb_vidq.stream.next, struct mx1_buffer, | |
600 | vb.stream); | |
601 | ||
602 | poll_wait(file, &buf->vb.done, pt); | |
603 | ||
604 | if (buf->vb.state == VIDEOBUF_DONE || | |
605 | buf->vb.state == VIDEOBUF_ERROR) | |
606 | return POLLIN | POLLRDNORM; | |
607 | ||
608 | return 0; | |
609 | } | |
610 | ||
611 | static int mx1_camera_querycap(struct soc_camera_host *ici, | |
612 | struct v4l2_capability *cap) | |
613 | { | |
614 | /* cap->name is set by the friendly caller:-> */ | |
615 | strlcpy(cap->card, "i.MX1/i.MXL Camera", sizeof(cap->card)); | |
616 | cap->version = VERSION_CODE; | |
617 | cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; | |
618 | ||
619 | return 0; | |
620 | } | |
621 | ||
622 | static struct soc_camera_host_ops mx1_soc_camera_host_ops = { | |
623 | .owner = THIS_MODULE, | |
624 | .add = mx1_camera_add_device, | |
625 | .remove = mx1_camera_remove_device, | |
626 | .set_bus_param = mx1_camera_set_bus_param, | |
627 | .set_crop = mx1_camera_set_crop, | |
628 | .set_fmt = mx1_camera_set_fmt, | |
629 | .try_fmt = mx1_camera_try_fmt, | |
630 | .init_videobuf = mx1_camera_init_videobuf, | |
631 | .reqbufs = mx1_camera_reqbufs, | |
632 | .poll = mx1_camera_poll, | |
633 | .querycap = mx1_camera_querycap, | |
634 | }; | |
635 | ||
6acc81c3 PZ |
636 | static struct fiq_handler fh = { |
637 | .name = "csi_sof" | |
638 | }; | |
639 | ||
640 | static int __init mx1_camera_probe(struct platform_device *pdev) | |
641 | { | |
642 | struct mx1_camera_dev *pcdev; | |
643 | struct resource *res; | |
644 | struct pt_regs regs; | |
645 | struct clk *clk; | |
646 | void __iomem *base; | |
647 | unsigned int irq; | |
648 | int err = 0; | |
649 | ||
650 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
651 | irq = platform_get_irq(pdev, 0); | |
652 | if (!res || !irq) { | |
653 | err = -ENODEV; | |
654 | goto exit; | |
655 | } | |
656 | ||
657 | clk = clk_get(&pdev->dev, "csi_clk"); | |
658 | if (IS_ERR(clk)) { | |
659 | err = PTR_ERR(clk); | |
660 | goto exit; | |
661 | } | |
662 | ||
663 | pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL); | |
664 | if (!pcdev) { | |
665 | dev_err(&pdev->dev, "Could not allocate pcdev\n"); | |
666 | err = -ENOMEM; | |
667 | goto exit_put_clk; | |
668 | } | |
669 | ||
6acc81c3 PZ |
670 | pcdev->res = res; |
671 | pcdev->clk = clk; | |
672 | ||
673 | pcdev->pdata = pdev->dev.platform_data; | |
674 | ||
675 | if (pcdev->pdata) | |
676 | pcdev->mclk = pcdev->pdata->mclk_10khz * 10000; | |
677 | ||
678 | if (!pcdev->mclk) { | |
679 | dev_warn(&pdev->dev, | |
680 | "mclk_10khz == 0! Please, fix your platform data. " | |
681 | "Using default 20MHz\n"); | |
682 | pcdev->mclk = 20000000; | |
683 | } | |
684 | ||
685 | INIT_LIST_HEAD(&pcdev->capture); | |
686 | spin_lock_init(&pcdev->lock); | |
687 | ||
688 | /* | |
689 | * Request the regions. | |
690 | */ | |
691 | if (!request_mem_region(res->start, resource_size(res), DRIVER_NAME)) { | |
692 | err = -EBUSY; | |
693 | goto exit_kfree; | |
694 | } | |
695 | ||
696 | base = ioremap(res->start, resource_size(res)); | |
697 | if (!base) { | |
698 | err = -ENOMEM; | |
699 | goto exit_release; | |
700 | } | |
701 | pcdev->irq = irq; | |
702 | pcdev->base = base; | |
6acc81c3 PZ |
703 | |
704 | /* request dma */ | |
705 | pcdev->dma_chan = imx_dma_request_by_prio(DRIVER_NAME, DMA_PRIO_HIGH); | |
706 | if (pcdev->dma_chan < 0) { | |
eff505fa | 707 | dev_err(&pdev->dev, "Can't request DMA for MX1 CSI\n"); |
6acc81c3 PZ |
708 | err = -EBUSY; |
709 | goto exit_iounmap; | |
710 | } | |
eff505fa | 711 | dev_dbg(&pdev->dev, "got DMA channel %d\n", pcdev->dma_chan); |
6acc81c3 PZ |
712 | |
713 | imx_dma_setup_handlers(pcdev->dma_chan, mx1_camera_dma_irq, NULL, | |
714 | pcdev); | |
715 | ||
716 | imx_dma_config_channel(pcdev->dma_chan, IMX_DMA_TYPE_FIFO, | |
717 | IMX_DMA_MEMSIZE_32, DMA_REQ_CSI_R, 0); | |
718 | /* burst length : 16 words = 64 bytes */ | |
719 | imx_dma_config_burstlen(pcdev->dma_chan, 0); | |
720 | ||
721 | /* request irq */ | |
722 | err = claim_fiq(&fh); | |
723 | if (err) { | |
eff505fa | 724 | dev_err(&pdev->dev, "Camera interrupt register failed \n"); |
6acc81c3 PZ |
725 | goto exit_free_dma; |
726 | } | |
727 | ||
728 | set_fiq_handler(&mx1_camera_sof_fiq_start, &mx1_camera_sof_fiq_end - | |
729 | &mx1_camera_sof_fiq_start); | |
730 | ||
731 | regs.ARM_r8 = DMA_BASE + DMA_DIMR; | |
732 | regs.ARM_r9 = DMA_BASE + DMA_CCR(pcdev->dma_chan); | |
733 | regs.ARM_r10 = (long)pcdev->base + CSICR1; | |
734 | regs.ARM_fp = (long)pcdev->base + CSISR; | |
735 | regs.ARM_sp = 1 << pcdev->dma_chan; | |
736 | set_fiq_regs(®s); | |
737 | ||
738 | mxc_set_irq_fiq(irq, 1); | |
739 | enable_fiq(irq); | |
740 | ||
eb6c8558 GL |
741 | pcdev->soc_host.drv_name = DRIVER_NAME; |
742 | pcdev->soc_host.ops = &mx1_soc_camera_host_ops; | |
743 | pcdev->soc_host.priv = pcdev; | |
eff505fa | 744 | pcdev->soc_host.dev = &pdev->dev; |
eb6c8558 GL |
745 | pcdev->soc_host.nr = pdev->id; |
746 | err = soc_camera_host_register(&pcdev->soc_host); | |
6acc81c3 PZ |
747 | if (err) |
748 | goto exit_free_irq; | |
749 | ||
750 | dev_info(&pdev->dev, "MX1 Camera driver loaded\n"); | |
751 | ||
752 | return 0; | |
753 | ||
754 | exit_free_irq: | |
755 | disable_fiq(irq); | |
756 | mxc_set_irq_fiq(irq, 0); | |
757 | release_fiq(&fh); | |
758 | exit_free_dma: | |
759 | imx_dma_free(pcdev->dma_chan); | |
760 | exit_iounmap: | |
761 | iounmap(base); | |
762 | exit_release: | |
763 | release_mem_region(res->start, resource_size(res)); | |
764 | exit_kfree: | |
765 | kfree(pcdev); | |
766 | exit_put_clk: | |
767 | clk_put(clk); | |
768 | exit: | |
769 | return err; | |
770 | } | |
771 | ||
772 | static int __exit mx1_camera_remove(struct platform_device *pdev) | |
773 | { | |
eff505fa GL |
774 | struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev); |
775 | struct mx1_camera_dev *pcdev = container_of(soc_host, | |
776 | struct mx1_camera_dev, soc_host); | |
6acc81c3 PZ |
777 | struct resource *res; |
778 | ||
779 | imx_dma_free(pcdev->dma_chan); | |
780 | disable_fiq(pcdev->irq); | |
781 | mxc_set_irq_fiq(pcdev->irq, 0); | |
782 | release_fiq(&fh); | |
783 | ||
784 | clk_put(pcdev->clk); | |
785 | ||
eff505fa | 786 | soc_camera_host_unregister(soc_host); |
6acc81c3 PZ |
787 | |
788 | iounmap(pcdev->base); | |
789 | ||
790 | res = pcdev->res; | |
791 | release_mem_region(res->start, resource_size(res)); | |
792 | ||
793 | kfree(pcdev); | |
794 | ||
795 | dev_info(&pdev->dev, "MX1 Camera driver unloaded\n"); | |
796 | ||
797 | return 0; | |
798 | } | |
799 | ||
800 | static struct platform_driver mx1_camera_driver = { | |
801 | .driver = { | |
802 | .name = DRIVER_NAME, | |
803 | }, | |
804 | .remove = __exit_p(mx1_camera_remove), | |
805 | }; | |
806 | ||
807 | static int __init mx1_camera_init(void) | |
808 | { | |
809 | return platform_driver_probe(&mx1_camera_driver, mx1_camera_probe); | |
810 | } | |
811 | ||
812 | static void __exit mx1_camera_exit(void) | |
813 | { | |
814 | return platform_driver_unregister(&mx1_camera_driver); | |
815 | } | |
816 | ||
817 | module_init(mx1_camera_init); | |
818 | module_exit(mx1_camera_exit); | |
819 | ||
820 | MODULE_DESCRIPTION("i.MX1/i.MXL SoC Camera Host driver"); | |
821 | MODULE_AUTHOR("Paulius Zaleckas <paulius.zaleckas@teltonika.lt>"); | |
822 | MODULE_LICENSE("GPL v2"); | |
823 | MODULE_ALIAS("platform:" DRIVER_NAME); |