Commit | Line | Data |
---|---|---|
a6c2ba28 | 1 | /* |
0e7072ef | 2 | em28xx.h - driver for Empia EM2800/EM2820/2840 USB video capture devices |
a6c2ba28 AM |
3 | |
4 | Copyright (C) 2005 Markus Rechberger <mrechberger@gmail.com> | |
4ac97914 | 5 | Ludovico Cavedon <cavedon@sssup.it> |
2e7c6dc3 | 6 | Mauro Carvalho Chehab <mchehab@infradead.org> |
a6c2ba28 AM |
7 | |
8 | Based on the em2800 driver from Sascha Sommer <saschasommer@freenet.de> | |
9 | ||
10 | This program is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2 of the License, or | |
13 | (at your option) any later version. | |
14 | ||
15 | This program is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with this program; if not, write to the Free Software | |
22 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
23 | */ | |
24 | ||
3acf2809 MCC |
25 | #ifndef _EM28XX_H |
26 | #define _EM28XX_H | |
a6c2ba28 | 27 | |
cb77d010 | 28 | #include <linux/videodev2.h> |
ad0ebb96 | 29 | #include <media/videobuf-vmalloc.h> |
f2cf250a | 30 | #include <media/v4l2-device.h> |
ad0ebb96 | 31 | |
a6c2ba28 | 32 | #include <linux/i2c.h> |
3593cab5 | 33 | #include <linux/mutex.h> |
d5e52653 | 34 | #include <media/ir-kbd-i2c.h> |
3aefb79a MCC |
35 | #if defined(CONFIG_VIDEO_EM28XX_DVB) || defined(CONFIG_VIDEO_EM28XX_DVB_MODULE) |
36 | #include <media/videobuf-dvb.h> | |
37 | #endif | |
3ca9c093 | 38 | #include "tuner-xc2028.h" |
2ba890ec | 39 | #include "em28xx-reg.h" |
3aefb79a MCC |
40 | |
41 | /* Boards supported by driver */ | |
42 | #define EM2800_BOARD_UNKNOWN 0 | |
43 | #define EM2820_BOARD_UNKNOWN 1 | |
44 | #define EM2820_BOARD_TERRATEC_CINERGY_250 2 | |
45 | #define EM2820_BOARD_PINNACLE_USB_2 3 | |
46 | #define EM2820_BOARD_HAUPPAUGE_WINTV_USB_2 4 | |
47 | #define EM2820_BOARD_MSI_VOX_USB_2 5 | |
48 | #define EM2800_BOARD_TERRATEC_CINERGY_200 6 | |
49 | #define EM2800_BOARD_LEADTEK_WINFAST_USBII 7 | |
50 | #define EM2800_BOARD_KWORLD_USB2800 8 | |
51 | #define EM2820_BOARD_PINNACLE_DVC_90 9 | |
52 | #define EM2880_BOARD_HAUPPAUGE_WINTV_HVR_900 10 | |
53 | #define EM2880_BOARD_TERRATEC_HYBRID_XS 11 | |
54 | #define EM2820_BOARD_KWORLD_PVRTV2800RF 12 | |
55 | #define EM2880_BOARD_TERRATEC_PRODIGY_XS 13 | |
56 | #define EM2820_BOARD_PROLINK_PLAYTV_USB2 14 | |
57 | #define EM2800_BOARD_VGEAR_POCKETTV 15 | |
10ac6603 | 58 | #define EM2883_BOARD_HAUPPAUGE_WINTV_HVR_950 16 |
4fd305b2 | 59 | #define EM2880_BOARD_PINNACLE_PCTV_HD_PRO 17 |
17d9d558 | 60 | #define EM2880_BOARD_HAUPPAUGE_WINTV_HVR_900_R2 18 |
3ed58baf | 61 | #define EM2860_BOARD_SAA711X_REFERENCE_DESIGN 19 |
e14b3658 | 62 | #define EM2880_BOARD_AMD_ATI_TV_WONDER_HD_600 20 |
59d07f1b | 63 | #define EM2800_BOARD_GRABBEEX_USB2800 21 |
95b86a9a DSL |
64 | #define EM2750_BOARD_UNKNOWN 22 |
65 | #define EM2750_BOARD_DLCW_130 23 | |
66 | #define EM2820_BOARD_DLINK_USB_TV 24 | |
67 | #define EM2820_BOARD_GADMEI_UTV310 25 | |
68 | #define EM2820_BOARD_HERCULES_SMART_TV_USB2 26 | |
69 | #define EM2820_BOARD_PINNACLE_USB_2_FM1216ME 27 | |
70 | #define EM2820_BOARD_LEADTEK_WINFAST_USBII_DELUXE 28 | |
95b86a9a DSL |
71 | #define EM2820_BOARD_VIDEOLOGY_20K14XUSB 30 |
72 | #define EM2821_BOARD_USBGEAR_VD204 31 | |
73 | #define EM2821_BOARD_SUPERCOMP_USB_2 32 | |
95b86a9a DSL |
74 | #define EM2860_BOARD_TERRATEC_HYBRID_XS 34 |
75 | #define EM2860_BOARD_TYPHOON_DVD_MAKER 35 | |
76 | #define EM2860_BOARD_NETGMBH_CAM 36 | |
77 | #define EM2860_BOARD_GADMEI_UTV330 37 | |
78 | #define EM2861_BOARD_YAKUMO_MOVIE_MIXER 38 | |
79 | #define EM2861_BOARD_KWORLD_PVRTV_300U 39 | |
80 | #define EM2861_BOARD_PLEXTOR_PX_TV100U 40 | |
81 | #define EM2870_BOARD_KWORLD_350U 41 | |
82 | #define EM2870_BOARD_KWORLD_355U 42 | |
83 | #define EM2870_BOARD_TERRATEC_XS 43 | |
84 | #define EM2870_BOARD_TERRATEC_XS_MT2060 44 | |
85 | #define EM2870_BOARD_PINNACLE_PCTV_DVB 45 | |
86 | #define EM2870_BOARD_COMPRO_VIDEOMATE 46 | |
87 | #define EM2880_BOARD_KWORLD_DVB_305U 47 | |
88 | #define EM2880_BOARD_KWORLD_DVB_310U 48 | |
89 | #define EM2880_BOARD_MSI_DIGIVOX_AD 49 | |
90 | #define EM2880_BOARD_MSI_DIGIVOX_AD_II 50 | |
91 | #define EM2880_BOARD_TERRATEC_HYBRID_XS_FR 51 | |
92 | #define EM2881_BOARD_DNT_DA2_HYBRID 52 | |
93 | #define EM2881_BOARD_PINNACLE_HYBRID_PRO 53 | |
94 | #define EM2882_BOARD_KWORLD_VS_DVBT 54 | |
95 | #define EM2882_BOARD_TERRATEC_HYBRID_XS 55 | |
96 | #define EM2882_BOARD_PINNACLE_HYBRID_PRO 56 | |
6e7b9ea0 | 97 | #define EM2883_BOARD_KWORLD_HYBRID_330U 57 |
ee281b85 | 98 | #define EM2820_BOARD_COMPRO_VIDEOMATE_FORYOU 58 |
f89bc329 | 99 | #define EM2883_BOARD_HAUPPAUGE_WINTV_HVR_850 60 |
1e1addd5 | 100 | #define EM2820_BOARD_PROLINK_PLAYTV_BOX4_USB2 61 |
f7fe3e6f | 101 | #define EM2820_BOARD_GADMEI_TVR200 62 |
56ee3807 MCC |
102 | #define EM2860_BOARD_KAIOMY_TVNPC_U2 63 |
103 | #define EM2860_BOARD_EASYCAP 64 | |
f74a61e3 | 104 | #define EM2820_BOARD_IODATA_GVMVP_SZ 65 |
e5db5d44 | 105 | #define EM2880_BOARD_EMPIRE_DUAL_TV 66 |
4557af9c | 106 | #define EM2860_BOARD_TERRATEC_GRABBY 67 |
766ed64d | 107 | #define EM2860_BOARD_TERRATEC_AV350 68 |
d7de5d8f | 108 | #define EM2882_BOARD_KWORLD_ATSC_315U 69 |
19859229 | 109 | #define EM2882_BOARD_EVGA_INDTUBE 70 |
02e7804b | 110 | #define EM2820_BOARD_SILVERCREST_WEBCAM 71 |
6d888a66 | 111 | #define EM2861_BOARD_GADMEI_UTV330PLUS 72 |
3aefb79a MCC |
112 | |
113 | /* Limits minimum and default number of buffers */ | |
114 | #define EM28XX_MIN_BUF 4 | |
115 | #define EM28XX_DEF_BUF 8 | |
a6c2ba28 | 116 | |
c4a98793 MCC |
117 | /*Limits the max URB message size */ |
118 | #define URB_MAX_CTRL_SIZE 80 | |
119 | ||
95b86a9a DSL |
120 | /* Params for validated field */ |
121 | #define EM28XX_BOARD_NOT_VALIDATED 1 | |
122 | #define EM28XX_BOARD_VALIDATED 0 | |
123 | ||
22cff7b3 DSL |
124 | /* Params for em28xx_cmd() audio */ |
125 | #define EM28XX_START_AUDIO 1 | |
126 | #define EM28XX_STOP_AUDIO 0 | |
127 | ||
596d92d5 | 128 | /* maximum number of em28xx boards */ |
3687e1e6 | 129 | #define EM28XX_MAXBOARDS 4 /*FIXME: should be bigger */ |
596d92d5 | 130 | |
a6c2ba28 | 131 | /* maximum number of frames that can be queued */ |
3acf2809 | 132 | #define EM28XX_NUM_FRAMES 5 |
a6c2ba28 | 133 | /* number of frames that get used for v4l2_read() */ |
3acf2809 | 134 | #define EM28XX_NUM_READ_FRAMES 2 |
a6c2ba28 AM |
135 | |
136 | /* number of buffers for isoc transfers */ | |
3acf2809 | 137 | #define EM28XX_NUM_BUFS 5 |
a6c2ba28 | 138 | |
d5e52653 MCC |
139 | /* number of packets for each buffer |
140 | windows requests only 40 packets .. so we better do the same | |
141 | this is what I found out for all alternate numbers there! | |
142 | */ | |
3acf2809 | 143 | #define EM28XX_NUM_PACKETS 40 |
a6c2ba28 | 144 | |
a6c2ba28 | 145 | /* default alternate; 0 means choose the best */ |
3acf2809 | 146 | #define EM28XX_PINOUT 0 |
a6c2ba28 | 147 | |
3acf2809 | 148 | #define EM28XX_INTERLACED_DEFAULT 1 |
a6c2ba28 AM |
149 | |
150 | /* | |
151 | #define (use usbview if you want to get the other alternate number infos) | |
152 | #define | |
153 | #define alternate number 2 | |
154 | #define Endpoint Address: 82 | |
155 | Direction: in | |
156 | Attribute: 1 | |
157 | Type: Isoc | |
158 | Max Packet Size: 1448 | |
159 | Interval: 125us | |
160 | ||
161 | alternate number 7 | |
162 | ||
163 | Endpoint Address: 82 | |
164 | Direction: in | |
165 | Attribute: 1 | |
166 | Type: Isoc | |
167 | Max Packet Size: 3072 | |
168 | Interval: 125us | |
169 | */ | |
170 | ||
171 | /* time to wait when stopping the isoc transfer */ | |
a1a6ee74 NS |
172 | #define EM28XX_URB_TIMEOUT \ |
173 | msecs_to_jiffies(EM28XX_NUM_BUFS * EM28XX_NUM_PACKETS) | |
a6c2ba28 | 174 | |
596d92d5 MCC |
175 | /* time in msecs to wait for i2c writes to finish */ |
176 | #define EM2800_I2C_WRITE_TIMEOUT 20 | |
177 | ||
3aefb79a | 178 | enum em28xx_mode { |
2fe3e2ee | 179 | EM28XX_SUSPEND, |
3aefb79a MCC |
180 | EM28XX_ANALOG_MODE, |
181 | EM28XX_DIGITAL_MODE, | |
182 | }; | |
183 | ||
3acf2809 | 184 | enum em28xx_stream_state { |
a6c2ba28 AM |
185 | STREAM_OFF, |
186 | STREAM_INTERRUPT, | |
187 | STREAM_ON, | |
188 | }; | |
189 | ||
579f72e4 AT |
190 | struct em28xx; |
191 | ||
ad0ebb96 MCC |
192 | struct em28xx_usb_isoc_ctl { |
193 | /* max packet size of isoc transaction */ | |
194 | int max_pkt_size; | |
195 | ||
196 | /* number of allocated urbs */ | |
197 | int num_bufs; | |
198 | ||
199 | /* urb for isoc transfers */ | |
200 | struct urb **urb; | |
201 | ||
202 | /* transfer buffers for isoc transfer */ | |
203 | char **transfer_buffer; | |
204 | ||
205 | /* Last buffer command and region */ | |
206 | u8 cmd; | |
207 | int pos, size, pktsize; | |
208 | ||
209 | /* Last field: ODD or EVEN? */ | |
210 | int field; | |
211 | ||
212 | /* Stores incomplete commands */ | |
213 | u32 tmp_buf; | |
214 | int tmp_buf_len; | |
215 | ||
216 | /* Stores already requested buffers */ | |
217 | struct em28xx_buffer *buf; | |
218 | ||
219 | /* Stores the number of received fields */ | |
220 | int nfields; | |
579f72e4 AT |
221 | |
222 | /* isoc urb callback */ | |
223 | int (*isoc_copy) (struct em28xx *dev, struct urb *urb); | |
224 | ||
ad0ebb96 MCC |
225 | }; |
226 | ||
bddcf633 | 227 | /* Struct to enumberate video formats */ |
ad0ebb96 MCC |
228 | struct em28xx_fmt { |
229 | char *name; | |
230 | u32 fourcc; /* v4l2 format id */ | |
bddcf633 MCC |
231 | int depth; |
232 | int reg; | |
ad0ebb96 MCC |
233 | }; |
234 | ||
235 | /* buffer for one video frame */ | |
236 | struct em28xx_buffer { | |
237 | /* common v4l buffer stuff -- must be first */ | |
238 | struct videobuf_buffer vb; | |
239 | ||
a6c2ba28 | 240 | struct list_head frame; |
a6c2ba28 | 241 | int top_field; |
ad0ebb96 MCC |
242 | int receiving; |
243 | }; | |
244 | ||
245 | struct em28xx_dmaqueue { | |
246 | struct list_head active; | |
247 | struct list_head queued; | |
ad0ebb96 MCC |
248 | |
249 | wait_queue_head_t wq; | |
250 | ||
251 | /* Counters to control buffer fill */ | |
252 | int pos; | |
a6c2ba28 AM |
253 | }; |
254 | ||
255 | /* io methods */ | |
3acf2809 | 256 | enum em28xx_io_method { |
a6c2ba28 AM |
257 | IO_NONE, |
258 | IO_READ, | |
259 | IO_MMAP, | |
260 | }; | |
261 | ||
262 | /* inputs */ | |
263 | ||
3acf2809 MCC |
264 | #define MAX_EM28XX_INPUT 4 |
265 | enum enum28xx_itype { | |
266 | EM28XX_VMUX_COMPOSITE1 = 1, | |
267 | EM28XX_VMUX_COMPOSITE2, | |
268 | EM28XX_VMUX_COMPOSITE3, | |
269 | EM28XX_VMUX_COMPOSITE4, | |
270 | EM28XX_VMUX_SVIDEO, | |
271 | EM28XX_VMUX_TELEVISION, | |
272 | EM28XX_VMUX_CABLE, | |
273 | EM28XX_VMUX_DVB, | |
274 | EM28XX_VMUX_DEBUG, | |
275 | EM28XX_RADIO, | |
a6c2ba28 AM |
276 | }; |
277 | ||
35643943 MCC |
278 | enum em28xx_ac97_mode { |
279 | EM28XX_NO_AC97 = 0, | |
280 | EM28XX_AC97_EM202, | |
209acc02 | 281 | EM28XX_AC97_SIGMATEL, |
35643943 MCC |
282 | EM28XX_AC97_OTHER, |
283 | }; | |
284 | ||
285 | struct em28xx_audio_mode { | |
286 | enum em28xx_ac97_mode ac97; | |
287 | ||
288 | u16 ac97_feat; | |
16c7bcad | 289 | u32 ac97_vendor_id; |
35643943 MCC |
290 | |
291 | unsigned int has_audio:1; | |
292 | ||
293 | unsigned int i2s_3rates:1; | |
294 | unsigned int i2s_5rates:1; | |
5c2231c8 DH |
295 | }; |
296 | ||
5faff789 MCC |
297 | /* em28xx has two audio inputs: tuner and line in. |
298 | However, on most devices, an auxiliary AC97 codec device is used. | |
299 | The AC97 device may have several different inputs and outputs, | |
300 | depending on their model. So, it is possible to use AC97 mixer to | |
301 | address more than two different entries. | |
302 | */ | |
539c96d0 | 303 | enum em28xx_amux { |
5faff789 MCC |
304 | /* This is the only entry for em28xx tuner input */ |
305 | EM28XX_AMUX_VIDEO, /* em28xx tuner, AC97 mixer Video */ | |
306 | ||
307 | EM28XX_AMUX_LINE_IN, /* AC97 mixer Line In */ | |
308 | ||
309 | /* Some less-common mixer setups */ | |
310 | EM28XX_AMUX_VIDEO2, /* em28xx Line in, AC97 mixer Video */ | |
311 | EM28XX_AMUX_PHONE, | |
312 | EM28XX_AMUX_MIC, | |
313 | EM28XX_AMUX_CD, | |
314 | EM28XX_AMUX_AUX, | |
315 | EM28XX_AMUX_PCM_OUT, | |
539c96d0 MCC |
316 | }; |
317 | ||
35ae6f04 | 318 | enum em28xx_aout { |
8866f9cf | 319 | /* AC97 outputs */ |
e879b8eb MCC |
320 | EM28XX_AOUT_MASTER = 1 << 0, |
321 | EM28XX_AOUT_LINE = 1 << 1, | |
322 | EM28XX_AOUT_MONO = 1 << 2, | |
323 | EM28XX_AOUT_LFE = 1 << 3, | |
324 | EM28XX_AOUT_SURR = 1 << 4, | |
8866f9cf MCC |
325 | |
326 | /* PCM IN Mixer - used by AC97_RECORD_SELECT register */ | |
327 | EM28XX_AOUT_PCM_IN = 1 << 7, | |
328 | ||
329 | /* Bits 10-8 are used to indicate the PCM IN record select */ | |
330 | EM28XX_AOUT_PCM_MIC_PCM = 0 << 8, | |
331 | EM28XX_AOUT_PCM_CD = 1 << 8, | |
332 | EM28XX_AOUT_PCM_VIDEO = 2 << 8, | |
333 | EM28XX_AOUT_PCM_AUX = 3 << 8, | |
334 | EM28XX_AOUT_PCM_LINE = 4 << 8, | |
335 | EM28XX_AOUT_PCM_STEREO = 5 << 8, | |
336 | EM28XX_AOUT_PCM_MONO = 6 << 8, | |
337 | EM28XX_AOUT_PCM_PHONE = 7 << 8, | |
35ae6f04 MCC |
338 | }; |
339 | ||
32929fb4 | 340 | static inline int ac97_return_record_select(int a_out) |
8866f9cf MCC |
341 | { |
342 | return (a_out & 0x700) >> 8; | |
343 | } | |
344 | ||
122b77e5 MCC |
345 | struct em28xx_reg_seq { |
346 | int reg; | |
347 | unsigned char val, mask; | |
348 | int sleep; | |
349 | }; | |
350 | ||
3acf2809 MCC |
351 | struct em28xx_input { |
352 | enum enum28xx_itype type; | |
a6c2ba28 | 353 | unsigned int vmux; |
539c96d0 | 354 | enum em28xx_amux amux; |
35ae6f04 | 355 | enum em28xx_aout aout; |
122b77e5 | 356 | struct em28xx_reg_seq *gpio; |
a6c2ba28 AM |
357 | }; |
358 | ||
3acf2809 | 359 | #define INPUT(nr) (&em28xx_boards[dev->model].input[nr]) |
a6c2ba28 | 360 | |
3acf2809 | 361 | enum em28xx_decoder { |
527f09a9 | 362 | EM28XX_NODECODER = 0, |
3acf2809 | 363 | EM28XX_TVP5150, |
ec5de990 | 364 | EM28XX_SAA711X, |
527f09a9 MCC |
365 | }; |
366 | ||
367 | enum em28xx_sensor { | |
368 | EM28XX_NOSENSOR = 0, | |
02e7804b | 369 | EM28XX_MT9V011, |
b80fd2d8 | 370 | EM28XX_MT9M001, |
f2e26ae7 | 371 | EM28XX_MT9M111, |
a6c2ba28 AM |
372 | }; |
373 | ||
df7fa09c MCC |
374 | enum em28xx_adecoder { |
375 | EM28XX_NOADECODER = 0, | |
376 | EM28XX_TVAUDIO, | |
377 | }; | |
378 | ||
3acf2809 | 379 | struct em28xx_board { |
a6c2ba28 | 380 | char *name; |
505b6d0b | 381 | int vchannels; |
a6c2ba28 | 382 | int tuner_type; |
66767920 | 383 | int tuner_addr; |
a6c2ba28 AM |
384 | |
385 | /* i2c flags */ | |
386 | unsigned int tda9887_conf; | |
387 | ||
017ab4b1 | 388 | /* GPIO sequences */ |
122b77e5 | 389 | struct em28xx_reg_seq *dvb_gpio; |
2fe3e2ee | 390 | struct em28xx_reg_seq *suspend_gpio; |
017ab4b1 | 391 | struct em28xx_reg_seq *tuner_gpio; |
2bd1d9eb | 392 | struct em28xx_reg_seq *mute_gpio; |
122b77e5 | 393 | |
74f38a82 | 394 | unsigned int is_em2800:1; |
a6c2ba28 | 395 | unsigned int has_msp34xx:1; |
5add9a6f | 396 | unsigned int mts_firmware:1; |
c8793b03 | 397 | unsigned int max_range_640_480:1; |
3aefb79a | 398 | unsigned int has_dvb:1; |
a9fc52bc | 399 | unsigned int has_snapshot_button:1; |
c43221df | 400 | unsigned int is_webcam:1; |
95b86a9a | 401 | unsigned int valid:1; |
3abee53e | 402 | |
a2070c66 | 403 | unsigned char xclk, i2c_speed; |
f2cf250a DSL |
404 | unsigned char radio_addr; |
405 | unsigned short tvaudio_addr; | |
a2070c66 | 406 | |
3acf2809 | 407 | enum em28xx_decoder decoder; |
df7fa09c | 408 | enum em28xx_adecoder adecoder; |
a6c2ba28 | 409 | |
3acf2809 | 410 | struct em28xx_input input[MAX_EM28XX_INPUT]; |
0be43754 | 411 | struct em28xx_input radio; |
715a2233 | 412 | struct ir_scancode_table *ir_codes; |
a6c2ba28 AM |
413 | }; |
414 | ||
3acf2809 | 415 | struct em28xx_eeprom { |
a6c2ba28 AM |
416 | u32 id; /* 0x9567eb1a */ |
417 | u16 vendor_ID; | |
418 | u16 product_ID; | |
419 | ||
420 | u16 chip_conf; | |
421 | ||
422 | u16 board_conf; | |
423 | ||
424 | u16 string1, string2, string3; | |
425 | ||
426 | u8 string_idx_table; | |
427 | }; | |
428 | ||
429 | /* device states */ | |
3acf2809 | 430 | enum em28xx_dev_state { |
a6c2ba28 AM |
431 | DEV_INITIALIZED = 0x01, |
432 | DEV_DISCONNECTED = 0x02, | |
433 | DEV_MISCONFIGURED = 0x04, | |
434 | }; | |
435 | ||
6d79468d MCC |
436 | #define EM28XX_AUDIO_BUFS 5 |
437 | #define EM28XX_NUM_AUDIO_PACKETS 64 | |
438 | #define EM28XX_AUDIO_MAX_PACKET_SIZE 196 /* static value */ | |
439 | #define EM28XX_CAPTURE_STREAM_EN 1 | |
3aefb79a MCC |
440 | |
441 | /* em28xx extensions */ | |
6d79468d | 442 | #define EM28XX_AUDIO 0x10 |
3aefb79a | 443 | #define EM28XX_DVB 0x20 |
6d79468d MCC |
444 | |
445 | struct em28xx_audio { | |
446 | char name[50]; | |
447 | char *transfer_buffer[EM28XX_AUDIO_BUFS]; | |
448 | struct urb *urb[EM28XX_AUDIO_BUFS]; | |
449 | struct usb_device *udev; | |
450 | unsigned int capture_transfer_done; | |
451 | struct snd_pcm_substream *capture_pcm_substream; | |
452 | ||
453 | unsigned int hwptr_done_capture; | |
454 | struct snd_card *sndcard; | |
455 | ||
c744dff2 | 456 | int users; |
6d79468d MCC |
457 | enum em28xx_stream_state capture_stream; |
458 | spinlock_t slock; | |
459 | }; | |
460 | ||
52284c3e MCC |
461 | struct em28xx; |
462 | ||
463 | struct em28xx_fh { | |
464 | struct em28xx *dev; | |
465 | unsigned int stream_on:1; /* Locks streams */ | |
466 | int radio; | |
467 | ||
468 | struct videobuf_queue vb_vidq; | |
469 | ||
470 | enum v4l2_buf_type type; | |
471 | }; | |
472 | ||
a6c2ba28 | 473 | /* main device struct */ |
3acf2809 | 474 | struct em28xx { |
a6c2ba28 AM |
475 | /* generic device properties */ |
476 | char name[30]; /* name (including minor) of the device */ | |
477 | int model; /* index in the device_data struct */ | |
e5589bef | 478 | int devno; /* marks the number of this device */ |
600bd7f0 | 479 | enum em28xx_chip_id chip_id; |
505b6d0b | 480 | |
f2cf250a | 481 | struct v4l2_device v4l2_dev; |
505b6d0b MCC |
482 | struct em28xx_board board; |
483 | ||
d36bb4e7 | 484 | /* Webcam specific fields */ |
527f09a9 | 485 | enum em28xx_sensor em28xx_sensor; |
55699964 | 486 | int sensor_xres, sensor_yres; |
d36bb4e7 | 487 | int sensor_xtal; |
527f09a9 | 488 | |
c2a6b54a MCC |
489 | /* Allows progressive (e. g. non-interlaced) mode */ |
490 | int progressive; | |
491 | ||
579d3152 MCC |
492 | /* Vinmode/Vinctl used at the driver */ |
493 | int vinmode, vinctl; | |
494 | ||
a225452e | 495 | unsigned int stream_on:1; /* Locks streams */ |
d7448a8d | 496 | unsigned int has_audio_class:1; |
24a613e4 | 497 | unsigned int has_alsa_audio:1; |
a2070c66 | 498 | |
bddcf633 MCC |
499 | struct em28xx_fmt *format; |
500 | ||
a924a499 MCC |
501 | struct em28xx_IR *ir; |
502 | ||
89b329ef MCC |
503 | /* Some older em28xx chips needs a waiting time after writing */ |
504 | unsigned int wait_after_write; | |
505 | ||
74f38a82 MCC |
506 | struct list_head devlist; |
507 | ||
9bb13a6d MCC |
508 | u32 i2s_speed; /* I2S speed for audio digital stream */ |
509 | ||
35643943 | 510 | struct em28xx_audio_mode audio_mode; |
a6c2ba28 AM |
511 | |
512 | int tuner_type; /* type of the tuner */ | |
513 | int tuner_addr; /* tuner address */ | |
514 | int tda9887_conf; | |
515 | /* i2c i/o */ | |
516 | struct i2c_adapter i2c_adap; | |
517 | struct i2c_client i2c_client; | |
518 | /* video for linux */ | |
519 | int users; /* user count for exclusive use */ | |
520 | struct video_device *vdev; /* video for linux device struct */ | |
7d497f8a | 521 | v4l2_std_id norm; /* selected tv norm */ |
a6c2ba28 AM |
522 | int ctl_freq; /* selected frequency */ |
523 | unsigned int ctl_input; /* selected input */ | |
95b86a9a | 524 | unsigned int ctl_ainput;/* selected audio input */ |
35ae6f04 | 525 | unsigned int ctl_aoutput;/* selected audio output */ |
a6c2ba28 AM |
526 | int mute; |
527 | int volume; | |
528 | /* frame properties */ | |
a6c2ba28 AM |
529 | int width; /* current frame width */ |
530 | int height; /* current frame height */ | |
d45b9b8a HV |
531 | unsigned hscale; /* horizontal scale factor (see datasheet) */ |
532 | unsigned vscale; /* vertical scale factor (see datasheet) */ | |
a6c2ba28 | 533 | int interlaced; /* 1=interlace fileds, 0=just top fileds */ |
9e31ced8 | 534 | unsigned int video_bytesread; /* Number of bytes read */ |
a6c2ba28 | 535 | |
03910cc3 | 536 | unsigned long hash; /* eeprom hash - for boards with generic ID */ |
6ea54d93 DSL |
537 | unsigned long i2c_hash; /* i2c devicelist hash - |
538 | for boards with generic ID */ | |
03910cc3 | 539 | |
9baed99e | 540 | struct em28xx_audio adev; |
6d79468d | 541 | |
a6c2ba28 | 542 | /* states */ |
3acf2809 | 543 | enum em28xx_dev_state state; |
3acf2809 | 544 | enum em28xx_io_method io; |
9e31ced8 | 545 | |
d7448a8d MCC |
546 | struct work_struct request_module_wk; |
547 | ||
a6c2ba28 | 548 | /* locks */ |
5a80415b | 549 | struct mutex lock; |
f2a2e491 | 550 | struct mutex ctrl_urb_lock; /* protects urb_buf */ |
d7aa8020 | 551 | /* spinlock_t queue_lock; */ |
a6c2ba28 AM |
552 | struct list_head inqueue, outqueue; |
553 | wait_queue_head_t open, wait_frame, wait_stream; | |
554 | struct video_device *vbi_dev; | |
0be43754 | 555 | struct video_device *radio_dev; |
a6c2ba28 AM |
556 | |
557 | unsigned char eedata[256]; | |
558 | ||
ad0ebb96 MCC |
559 | /* Isoc control struct */ |
560 | struct em28xx_dmaqueue vidq; | |
561 | struct em28xx_usb_isoc_ctl isoc_ctl; | |
562 | spinlock_t slock; | |
563 | ||
a6c2ba28 AM |
564 | /* usb transfer */ |
565 | struct usb_device *udev; /* the usb device */ | |
566 | int alt; /* alternate */ | |
567 | int max_pkt_size; /* max packet size of isoc transaction */ | |
9d4d9c05 MCC |
568 | int num_alt; /* Number of alternative settings */ |
569 | unsigned int *alt_max_pkt_size; /* array of wMaxPacketSize */ | |
3acf2809 | 570 | struct urb *urb[EM28XX_NUM_BUFS]; /* urb for isoc transfers */ |
a1a6ee74 NS |
571 | char *transfer_buffer[EM28XX_NUM_BUFS]; /* transfer buffers for isoc |
572 | transfer */ | |
c4a98793 MCC |
573 | char urb_buf[URB_MAX_CTRL_SIZE]; /* urb control msg buffer */ |
574 | ||
a6c2ba28 | 575 | /* helper funcs that call usb_control_msg */ |
6ea54d93 | 576 | int (*em28xx_write_regs) (struct em28xx *dev, u16 reg, |
a6c2ba28 | 577 | char *buf, int len); |
6ea54d93 DSL |
578 | int (*em28xx_read_reg) (struct em28xx *dev, u16 reg); |
579 | int (*em28xx_read_reg_req_len) (struct em28xx *dev, u8 req, u16 reg, | |
580 | char *buf, int len); | |
581 | int (*em28xx_write_regs_req) (struct em28xx *dev, u8 req, u16 reg, | |
a6c2ba28 | 582 | char *buf, int len); |
6ea54d93 | 583 | int (*em28xx_read_reg_req) (struct em28xx *dev, u8 req, u16 reg); |
3aefb79a MCC |
584 | |
585 | enum em28xx_mode mode; | |
586 | ||
6a1acc3b DH |
587 | /* register numbers for GPO/GPIO registers */ |
588 | u16 reg_gpo_num, reg_gpio_num; | |
589 | ||
c67ec53f MCC |
590 | /* Caches GPO and GPIO registers */ |
591 | unsigned char reg_gpo, reg_gpio; | |
592 | ||
a9fc52bc DH |
593 | /* Snapshot button */ |
594 | char snapshot_button_path[30]; /* path of the input dev */ | |
595 | struct input_dev *sbutton_input_dev; | |
596 | struct delayed_work sbutton_query_work; | |
597 | ||
3421b778 | 598 | struct em28xx_dvb *dvb; |
d2ebd0f8 MCC |
599 | |
600 | /* I2C keyboard data */ | |
601 | struct i2c_board_info info; | |
602 | struct IR_i2c_init_data init_data; | |
a6c2ba28 AM |
603 | }; |
604 | ||
6d79468d MCC |
605 | struct em28xx_ops { |
606 | struct list_head next; | |
607 | char *name; | |
608 | int id; | |
609 | int (*init)(struct em28xx *); | |
610 | int (*fini)(struct em28xx *); | |
a3a048ce MCC |
611 | }; |
612 | ||
3acf2809 | 613 | /* Provided by em28xx-i2c.c */ |
fad7b958 | 614 | void em28xx_do_i2c_scan(struct em28xx *dev); |
f2cf250a DSL |
615 | int em28xx_i2c_register(struct em28xx *dev); |
616 | int em28xx_i2c_unregister(struct em28xx *dev); | |
a6c2ba28 | 617 | |
3acf2809 | 618 | /* Provided by em28xx-core.c */ |
a6c2ba28 | 619 | |
3acf2809 MCC |
620 | u32 em28xx_request_buffers(struct em28xx *dev, u32 count); |
621 | void em28xx_queue_unusedframes(struct em28xx *dev); | |
622 | void em28xx_release_buffers(struct em28xx *dev); | |
a6c2ba28 | 623 | |
3acf2809 | 624 | int em28xx_read_reg_req_len(struct em28xx *dev, u8 req, u16 reg, |
a6c2ba28 | 625 | char *buf, int len); |
3acf2809 MCC |
626 | int em28xx_read_reg_req(struct em28xx *dev, u8 req, u16 reg); |
627 | int em28xx_read_reg(struct em28xx *dev, u16 reg); | |
628 | int em28xx_write_regs_req(struct em28xx *dev, u8 req, u16 reg, char *buf, | |
a6c2ba28 | 629 | int len); |
3acf2809 | 630 | int em28xx_write_regs(struct em28xx *dev, u16 reg, char *buf, int len); |
b6972489 DH |
631 | int em28xx_write_reg(struct em28xx *dev, u16 reg, u8 val); |
632 | ||
531c98e7 MCC |
633 | int em28xx_read_ac97(struct em28xx *dev, u8 reg); |
634 | int em28xx_write_ac97(struct em28xx *dev, u8 reg, u16 val); | |
635 | ||
3acf2809 | 636 | int em28xx_audio_analog_set(struct em28xx *dev); |
35643943 | 637 | int em28xx_audio_setup(struct em28xx *dev); |
539c96d0 | 638 | |
3acf2809 MCC |
639 | int em28xx_colorlevels_set_default(struct em28xx *dev); |
640 | int em28xx_capture_start(struct em28xx *dev, int start); | |
bddcf633 | 641 | int em28xx_set_outfmt(struct em28xx *dev); |
3acf2809 | 642 | int em28xx_resolution_set(struct em28xx *dev); |
3acf2809 | 643 | int em28xx_set_alternate(struct em28xx *dev); |
579f72e4 AT |
644 | int em28xx_init_isoc(struct em28xx *dev, int max_packets, |
645 | int num_bufs, int max_pkt_size, | |
c67ec53f | 646 | int (*isoc_copy) (struct em28xx *dev, struct urb *urb)); |
579f72e4 | 647 | void em28xx_uninit_isoc(struct em28xx *dev); |
d18e2fda | 648 | int em28xx_isoc_dvb_max_packetsize(struct em28xx *dev); |
c67ec53f MCC |
649 | int em28xx_set_mode(struct em28xx *dev, enum em28xx_mode set_mode); |
650 | int em28xx_gpio_set(struct em28xx *dev, struct em28xx_reg_seq *gpio); | |
1a23f81b MCC |
651 | void em28xx_wake_i2c(struct em28xx *dev); |
652 | void em28xx_remove_from_devlist(struct em28xx *dev); | |
653 | void em28xx_add_into_devlist(struct em28xx *dev); | |
bec43661 | 654 | struct em28xx *em28xx_get_device(int minor, |
1a23f81b MCC |
655 | enum v4l2_buf_type *fh_type, |
656 | int *has_radio); | |
6d79468d MCC |
657 | int em28xx_register_extension(struct em28xx_ops *dev); |
658 | void em28xx_unregister_extension(struct em28xx_ops *dev); | |
1a23f81b MCC |
659 | void em28xx_init_extension(struct em28xx *dev); |
660 | void em28xx_close_extension(struct em28xx *dev); | |
661 | ||
662 | /* Provided by em28xx-video.c */ | |
1a23f81b MCC |
663 | int em28xx_register_analog_devices(struct em28xx *dev); |
664 | void em28xx_release_analog_resources(struct em28xx *dev); | |
6d79468d | 665 | |
3acf2809 | 666 | /* Provided by em28xx-cards.c */ |
6ea54d93 | 667 | extern int em2800_variant_detect(struct usb_device *udev, int model); |
a94e95b4 | 668 | extern void em28xx_pre_card_setup(struct em28xx *dev); |
3acf2809 MCC |
669 | extern void em28xx_card_setup(struct em28xx *dev); |
670 | extern struct em28xx_board em28xx_boards[]; | |
671 | extern struct usb_device_id em28xx_id_table[]; | |
672 | extern const unsigned int em28xx_bcount; | |
c668f32d | 673 | void em28xx_register_i2c_ir(struct em28xx *dev); |
d7cba043 | 674 | int em28xx_tuner_callback(void *ptr, int component, int command, int arg); |
1a23f81b | 675 | void em28xx_release_resources(struct em28xx *dev); |
c8793b03 MCC |
676 | |
677 | /* Provided by em28xx-input.c */ | |
c8793b03 MCC |
678 | int em28xx_get_key_terratec(struct IR_i2c *ir, u32 *ir_key, u32 *ir_raw); |
679 | int em28xx_get_key_em_haup(struct IR_i2c *ir, u32 *ir_key, u32 *ir_raw); | |
680 | int em28xx_get_key_pinnacle_usb_grey(struct IR_i2c *ir, u32 *ir_key, | |
681 | u32 *ir_raw); | |
a9fc52bc DH |
682 | void em28xx_register_snapshot_button(struct em28xx *dev); |
683 | void em28xx_deregister_snapshot_button(struct em28xx *dev); | |
a6c2ba28 | 684 | |
a924a499 MCC |
685 | int em28xx_ir_init(struct em28xx *dev); |
686 | int em28xx_ir_fini(struct em28xx *dev); | |
687 | ||
a6c2ba28 AM |
688 | /* printk macros */ |
689 | ||
3acf2809 | 690 | #define em28xx_err(fmt, arg...) do {\ |
f85c657f | 691 | printk(KERN_ERR fmt , ##arg); } while (0) |
a6c2ba28 | 692 | |
3acf2809 | 693 | #define em28xx_errdev(fmt, arg...) do {\ |
4ac97914 | 694 | printk(KERN_ERR "%s: "fmt,\ |
f85c657f | 695 | dev->name , ##arg); } while (0) |
a6c2ba28 | 696 | |
3acf2809 | 697 | #define em28xx_info(fmt, arg...) do {\ |
4ac97914 | 698 | printk(KERN_INFO "%s: "fmt,\ |
f85c657f | 699 | dev->name , ##arg); } while (0) |
3acf2809 | 700 | #define em28xx_warn(fmt, arg...) do {\ |
4ac97914 | 701 | printk(KERN_WARNING "%s: "fmt,\ |
f85c657f | 702 | dev->name , ##arg); } while (0) |
a6c2ba28 | 703 | |
6ea54d93 | 704 | static inline int em28xx_compression_disable(struct em28xx *dev) |
a6c2ba28 AM |
705 | { |
706 | /* side effect of disabling scaler and mixer */ | |
2a29a0d7 | 707 | return em28xx_write_reg(dev, EM28XX_R26_COMPR, 0x00); |
a6c2ba28 AM |
708 | } |
709 | ||
6ea54d93 | 710 | static inline int em28xx_contrast_get(struct em28xx *dev) |
a6c2ba28 | 711 | { |
41facaa4 | 712 | return em28xx_read_reg(dev, EM28XX_R20_YGAIN) & 0x1f; |
a6c2ba28 AM |
713 | } |
714 | ||
6ea54d93 | 715 | static inline int em28xx_brightness_get(struct em28xx *dev) |
a6c2ba28 | 716 | { |
41facaa4 | 717 | return em28xx_read_reg(dev, EM28XX_R21_YOFFSET); |
a6c2ba28 AM |
718 | } |
719 | ||
6ea54d93 | 720 | static inline int em28xx_saturation_get(struct em28xx *dev) |
a6c2ba28 | 721 | { |
41facaa4 | 722 | return em28xx_read_reg(dev, EM28XX_R22_UVGAIN) & 0x1f; |
a6c2ba28 AM |
723 | } |
724 | ||
6ea54d93 | 725 | static inline int em28xx_u_balance_get(struct em28xx *dev) |
a6c2ba28 | 726 | { |
41facaa4 | 727 | return em28xx_read_reg(dev, EM28XX_R23_UOFFSET); |
a6c2ba28 AM |
728 | } |
729 | ||
6ea54d93 | 730 | static inline int em28xx_v_balance_get(struct em28xx *dev) |
a6c2ba28 | 731 | { |
41facaa4 | 732 | return em28xx_read_reg(dev, EM28XX_R24_VOFFSET); |
a6c2ba28 AM |
733 | } |
734 | ||
6ea54d93 | 735 | static inline int em28xx_gamma_get(struct em28xx *dev) |
a6c2ba28 | 736 | { |
41facaa4 | 737 | return em28xx_read_reg(dev, EM28XX_R14_GAMMA) & 0x3f; |
a6c2ba28 AM |
738 | } |
739 | ||
6ea54d93 | 740 | static inline int em28xx_contrast_set(struct em28xx *dev, s32 val) |
a6c2ba28 AM |
741 | { |
742 | u8 tmp = (u8) val; | |
41facaa4 | 743 | return em28xx_write_regs(dev, EM28XX_R20_YGAIN, &tmp, 1); |
a6c2ba28 AM |
744 | } |
745 | ||
6ea54d93 | 746 | static inline int em28xx_brightness_set(struct em28xx *dev, s32 val) |
a6c2ba28 AM |
747 | { |
748 | u8 tmp = (u8) val; | |
41facaa4 | 749 | return em28xx_write_regs(dev, EM28XX_R21_YOFFSET, &tmp, 1); |
a6c2ba28 AM |
750 | } |
751 | ||
6ea54d93 | 752 | static inline int em28xx_saturation_set(struct em28xx *dev, s32 val) |
a6c2ba28 AM |
753 | { |
754 | u8 tmp = (u8) val; | |
41facaa4 | 755 | return em28xx_write_regs(dev, EM28XX_R22_UVGAIN, &tmp, 1); |
a6c2ba28 AM |
756 | } |
757 | ||
6ea54d93 | 758 | static inline int em28xx_u_balance_set(struct em28xx *dev, s32 val) |
a6c2ba28 AM |
759 | { |
760 | u8 tmp = (u8) val; | |
41facaa4 | 761 | return em28xx_write_regs(dev, EM28XX_R23_UOFFSET, &tmp, 1); |
a6c2ba28 AM |
762 | } |
763 | ||
6ea54d93 | 764 | static inline int em28xx_v_balance_set(struct em28xx *dev, s32 val) |
a6c2ba28 AM |
765 | { |
766 | u8 tmp = (u8) val; | |
41facaa4 | 767 | return em28xx_write_regs(dev, EM28XX_R24_VOFFSET, &tmp, 1); |
a6c2ba28 AM |
768 | } |
769 | ||
6ea54d93 | 770 | static inline int em28xx_gamma_set(struct em28xx *dev, s32 val) |
a6c2ba28 AM |
771 | { |
772 | u8 tmp = (u8) val; | |
41facaa4 | 773 | return em28xx_write_regs(dev, EM28XX_R14_GAMMA, &tmp, 1); |
a6c2ba28 AM |
774 | } |
775 | ||
776 | /*FIXME: maxw should be dependent of alt mode */ | |
6ea54d93 | 777 | static inline unsigned int norm_maxw(struct em28xx *dev) |
30556b23 | 778 | { |
55699964 MCC |
779 | if (dev->board.is_webcam) |
780 | return dev->sensor_xres; | |
781 | ||
505b6d0b | 782 | if (dev->board.max_range_640_480) |
7d497f8a | 783 | return 640; |
55699964 MCC |
784 | |
785 | return 720; | |
30556b23 MR |
786 | } |
787 | ||
6ea54d93 | 788 | static inline unsigned int norm_maxh(struct em28xx *dev) |
a6c2ba28 | 789 | { |
55699964 MCC |
790 | if (dev->board.is_webcam) |
791 | return dev->sensor_yres; | |
792 | ||
505b6d0b | 793 | if (dev->board.max_range_640_480) |
7d497f8a | 794 | return 480; |
55699964 MCC |
795 | |
796 | return (dev->norm & V4L2_STD_625_50) ? 576 : 480; | |
a6c2ba28 | 797 | } |
a6c2ba28 | 798 | #endif |