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microblaze: generic atomic64 support
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / media / video / em28xx / em28xx-dvb.c
CommitLineData
3aefb79a
MCC		 1/*
2 DVB device driver for em28xx
3
fec528b7 4 (c) 2008-2011 Mauro Carvalho Chehab <mchehab@infradead.org>
3aefb79a 5
bdfbf952
DH		 6 (c) 2008 Devin Heitmueller <devin.heitmueller@gmail.com>
7 - Fixes for the driver to properly work with HVR-950
4fd305b2 8 - Fixes for the driver to properly work with Pinnacle PCTV HD Pro Stick
e14b3658 9 - Fixes for the driver to properly work with AMD ATI TV Wonder HD 600
bdfbf952 10
3421b778
AT		 11 (c) 2008 Aidan Thornton <makosoft@googlemail.com>
12
13 Based on cx88-dvb, saa7134-dvb and videobuf-dvb originally written by:
3aefb79a
MCC		 14 (c) 2004, 2005 Chris Pascoe <c.pascoe@itee.uq.edu.au>
15 (c) 2004 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]
16
17 This program is free software; you can redistribute it and/or modify
18 it under the terms of the GNU General Public License as published by
19 the Free Software Foundation; either version 2 of the License.
20 */
21
22#include <linux/kernel.h>
5a0e3ad6 23#include <linux/slab.h>
3aefb79a
MCC		 24#include <linux/usb.h>
25
26#include "em28xx.h"
27#include <media/v4l2-common.h>
28#include <media/videobuf-vmalloc.h>
d7de5d8f
FM		 29#include <media/tuner.h>
30#include "tuner-simple.h"
3aefb79a
MCC		 31
32#include "lgdt330x.h"
7e48b30a 33#include "lgdt3305.h"
7e6388a1 34#include "zl10353.h"
6e7b9ea0 35#include "s5h1409.h"
4fb202a8
DH		 36#include "mt352.h"
37#include "mt352_priv.h" /* FIXME */
285eb1a4 38#include "tda1002x.h"
7e48b30a 39#include "tda18271.h"
ca3dfd6a 40#include "s921.h"
75e2b869 41#include "drxd.h"
d6a5f921 42#include "cxd2820r.h"
fec528b7
MCC		 43#include "tda18271c2dd.h"
44#include "drxk.h"
36588715
AP		 45#include "tda10071.h"
46#include "a8293.h"
1985f6fb 47#include "qt1010.h"
3aefb79a
MCC		 48
49MODULE_DESCRIPTION("driver for em28xx based DVB cards");
50MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@infradead.org>");
51MODULE_LICENSE("GPL");
52
53static unsigned int debug;
54module_param(debug, int, 0644);
55MODULE_PARM_DESC(debug, "enable debug messages [dvb]");
56
57DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
58
59#define dprintk(level, fmt, arg...) do { \
60if (debug >= level) \
3421b778 61 printk(KERN_DEBUG "%s/2-dvb: " fmt, dev->name, ## arg); \
3aefb79a
MCC		 62} while (0)
63
3421b778 64#define EM28XX_DVB_NUM_BUFS 5
3421b778
AT		 65#define EM28XX_DVB_MAX_PACKETS 64
66
67struct em28xx_dvb {
f71095be 68 struct dvb_frontend *fe[2];
3421b778
AT		 69
70 /* feed count management */
71 struct mutex lock;
72 int nfeeds;
73
74 /* general boilerplate stuff */
75 struct dvb_adapter adapter;
76 struct dvb_demux demux;
77 struct dmxdev dmxdev;
78 struct dmx_frontend fe_hw;
79 struct dmx_frontend fe_mem;
80 struct dvb_net net;
fec528b7 81
c4c3a3d3 82 /* Due to DRX-K - probably need changes */
fec528b7
MCC		 83 int (*gate_ctrl)(struct dvb_frontend *, int);
84 struct semaphore pll_mutex;
c4c3a3d3 85 bool dont_attach_fe1;
3421b778
AT		 86};
87
88
89static inline void print_err_status(struct em28xx *dev,
90 int packet, int status)
3aefb79a 91{
3421b778 92 char *errmsg = "Unknown";
3aefb79a 93
3421b778
AT		 94 switch (status) {
95 case -ENOENT:
96 errmsg = "unlinked synchronuously";
97 break;
98 case -ECONNRESET:
99 errmsg = "unlinked asynchronuously";
100 break;
101 case -ENOSR:
102 errmsg = "Buffer error (overrun)";
103 break;
104 case -EPIPE:
105 errmsg = "Stalled (device not responding)";
106 break;
107 case -EOVERFLOW:
108 errmsg = "Babble (bad cable?)";
109 break;
110 case -EPROTO:
111 errmsg = "Bit-stuff error (bad cable?)";
112 break;
113 case -EILSEQ:
114 errmsg = "CRC/Timeout (could be anything)";
115 break;
116 case -ETIME:
117 errmsg = "Device does not respond";
118 break;
119 }
120 if (packet < 0) {
121 dprintk(1, "URB status %d [%s].\n", status, errmsg);
122 } else {
6ea54d93
DSL		 123 dprintk(1, "URB packet %d, status %d [%s].\n",
124 packet, status, errmsg);
3421b778
AT		 125 }
126}
3aefb79a 127
f2d0c1c6 128static inline int em28xx_dvb_isoc_copy(struct em28xx *dev, struct urb *urb)
3421b778
AT		 129{
130 int i;
3aefb79a 131
3421b778
AT		 132 if (!dev)
133 return 0;
3aefb79a 134
3421b778
AT		 135 if ((dev->state & DEV_DISCONNECTED) || (dev->state & DEV_MISCONFIGURED))
136 return 0;
137
138 if (urb->status < 0) {
139 print_err_status(dev, -1, urb->status);
140 if (urb->status == -ENOENT)
141 return 0;
142 }
143
144 for (i = 0; i < urb->number_of_packets; i++) {
145 int status = urb->iso_frame_desc[i].status;
146
147 if (status < 0) {
148 print_err_status(dev, i, status);
149 if (urb->iso_frame_desc[i].status != -EPROTO)
150 continue;
151 }
152
153 dvb_dmx_swfilter(&dev->dvb->demux, urb->transfer_buffer +
154 urb->iso_frame_desc[i].offset,
155 urb->iso_frame_desc[i].actual_length);
156 }
157
158 return 0;
159}
160
f2d0c1c6 161static int em28xx_start_streaming(struct em28xx_dvb *dvb)
6ea54d93 162{
c67ec53f 163 int rc;
3421b778 164 struct em28xx *dev = dvb->adapter.priv;
d18e2fda 165 int max_dvb_packet_size;
3421b778 166
8ab33626 167 usb_set_interface(dev->udev, 0, dev->dvb_alt);
c67ec53f
MCC		 168 rc = em28xx_set_mode(dev, EM28XX_DIGITAL_MODE);
169 if (rc < 0)
170 return rc;
3421b778 171
8ab33626 172 max_dvb_packet_size = dev->dvb_max_pkt_size;
f7acc4bb
MCC		 173 if (max_dvb_packet_size < 0)
174 return max_dvb_packet_size;
175 dprintk(1, "Using %d buffers each with %d bytes\n",
176 EM28XX_DVB_NUM_BUFS,
177 max_dvb_packet_size);
d18e2fda 178
3421b778 179 return em28xx_init_isoc(dev, EM28XX_DVB_MAX_PACKETS,
d18e2fda 180 EM28XX_DVB_NUM_BUFS, max_dvb_packet_size,
f2d0c1c6 181 em28xx_dvb_isoc_copy);
3421b778
AT		 182}
183
f2d0c1c6 184static int em28xx_stop_streaming(struct em28xx_dvb *dvb)
6ea54d93 185{
3421b778
AT		 186 struct em28xx *dev = dvb->adapter.priv;
187
188 em28xx_uninit_isoc(dev);
c67ec53f 189
2fe3e2ee 190 em28xx_set_mode(dev, EM28XX_SUSPEND);
c67ec53f 191
3aefb79a
MCC		 192 return 0;
193}
194
f2d0c1c6 195static int em28xx_start_feed(struct dvb_demux_feed *feed)
3421b778
AT		 196{
197 struct dvb_demux *demux = feed->demux;
198 struct em28xx_dvb *dvb = demux->priv;
199 int rc, ret;
200
201 if (!demux->dmx.frontend)
202 return -EINVAL;
203
204 mutex_lock(&dvb->lock);
205 dvb->nfeeds++;
206 rc = dvb->nfeeds;
207
208 if (dvb->nfeeds == 1) {
f2d0c1c6 209 ret = em28xx_start_streaming(dvb);
6ea54d93
DSL		 210 if (ret < 0)
211 rc = ret;
3421b778
AT		 212 }
213
214 mutex_unlock(&dvb->lock);
215 return rc;
216}
217
f2d0c1c6 218static int em28xx_stop_feed(struct dvb_demux_feed *feed)
3421b778
AT		 219{
220 struct dvb_demux *demux = feed->demux;
221 struct em28xx_dvb *dvb = demux->priv;
222 int err = 0;
223
224 mutex_lock(&dvb->lock);
225 dvb->nfeeds--;
6ea54d93
DSL		 226
227 if (0 == dvb->nfeeds)
f2d0c1c6 228 err = em28xx_stop_streaming(dvb);
6ea54d93 229
3421b778
AT		 230 mutex_unlock(&dvb->lock);
231 return err;
232}
233
234
e3569abc
MCC		 235
236/* ------------------------------------------------------------------ */
237static int em28xx_dvb_bus_ctrl(struct dvb_frontend *fe, int acquire)
238{
239 struct em28xx *dev = fe->dvb->priv;
240
241 if (acquire)
242 return em28xx_set_mode(dev, EM28XX_DIGITAL_MODE);
243 else
2fe3e2ee 244 return em28xx_set_mode(dev, EM28XX_SUSPEND);
e3569abc
MCC		 245}
246
3aefb79a
MCC		 247/* ------------------------------------------------------------------ */
248
227ad4ab
MCC		 249static struct lgdt330x_config em2880_lgdt3303_dev = {
250 .demod_address = 0x0e,
251 .demod_chip = LGDT3303,
252};
3aefb79a 253
7e48b30a
JW		 254static struct lgdt3305_config em2870_lgdt3304_dev = {
255 .i2c_addr = 0x0e,
256 .demod_chip = LGDT3304,
257 .spectral_inversion = 1,
258 .deny_i2c_rptr = 1,
259 .mpeg_mode = LGDT3305_MPEG_PARALLEL,
260 .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE,
261 .tpvalid_polarity = LGDT3305_TP_VALID_HIGH,
262 .vsb_if_khz = 3250,
263 .qam_if_khz = 4000,
264};
265
ca3dfd6a
MCC		 266static struct s921_config sharp_isdbt = {
267 .demod_address = 0x30 >> 1
268};
269
7e6388a1
AT		 270static struct zl10353_config em28xx_zl10353_with_xc3028 = {
271 .demod_address = (0x1e >> 1),
272 .no_tuner = 1,
273 .parallel_ts = 1,
274 .if2 = 45600,
275};
276
6e7b9ea0
RK		 277static struct s5h1409_config em28xx_s5h1409_with_xc3028 = {
278 .demod_address = 0x32 >> 1,
279 .output_mode = S5H1409_PARALLEL_OUTPUT,
280 .gpio = S5H1409_GPIO_OFF,
281 .inversion = S5H1409_INVERSION_OFF,
282 .status_mode = S5H1409_DEMODLOCKING,
283 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK
284};
285
7e48b30a
JW		 286static struct tda18271_std_map kworld_a340_std_map = {
287 .atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 0,
288 .if_lvl = 1, .rfagc_top = 0x37, },
289 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 1,
290 .if_lvl = 1, .rfagc_top = 0x37, },
291};
292
293static struct tda18271_config kworld_a340_config = {
294 .std_map = &kworld_a340_std_map,
295};
296
a84f79ae 297static struct zl10353_config em28xx_zl10353_xc3028_no_i2c_gate = {
f797608c
DH		 298 .demod_address = (0x1e >> 1),
299 .no_tuner = 1,
300 .disable_i2c_gate_ctrl = 1,
301 .parallel_ts = 1,
302 .if2 = 45600,
303};
304
75e2b869 305static struct drxd_config em28xx_drxd = {
aac865f7
MCC		 306 .demod_address = 0x70,
307 .demod_revision = 0xa2,
308 .pll_type = DRXD_PLL_NONE,
309 .clock = 12000,
310 .insert_rs_byte = 1,
311 .IF = 42800000,
6b142b3c 312 .disable_i2c_gate_ctrl = 1,
17d9d558 313};
17d9d558 314
fec528b7
MCC		 315struct drxk_config terratec_h5_drxk = {
316 .adr = 0x29,
e4f4f875 317 .single_master = 1,
f1fe1b75 318 .no_i2c_bridge = 1,
8b9456ae 319 .microcode_name = "dvb-usb-terratec-h5-drxk.fw",
fec528b7
MCC		 320};
321
82e7dbbd
EDP		 322struct drxk_config hauppauge_930c_drxk = {
323 .adr = 0x29,
324 .single_master = 1,
325 .no_i2c_bridge = 1,
326 .microcode_name = "dvb-usb-hauppauge-hvr930c-drxk.fw",
327 .chunk_size = 56,
328};
329
fec528b7
MCC		 330static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable)
331{
332 struct em28xx_dvb *dvb = fe->sec_priv;
333 int status;
334
335 if (!dvb)
336 return -EINVAL;
337
338 if (enable) {
339 down(&dvb->pll_mutex);
340 status = dvb->gate_ctrl(fe, 1);
341 } else {
342 status = dvb->gate_ctrl(fe, 0);
343 up(&dvb->pll_mutex);
344 }
345 return status;
346}
347
82e7dbbd
EDP		 348static void hauppauge_hvr930c_init(struct em28xx *dev)
349{
350 int i;
351
352 struct em28xx_reg_seq hauppauge_hvr930c_init[] = {
de72405f
MCC		 353 {EM2874_R80_GPIO, 0xff, 0xff, 0x65},
354 {EM2874_R80_GPIO, 0xfb, 0xff, 0x32},
355 {EM2874_R80_GPIO, 0xff, 0xff, 0xb8},
82e7dbbd
EDP		 356 { -1, -1, -1, -1},
357 };
358 struct em28xx_reg_seq hauppauge_hvr930c_end[] = {
de72405f
MCC		 359 {EM2874_R80_GPIO, 0xef, 0xff, 0x01},
360 {EM2874_R80_GPIO, 0xaf, 0xff, 0x65},
361 {EM2874_R80_GPIO, 0xef, 0xff, 0x76},
362 {EM2874_R80_GPIO, 0xef, 0xff, 0x01},
363 {EM2874_R80_GPIO, 0xcf, 0xff, 0x0b},
364 {EM2874_R80_GPIO, 0xef, 0xff, 0x40},
365
366 {EM2874_R80_GPIO, 0xcf, 0xff, 0x65},
367 {EM2874_R80_GPIO, 0xef, 0xff, 0x65},
368 {EM2874_R80_GPIO, 0xcf, 0xff, 0x0b},
369 {EM2874_R80_GPIO, 0xef, 0xff, 0x65},
82e7dbbd 370
82e7dbbd
EDP		 371 { -1, -1, -1, -1},
372 };
373
82e7dbbd
EDP		 374 struct {
375 unsigned char r[4];
376 int len;
377 } regs[] = {
378 {{ 0x06, 0x02, 0x00, 0x31 }, 4},
379 {{ 0x01, 0x02 }, 2},
380 {{ 0x01, 0x02, 0x00, 0xc6 }, 4},
381 {{ 0x01, 0x00 }, 2},
382 {{ 0x01, 0x00, 0xff, 0xaf }, 4},
383 {{ 0x01, 0x00, 0x03, 0xa0 }, 4},
384 {{ 0x01, 0x00 }, 2},
385 {{ 0x01, 0x00, 0x73, 0xaf }, 4},
386 {{ 0x04, 0x00 }, 2},
387 {{ 0x00, 0x04 }, 2},
388 {{ 0x00, 0x04, 0x00, 0x0a }, 4},
389 {{ 0x04, 0x14 }, 2},
390 {{ 0x04, 0x14, 0x00, 0x00 }, 4},
391 };
392
393 em28xx_gpio_set(dev, hauppauge_hvr930c_init);
394 em28xx_write_reg(dev, EM28XX_R06_I2C_CLK, 0x40);
395 msleep(10);
396 em28xx_write_reg(dev, EM28XX_R06_I2C_CLK, 0x44);
397 msleep(10);
398
399 dev->i2c_client.addr = 0x82 >> 1;
400
401 for (i = 0; i < ARRAY_SIZE(regs); i++)
402 i2c_master_send(&dev->i2c_client, regs[i].r, regs[i].len);
403 em28xx_gpio_set(dev, hauppauge_hvr930c_end);
404
405 msleep(100);
406
407 em28xx_write_reg(dev, EM28XX_R06_I2C_CLK, 0x44);
408 msleep(30);
409
82e7dbbd
EDP		 410 em28xx_write_reg(dev, EM28XX_R06_I2C_CLK, 0x45);
411 msleep(10);
412
413}
414
fec528b7
MCC		 415static void terratec_h5_init(struct em28xx *dev)
416{
417 int i;
418 struct em28xx_reg_seq terratec_h5_init[] = {
419 {EM28XX_R08_GPIO, 0xff, 0xff, 10},
420 {EM2874_R80_GPIO, 0xf6, 0xff, 100},
421 {EM2874_R80_GPIO, 0xf2, 0xff, 50},
422 {EM2874_R80_GPIO, 0xf6, 0xff, 100},
423 { -1, -1, -1, -1},
424 };
425 struct em28xx_reg_seq terratec_h5_end[] = {
426 {EM2874_R80_GPIO, 0xe6, 0xff, 100},
427 {EM2874_R80_GPIO, 0xa6, 0xff, 50},
428 {EM2874_R80_GPIO, 0xe6, 0xff, 100},
429 { -1, -1, -1, -1},
430 };
431 struct {
432 unsigned char r[4];
433 int len;
434 } regs[] = {
435 {{ 0x06, 0x02, 0x00, 0x31 }, 4},
436 {{ 0x01, 0x02 }, 2},
437 {{ 0x01, 0x02, 0x00, 0xc6 }, 4},
438 {{ 0x01, 0x00 }, 2},
439 {{ 0x01, 0x00, 0xff, 0xaf }, 4},
440 {{ 0x01, 0x00, 0x03, 0xa0 }, 4},
441 {{ 0x01, 0x00 }, 2},
442 {{ 0x01, 0x00, 0x73, 0xaf }, 4},
443 {{ 0x04, 0x00 }, 2},
444 {{ 0x00, 0x04 }, 2},
445 {{ 0x00, 0x04, 0x00, 0x0a }, 4},
446 {{ 0x04, 0x14 }, 2},
447 {{ 0x04, 0x14, 0x00, 0x00 }, 4},
448 };
449
450 em28xx_gpio_set(dev, terratec_h5_init);
451 em28xx_write_reg(dev, EM28XX_R06_I2C_CLK, 0x40);
452 msleep(10);
453 em28xx_write_reg(dev, EM28XX_R06_I2C_CLK, 0x45);
454 msleep(10);
455
456 dev->i2c_client.addr = 0x82 >> 1;
457
458 for (i = 0; i < ARRAY_SIZE(regs); i++)
459 i2c_master_send(&dev->i2c_client, regs[i].r, regs[i].len);
460 em28xx_gpio_set(dev, terratec_h5_end);
461};
462
f2d0c1c6 463static int em28xx_mt352_terratec_xs_init(struct dvb_frontend *fe)
4fb202a8
DH		 464{
465 /* Values extracted from a USB trace of the Terratec Windows driver */
466 static u8 clock_config[] = { CLOCK_CTL, 0x38, 0x2c };
467 static u8 reset[] = { RESET, 0x80 };
468 static u8 adc_ctl_1_cfg[] = { ADC_CTL_1, 0x40 };
469 static u8 agc_cfg[] = { AGC_TARGET, 0x28, 0xa0 };
470 static u8 input_freq_cfg[] = { INPUT_FREQ_1, 0x31, 0xb8 };
471 static u8 rs_err_cfg[] = { RS_ERR_PER_1, 0x00, 0x4d };
472 static u8 capt_range_cfg[] = { CAPT_RANGE, 0x32 };
473 static u8 trl_nom_cfg[] = { TRL_NOMINAL_RATE_1, 0x64, 0x00 };
474 static u8 tps_given_cfg[] = { TPS_GIVEN_1, 0x40, 0x80, 0x50 };
ff69786b 475 static u8 tuner_go[] = { TUNER_GO, 0x01};
4fb202a8
DH		 476
477 mt352_write(fe, clock_config, sizeof(clock_config));
478 udelay(200);
479 mt352_write(fe, reset, sizeof(reset));
480 mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
481 mt352_write(fe, agc_cfg, sizeof(agc_cfg));
482 mt352_write(fe, input_freq_cfg, sizeof(input_freq_cfg));
483 mt352_write(fe, rs_err_cfg, sizeof(rs_err_cfg));
484 mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
485 mt352_write(fe, trl_nom_cfg, sizeof(trl_nom_cfg));
486 mt352_write(fe, tps_given_cfg, sizeof(tps_given_cfg));
487 mt352_write(fe, tuner_go, sizeof(tuner_go));
488 return 0;
489}
490
491static struct mt352_config terratec_xs_mt352_cfg = {
492 .demod_address = (0x1e >> 1),
493 .no_tuner = 1,
494 .if2 = 45600,
f2d0c1c6 495 .demod_init = em28xx_mt352_terratec_xs_init,
4fb202a8
DH		 496};
497
285eb1a4
AP		 498static struct tda10023_config em28xx_tda10023_config = {
499 .demod_address = 0x0c,
500 .invert = 1,
501};
502
d6a5f921
AP		 503static struct cxd2820r_config em28xx_cxd2820r_config = {
504 .i2c_address = (0xd8 >> 1),
505 .ts_mode = CXD2820R_TS_SERIAL,
d6a5f921
AP		 506
507 /* enable LNA for DVB-T2 and DVB-C */
508 .gpio_dvbt2[0] = CXD2820R_GPIO_E | CXD2820R_GPIO_O | CXD2820R_GPIO_L,
509 .gpio_dvbc[0] = CXD2820R_GPIO_E | CXD2820R_GPIO_O | CXD2820R_GPIO_L,
510};
511
512static struct tda18271_config em28xx_cxd2820r_tda18271_config = {
513 .output_opt = TDA18271_OUTPUT_LT_OFF,
0db4bf42 514 .gate = TDA18271_GATE_DIGITAL,
d6a5f921
AP		 515};
516
36588715
AP		 517static const struct tda10071_config em28xx_tda10071_config = {
518 .i2c_address = 0x55, /* (0xaa >> 1) */
519 .i2c_wr_max = 64,
520 .ts_mode = TDA10071_TS_SERIAL,
521 .spec_inv = 0,
522 .xtal = 40444000, /* 40.444 MHz */
523 .pll_multiplier = 20,
524};
525
526static const struct a8293_config em28xx_a8293_config = {
527 .i2c_addr = 0x08, /* (0x10 >> 1) */
528};
529
1985f6fb
AP		 530static struct zl10353_config em28xx_zl10353_no_i2c_gate_dev = {
531 .demod_address = (0x1e >> 1),
532 .disable_i2c_gate_ctrl = 1,
533 .no_tuner = 1,
534 .parallel_ts = 1,
535};
536static struct qt1010_config em28xx_qt1010_config = {
537 .i2c_address = 0x62
538
539};
540
3aefb79a
MCC		 541/* ------------------------------------------------------------------ */
542
f2d0c1c6 543static int em28xx_attach_xc3028(u8 addr, struct em28xx *dev)
3aefb79a
MCC		 544{
545 struct dvb_frontend *fe;
3ca9c093
MCC		 546 struct xc2028_config cfg;
547
6ea54d93 548 memset(&cfg, 0, sizeof(cfg));
3ca9c093
MCC		 549 cfg.i2c_adap = &dev->i2c_adap;
550 cfg.i2c_addr = addr;
3ca9c093 551
f71095be 552 if (!dev->dvb->fe[0]) {
480be185
FR		 553 em28xx_errdev("/2: dvb frontend not attached. "
554 "Can't attach xc3028\n");
3aefb79a
MCC		 555 return -EINVAL;
556 }
557
f71095be 558 fe = dvb_attach(xc2028_attach, dev->dvb->fe[0], &cfg);
3aefb79a 559 if (!fe) {
480be185 560 em28xx_errdev("/2: xc3028 attach failed\n");
f71095be
AP		 561 dvb_frontend_detach(dev->dvb->fe[0]);
562 dev->dvb->fe[0] = NULL;
3aefb79a
MCC		 563 return -EINVAL;
564 }
565
480be185 566 em28xx_info("%s/2: xc3028 attached\n", dev->name);
3aefb79a
MCC		 567
568 return 0;
569}
570
3421b778
AT		 571/* ------------------------------------------------------------------ */
572
f2d0c1c6
JW		 573static int em28xx_register_dvb(struct em28xx_dvb *dvb, struct module *module,
574 struct em28xx *dev, struct device *device)
3aefb79a 575{
3421b778 576 int result;
3aefb79a 577
3421b778 578 mutex_init(&dvb->lock);
3aefb79a 579
3421b778
AT		 580 /* register adapter */
581 result = dvb_register_adapter(&dvb->adapter, dev->name, module, device,
582 adapter_nr);
583 if (result < 0) {
584 printk(KERN_WARNING "%s: dvb_register_adapter failed (errno = %d)\n",
585 dev->name, result);
586 goto fail_adapter;
587 }
e3569abc
MCC		 588
589 /* Ensure all frontends negotiate bus access */
f71095be
AP		 590 dvb->fe[0]->ops.ts_bus_ctrl = em28xx_dvb_bus_ctrl;
591 if (dvb->fe[1])
592 dvb->fe[1]->ops.ts_bus_ctrl = em28xx_dvb_bus_ctrl;
e3569abc 593
3421b778
AT		 594 dvb->adapter.priv = dev;
595
596 /* register frontend */
f71095be 597 result = dvb_register_frontend(&dvb->adapter, dvb->fe[0]);
3421b778
AT		 598 if (result < 0) {
599 printk(KERN_WARNING "%s: dvb_register_frontend failed (errno = %d)\n",
600 dev->name, result);
f71095be
AP		 601 goto fail_frontend0;
602 }
603
604 /* register 2nd frontend */
605 if (dvb->fe[1]) {
606 result = dvb_register_frontend(&dvb->adapter, dvb->fe[1]);
607 if (result < 0) {
608 printk(KERN_WARNING "%s: 2nd dvb_register_frontend failed (errno = %d)\n",
609 dev->name, result);
610 goto fail_frontend1;
611 }
3421b778
AT		 612 }
613
614 /* register demux stuff */
615 dvb->demux.dmx.capabilities =
616 DMX_TS_FILTERING | DMX_SECTION_FILTERING |
617 DMX_MEMORY_BASED_FILTERING;
618 dvb->demux.priv = dvb;
619 dvb->demux.filternum = 256;
620 dvb->demux.feednum = 256;
f2d0c1c6
JW		 621 dvb->demux.start_feed = em28xx_start_feed;
622 dvb->demux.stop_feed = em28xx_stop_feed;
e3569abc 623
3421b778
AT		 624 result = dvb_dmx_init(&dvb->demux);
625 if (result < 0) {
626 printk(KERN_WARNING "%s: dvb_dmx_init failed (errno = %d)\n",
627 dev->name, result);
628 goto fail_dmx;
629 }
630
631 dvb->dmxdev.filternum = 256;
632 dvb->dmxdev.demux = &dvb->demux.dmx;
633 dvb->dmxdev.capabilities = 0;
634 result = dvb_dmxdev_init(&dvb->dmxdev, &dvb->adapter);
635 if (result < 0) {
636 printk(KERN_WARNING "%s: dvb_dmxdev_init failed (errno = %d)\n",
637 dev->name, result);
638 goto fail_dmxdev;
639 }
52284c3e 640
3421b778
AT		 641 dvb->fe_hw.source = DMX_FRONTEND_0;
642 result = dvb->demux.dmx.add_frontend(&dvb->demux.dmx, &dvb->fe_hw);
643 if (result < 0) {
644 printk(KERN_WARNING "%s: add_frontend failed (DMX_FRONTEND_0, errno = %d)\n",
645 dev->name, result);
646 goto fail_fe_hw;
647 }
648
649 dvb->fe_mem.source = DMX_MEMORY_FE;
650 result = dvb->demux.dmx.add_frontend(&dvb->demux.dmx, &dvb->fe_mem);
651 if (result < 0) {
652 printk(KERN_WARNING "%s: add_frontend failed (DMX_MEMORY_FE, errno = %d)\n",
653 dev->name, result);
654 goto fail_fe_mem;
655 }
656
657 result = dvb->demux.dmx.connect_frontend(&dvb->demux.dmx, &dvb->fe_hw);
658 if (result < 0) {
659 printk(KERN_WARNING "%s: connect_frontend failed (errno = %d)\n",
660 dev->name, result);
661 goto fail_fe_conn;
662 }
663
664 /* register network adapter */
665 dvb_net_init(&dvb->adapter, &dvb->net, &dvb->demux.dmx);
666 return 0;
667
668fail_fe_conn:
669 dvb->demux.dmx.remove_frontend(&dvb->demux.dmx, &dvb->fe_mem);
670fail_fe_mem:
671 dvb->demux.dmx.remove_frontend(&dvb->demux.dmx, &dvb->fe_hw);
672fail_fe_hw:
673 dvb_dmxdev_release(&dvb->dmxdev);
674fail_dmxdev:
675 dvb_dmx_release(&dvb->demux);
676fail_dmx:
f71095be
AP		 677 if (dvb->fe[1])
678 dvb_unregister_frontend(dvb->fe[1]);
679 dvb_unregister_frontend(dvb->fe[0]);
680fail_frontend1:
681 if (dvb->fe[1])
682 dvb_frontend_detach(dvb->fe[1]);
683fail_frontend0:
684 dvb_frontend_detach(dvb->fe[0]);
3421b778
AT		 685 dvb_unregister_adapter(&dvb->adapter);
686fail_adapter:
687 return result;
688}
689
f2d0c1c6 690static void em28xx_unregister_dvb(struct em28xx_dvb *dvb)
3421b778
AT		 691{
692 dvb_net_release(&dvb->net);
693 dvb->demux.dmx.remove_frontend(&dvb->demux.dmx, &dvb->fe_mem);
694 dvb->demux.dmx.remove_frontend(&dvb->demux.dmx, &dvb->fe_hw);
695 dvb_dmxdev_release(&dvb->dmxdev);
696 dvb_dmx_release(&dvb->demux);
f71095be
AP		 697 if (dvb->fe[1])
698 dvb_unregister_frontend(dvb->fe[1]);
699 dvb_unregister_frontend(dvb->fe[0]);
c4c3a3d3 700 if (dvb->fe[1] && !dvb->dont_attach_fe1)
f71095be
AP		 701 dvb_frontend_detach(dvb->fe[1]);
702 dvb_frontend_detach(dvb->fe[0]);
3421b778
AT		 703 dvb_unregister_adapter(&dvb->adapter);
704}
705
f2d0c1c6 706static int em28xx_dvb_init(struct em28xx *dev)
3421b778 707{
e3645437 708 int result = 0, mfe_shared = 0;
3421b778
AT		 709 struct em28xx_dvb *dvb;
710
505b6d0b 711 if (!dev->board.has_dvb) {
df619181 712 /* This device does not support the extension */
ca3dfd6a 713 printk(KERN_INFO "em28xx_dvb: This device does not support the extension\n");
df619181
DH		 714 return 0;
715 }
716
3421b778 717 dvb = kzalloc(sizeof(struct em28xx_dvb), GFP_KERNEL);
6ea54d93
DSL		 718
719 if (dvb == NULL) {
480be185 720 em28xx_info("em28xx_dvb: memory allocation failed\n");
3421b778
AT		 721 return -ENOMEM;
722 }
723 dev->dvb = dvb;
f71095be 724 dvb->fe[0] = dvb->fe[1] = NULL;
3aefb79a 725
5013318c 726 mutex_lock(&dev->lock);
c67ec53f 727 em28xx_set_mode(dev, EM28XX_DIGITAL_MODE);
3aefb79a
MCC		 728 /* init frontend */
729 switch (dev->model) {
ebaefdb7 730 case EM2874_BOARD_LEADERSHIP_ISDBT:
f71095be 731 dvb->fe[0] = dvb_attach(s921_attach,
ca3dfd6a
MCC		 732 &sharp_isdbt, &dev->i2c_adap);
733
f71095be 734 if (!dvb->fe[0]) {
ca3dfd6a
MCC		 735 result = -EINVAL;
736 goto out_free;
737 }
738
739 break;
f89bc329 740 case EM2883_BOARD_HAUPPAUGE_WINTV_HVR_850:
10ac6603 741 case EM2883_BOARD_HAUPPAUGE_WINTV_HVR_950:
4fd305b2 742 case EM2880_BOARD_PINNACLE_PCTV_HD_PRO:
e14b3658 743 case EM2880_BOARD_AMD_ATI_TV_WONDER_HD_600:
f71095be 744 dvb->fe[0] = dvb_attach(lgdt330x_attach,
3421b778
AT		 745 &em2880_lgdt3303_dev,
746 &dev->i2c_adap);
f2d0c1c6 747 if (em28xx_attach_xc3028(0x61, dev) < 0) {
3421b778
AT		 748 result = -EINVAL;
749 goto out_free;
750 }
227ad4ab 751 break;
46510b56 752 case EM2880_BOARD_KWORLD_DVB_310U:
f71095be 753 dvb->fe[0] = dvb_attach(zl10353_attach,
3421b778
AT		 754 &em28xx_zl10353_with_xc3028,
755 &dev->i2c_adap);
f2d0c1c6 756 if (em28xx_attach_xc3028(0x61, dev) < 0) {
3421b778
AT		 757 result = -EINVAL;
758 goto out_free;
759 }
7e6388a1 760 break;
a84f79ae 761 case EM2880_BOARD_HAUPPAUGE_WINTV_HVR_900:
ec994d05 762 case EM2882_BOARD_TERRATEC_HYBRID_XS:
01a5fd6f 763 case EM2880_BOARD_EMPIRE_DUAL_TV:
f71095be 764 dvb->fe[0] = dvb_attach(zl10353_attach,
a84f79ae
DH		 765 &em28xx_zl10353_xc3028_no_i2c_gate,
766 &dev->i2c_adap);
f2d0c1c6 767 if (em28xx_attach_xc3028(0x61, dev) < 0) {
a84f79ae
DH		 768 result = -EINVAL;
769 goto out_free;
770 }
771 break;
f797608c 772 case EM2880_BOARD_TERRATEC_HYBRID_XS:
65638011 773 case EM2880_BOARD_TERRATEC_HYBRID_XS_FR:
d5b3ba9c 774 case EM2881_BOARD_PINNACLE_HYBRID_PRO:
7ca7ef60 775 case EM2882_BOARD_DIKOM_DK300:
811fab62 776 case EM2882_BOARD_KWORLD_VS_DVBT:
f71095be 777 dvb->fe[0] = dvb_attach(zl10353_attach,
a84f79ae 778 &em28xx_zl10353_xc3028_no_i2c_gate,
f797608c 779 &dev->i2c_adap);
f71095be 780 if (dvb->fe[0] == NULL) {
f797608c
DH		 781 /* This board could have either a zl10353 or a mt352.
782 If the chip id isn't for zl10353, try mt352 */
f71095be 783 dvb->fe[0] = dvb_attach(mt352_attach,
4fb202a8
DH		 784 &terratec_xs_mt352_cfg,
785 &dev->i2c_adap);
f797608c 786 }
4fb202a8 787
f2d0c1c6 788 if (em28xx_attach_xc3028(0x61, dev) < 0) {
f797608c
DH		 789 result = -EINVAL;
790 goto out_free;
791 }
792 break;
1985f6fb
AP		 793 case EM2870_BOARD_KWORLD_355U:
794 dvb->fe[0] = dvb_attach(zl10353_attach,
795 &em28xx_zl10353_no_i2c_gate_dev,
796 &dev->i2c_adap);
797 if (dvb->fe[0] != NULL)
798 dvb_attach(qt1010_attach, dvb->fe[0],
799 &dev->i2c_adap, &em28xx_qt1010_config);
800 break;
6e7b9ea0 801 case EM2883_BOARD_KWORLD_HYBRID_330U:
19859229 802 case EM2882_BOARD_EVGA_INDTUBE:
f71095be 803 dvb->fe[0] = dvb_attach(s5h1409_attach,
6e7b9ea0
RK		 804 &em28xx_s5h1409_with_xc3028,
805 &dev->i2c_adap);
f2d0c1c6 806 if (em28xx_attach_xc3028(0x61, dev) < 0) {
6e7b9ea0
RK		 807 result = -EINVAL;
808 goto out_free;
809 }
810 break;
d7de5d8f 811 case EM2882_BOARD_KWORLD_ATSC_315U:
f71095be 812 dvb->fe[0] = dvb_attach(lgdt330x_attach,
d7de5d8f
FM		 813 &em2880_lgdt3303_dev,
814 &dev->i2c_adap);
f71095be
AP		 815 if (dvb->fe[0] != NULL) {
816 if (!dvb_attach(simple_tuner_attach, dvb->fe[0],
d7de5d8f
FM		 817 &dev->i2c_adap, 0x61, TUNER_THOMSON_DTT761X)) {
818 result = -EINVAL;
819 goto out_free;
820 }
821 }
822 break;
17d9d558 823 case EM2880_BOARD_HAUPPAUGE_WINTV_HVR_900_R2:
ad9b4bb2 824 case EM2882_BOARD_PINNACLE_HYBRID_PRO_330E:
f71095be 825 dvb->fe[0] = dvb_attach(drxd_attach, &em28xx_drxd, NULL,
75e2b869 826 &dev->i2c_adap, &dev->udev->dev);
f2d0c1c6 827 if (em28xx_attach_xc3028(0x61, dev) < 0) {
17d9d558
DH		 828 result = -EINVAL;
829 goto out_free;
830 }
831 break;
285eb1a4
AP		 832 case EM2870_BOARD_REDDO_DVB_C_USB_BOX:
833 /* Philips CU1216L NIM (Philips TDA10023 + Infineon TUA6034) */
f71095be 834 dvb->fe[0] = dvb_attach(tda10023_attach,
285eb1a4
AP		 835 &em28xx_tda10023_config,
836 &dev->i2c_adap, 0x48);
f71095be
AP		 837 if (dvb->fe[0]) {
838 if (!dvb_attach(simple_tuner_attach, dvb->fe[0],
285eb1a4
AP		 839 &dev->i2c_adap, 0x60, TUNER_PHILIPS_CU1216L)) {
840 result = -EINVAL;
841 goto out_free;
842 }
843 }
844 break;
7e48b30a 845 case EM2870_BOARD_KWORLD_A340:
f71095be 846 dvb->fe[0] = dvb_attach(lgdt3305_attach,
7e48b30a
JW		 847 &em2870_lgdt3304_dev,
848 &dev->i2c_adap);
f71095be
AP		 849 if (dvb->fe[0] != NULL)
850 dvb_attach(tda18271_attach, dvb->fe[0], 0x60,
7e48b30a
JW		 851 &dev->i2c_adap, &kworld_a340_config);
852 break;
d6a5f921 853 case EM28174_BOARD_PCTV_290E:
d6a5f921 854 dvb->fe[0] = dvb_attach(cxd2820r_attach,
7e7b8287
MA		 855 &em28xx_cxd2820r_config,
856 &dev->i2c_adap,
857 NULL);
d6a5f921 858 if (dvb->fe[0]) {
d6a5f921 859 /* FE 0 attach tuner */
7e7b8287
MA		 860 if (!dvb_attach(tda18271_attach,
861 dvb->fe[0],
862 0x60,
863 &dev->i2c_adap,
864 &em28xx_cxd2820r_tda18271_config)) {
865
d6a5f921
AP		 866 dvb_frontend_detach(dvb->fe[0]);
867 result = -EINVAL;
868 goto out_free;
869 }
d6a5f921 870 }
82e7dbbd
EDP		 871 break;
872 case EM2884_BOARD_HAUPPAUGE_WINTV_HVR_930C:
8503232f
MCC		 873 {
874 struct xc5000_config cfg;
82e7dbbd
EDP		 875 hauppauge_hvr930c_init(dev);
876
de72405f 877 dvb->fe[0] = dvb_attach(drxk_attach,
fa4b2a17 878 &hauppauge_930c_drxk, &dev->i2c_adap);
82e7dbbd
EDP		 879 if (!dvb->fe[0]) {
880 result = -EINVAL;
881 goto out_free;
882 }
883 /* FIXME: do we need a pll semaphore? */
884 dvb->fe[0]->sec_priv = dvb;
885 sema_init(&dvb->pll_mutex, 1);
886 dvb->gate_ctrl = dvb->fe[0]->ops.i2c_gate_ctrl;
887 dvb->fe[0]->ops.i2c_gate_ctrl = drxk_gate_ctrl;
82e7dbbd
EDP		 888
889 /* Attach xc5000 */
82e7dbbd
EDP		 890 memset(&cfg, 0, sizeof(cfg));
891 cfg.i2c_address = 0x61;
de72405f 892 cfg.if_khz = 4000;
82e7dbbd
EDP		 893
894 if (dvb->fe[0]->ops.i2c_gate_ctrl)
895 dvb->fe[0]->ops.i2c_gate_ctrl(dvb->fe[0], 1);
de72405f
MCC		 896 if (!dvb_attach(xc5000_attach, dvb->fe[0], &dev->i2c_adap,
897 &cfg)) {
82e7dbbd
EDP		 898 result = -EINVAL;
899 goto out_free;
900 }
82e7dbbd
EDP		 901 if (dvb->fe[0]->ops.i2c_gate_ctrl)
902 dvb->fe[0]->ops.i2c_gate_ctrl(dvb->fe[0], 0);
903
fec528b7 904 break;
8503232f 905 }
fec528b7 906 case EM2884_BOARD_TERRATEC_H5:
a1ed02e9 907 case EM2884_BOARD_CINERGY_HTC_STICK:
fec528b7
MCC		 908 terratec_h5_init(dev);
909
fa4b2a17 910 dvb->fe[0] = dvb_attach(drxk_attach, &terratec_h5_drxk, &dev->i2c_adap);
c4c3a3d3 911 if (!dvb->fe[0]) {
fec528b7
MCC		 912 result = -EINVAL;
913 goto out_free;
914 }
915 /* FIXME: do we need a pll semaphore? */
916 dvb->fe[0]->sec_priv = dvb;
917 sema_init(&dvb->pll_mutex, 1);
918 dvb->gate_ctrl = dvb->fe[0]->ops.i2c_gate_ctrl;
919 dvb->fe[0]->ops.i2c_gate_ctrl = drxk_gate_ctrl;
fec528b7 920
c4c3a3d3 921 /* Attach tda18271 to DVB-C frontend */
fec528b7
MCC		 922 if (dvb->fe[0]->ops.i2c_gate_ctrl)
923 dvb->fe[0]->ops.i2c_gate_ctrl(dvb->fe[0], 1);
924 if (!dvb_attach(tda18271c2dd_attach, dvb->fe[0], &dev->i2c_adap, 0x60)) {
925 result = -EINVAL;
926 goto out_free;
927 }
928 if (dvb->fe[0]->ops.i2c_gate_ctrl)
929 dvb->fe[0]->ops.i2c_gate_ctrl(dvb->fe[0], 0);
c4c3a3d3 930
d6a5f921 931 break;
36588715
AP		 932 case EM28174_BOARD_PCTV_460E:
933 /* attach demod */
934 dvb->fe[0] = dvb_attach(tda10071_attach,
935 &em28xx_tda10071_config, &dev->i2c_adap);
936
937 /* attach SEC */
938 if (dvb->fe[0])
939 dvb_attach(a8293_attach, dvb->fe[0], &dev->i2c_adap,
940 &em28xx_a8293_config);
941 break;
3aefb79a 942 default:
480be185
FR		 943 em28xx_errdev("/2: The frontend of your DVB/ATSC card"
944 " isn't supported yet\n");
3aefb79a
MCC		 945 break;
946 }
f71095be 947 if (NULL == dvb->fe[0]) {
480be185 948 em28xx_errdev("/2: frontend initialization failed\n");
3421b778
AT		 949 result = -EINVAL;
950 goto out_free;
3aefb79a 951 }
d7cba043 952 /* define general-purpose callback pointer */
f71095be 953 dvb->fe[0]->callback = em28xx_tuner_callback;
82e7dbbd 954 if (dvb->fe[1])
de72405f 955 dvb->fe[1]->callback = em28xx_tuner_callback;
3aefb79a
MCC		 956
957 /* register everything */
f2d0c1c6 958 result = em28xx_register_dvb(dvb, THIS_MODULE, dev, &dev->udev->dev);
3421b778 959
6ea54d93 960 if (result < 0)
3421b778 961 goto out_free;
3421b778 962
e3645437
AP		 963 /* MFE lock */
964 dvb->adapter.mfe_shared = mfe_shared;
965
480be185 966 em28xx_info("Successfully loaded em28xx-dvb\n");
5013318c
MCC		 967ret:
968 em28xx_set_mode(dev, EM28XX_SUSPEND);
969 mutex_unlock(&dev->lock);
970 return result;
3421b778
AT		 971
972out_free:
973 kfree(dvb);
974 dev->dvb = NULL;
5013318c 975 goto ret;
3aefb79a
MCC		 976}
977
0b8bd83c
CR		 978static inline void prevent_sleep(struct dvb_frontend_ops *ops)
979{
980 ops->set_voltage = NULL;
981 ops->sleep = NULL;
982 ops->tuner_ops.sleep = NULL;
983}
984
f2d0c1c6 985static int em28xx_dvb_fini(struct em28xx *dev)
3aefb79a 986{
505b6d0b 987 if (!dev->board.has_dvb) {
df619181
DH		 988 /* This device does not support the extension */
989 return 0;
990 }
991
3421b778 992 if (dev->dvb) {
0b8bd83c
CR		 993 struct em28xx_dvb *dvb = dev->dvb;
994
995 if (dev->state & DEV_DISCONNECTED) {
996 /* We cannot tell the device to sleep
997 * once it has been unplugged. */
998 if (dvb->fe[0])
999 prevent_sleep(&dvb->fe[0]->ops);
1000 if (dvb->fe[1])
1001 prevent_sleep(&dvb->fe[1]->ops);
1002 }
1003
1004 em28xx_unregister_dvb(dvb);
1005 kfree(dvb);
3421b778
AT		 1006 dev->dvb = NULL;
1007 }
3aefb79a
MCC		 1008
1009 return 0;
1010}
1011
1012static struct em28xx_ops dvb_ops = {
1013 .id = EM28XX_DVB,
1014 .name = "Em28xx dvb Extension",
f2d0c1c6
JW		 1015 .init = em28xx_dvb_init,
1016 .fini = em28xx_dvb_fini,
3aefb79a
MCC		 1017};
1018
1019static int __init em28xx_dvb_register(void)
1020{
1021 return em28xx_register_extension(&dvb_ops);
1022}
1023
1024static void __exit em28xx_dvb_unregister(void)
1025{
1026 em28xx_unregister_extension(&dvb_ops);
1027}
1028
1029module_init(em28xx_dvb_register);
1030module_exit(em28xx_dvb_unregister);
kernel source for telekom puls (alcatel/mediatek)