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V4L/DVB (7094): static memory
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / media / video / cx88 / cx88-tvaudio.c
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1da177e4 1/*
1da177e4
LT		 2
3 cx88x-audio.c - Conexant CX23880/23881 audio downstream driver driver
4
5 (c) 2001 Michael Eskin, Tom Zakrajsek [Windows version]
6 (c) 2002 Yurij Sysoev <yurij@naturesoft.net>
7 (c) 2003 Gerd Knorr <kraxel@bytesex.org>
8
9 -----------------------------------------------------------------------
10
11 Lot of voodoo here. Even the data sheet doesn't help to
12 understand what is going on here, the documentation for the audio
13 part of the cx2388x chip is *very* bad.
14
15 Some of this comes from party done linux driver sources I got from
16 [undocumented].
17
18 Some comes from the dscaler sources, one of the dscaler driver guy works
19 for Conexant ...
20
21 -----------------------------------------------------------------------
22
23 This program is free software; you can redistribute it and/or modify
24 it under the terms of the GNU General Public License as published by
25 the Free Software Foundation; either version 2 of the License, or
26 (at your option) any later version.
27
28 This program is distributed in the hope that it will be useful,
29 but WITHOUT ANY WARRANTY; without even the implied warranty of
30 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 GNU General Public License for more details.
32
33 You should have received a copy of the GNU General Public License
34 along with this program; if not, write to the Free Software
35 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
36*/
37
38#include <linux/module.h>
1da177e4 39#include <linux/errno.h>
a96afb3e 40#include <linux/freezer.h>
1da177e4
LT		 41#include <linux/kernel.h>
42#include <linux/slab.h>
43#include <linux/mm.h>
44#include <linux/poll.h>
1da177e4
LT		 45#include <linux/signal.h>
46#include <linux/ioport.h>
1da177e4
LT		 47#include <linux/types.h>
48#include <linux/interrupt.h>
49#include <linux/vmalloc.h>
50#include <linux/init.h>
1da177e4
LT		 51#include <linux/delay.h>
52#include <linux/kthread.h>
53
54#include "cx88.h"
55
ff699e6b 56static unsigned int audio_debug;
7b3c6d65
NS		 57module_param(audio_debug, int, 0644);
58MODULE_PARM_DESC(audio_debug, "enable debug messages [audio]");
1da177e4 59
ff699e6b 60static unsigned int always_analog;
7d83e843
PC		 61module_param(always_analog,int,0644);
62MODULE_PARM_DESC(always_analog,"force analog audio out");
63
ff699e6b 64static unsigned int radio_deemphasis;
fa40b223
TP		 65module_param(radio_deemphasis,int,0644);
66MODULE_PARM_DESC(radio_deemphasis, "Radio deemphasis time constant, "
67 "0=None, 1=50us (elsewhere), 2=75us (USA)");
7d83e843 68
1da177e4
LT		 69#define dprintk(fmt, arg...) if (audio_debug) \
70 printk(KERN_DEBUG "%s/0: " fmt, core->name , ## arg)
71
72/* ----------------------------------------------------------- */
73
7b3c6d65
NS		 74static char *aud_ctl_names[64] = {
75 [EN_BTSC_FORCE_MONO] = "BTSC_FORCE_MONO",
76 [EN_BTSC_FORCE_STEREO] = "BTSC_FORCE_STEREO",
77 [EN_BTSC_FORCE_SAP] = "BTSC_FORCE_SAP",
78 [EN_BTSC_AUTO_STEREO] = "BTSC_AUTO_STEREO",
79 [EN_BTSC_AUTO_SAP] = "BTSC_AUTO_SAP",
80 [EN_A2_FORCE_MONO1] = "A2_FORCE_MONO1",
81 [EN_A2_FORCE_MONO2] = "A2_FORCE_MONO2",
82 [EN_A2_FORCE_STEREO] = "A2_FORCE_STEREO",
83 [EN_A2_AUTO_MONO2] = "A2_AUTO_MONO2",
84 [EN_A2_AUTO_STEREO] = "A2_AUTO_STEREO",
85 [EN_EIAJ_FORCE_MONO1] = "EIAJ_FORCE_MONO1",
86 [EN_EIAJ_FORCE_MONO2] = "EIAJ_FORCE_MONO2",
87 [EN_EIAJ_FORCE_STEREO] = "EIAJ_FORCE_STEREO",
88 [EN_EIAJ_AUTO_MONO2] = "EIAJ_AUTO_MONO2",
89 [EN_EIAJ_AUTO_STEREO] = "EIAJ_AUTO_STEREO",
90 [EN_NICAM_FORCE_MONO1] = "NICAM_FORCE_MONO1",
91 [EN_NICAM_FORCE_MONO2] = "NICAM_FORCE_MONO2",
92 [EN_NICAM_FORCE_STEREO] = "NICAM_FORCE_STEREO",
93 [EN_NICAM_AUTO_MONO2] = "NICAM_AUTO_MONO2",
94 [EN_NICAM_AUTO_STEREO] = "NICAM_AUTO_STEREO",
95 [EN_FMRADIO_FORCE_MONO] = "FMRADIO_FORCE_MONO",
96 [EN_FMRADIO_FORCE_STEREO] = "FMRADIO_FORCE_STEREO",
97 [EN_FMRADIO_AUTO_STEREO] = "FMRADIO_AUTO_STEREO",
1da177e4
LT		 98};
99
100struct rlist {
101 u32 reg;
102 u32 val;
103};
104
7b3c6d65 105static void set_audio_registers(struct cx88_core *core, const struct rlist *l)
1da177e4
LT		 106{
107 int i;
108
109 for (i = 0; l[i].reg; i++) {
110 switch (l[i].reg) {
111 case AUD_PDF_DDS_CNST_BYTE2:
112 case AUD_PDF_DDS_CNST_BYTE1:
113 case AUD_PDF_DDS_CNST_BYTE0:
114 case AUD_QAM_MODE:
115 case AUD_PHACC_FREQ_8MSB:
116 case AUD_PHACC_FREQ_8LSB:
117 cx_writeb(l[i].reg, l[i].val);
118 break;
119 default:
120 cx_write(l[i].reg, l[i].val);
121 break;
122 }
123 }
124}
125
7b3c6d65 126static void set_audio_start(struct cx88_core *core, u32 mode)
1da177e4 127{
53a7338a 128 /* mute */
7b3c6d65 129 cx_write(AUD_VOL_CTL, (1 << 6));
1da177e4 130
53a7338a 131 /* start programming */
7b3c6d65
NS		 132 cx_write(AUD_INIT, mode);
133 cx_write(AUD_INIT_LD, 0x0001);
134 cx_write(AUD_SOFT_RESET, 0x0001);
1da177e4
LT		 135}
136
e52e98a7 137static void set_audio_finish(struct cx88_core *core, u32 ctl)
1da177e4
LT		 138{
139 u32 volume;
140
6f502b8a
MCC		 141 /* restart dma; This avoids buzz in NICAM and is good in others */
142 cx88_stop_audio_dma(core);
53a7338a 143 cx_write(AUD_RATE_THRES_DMD, 0x000000C0);
6f502b8a 144 cx88_start_audio_dma(core);
53a7338a 145
6a59d64c 146 if (core->board.mpeg & CX88_MPEG_BLACKBIRD) {
b45009b0
MCC		 147 cx_write(AUD_I2SINPUTCNTL, 4);
148 cx_write(AUD_BAUDRATE, 1);
53a7338a 149 /* 'pass-thru mode': this enables the i2s output to the mpeg encoder */
b45009b0 150 cx_set(AUD_CTL, EN_I2SOUT_ENABLE);
1da177e4 151 cx_write(AUD_I2SOUTPUTCNTL, 1);
b45009b0 152 cx_write(AUD_I2SCNTL, 0);
53a7338a 153 /* cx_write(AUD_APB_IN_RATE_ADJ, 0); */
7d83e843 154 }
6a59d64c 155 if ((always_analog) || (!(core->board.mpeg & CX88_MPEG_BLACKBIRD))) {
7b3c6d65
NS		 156 ctl |= EN_DAC_ENABLE;
157 cx_write(AUD_CTL, ctl);
1da177e4
LT		 158 }
159
e52e98a7 160 /* finish programming */
1da177e4
LT		 161 cx_write(AUD_SOFT_RESET, 0x0000);
162
e52e98a7 163 /* unmute */
1da177e4
LT		 164 volume = cx_sread(SHADOW_AUD_VOL_CTL);
165 cx_swrite(SHADOW_AUD_VOL_CTL, AUD_VOL_CTL, volume);
166}
167
168/* ----------------------------------------------------------- */
169
7b3c6d65
NS		 170static void set_audio_standard_BTSC(struct cx88_core *core, unsigned int sap,
171 u32 mode)
1da177e4
LT		 172{
173 static const struct rlist btsc[] = {
7b3c6d65
NS		 174 {AUD_AFE_12DB_EN, 0x00000001},
175 {AUD_OUT1_SEL, 0x00000013},
176 {AUD_OUT1_SHIFT, 0x00000000},
177 {AUD_POLY0_DDS_CONSTANT, 0x0012010c},
178 {AUD_DMD_RA_DDS, 0x00c3e7aa},
179 {AUD_DBX_IN_GAIN, 0x00004734},
180 {AUD_DBX_WBE_GAIN, 0x00004640},
181 {AUD_DBX_SE_GAIN, 0x00008d31},
182 {AUD_DCOC_0_SRC, 0x0000001a},
183 {AUD_IIR1_4_SEL, 0x00000021},
184 {AUD_DCOC_PASS_IN, 0x00000003},
185 {AUD_DCOC_0_SHIFT_IN0, 0x0000000a},
186 {AUD_DCOC_0_SHIFT_IN1, 0x00000008},
187 {AUD_DCOC_1_SHIFT_IN0, 0x0000000a},
188 {AUD_DCOC_1_SHIFT_IN1, 0x00000008},
189 {AUD_DN0_FREQ, 0x0000283b},
190 {AUD_DN2_SRC_SEL, 0x00000008},
191 {AUD_DN2_FREQ, 0x00003000},
192 {AUD_DN2_AFC, 0x00000002},
193 {AUD_DN2_SHFT, 0x00000000},
194 {AUD_IIR2_2_SEL, 0x00000020},
195 {AUD_IIR2_2_SHIFT, 0x00000000},
196 {AUD_IIR2_3_SEL, 0x0000001f},
197 {AUD_IIR2_3_SHIFT, 0x00000000},
198 {AUD_CRDC1_SRC_SEL, 0x000003ce},
199 {AUD_CRDC1_SHIFT, 0x00000000},
200 {AUD_CORDIC_SHIFT_1, 0x00000007},
201 {AUD_DCOC_1_SRC, 0x0000001b},
202 {AUD_DCOC1_SHIFT, 0x00000000},
203 {AUD_RDSI_SEL, 0x00000008},
204 {AUD_RDSQ_SEL, 0x00000008},
205 {AUD_RDSI_SHIFT, 0x00000000},
206 {AUD_RDSQ_SHIFT, 0x00000000},
207 {AUD_POLYPH80SCALEFAC, 0x00000003},
e52e98a7 208 { /* end of list */ },
1da177e4
LT		 209 };
210 static const struct rlist btsc_sap[] = {
7b3c6d65
NS		 211 {AUD_AFE_12DB_EN, 0x00000001},
212 {AUD_DBX_IN_GAIN, 0x00007200},
213 {AUD_DBX_WBE_GAIN, 0x00006200},
214 {AUD_DBX_SE_GAIN, 0x00006200},
215 {AUD_IIR1_1_SEL, 0x00000000},
216 {AUD_IIR1_3_SEL, 0x00000001},
217 {AUD_DN1_SRC_SEL, 0x00000007},
218 {AUD_IIR1_4_SHIFT, 0x00000006},
219 {AUD_IIR2_1_SHIFT, 0x00000000},
220 {AUD_IIR2_2_SHIFT, 0x00000000},
221 {AUD_IIR3_0_SHIFT, 0x00000000},
222 {AUD_IIR3_1_SHIFT, 0x00000000},
223 {AUD_IIR3_0_SEL, 0x0000000d},
224 {AUD_IIR3_1_SEL, 0x0000000e},
225 {AUD_DEEMPH1_SRC_SEL, 0x00000014},
226 {AUD_DEEMPH1_SHIFT, 0x00000000},
227 {AUD_DEEMPH1_G0, 0x00004000},
228 {AUD_DEEMPH1_A0, 0x00000000},
229 {AUD_DEEMPH1_B0, 0x00000000},
230 {AUD_DEEMPH1_A1, 0x00000000},
231 {AUD_DEEMPH1_B1, 0x00000000},
232 {AUD_OUT0_SEL, 0x0000003f},
233 {AUD_OUT1_SEL, 0x0000003f},
234 {AUD_DN1_AFC, 0x00000002},
235 {AUD_DCOC_0_SHIFT_IN0, 0x0000000a},
236 {AUD_DCOC_0_SHIFT_IN1, 0x00000008},
237 {AUD_DCOC_1_SHIFT_IN0, 0x0000000a},
238 {AUD_DCOC_1_SHIFT_IN1, 0x00000008},
239 {AUD_IIR1_0_SEL, 0x0000001d},
240 {AUD_IIR1_2_SEL, 0x0000001e},
241 {AUD_IIR2_1_SEL, 0x00000002},
242 {AUD_IIR2_2_SEL, 0x00000004},
243 {AUD_IIR3_2_SEL, 0x0000000f},
244 {AUD_DCOC2_SHIFT, 0x00000001},
245 {AUD_IIR3_2_SHIFT, 0x00000001},
246 {AUD_DEEMPH0_SRC_SEL, 0x00000014},
247 {AUD_CORDIC_SHIFT_1, 0x00000006},
248 {AUD_POLY0_DDS_CONSTANT, 0x000e4db2},
249 {AUD_DMD_RA_DDS, 0x00f696e6},
250 {AUD_IIR2_3_SEL, 0x00000025},
251 {AUD_IIR1_4_SEL, 0x00000021},
252 {AUD_DN1_FREQ, 0x0000c965},
253 {AUD_DCOC_PASS_IN, 0x00000003},
254 {AUD_DCOC_0_SRC, 0x0000001a},
255 {AUD_DCOC_1_SRC, 0x0000001b},
256 {AUD_DCOC1_SHIFT, 0x00000000},
257 {AUD_RDSI_SEL, 0x00000009},
258 {AUD_RDSQ_SEL, 0x00000009},
259 {AUD_RDSI_SHIFT, 0x00000000},
260 {AUD_RDSQ_SHIFT, 0x00000000},
261 {AUD_POLYPH80SCALEFAC, 0x00000003},
e52e98a7 262 { /* end of list */ },
1da177e4
LT		 263 };
264
e52e98a7
MCC		 265 mode |= EN_FMRADIO_EN_RDS;
266
1da177e4 267 if (sap) {
7b3c6d65
NS		 268 dprintk("%s SAP (status: unknown)\n", __FUNCTION__);
269 set_audio_start(core, SEL_SAP);
1da177e4 270 set_audio_registers(core, btsc_sap);
e52e98a7 271 set_audio_finish(core, mode);
1da177e4 272 } else {
7b3c6d65
NS		 273 dprintk("%s (status: known-good)\n", __FUNCTION__);
274 set_audio_start(core, SEL_BTSC);
1da177e4 275 set_audio_registers(core, btsc);
e52e98a7 276 set_audio_finish(core, mode);
1da177e4 277 }
1da177e4
LT		 278}
279
b1706b91 280static void set_audio_standard_NICAM(struct cx88_core *core, u32 mode)
1da177e4 281{
e52e98a7 282 static const struct rlist nicam_l[] = {
7b3c6d65
NS		 283 {AUD_AFE_12DB_EN, 0x00000001},
284 {AUD_RATE_ADJ1, 0x00000060},
285 {AUD_RATE_ADJ2, 0x000000F9},
286 {AUD_RATE_ADJ3, 0x000001CC},
287 {AUD_RATE_ADJ4, 0x000002B3},
288 {AUD_RATE_ADJ5, 0x00000726},
289 {AUD_DEEMPHDENOM1_R, 0x0000F3D0},
290 {AUD_DEEMPHDENOM2_R, 0x00000000},
291 {AUD_ERRLOGPERIOD_R, 0x00000064},
292 {AUD_ERRINTRPTTHSHLD1_R, 0x00000FFF},
293 {AUD_ERRINTRPTTHSHLD2_R, 0x0000001F},
294 {AUD_ERRINTRPTTHSHLD3_R, 0x0000000F},
295 {AUD_POLYPH80SCALEFAC, 0x00000003},
296 {AUD_DMD_RA_DDS, 0x00C00000},
297 {AUD_PLL_INT, 0x0000001E},
298 {AUD_PLL_DDS, 0x00000000},
299 {AUD_PLL_FRAC, 0x0000E542},
300 {AUD_START_TIMER, 0x00000000},
301 {AUD_DEEMPHNUMER1_R, 0x000353DE},
302 {AUD_DEEMPHNUMER2_R, 0x000001B1},
303 {AUD_PDF_DDS_CNST_BYTE2, 0x06},
304 {AUD_PDF_DDS_CNST_BYTE1, 0x82},
305 {AUD_PDF_DDS_CNST_BYTE0, 0x12},
306 {AUD_QAM_MODE, 0x05},
307 {AUD_PHACC_FREQ_8MSB, 0x34},
308 {AUD_PHACC_FREQ_8LSB, 0x4C},
309 {AUD_DEEMPHGAIN_R, 0x00006680},
310 {AUD_RATE_THRES_DMD, 0x000000C0},
311 { /* end of list */ },
312 };
1da177e4 313
b1706b91 314 static const struct rlist nicam_bgdki_common[] = {
7b3c6d65
NS		 315 {AUD_AFE_12DB_EN, 0x00000001},
316 {AUD_RATE_ADJ1, 0x00000010},
317 {AUD_RATE_ADJ2, 0x00000040},
318 {AUD_RATE_ADJ3, 0x00000100},
319 {AUD_RATE_ADJ4, 0x00000400},
320 {AUD_RATE_ADJ5, 0x00001000},
7b3c6d65
NS		 321 {AUD_ERRLOGPERIOD_R, 0x00000fff},
322 {AUD_ERRINTRPTTHSHLD1_R, 0x000003ff},
323 {AUD_ERRINTRPTTHSHLD2_R, 0x000000ff},
324 {AUD_ERRINTRPTTHSHLD3_R, 0x0000003f},
325 {AUD_POLYPH80SCALEFAC, 0x00000003},
326 {AUD_DEEMPHGAIN_R, 0x000023c2},
327 {AUD_DEEMPHNUMER1_R, 0x0002a7bc},
328 {AUD_DEEMPHNUMER2_R, 0x0003023e},
329 {AUD_DEEMPHDENOM1_R, 0x0000f3d0},
330 {AUD_DEEMPHDENOM2_R, 0x00000000},
d0fcdd78 331 {AUD_PDF_DDS_CNST_BYTE2, 0x06},
7b3c6d65 332 {AUD_PDF_DDS_CNST_BYTE1, 0x82},
7b3c6d65
NS		 333 {AUD_QAM_MODE, 0x05},
334 { /* end of list */ },
b1706b91
TS		 335 };
336
337 static const struct rlist nicam_i[] = {
7b3c6d65
NS		 338 {AUD_PDF_DDS_CNST_BYTE0, 0x12},
339 {AUD_PHACC_FREQ_8MSB, 0x3a},
340 {AUD_PHACC_FREQ_8LSB, 0x93},
341 { /* end of list */ },
e52e98a7
MCC		 342 };
343
b1706b91 344 static const struct rlist nicam_default[] = {
7b3c6d65
NS		 345 {AUD_PDF_DDS_CNST_BYTE0, 0x16},
346 {AUD_PHACC_FREQ_8MSB, 0x34},
347 {AUD_PHACC_FREQ_8LSB, 0x4c},
348 { /* end of list */ },
b1706b91 349 };
e52e98a7 350
7f7e846c 351 set_audio_start(core,SEL_NICAM);
b1706b91
TS		 352 switch (core->tvaudio) {
353 case WW_L:
7b3c6d65 354 dprintk("%s SECAM-L NICAM (status: devel)\n", __FUNCTION__);
b1706b91
TS		 355 set_audio_registers(core, nicam_l);
356 break;
357 case WW_I:
53a7338a 358 dprintk("%s PAL-I NICAM (status: known-good)\n", __FUNCTION__);
b1706b91
TS		 359 set_audio_registers(core, nicam_bgdki_common);
360 set_audio_registers(core, nicam_i);
361 break;
362 default:
53a7338a 363 dprintk("%s PAL-BGDK NICAM (status: known-good)\n", __FUNCTION__);
b1706b91
TS		 364 set_audio_registers(core, nicam_bgdki_common);
365 set_audio_registers(core, nicam_default);
366 break;
367 };
368
369 mode |= EN_DMTRX_LR | EN_DMTRX_BYPASS;
370 set_audio_finish(core, mode);
1da177e4
LT		 371}
372
e52e98a7 373static void set_audio_standard_A2(struct cx88_core *core, u32 mode)
1da177e4 374{
b1706b91 375 static const struct rlist a2_bgdk_common[] = {
7b3c6d65
NS		 376 {AUD_ERRLOGPERIOD_R, 0x00000064},
377 {AUD_ERRINTRPTTHSHLD1_R, 0x00000fff},
378 {AUD_ERRINTRPTTHSHLD2_R, 0x0000001f},
379 {AUD_ERRINTRPTTHSHLD3_R, 0x0000000f},
380 {AUD_PDF_DDS_CNST_BYTE2, 0x06},
381 {AUD_PDF_DDS_CNST_BYTE1, 0x82},
382 {AUD_PDF_DDS_CNST_BYTE0, 0x12},
383 {AUD_QAM_MODE, 0x05},
384 {AUD_PHACC_FREQ_8MSB, 0x34},
385 {AUD_PHACC_FREQ_8LSB, 0x4c},
386 {AUD_RATE_ADJ1, 0x00000100},
387 {AUD_RATE_ADJ2, 0x00000200},
388 {AUD_RATE_ADJ3, 0x00000300},
389 {AUD_RATE_ADJ4, 0x00000400},
390 {AUD_RATE_ADJ5, 0x00000500},
391 {AUD_THR_FR, 0x00000000},
392 {AAGC_HYST, 0x0000001a},
393 {AUD_PILOT_BQD_1_K0, 0x0000755b},
394 {AUD_PILOT_BQD_1_K1, 0x00551340},
395 {AUD_PILOT_BQD_1_K2, 0x006d30be},
396 {AUD_PILOT_BQD_1_K3, 0xffd394af},
397 {AUD_PILOT_BQD_1_K4, 0x00400000},
398 {AUD_PILOT_BQD_2_K0, 0x00040000},
399 {AUD_PILOT_BQD_2_K1, 0x002a4841},
400 {AUD_PILOT_BQD_2_K2, 0x00400000},
401 {AUD_PILOT_BQD_2_K3, 0x00000000},
402 {AUD_PILOT_BQD_2_K4, 0x00000000},
403 {AUD_MODE_CHG_TIMER, 0x00000040},
404 {AUD_AFE_12DB_EN, 0x00000001},
405 {AUD_CORDIC_SHIFT_0, 0x00000007},
406 {AUD_CORDIC_SHIFT_1, 0x00000007},
407 {AUD_DEEMPH0_G0, 0x00000380},
408 {AUD_DEEMPH1_G0, 0x00000380},
409 {AUD_DCOC_0_SRC, 0x0000001a},
410 {AUD_DCOC0_SHIFT, 0x00000000},
411 {AUD_DCOC_0_SHIFT_IN0, 0x0000000a},
412 {AUD_DCOC_0_SHIFT_IN1, 0x00000008},
413 {AUD_DCOC_PASS_IN, 0x00000003},
414 {AUD_IIR3_0_SEL, 0x00000021},
415 {AUD_DN2_AFC, 0x00000002},
416 {AUD_DCOC_1_SRC, 0x0000001b},
417 {AUD_DCOC1_SHIFT, 0x00000000},
418 {AUD_DCOC_1_SHIFT_IN0, 0x0000000a},
419 {AUD_DCOC_1_SHIFT_IN1, 0x00000008},
420 {AUD_IIR3_1_SEL, 0x00000023},
421 {AUD_RDSI_SEL, 0x00000017},
422 {AUD_RDSI_SHIFT, 0x00000000},
423 {AUD_RDSQ_SEL, 0x00000017},
424 {AUD_RDSQ_SHIFT, 0x00000000},
425 {AUD_PLL_INT, 0x0000001e},
426 {AUD_PLL_DDS, 0x00000000},
427 {AUD_PLL_FRAC, 0x0000e542},
428 {AUD_POLYPH80SCALEFAC, 0x00000001},
429 {AUD_START_TIMER, 0x00000000},
430 { /* end of list */ },
e52e98a7 431 };
1da177e4 432
e52e98a7 433 static const struct rlist a2_bg[] = {
7b3c6d65
NS		 434 {AUD_DMD_RA_DDS, 0x002a4f2f},
435 {AUD_C1_UP_THR, 0x00007000},
436 {AUD_C1_LO_THR, 0x00005400},
437 {AUD_C2_UP_THR, 0x00005400},
438 {AUD_C2_LO_THR, 0x00003000},
439 { /* end of list */ },
1da177e4
LT		 440 };
441
e52e98a7 442 static const struct rlist a2_dk[] = {
7b3c6d65
NS		 443 {AUD_DMD_RA_DDS, 0x002a4f2f},
444 {AUD_C1_UP_THR, 0x00007000},
445 {AUD_C1_LO_THR, 0x00005400},
446 {AUD_C2_UP_THR, 0x00005400},
447 {AUD_C2_LO_THR, 0x00003000},
448 {AUD_DN0_FREQ, 0x00003a1c},
449 {AUD_DN2_FREQ, 0x0000d2e0},
450 { /* end of list */ },
1da177e4 451 };
b1706b91
TS		 452
453 static const struct rlist a1_i[] = {
7b3c6d65
NS		 454 {AUD_ERRLOGPERIOD_R, 0x00000064},
455 {AUD_ERRINTRPTTHSHLD1_R, 0x00000fff},
456 {AUD_ERRINTRPTTHSHLD2_R, 0x0000001f},
457 {AUD_ERRINTRPTTHSHLD3_R, 0x0000000f},
458 {AUD_PDF_DDS_CNST_BYTE2, 0x06},
459 {AUD_PDF_DDS_CNST_BYTE1, 0x82},
460 {AUD_PDF_DDS_CNST_BYTE0, 0x12},
461 {AUD_QAM_MODE, 0x05},
462 {AUD_PHACC_FREQ_8MSB, 0x3a},
463 {AUD_PHACC_FREQ_8LSB, 0x93},
464 {AUD_DMD_RA_DDS, 0x002a4f2f},
465 {AUD_PLL_INT, 0x0000001e},
466 {AUD_PLL_DDS, 0x00000004},
467 {AUD_PLL_FRAC, 0x0000e542},
468 {AUD_RATE_ADJ1, 0x00000100},
469 {AUD_RATE_ADJ2, 0x00000200},
470 {AUD_RATE_ADJ3, 0x00000300},
471 {AUD_RATE_ADJ4, 0x00000400},
472 {AUD_RATE_ADJ5, 0x00000500},
473 {AUD_THR_FR, 0x00000000},
474 {AUD_PILOT_BQD_1_K0, 0x0000755b},
475 {AUD_PILOT_BQD_1_K1, 0x00551340},
476 {AUD_PILOT_BQD_1_K2, 0x006d30be},
477 {AUD_PILOT_BQD_1_K3, 0xffd394af},
478 {AUD_PILOT_BQD_1_K4, 0x00400000},
479 {AUD_PILOT_BQD_2_K0, 0x00040000},
480 {AUD_PILOT_BQD_2_K1, 0x002a4841},
481 {AUD_PILOT_BQD_2_K2, 0x00400000},
482 {AUD_PILOT_BQD_2_K3, 0x00000000},
483 {AUD_PILOT_BQD_2_K4, 0x00000000},
484 {AUD_MODE_CHG_TIMER, 0x00000060},
485 {AUD_AFE_12DB_EN, 0x00000001},
486 {AAGC_HYST, 0x0000000a},
487 {AUD_CORDIC_SHIFT_0, 0x00000007},
488 {AUD_CORDIC_SHIFT_1, 0x00000007},
489 {AUD_C1_UP_THR, 0x00007000},
490 {AUD_C1_LO_THR, 0x00005400},
491 {AUD_C2_UP_THR, 0x00005400},
492 {AUD_C2_LO_THR, 0x00003000},
493 {AUD_DCOC_0_SRC, 0x0000001a},
494 {AUD_DCOC0_SHIFT, 0x00000000},
495 {AUD_DCOC_0_SHIFT_IN0, 0x0000000a},
496 {AUD_DCOC_0_SHIFT_IN1, 0x00000008},
497 {AUD_DCOC_PASS_IN, 0x00000003},
498 {AUD_IIR3_0_SEL, 0x00000021},
499 {AUD_DN2_AFC, 0x00000002},
500 {AUD_DCOC_1_SRC, 0x0000001b},
501 {AUD_DCOC1_SHIFT, 0x00000000},
502 {AUD_DCOC_1_SHIFT_IN0, 0x0000000a},
503 {AUD_DCOC_1_SHIFT_IN1, 0x00000008},
504 {AUD_IIR3_1_SEL, 0x00000023},
505 {AUD_DN0_FREQ, 0x000035a3},
506 {AUD_DN2_FREQ, 0x000029c7},
507 {AUD_CRDC0_SRC_SEL, 0x00000511},
508 {AUD_IIR1_0_SEL, 0x00000001},
509 {AUD_IIR1_1_SEL, 0x00000000},
510 {AUD_IIR3_2_SEL, 0x00000003},
511 {AUD_IIR3_2_SHIFT, 0x00000000},
512 {AUD_IIR3_0_SEL, 0x00000002},
513 {AUD_IIR2_0_SEL, 0x00000021},
514 {AUD_IIR2_0_SHIFT, 0x00000002},
515 {AUD_DEEMPH0_SRC_SEL, 0x0000000b},
516 {AUD_DEEMPH1_SRC_SEL, 0x0000000b},
517 {AUD_POLYPH80SCALEFAC, 0x00000001},
518 {AUD_START_TIMER, 0x00000000},
519 { /* end of list */ },
b1706b91
TS		 520 };
521
522 static const struct rlist am_l[] = {
7b3c6d65
NS		 523 {AUD_ERRLOGPERIOD_R, 0x00000064},
524 {AUD_ERRINTRPTTHSHLD1_R, 0x00000FFF},
525 {AUD_ERRINTRPTTHSHLD2_R, 0x0000001F},
526 {AUD_ERRINTRPTTHSHLD3_R, 0x0000000F},
527 {AUD_PDF_DDS_CNST_BYTE2, 0x48},
528 {AUD_PDF_DDS_CNST_BYTE1, 0x3D},
529 {AUD_QAM_MODE, 0x00},
530 {AUD_PDF_DDS_CNST_BYTE0, 0xf5},
531 {AUD_PHACC_FREQ_8MSB, 0x3a},
532 {AUD_PHACC_FREQ_8LSB, 0x4a},
533 {AUD_DEEMPHGAIN_R, 0x00006680},
534 {AUD_DEEMPHNUMER1_R, 0x000353DE},
535 {AUD_DEEMPHNUMER2_R, 0x000001B1},
536 {AUD_DEEMPHDENOM1_R, 0x0000F3D0},
537 {AUD_DEEMPHDENOM2_R, 0x00000000},
538 {AUD_FM_MODE_ENABLE, 0x00000007},
539 {AUD_POLYPH80SCALEFAC, 0x00000003},
540 {AUD_AFE_12DB_EN, 0x00000001},
541 {AAGC_GAIN, 0x00000000},
542 {AAGC_HYST, 0x00000018},
543 {AAGC_DEF, 0x00000020},
544 {AUD_DN0_FREQ, 0x00000000},
545 {AUD_POLY0_DDS_CONSTANT, 0x000E4DB2},
546 {AUD_DCOC_0_SRC, 0x00000021},
547 {AUD_IIR1_0_SEL, 0x00000000},
548 {AUD_IIR1_0_SHIFT, 0x00000007},
549 {AUD_IIR1_1_SEL, 0x00000002},
550 {AUD_IIR1_1_SHIFT, 0x00000000},
551 {AUD_DCOC_1_SRC, 0x00000003},
552 {AUD_DCOC1_SHIFT, 0x00000000},
553 {AUD_DCOC_PASS_IN, 0x00000000},
554 {AUD_IIR1_2_SEL, 0x00000023},
555 {AUD_IIR1_2_SHIFT, 0x00000000},
556 {AUD_IIR1_3_SEL, 0x00000004},
557 {AUD_IIR1_3_SHIFT, 0x00000007},
558 {AUD_IIR1_4_SEL, 0x00000005},
559 {AUD_IIR1_4_SHIFT, 0x00000007},
560 {AUD_IIR3_0_SEL, 0x00000007},
561 {AUD_IIR3_0_SHIFT, 0x00000000},
562 {AUD_DEEMPH0_SRC_SEL, 0x00000011},
563 {AUD_DEEMPH0_SHIFT, 0x00000000},
564 {AUD_DEEMPH0_G0, 0x00007000},
565 {AUD_DEEMPH0_A0, 0x00000000},
566 {AUD_DEEMPH0_B0, 0x00000000},
567 {AUD_DEEMPH0_A1, 0x00000000},
568 {AUD_DEEMPH0_B1, 0x00000000},
569 {AUD_DEEMPH1_SRC_SEL, 0x00000011},
570 {AUD_DEEMPH1_SHIFT, 0x00000000},
571 {AUD_DEEMPH1_G0, 0x00007000},
572 {AUD_DEEMPH1_A0, 0x00000000},
573 {AUD_DEEMPH1_B0, 0x00000000},
574 {AUD_DEEMPH1_A1, 0x00000000},
575 {AUD_DEEMPH1_B1, 0x00000000},
576 {AUD_OUT0_SEL, 0x0000003F},
577 {AUD_OUT1_SEL, 0x0000003F},
578 {AUD_DMD_RA_DDS, 0x00F5C285},
579 {AUD_PLL_INT, 0x0000001E},
580 {AUD_PLL_DDS, 0x00000000},
581 {AUD_PLL_FRAC, 0x0000E542},
582 {AUD_RATE_ADJ1, 0x00000100},
583 {AUD_RATE_ADJ2, 0x00000200},
584 {AUD_RATE_ADJ3, 0x00000300},
585 {AUD_RATE_ADJ4, 0x00000400},
586 {AUD_RATE_ADJ5, 0x00000500},
587 {AUD_RATE_THRES_DMD, 0x000000C0},
588 { /* end of list */ },
1da177e4 589 };
e52e98a7
MCC		 590
591 static const struct rlist a2_deemph50[] = {
7b3c6d65
NS		 592 {AUD_DEEMPH0_G0, 0x00000380},
593 {AUD_DEEMPH1_G0, 0x00000380},
594 {AUD_DEEMPHGAIN_R, 0x000011e1},
595 {AUD_DEEMPHNUMER1_R, 0x0002a7bc},
596 {AUD_DEEMPHNUMER2_R, 0x0003023c},
597 { /* end of list */ },
e52e98a7
MCC		 598 };
599
e52e98a7 600 set_audio_start(core, SEL_A2);
1da177e4 601 switch (core->tvaudio) {
b1706b91 602 case WW_BG:
7b3c6d65 603 dprintk("%s PAL-BG A1/2 (status: known-good)\n", __FUNCTION__);
b1706b91
TS		 604 set_audio_registers(core, a2_bgdk_common);
605 set_audio_registers(core, a2_bg);
606 set_audio_registers(core, a2_deemph50);
1da177e4 607 break;
b1706b91 608 case WW_DK:
7b3c6d65 609 dprintk("%s PAL-DK A1/2 (status: known-good)\n", __FUNCTION__);
b1706b91
TS		 610 set_audio_registers(core, a2_bgdk_common);
611 set_audio_registers(core, a2_dk);
612 set_audio_registers(core, a2_deemph50);
1da177e4 613 break;
b1706b91 614 case WW_I:
7b3c6d65 615 dprintk("%s PAL-I A1 (status: known-good)\n", __FUNCTION__);
b1706b91
TS		 616 set_audio_registers(core, a1_i);
617 set_audio_registers(core, a2_deemph50);
618 break;
619 case WW_L:
7b3c6d65 620 dprintk("%s AM-L (status: devel)\n", __FUNCTION__);
b1706b91
TS		 621 set_audio_registers(core, am_l);
622 break;
623 default:
7b3c6d65 624 dprintk("%s Warning: wrong value\n", __FUNCTION__);
b1706b91 625 return;
1da177e4
LT		 626 break;
627 };
e52e98a7
MCC		 628
629 mode |= EN_FMRADIO_EN_RDS | EN_DMTRX_SUMDIFF;
630 set_audio_finish(core, mode);
1da177e4
LT		 631}
632
633static void set_audio_standard_EIAJ(struct cx88_core *core)
634{
635 static const struct rlist eiaj[] = {
636 /* TODO: eiaj register settings are not there yet ... */
637
638 { /* end of list */ },
639 };
7b3c6d65 640 dprintk("%s (status: unknown)\n", __FUNCTION__);
1da177e4 641
e52e98a7 642 set_audio_start(core, SEL_EIAJ);
1da177e4 643 set_audio_registers(core, eiaj);
e52e98a7 644 set_audio_finish(core, EN_EIAJ_AUTO_STEREO);
1da177e4
LT		 645}
646
7b3c6d65
NS		 647static void set_audio_standard_FM(struct cx88_core *core,
648 enum cx88_deemph_type deemph)
1da177e4 649{
b45009b0 650 static const struct rlist fm_deemph_50[] = {
7b3c6d65
NS		 651 {AUD_DEEMPH0_G0, 0x0C45},
652 {AUD_DEEMPH0_A0, 0x6262},
653 {AUD_DEEMPH0_B0, 0x1C29},
654 {AUD_DEEMPH0_A1, 0x3FC66},
655 {AUD_DEEMPH0_B1, 0x399A},
656
657 {AUD_DEEMPH1_G0, 0x0D80},
658 {AUD_DEEMPH1_A0, 0x6262},
659 {AUD_DEEMPH1_B0, 0x1C29},
660 {AUD_DEEMPH1_A1, 0x3FC66},
661 {AUD_DEEMPH1_B1, 0x399A},
662
663 {AUD_POLYPH80SCALEFAC, 0x0003},
b45009b0
MCC		 664 { /* end of list */ },
665 };
666 static const struct rlist fm_deemph_75[] = {
7b3c6d65
NS		 667 {AUD_DEEMPH0_G0, 0x091B},
668 {AUD_DEEMPH0_A0, 0x6B68},
669 {AUD_DEEMPH0_B0, 0x11EC},
670 {AUD_DEEMPH0_A1, 0x3FC66},
671 {AUD_DEEMPH0_B1, 0x399A},
672
673 {AUD_DEEMPH1_G0, 0x0AA0},
674 {AUD_DEEMPH1_A0, 0x6B68},
675 {AUD_DEEMPH1_B0, 0x11EC},
676 {AUD_DEEMPH1_A1, 0x3FC66},
677 {AUD_DEEMPH1_B1, 0x399A},
678
679 {AUD_POLYPH80SCALEFAC, 0x0003},
b45009b0
MCC		 680 { /* end of list */ },
681 };
1da177e4 682
b45009b0 683 /* It is enough to leave default values? */
fa40b223
TP		 684 /* No, it's not! The deemphasis registers are reset to the 75us
685 * values by default. Analyzing the spectrum of the decoded audio
686 * reveals that "no deemphasis" is the same as 75 us, while the 50 us
687 * setting results in less deemphasis. */
b45009b0 688 static const struct rlist fm_no_deemph[] = {
1da177e4 689
7b3c6d65 690 {AUD_POLYPH80SCALEFAC, 0x0003},
b45009b0
MCC		 691 { /* end of list */ },
692 };
1da177e4 693
7b3c6d65 694 dprintk("%s (status: unknown)\n", __FUNCTION__);
e52e98a7 695 set_audio_start(core, SEL_FMRADIO);
1da177e4 696
7b3c6d65 697 switch (deemph) {
fa40b223 698 default:
7b3c6d65
NS		 699 case FM_NO_DEEMPH:
700 set_audio_registers(core, fm_no_deemph);
701 break;
1da177e4 702
7b3c6d65
NS		 703 case FM_DEEMPH_50:
704 set_audio_registers(core, fm_deemph_50);
705 break;
1da177e4 706
7b3c6d65
NS		 707 case FM_DEEMPH_75:
708 set_audio_registers(core, fm_deemph_75);
709 break;
b45009b0 710 }
1da177e4 711
e52e98a7 712 set_audio_finish(core, EN_FMRADIO_AUTO_STEREO);
1da177e4
LT		 713}
714
715/* ----------------------------------------------------------- */
716
dff47bf2 717static int cx88_detect_nicam(struct cx88_core *core)
b1706b91 718{
7b3c6d65 719 int i, j = 0;
b1706b91
TS		 720
721 dprintk("start nicam autodetect.\n");
722
7b3c6d65
NS		 723 for (i = 0; i < 6; i++) {
724 /* if bit1=1 then nicam is detected */
725 j += ((cx_read(AUD_NICAM_STATUS2) & 0x02) >> 1);
b1706b91 726
53a7338a 727 if (j == 1) {
b1706b91
TS		 728 dprintk("nicam is detected.\n");
729 return 1;
730 }
731
732 /* wait a little bit for next reading status */
7b3c6d65 733 msleep(10);
b1706b91
TS		 734 }
735
736 dprintk("nicam is not detected.\n");
737 return 0;
738}
739
1da177e4
LT		 740void cx88_set_tvaudio(struct cx88_core *core)
741{
742 switch (core->tvaudio) {
743 case WW_BTSC:
e52e98a7 744 set_audio_standard_BTSC(core, 0, EN_BTSC_AUTO_STEREO);
1da177e4 745 break;
b1706b91
TS		 746 case WW_BG:
747 case WW_DK:
748 case WW_I:
749 case WW_L:
750 /* prepare all dsp registers */
751 set_audio_standard_A2(core, EN_A2_FORCE_MONO1);
752
753 /* set nicam mode - otherwise
754 AUD_NICAM_STATUS2 contains wrong values */
7f7e846c 755 set_audio_standard_NICAM(core, EN_NICAM_AUTO_STEREO);
7b3c6d65 756 if (0 == cx88_detect_nicam(core)) {
b1706b91
TS		 757 /* fall back to fm / am mono */
758 set_audio_standard_A2(core, EN_A2_FORCE_MONO1);
759 core->use_nicam = 0;
7b3c6d65 760 } else {
b1706b91 761 core->use_nicam = 1;
7b3c6d65 762 }
1da177e4
LT		 763 break;
764 case WW_EIAJ:
765 set_audio_standard_EIAJ(core);
766 break;
767 case WW_FM:
fa40b223 768 set_audio_standard_FM(core, radio_deemphasis);
1da177e4 769 break;
1da177e4
LT		 770 case WW_NONE:
771 default:
772 printk("%s/0: unknown tv audio mode [%d]\n",
7b3c6d65 773 core->name, core->tvaudio);
1da177e4
LT		 774 break;
775 }
776 return;
777}
778
779void cx88_newstation(struct cx88_core *core)
780{
781 core->audiomode_manual = UNSET;
1da177e4
LT		 782}
783
784void cx88_get_stereo(struct cx88_core *core, struct v4l2_tuner *t)
785{
7b3c6d65
NS		 786 static char *m[] = { "stereo", "dual mono", "mono", "sap" };
787 static char *p[] = { "no pilot", "pilot c1", "pilot c2", "?" };
788 u32 reg, mode, pilot;
1da177e4 789
7b3c6d65
NS		 790 reg = cx_read(AUD_STATUS);
791 mode = reg & 0x03;
1da177e4
LT		 792 pilot = (reg >> 2) & 0x03;
793
794 if (core->astat != reg)
795 dprintk("AUD_STATUS: 0x%x [%s/%s] ctl=%s\n",
796 reg, m[mode], p[pilot],
797 aud_ctl_names[cx_read(AUD_CTL) & 63]);
798 core->astat = reg;
799
e52e98a7 800/* TODO
b930e1d8
MK		 801 Reading from AUD_STATUS is not enough
802 for auto-detecting sap/dual-fm/nicam.
803 Add some code here later.
e52e98a7
MCC		 804*/
805
1da177e4
LT		 806 return;
807}
808
809void cx88_set_stereo(struct cx88_core *core, u32 mode, int manual)
810{
7b3c6d65 811 u32 ctl = UNSET;
1da177e4
LT		 812 u32 mask = UNSET;
813
814 if (manual) {
815 core->audiomode_manual = mode;
816 } else {
817 if (UNSET != core->audiomode_manual)
818 return;
819 }
820 core->audiomode_current = mode;
821
822 switch (core->tvaudio) {
823 case WW_BTSC:
824 switch (mode) {
825 case V4L2_TUNER_MODE_MONO:
e52e98a7 826 set_audio_standard_BTSC(core, 0, EN_BTSC_FORCE_MONO);
1da177e4 827 break;
e52e98a7
MCC		 828 case V4L2_TUNER_MODE_LANG1:
829 set_audio_standard_BTSC(core, 0, EN_BTSC_AUTO_STEREO);
830 break;
831 case V4L2_TUNER_MODE_LANG2:
832 set_audio_standard_BTSC(core, 1, EN_BTSC_FORCE_SAP);
1da177e4
LT		 833 break;
834 case V4L2_TUNER_MODE_STEREO:
301e22d6 835 case V4L2_TUNER_MODE_LANG1_LANG2:
e52e98a7 836 set_audio_standard_BTSC(core, 0, EN_BTSC_FORCE_STEREO);
1da177e4
LT		 837 break;
838 }
839 break;
b1706b91
TS		 840 case WW_BG:
841 case WW_DK:
842 case WW_I:
843 case WW_L:
7b3c6d65 844 if (1 == core->use_nicam) {
b1706b91
TS		 845 switch (mode) {
846 case V4L2_TUNER_MODE_MONO:
847 case V4L2_TUNER_MODE_LANG1:
7b3c6d65
NS		 848 set_audio_standard_NICAM(core,
849 EN_NICAM_FORCE_MONO1);
b1706b91
TS		 850 break;
851 case V4L2_TUNER_MODE_LANG2:
7b3c6d65
NS		 852 set_audio_standard_NICAM(core,
853 EN_NICAM_FORCE_MONO2);
b1706b91
TS		 854 break;
855 case V4L2_TUNER_MODE_STEREO:
301e22d6 856 case V4L2_TUNER_MODE_LANG1_LANG2:
7b3c6d65
NS		 857 set_audio_standard_NICAM(core,
858 EN_NICAM_FORCE_STEREO);
b1706b91
TS		 859 break;
860 }
861 } else {
7b3c6d65 862 if ((core->tvaudio == WW_I) || (core->tvaudio == WW_L)) {
b1706b91
TS		 863 /* fall back to fm / am mono */
864 set_audio_standard_A2(core, EN_A2_FORCE_MONO1);
865 } else {
866 /* TODO: Add A2 autodection */
867 switch (mode) {
868 case V4L2_TUNER_MODE_MONO:
869 case V4L2_TUNER_MODE_LANG1:
7b3c6d65
NS		 870 set_audio_standard_A2(core,
871 EN_A2_FORCE_MONO1);
b1706b91
TS		 872 break;
873 case V4L2_TUNER_MODE_LANG2:
7b3c6d65
NS		 874 set_audio_standard_A2(core,
875 EN_A2_FORCE_MONO2);
b1706b91
TS		 876 break;
877 case V4L2_TUNER_MODE_STEREO:
301e22d6 878 case V4L2_TUNER_MODE_LANG1_LANG2:
7b3c6d65
NS		 879 set_audio_standard_A2(core,
880 EN_A2_FORCE_STEREO);
b1706b91
TS		 881 break;
882 }
883 }
1da177e4
LT		 884 }
885 break;
886 case WW_FM:
887 switch (mode) {
888 case V4L2_TUNER_MODE_MONO:
7b3c6d65 889 ctl = EN_FMRADIO_FORCE_MONO;
1da177e4
LT		 890 mask = 0x3f;
891 break;
892 case V4L2_TUNER_MODE_STEREO:
7b3c6d65 893 ctl = EN_FMRADIO_AUTO_STEREO;
1da177e4
LT		 894 mask = 0x3f;
895 break;
896 }
897 break;
898 }
899
900 if (UNSET != ctl) {
901 dprintk("cx88_set_stereo: mask 0x%x, ctl 0x%x "
902 "[status=0x%x,ctl=0x%x,vol=0x%x]\n",
903 mask, ctl, cx_read(AUD_STATUS),
904 cx_read(AUD_CTL), cx_sread(SHADOW_AUD_VOL_CTL));
905 cx_andor(AUD_CTL, mask, ctl);
906 }
907 return;
908}
909
910int cx88_audio_thread(void *data)
911{
912 struct cx88_core *core = data;
913 struct v4l2_tuner t;
914 u32 mode = 0;
915
916 dprintk("cx88: tvaudio thread started\n");
83144186 917 set_freezable();
1da177e4
LT		 918 for (;;) {
919 msleep_interruptible(1000);
920 if (kthread_should_stop())
921 break;
a96afb3e 922 try_to_freeze();
1da177e4
LT		 923
924 /* just monitor the audio status for now ... */
7b3c6d65
NS		 925 memset(&t, 0, sizeof(t));
926 cx88_get_stereo(core, &t);
1da177e4
LT		 927
928 if (UNSET != core->audiomode_manual)
929 /* manually set, don't do anything. */
930 continue;
931
932 /* monitor signal */
933 if (t.rxsubchans & V4L2_TUNER_SUB_STEREO)
934 mode = V4L2_TUNER_MODE_STEREO;
935 else
936 mode = V4L2_TUNER_MODE_MONO;
937 if (mode == core->audiomode_current)
938 continue;
939
940 /* automatically switch to best available mode */
941 cx88_set_stereo(core, mode, 0);
942 }
943
944 dprintk("cx88: tvaudio thread exiting\n");
945 return 0;
946}
947
948/* ----------------------------------------------------------- */
949
950EXPORT_SYMBOL(cx88_set_tvaudio);
951EXPORT_SYMBOL(cx88_newstation);
952EXPORT_SYMBOL(cx88_set_stereo);
953EXPORT_SYMBOL(cx88_get_stereo);
954EXPORT_SYMBOL(cx88_audio_thread);
955
956/*
957 * Local variables:
958 * c-basic-offset: 8
959 * End:
b45009b0 960 * kate: eol "unix"; indent-width 3; remove-trailing-space on; replace-trailing-space-save on; tab-width 8; replace-tabs off; space-indent off; mixed-indent off
1da177e4 961 */
kernel source for telekom puls (alcatel/mediatek)