V4L/DVB (7094): static memory
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / media / video / cx88 / cx88-dvb.c
CommitLineData
1da177e4 1/*
1da177e4
LT
2 *
3 * device driver for Conexant 2388x based TV cards
4 * MPEG Transport Stream (DVB) routines
5 *
fc40b261 6 * (c) 2004, 2005 Chris Pascoe <c.pascoe@itee.uq.edu.au>
1da177e4
LT
7 * (c) 2004 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24#include <linux/module.h>
25#include <linux/init.h>
26#include <linux/device.h>
27#include <linux/fs.h>
28#include <linux/kthread.h>
29#include <linux/file.h>
30#include <linux/suspend.h>
31
1da177e4
LT
32#include "cx88.h"
33#include "dvb-pll.h"
5e453dc7 34#include <media/v4l2-common.h>
41ef7c1e 35
1f10c7af
AQ
36#include "mt352.h"
37#include "mt352_priv.h"
ecf854df 38#include "cx88-vp3054-i2c.h"
1f10c7af
AQ
39#include "zl10353.h"
40#include "cx22702.h"
41#include "or51132.h"
42#include "lgdt330x.h"
60464da8
ST
43#include "s5h1409.h"
44#include "xc5000.h"
1f10c7af
AQ
45#include "nxt200x.h"
46#include "cx24123.h"
cd20ca9f 47#include "isl6421.h"
1da177e4
LT
48
49MODULE_DESCRIPTION("driver for cx2388x based DVB cards");
50MODULE_AUTHOR("Chris Pascoe <c.pascoe@itee.uq.edu.au>");
51MODULE_AUTHOR("Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]");
52MODULE_LICENSE("GPL");
53
ff699e6b 54static unsigned int debug;
1da177e4
LT
55module_param(debug, int, 0644);
56MODULE_PARM_DESC(debug,"enable debug messages [dvb]");
57
58#define dprintk(level,fmt, arg...) if (debug >= level) \
6c5be74c 59 printk(KERN_DEBUG "%s/2-dvb: " fmt, core->name, ## arg)
1da177e4
LT
60
61/* ------------------------------------------------------------------ */
62
63static int dvb_buf_setup(struct videobuf_queue *q,
64 unsigned int *count, unsigned int *size)
65{
66 struct cx8802_dev *dev = q->priv_data;
67
68 dev->ts_packet_size = 188 * 4;
69 dev->ts_packet_count = 32;
70
71 *size = dev->ts_packet_size * dev->ts_packet_count;
72 *count = 32;
73 return 0;
74}
75
4a390558
MK
76static int dvb_buf_prepare(struct videobuf_queue *q,
77 struct videobuf_buffer *vb, enum v4l2_field field)
1da177e4
LT
78{
79 struct cx8802_dev *dev = q->priv_data;
c7b0ac05 80 return cx8802_buf_prepare(q, dev, (struct cx88_buffer*)vb,field);
1da177e4
LT
81}
82
83static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
84{
85 struct cx8802_dev *dev = q->priv_data;
86 cx8802_buf_queue(dev, (struct cx88_buffer*)vb);
87}
88
4a390558
MK
89static void dvb_buf_release(struct videobuf_queue *q,
90 struct videobuf_buffer *vb)
1da177e4 91{
c7b0ac05 92 cx88_free_buffer(q, (struct cx88_buffer*)vb);
1da177e4
LT
93}
94
408b664a 95static struct videobuf_queue_ops dvb_qops = {
1da177e4
LT
96 .buf_setup = dvb_buf_setup,
97 .buf_prepare = dvb_buf_prepare,
98 .buf_queue = dvb_buf_queue,
99 .buf_release = dvb_buf_release,
100};
101
102/* ------------------------------------------------------------------ */
22f3f17d
MK
103
104static int cx88_dvb_bus_ctrl(struct dvb_frontend* fe, int acquire)
105{
106 struct cx8802_dev *dev= fe->dvb->priv;
107 struct cx8802_driver *drv = NULL;
108 int ret = 0;
109
110 drv = cx8802_get_driver(dev, CX88_MPEG_DVB);
111 if (drv) {
4a390558 112 if (acquire)
22f3f17d
MK
113 ret = drv->request_acquire(drv);
114 else
115 ret = drv->request_release(drv);
116 }
117
118 return ret;
119}
120
121/* ------------------------------------------------------------------ */
122
3d7d027a 123static int dvico_fusionhdtv_demod_init(struct dvb_frontend* fe)
1da177e4
LT
124{
125 static u8 clock_config [] = { CLOCK_CTL, 0x38, 0x39 };
126 static u8 reset [] = { RESET, 0x80 };
127 static u8 adc_ctl_1_cfg [] = { ADC_CTL_1, 0x40 };
128 static u8 agc_cfg [] = { AGC_TARGET, 0x24, 0x20 };
129 static u8 gpp_ctl_cfg [] = { GPP_CTL, 0x33 };
130 static u8 capt_range_cfg[] = { CAPT_RANGE, 0x32 };
131
132 mt352_write(fe, clock_config, sizeof(clock_config));
133 udelay(200);
134 mt352_write(fe, reset, sizeof(reset));
135 mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
136
137 mt352_write(fe, agc_cfg, sizeof(agc_cfg));
138 mt352_write(fe, gpp_ctl_cfg, sizeof(gpp_ctl_cfg));
139 mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
140 return 0;
141}
142
43eabb4e
CP
143static int dvico_dual_demod_init(struct dvb_frontend *fe)
144{
145 static u8 clock_config [] = { CLOCK_CTL, 0x38, 0x38 };
146 static u8 reset [] = { RESET, 0x80 };
147 static u8 adc_ctl_1_cfg [] = { ADC_CTL_1, 0x40 };
148 static u8 agc_cfg [] = { AGC_TARGET, 0x28, 0x20 };
149 static u8 gpp_ctl_cfg [] = { GPP_CTL, 0x33 };
150 static u8 capt_range_cfg[] = { CAPT_RANGE, 0x32 };
151
152 mt352_write(fe, clock_config, sizeof(clock_config));
153 udelay(200);
154 mt352_write(fe, reset, sizeof(reset));
155 mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
156
157 mt352_write(fe, agc_cfg, sizeof(agc_cfg));
158 mt352_write(fe, gpp_ctl_cfg, sizeof(gpp_ctl_cfg));
159 mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
160
161 return 0;
162}
163
1da177e4
LT
164static int dntv_live_dvbt_demod_init(struct dvb_frontend* fe)
165{
166 static u8 clock_config [] = { 0x89, 0x38, 0x39 };
167 static u8 reset [] = { 0x50, 0x80 };
168 static u8 adc_ctl_1_cfg [] = { 0x8E, 0x40 };
169 static u8 agc_cfg [] = { 0x67, 0x10, 0x23, 0x00, 0xFF, 0xFF,
f2421ca3 170 0x00, 0xFF, 0x00, 0x40, 0x40 };
1da177e4
LT
171 static u8 dntv_extra[] = { 0xB5, 0x7A };
172 static u8 capt_range_cfg[] = { 0x75, 0x32 };
173
174 mt352_write(fe, clock_config, sizeof(clock_config));
175 udelay(2000);
176 mt352_write(fe, reset, sizeof(reset));
177 mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
178
179 mt352_write(fe, agc_cfg, sizeof(agc_cfg));
180 udelay(2000);
181 mt352_write(fe, dntv_extra, sizeof(dntv_extra));
182 mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
183
184 return 0;
185}
186
1da177e4 187static struct mt352_config dvico_fusionhdtv = {
f7b54b10 188 .demod_address = 0x0f,
3d7d027a 189 .demod_init = dvico_fusionhdtv_demod_init,
1da177e4
LT
190};
191
192static struct mt352_config dntv_live_dvbt_config = {
193 .demod_address = 0x0f,
194 .demod_init = dntv_live_dvbt_demod_init,
1da177e4 195};
fc40b261 196
43eabb4e 197static struct mt352_config dvico_fusionhdtv_dual = {
f7b54b10 198 .demod_address = 0x0f,
43eabb4e 199 .demod_init = dvico_dual_demod_init,
43eabb4e
CP
200};
201
ecf854df 202#if defined(CONFIG_VIDEO_CX88_VP3054) || (defined(CONFIG_VIDEO_CX88_VP3054_MODULE) && defined(MODULE))
3d7d027a
CP
203static int dntv_live_dvbt_pro_demod_init(struct dvb_frontend* fe)
204{
205 static u8 clock_config [] = { 0x89, 0x38, 0x38 };
206 static u8 reset [] = { 0x50, 0x80 };
207 static u8 adc_ctl_1_cfg [] = { 0x8E, 0x40 };
208 static u8 agc_cfg [] = { 0x67, 0x10, 0x20, 0x00, 0xFF, 0xFF,
209 0x00, 0xFF, 0x00, 0x40, 0x40 };
210 static u8 dntv_extra[] = { 0xB5, 0x7A };
211 static u8 capt_range_cfg[] = { 0x75, 0x32 };
212
213 mt352_write(fe, clock_config, sizeof(clock_config));
214 udelay(2000);
215 mt352_write(fe, reset, sizeof(reset));
216 mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
217
218 mt352_write(fe, agc_cfg, sizeof(agc_cfg));
219 udelay(2000);
220 mt352_write(fe, dntv_extra, sizeof(dntv_extra));
221 mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
222
223 return 0;
224}
225
fc40b261
CP
226static struct mt352_config dntv_live_dvbt_pro_config = {
227 .demod_address = 0x0f,
228 .no_tuner = 1,
3d7d027a 229 .demod_init = dntv_live_dvbt_pro_demod_init,
fc40b261
CP
230};
231#endif
1da177e4 232
780dfef3 233static struct zl10353_config dvico_fusionhdtv_hybrid = {
f7b54b10 234 .demod_address = 0x0f,
f54376e2 235 .no_tuner = 1,
780dfef3
CP
236};
237
238static struct zl10353_config dvico_fusionhdtv_plus_v1_1 = {
f7b54b10 239 .demod_address = 0x0f,
780dfef3 240};
780dfef3 241
1da177e4
LT
242static struct cx22702_config connexant_refboard_config = {
243 .demod_address = 0x43,
38d84c3b 244 .output_mode = CX22702_SERIAL_OUTPUT,
1da177e4
LT
245};
246
ed355260 247static struct cx22702_config hauppauge_hvr_config = {
aa481a65
ST
248 .demod_address = 0x63,
249 .output_mode = CX22702_SERIAL_OUTPUT,
250};
1da177e4 251
4a390558 252static int or51132_set_ts_param(struct dvb_frontend* fe, int is_punctured)
1da177e4
LT
253{
254 struct cx8802_dev *dev= fe->dvb->priv;
255 dev->ts_gen_cntrl = is_punctured ? 0x04 : 0x00;
256 return 0;
257}
258
408b664a 259static struct or51132_config pchdtv_hd3000 = {
f7b54b10
MK
260 .demod_address = 0x15,
261 .set_ts_params = or51132_set_ts_param,
1da177e4 262};
1da177e4 263
6ddcc919 264static int lgdt330x_pll_rf_set(struct dvb_frontend* fe, int index)
0ccef6db
MK
265{
266 struct cx8802_dev *dev= fe->dvb->priv;
267 struct cx88_core *core = dev->core;
268
269 dprintk(1, "%s: index = %d\n", __FUNCTION__, index);
270 if (index == 0)
271 cx_clear(MO_GP0_IO, 8);
272 else
273 cx_set(MO_GP0_IO, 8);
274 return 0;
275}
276
6ddcc919 277static int lgdt330x_set_ts_param(struct dvb_frontend* fe, int is_punctured)
f1798495
MK
278{
279 struct cx8802_dev *dev= fe->dvb->priv;
280 if (is_punctured)
281 dev->ts_gen_cntrl |= 0x04;
282 else
283 dev->ts_gen_cntrl &= ~0x04;
284 return 0;
285}
286
6ddcc919 287static struct lgdt330x_config fusionhdtv_3_gold = {
f7b54b10
MK
288 .demod_address = 0x0e,
289 .demod_chip = LGDT3302,
290 .serial_mpeg = 0x04, /* TPSERIAL for 3302 in TOP_CONTROL */
291 .set_ts_params = lgdt330x_set_ts_param,
0d723c09 292};
e52e98a7
MCC
293
294static struct lgdt330x_config fusionhdtv_5_gold = {
f7b54b10
MK
295 .demod_address = 0x0e,
296 .demod_chip = LGDT3303,
297 .serial_mpeg = 0x40, /* TPSERIAL for 3303 in TOP_CONTROL */
298 .set_ts_params = lgdt330x_set_ts_param,
e52e98a7 299};
da215d22
RS
300
301static struct lgdt330x_config pchdtv_hd5500 = {
f7b54b10
MK
302 .demod_address = 0x59,
303 .demod_chip = LGDT3303,
304 .serial_mpeg = 0x40, /* TPSERIAL for 3303 in TOP_CONTROL */
305 .set_ts_params = lgdt330x_set_ts_param,
da215d22 306};
f1798495 307
4a390558 308static int nxt200x_set_ts_param(struct dvb_frontend* fe, int is_punctured)
fde6d31e
KL
309{
310 struct cx8802_dev *dev= fe->dvb->priv;
311 dev->ts_gen_cntrl = is_punctured ? 0x04 : 0x00;
312 return 0;
313}
314
315static struct nxt200x_config ati_hdtvwonder = {
f7b54b10 316 .demod_address = 0x0a,
f7b54b10 317 .set_ts_params = nxt200x_set_ts_param,
fde6d31e 318};
fde6d31e 319
0fa14aa6
ST
320static int cx24123_set_ts_param(struct dvb_frontend* fe,
321 int is_punctured)
322{
323 struct cx8802_dev *dev= fe->dvb->priv;
f7b54b10 324 dev->ts_gen_cntrl = 0x02;
0fa14aa6
ST
325 return 0;
326}
327
f7b54b10
MK
328static int kworld_dvbs_100_set_voltage(struct dvb_frontend* fe,
329 fe_sec_voltage_t voltage)
0e0351e3
VC
330{
331 struct cx8802_dev *dev= fe->dvb->priv;
332 struct cx88_core *core = dev->core;
333
4a390558 334 if (voltage == SEC_VOLTAGE_OFF)
f7b54b10 335 cx_write(MO_GP0_IO, 0x000006fb);
4a390558 336 else
cd20ca9f 337 cx_write(MO_GP0_IO, 0x000006f9);
cd20ca9f
AQ
338
339 if (core->prev_set_voltage)
340 return core->prev_set_voltage(fe, voltage);
341 return 0;
0e0351e3
VC
342}
343
f7b54b10
MK
344static int geniatech_dvbs_set_voltage(struct dvb_frontend *fe,
345 fe_sec_voltage_t voltage)
c02a34f4
SA
346{
347 struct cx8802_dev *dev= fe->dvb->priv;
348 struct cx88_core *core = dev->core;
349
350 if (voltage == SEC_VOLTAGE_OFF) {
351 dprintk(1,"LNB Voltage OFF\n");
352 cx_write(MO_GP0_IO, 0x0000efff);
353 }
354
355 if (core->prev_set_voltage)
356 return core->prev_set_voltage(fe, voltage);
357 return 0;
358}
359
360static struct cx24123_config geniatech_dvbs_config = {
f7b54b10
MK
361 .demod_address = 0x55,
362 .set_ts_params = cx24123_set_ts_param,
c02a34f4
SA
363};
364
0fa14aa6 365static struct cx24123_config hauppauge_novas_config = {
f7b54b10
MK
366 .demod_address = 0x55,
367 .set_ts_params = cx24123_set_ts_param,
0e0351e3
VC
368};
369
370static struct cx24123_config kworld_dvbs_100_config = {
f7b54b10
MK
371 .demod_address = 0x15,
372 .set_ts_params = cx24123_set_ts_param,
ef76856d 373 .lnb_polarity = 1,
0fa14aa6 374};
0fa14aa6 375
60464da8
ST
376static struct s5h1409_config pinnacle_pctv_hd_800i_config = {
377 .demod_address = 0x32 >> 1,
378 .output_mode = S5H1409_PARALLEL_OUTPUT,
379 .gpio = S5H1409_GPIO_ON,
380 .qam_if = 44000,
381 .inversion = S5H1409_INVERSION_OFF,
382 .status_mode = S5H1409_DEMODLOCKING,
4917019d 383 .mpeg_timing = S5H1409_MPEGTIMING_NONCONTINOUS_NONINVERTING_CLOCK,
60464da8
ST
384};
385
386static struct xc5000_config pinnacle_pctv_hd_800i_tuner_config = {
387 .i2c_address = 0x64,
388 .if_khz = 5380,
60464da8
ST
389 .tuner_callback = cx88_tuner_callback,
390};
391
1da177e4
LT
392static int dvb_register(struct cx8802_dev *dev)
393{
394 /* init struct videobuf_dvb */
395 dev->dvb.name = dev->core->name;
396 dev->ts_gen_cntrl = 0x0c;
397
398 /* init frontend */
6a59d64c 399 switch (dev->core->boardnr) {
1da177e4 400 case CX88_BOARD_HAUPPAUGE_DVB_T1:
f7b54b10 401 dev->dvb.frontend = dvb_attach(cx22702_attach,
ed355260 402 &connexant_refboard_config,
f7b54b10 403 &dev->core->i2c_adap);
f54376e2 404 if (dev->dvb.frontend != NULL) {
2bfe031d 405 dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
f7b54b10 406 &dev->core->i2c_adap,
47a9991e 407 DVB_PLL_THOMSON_DTT759X);
f54376e2 408 }
1da177e4 409 break;
e057ee11 410 case CX88_BOARD_TERRATEC_CINERGY_1400_DVB_T1:
1da177e4 411 case CX88_BOARD_CONEXANT_DVB_T1:
f39624fd 412 case CX88_BOARD_KWORLD_DVB_T_CX22702:
2b5200a7 413 case CX88_BOARD_WINFAST_DTV1000:
f7b54b10
MK
414 dev->dvb.frontend = dvb_attach(cx22702_attach,
415 &connexant_refboard_config,
416 &dev->core->i2c_adap);
f54376e2 417 if (dev->dvb.frontend != NULL) {
2bfe031d 418 dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x60,
f7b54b10 419 &dev->core->i2c_adap,
47a9991e 420 DVB_PLL_THOMSON_DTT7579);
f54376e2 421 }
1da177e4 422 break;
4bd6e9d9 423 case CX88_BOARD_WINFAST_DTV2000H:
611900c1
ST
424 case CX88_BOARD_HAUPPAUGE_HVR1100:
425 case CX88_BOARD_HAUPPAUGE_HVR1100LP:
a5a2ecfc
TP
426 case CX88_BOARD_HAUPPAUGE_HVR1300:
427 case CX88_BOARD_HAUPPAUGE_HVR3000:
f7b54b10 428 dev->dvb.frontend = dvb_attach(cx22702_attach,
ed355260 429 &hauppauge_hvr_config,
f7b54b10 430 &dev->core->i2c_adap);
f54376e2 431 if (dev->dvb.frontend != NULL) {
2bfe031d 432 dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
47a9991e 433 &dev->core->i2c_adap, DVB_PLL_FMD1216ME);
f54376e2 434 }
611900c1 435 break;
780dfef3 436 case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_PLUS:
f7b54b10
MK
437 dev->dvb.frontend = dvb_attach(mt352_attach,
438 &dvico_fusionhdtv,
439 &dev->core->i2c_adap);
f54376e2 440 if (dev->dvb.frontend != NULL) {
2bfe031d 441 dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x60,
47a9991e 442 NULL, DVB_PLL_THOMSON_DTT7579);
780dfef3 443 break;
f54376e2 444 }
780dfef3 445 /* ZL10353 replaces MT352 on later cards */
f7b54b10
MK
446 dev->dvb.frontend = dvb_attach(zl10353_attach,
447 &dvico_fusionhdtv_plus_v1_1,
448 &dev->core->i2c_adap);
f54376e2 449 if (dev->dvb.frontend != NULL) {
2bfe031d 450 dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x60,
47a9991e 451 NULL, DVB_PLL_THOMSON_DTT7579);
f54376e2 452 }
c2af3cd6
MK
453 break;
454 case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL:
c2af3cd6
MK
455 /* The tin box says DEE1601, but it seems to be DTT7579
456 * compatible, with a slightly different MT352 AGC gain. */
f7b54b10
MK
457 dev->dvb.frontend = dvb_attach(mt352_attach,
458 &dvico_fusionhdtv_dual,
459 &dev->core->i2c_adap);
c2af3cd6 460 if (dev->dvb.frontend != NULL) {
2bfe031d 461 dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
47a9991e 462 NULL, DVB_PLL_THOMSON_DTT7579);
c2af3cd6
MK
463 break;
464 }
c2af3cd6 465 /* ZL10353 replaces MT352 on later cards */
f7b54b10
MK
466 dev->dvb.frontend = dvb_attach(zl10353_attach,
467 &dvico_fusionhdtv_plus_v1_1,
468 &dev->core->i2c_adap);
c2af3cd6 469 if (dev->dvb.frontend != NULL) {
2bfe031d 470 dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
47a9991e 471 NULL, DVB_PLL_THOMSON_DTT7579);
c2af3cd6 472 }
1da177e4 473 break;
780dfef3 474 case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T1:
f7b54b10
MK
475 dev->dvb.frontend = dvb_attach(mt352_attach,
476 &dvico_fusionhdtv,
477 &dev->core->i2c_adap);
f54376e2 478 if (dev->dvb.frontend != NULL) {
2bfe031d 479 dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
47a9991e 480 NULL, DVB_PLL_LG_Z201);
f54376e2 481 }
1da177e4
LT
482 break;
483 case CX88_BOARD_KWORLD_DVB_T:
484 case CX88_BOARD_DNTV_LIVE_DVB_T:
a82decf6 485 case CX88_BOARD_ADSTECH_DVB_T_PCI:
f7b54b10
MK
486 dev->dvb.frontend = dvb_attach(mt352_attach,
487 &dntv_live_dvbt_config,
488 &dev->core->i2c_adap);
f54376e2 489 if (dev->dvb.frontend != NULL) {
2bfe031d 490 dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
47a9991e 491 NULL, DVB_PLL_UNKNOWN_1);
f54376e2 492 }
1da177e4 493 break;
fc40b261 494 case CX88_BOARD_DNTV_LIVE_DVB_T_PRO:
ecf854df 495#if defined(CONFIG_VIDEO_CX88_VP3054) || (defined(CONFIG_VIDEO_CX88_VP3054_MODULE) && defined(MODULE))
f0ad9097 496 /* MT352 is on a secondary I2C bus made from some GPIO lines */
2bfe031d 497 dev->dvb.frontend = dvb_attach(mt352_attach, &dntv_live_dvbt_pro_config,
f0ad9097 498 &dev->vp3054->adap);
f54376e2 499 if (dev->dvb.frontend != NULL) {
b7754d74 500 dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
47a9991e 501 &dev->core->i2c_adap, DVB_PLL_FMD1216ME);
f54376e2 502 }
fc40b261 503#else
5772f813 504 printk(KERN_ERR "%s/2: built without vp3054 support\n", dev->core->name);
fc40b261
CP
505#endif
506 break;
780dfef3 507 case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_HYBRID:
f7b54b10
MK
508 dev->dvb.frontend = dvb_attach(zl10353_attach,
509 &dvico_fusionhdtv_hybrid,
510 &dev->core->i2c_adap);
f54376e2 511 if (dev->dvb.frontend != NULL) {
5786a34b
MK
512 dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
513 &dev->core->i2c_adap,
47a9991e 514 DVB_PLL_THOMSON_FE6600);
f54376e2 515 }
780dfef3 516 break;
1da177e4 517 case CX88_BOARD_PCHDTV_HD3000:
4a390558 518 dev->dvb.frontend = dvb_attach(or51132_attach, &pchdtv_hd3000,
f7b54b10 519 &dev->core->i2c_adap);
f54376e2 520 if (dev->dvb.frontend != NULL) {
2bfe031d 521 dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
f7b54b10 522 &dev->core->i2c_adap,
47a9991e 523 DVB_PLL_THOMSON_DTT761X);
f54376e2 524 }
1da177e4 525 break;
f1798495
MK
526 case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_Q:
527 dev->ts_gen_cntrl = 0x08;
528 {
529 /* Do a hardware reset of chip before using it. */
530 struct cx88_core *core = dev->core;
531
532 cx_clear(MO_GP0_IO, 1);
533 mdelay(100);
0ccef6db 534 cx_set(MO_GP0_IO, 1);
f1798495 535 mdelay(200);
0ccef6db
MK
536
537 /* Select RF connector callback */
6ddcc919 538 fusionhdtv_3_gold.pll_rf_set = lgdt330x_pll_rf_set;
f7b54b10
MK
539 dev->dvb.frontend = dvb_attach(lgdt330x_attach,
540 &fusionhdtv_3_gold,
541 &dev->core->i2c_adap);
f54376e2 542 if (dev->dvb.frontend != NULL) {
1d4bb7d3
MK
543 dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
544 &dev->core->i2c_adap,
47a9991e 545 DVB_PLL_MICROTUNE_4042);
f54376e2 546 }
f1798495
MK
547 }
548 break;
0d723c09
MK
549 case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_T:
550 dev->ts_gen_cntrl = 0x08;
551 {
552 /* Do a hardware reset of chip before using it. */
553 struct cx88_core *core = dev->core;
554
555 cx_clear(MO_GP0_IO, 1);
556 mdelay(100);
d975872c 557 cx_set(MO_GP0_IO, 9);
0d723c09 558 mdelay(200);
f7b54b10
MK
559 dev->dvb.frontend = dvb_attach(lgdt330x_attach,
560 &fusionhdtv_3_gold,
561 &dev->core->i2c_adap);
f54376e2 562 if (dev->dvb.frontend != NULL) {
1d4bb7d3
MK
563 dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
564 &dev->core->i2c_adap,
47a9991e 565 DVB_PLL_THOMSON_DTT761X);
f54376e2 566 }
0d723c09
MK
567 }
568 break;
e52e98a7
MCC
569 case CX88_BOARD_DVICO_FUSIONHDTV_5_GOLD:
570 dev->ts_gen_cntrl = 0x08;
571 {
572 /* Do a hardware reset of chip before using it. */
573 struct cx88_core *core = dev->core;
574
575 cx_clear(MO_GP0_IO, 1);
576 mdelay(100);
577 cx_set(MO_GP0_IO, 1);
578 mdelay(200);
f7b54b10
MK
579 dev->dvb.frontend = dvb_attach(lgdt330x_attach,
580 &fusionhdtv_5_gold,
581 &dev->core->i2c_adap);
f54376e2 582 if (dev->dvb.frontend != NULL) {
6bdcc6e6
TP
583 dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
584 &dev->core->i2c_adap,
47a9991e 585 DVB_PLL_LG_TDVS_H06XF);
f54376e2 586 }
e52e98a7
MCC
587 }
588 break;
da215d22
RS
589 case CX88_BOARD_PCHDTV_HD5500:
590 dev->ts_gen_cntrl = 0x08;
591 {
592 /* Do a hardware reset of chip before using it. */
593 struct cx88_core *core = dev->core;
594
595 cx_clear(MO_GP0_IO, 1);
596 mdelay(100);
597 cx_set(MO_GP0_IO, 1);
598 mdelay(200);
f7b54b10
MK
599 dev->dvb.frontend = dvb_attach(lgdt330x_attach,
600 &pchdtv_hd5500,
601 &dev->core->i2c_adap);
f54376e2 602 if (dev->dvb.frontend != NULL) {
6bdcc6e6
TP
603 dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
604 &dev->core->i2c_adap,
47a9991e 605 DVB_PLL_LG_TDVS_H06XF);
f54376e2 606 }
da215d22
RS
607 }
608 break;
fde6d31e 609 case CX88_BOARD_ATI_HDTVWONDER:
f7b54b10
MK
610 dev->dvb.frontend = dvb_attach(nxt200x_attach,
611 &ati_hdtvwonder,
612 &dev->core->i2c_adap);
f54376e2 613 if (dev->dvb.frontend != NULL) {
2bfe031d 614 dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
47a9991e 615 NULL, DVB_PLL_TUV1236D);
f54376e2 616 }
0fa14aa6 617 break;
0fa14aa6
ST
618 case CX88_BOARD_HAUPPAUGE_NOVASPLUS_S1:
619 case CX88_BOARD_HAUPPAUGE_NOVASE2_S1:
f7b54b10
MK
620 dev->dvb.frontend = dvb_attach(cx24123_attach,
621 &hauppauge_novas_config,
622 &dev->core->i2c_adap);
cd20ca9f 623 if (dev->dvb.frontend) {
f7b54b10
MK
624 dvb_attach(isl6421_attach, dev->dvb.frontend,
625 &dev->core->i2c_adap, 0x08, 0x00, 0x00);
cd20ca9f 626 }
0e0351e3
VC
627 break;
628 case CX88_BOARD_KWORLD_DVBS_100:
f7b54b10
MK
629 dev->dvb.frontend = dvb_attach(cx24123_attach,
630 &kworld_dvbs_100_config,
631 &dev->core->i2c_adap);
cd20ca9f 632 if (dev->dvb.frontend) {
dea74869
PB
633 dev->core->prev_set_voltage = dev->dvb.frontend->ops.set_voltage;
634 dev->dvb.frontend->ops.set_voltage = kworld_dvbs_100_set_voltage;
cd20ca9f 635 }
fde6d31e 636 break;
c02a34f4 637 case CX88_BOARD_GENIATECH_DVBS:
f7b54b10
MK
638 dev->dvb.frontend = dvb_attach(cx24123_attach,
639 &geniatech_dvbs_config,
640 &dev->core->i2c_adap);
c02a34f4
SA
641 if (dev->dvb.frontend) {
642 dev->core->prev_set_voltage = dev->dvb.frontend->ops.set_voltage;
643 dev->dvb.frontend->ops.set_voltage = geniatech_dvbs_set_voltage;
644 }
645 break;
60464da8 646 case CX88_BOARD_PINNACLE_PCTV_HD_800i:
60464da8
ST
647 dev->dvb.frontend = dvb_attach(s5h1409_attach,
648 &pinnacle_pctv_hd_800i_config,
649 &dev->core->i2c_adap);
650 if (dev->dvb.frontend != NULL) {
651 /* tuner_config.video_dev must point to
652 * i2c_adap.algo_data
653 */
73c993a8 654 pinnacle_pctv_hd_800i_tuner_config.priv =
60464da8
ST
655 dev->core->i2c_adap.algo_data;
656 dvb_attach(xc5000_attach, dev->dvb.frontend,
657 &dev->core->i2c_adap,
658 &pinnacle_pctv_hd_800i_tuner_config);
659 }
660 break;
1da177e4 661 default:
5772f813 662 printk(KERN_ERR "%s/2: The frontend of your DVB/ATSC card isn't supported yet\n",
1622c3fc 663 dev->core->name);
1da177e4
LT
664 break;
665 }
666 if (NULL == dev->dvb.frontend) {
5772f813 667 printk(KERN_ERR "%s/2: frontend initialization failed\n", dev->core->name);
1da177e4
LT
668 return -1;
669 }
670
6c5be74c
ST
671 /* Ensure all frontends negotiate bus access */
672 dev->dvb.frontend->ops.ts_bus_ctrl = cx88_dvb_bus_ctrl;
1da177e4 673
93352f5c
MCC
674 /* Put the analog decoder in standby to keep it quiet */
675 cx88_call_i2c_clients (dev->core, TUNER_SET_STANDBY, NULL);
676
1da177e4 677 /* register everything */
d09dbf92 678 return videobuf_dvb_register(&dev->dvb, THIS_MODULE, dev, &dev->pci->dev);
1da177e4
LT
679}
680
681/* ----------------------------------------------------------- */
682
6c5be74c
ST
683/* CX8802 MPEG -> mini driver - We have been given the hardware */
684static int cx8802_dvb_advise_acquire(struct cx8802_driver *drv)
1da177e4 685{
6c5be74c
ST
686 struct cx88_core *core = drv->core;
687 int err = 0;
688 dprintk( 1, "%s\n", __FUNCTION__);
689
6a59d64c 690 switch (core->boardnr) {
6c5be74c
ST
691 case CX88_BOARD_HAUPPAUGE_HVR1300:
692 /* We arrive here with either the cx23416 or the cx22702
693 * on the bus. Take the bus from the cx23416 and enable the
694 * cx22702 demod
695 */
696 cx_set(MO_GP0_IO, 0x00000080); /* cx22702 out of reset and enable */
697 cx_clear(MO_GP0_IO, 0x00000004);
698 udelay(1000);
699 break;
700 default:
701 err = -ENODEV;
702 }
703 return err;
704}
705
706/* CX8802 MPEG -> mini driver - We no longer have the hardware */
707static int cx8802_dvb_advise_release(struct cx8802_driver *drv)
708{
709 struct cx88_core *core = drv->core;
710 int err = 0;
711 dprintk( 1, "%s\n", __FUNCTION__);
712
6a59d64c 713 switch (core->boardnr) {
6c5be74c
ST
714 case CX88_BOARD_HAUPPAUGE_HVR1300:
715 /* Do Nothing, leave the cx22702 on the bus. */
716 break;
717 default:
718 err = -ENODEV;
719 }
720 return err;
721}
722
723static int cx8802_dvb_probe(struct cx8802_driver *drv)
724{
725 struct cx88_core *core = drv->core;
726 struct cx8802_dev *dev = drv->core->dvbdev;
1da177e4
LT
727 int err;
728
6c5be74c
ST
729 dprintk( 1, "%s\n", __FUNCTION__);
730 dprintk( 1, " ->being probed by Card=%d Name=%s, PCI %02x:%02x\n",
6a59d64c 731 core->boardnr,
6c5be74c
ST
732 core->name,
733 core->pci_bus,
734 core->pci_slot);
1da177e4
LT
735
736 err = -ENODEV;
6a59d64c 737 if (!(core->board.mpeg & CX88_MPEG_DVB))
1da177e4
LT
738 goto fail_core;
739
ecf854df 740 /* If vp3054 isn't enabled, a stub will just return 0 */
fc40b261
CP
741 err = vp3054_i2c_probe(dev);
742 if (0 != err)
6c5be74c 743 goto fail_core;
fc40b261 744
1da177e4 745 /* dvb stuff */
5772f813 746 printk(KERN_INFO "%s/2: cx2388x based DVB/ATSC card\n", core->name);
c1accaa2 747 videobuf_queue_pci_init(&dev->dvb.dvbq, &dvb_qops,
1da177e4
LT
748 dev->pci, &dev->slock,
749 V4L2_BUF_TYPE_VIDEO_CAPTURE,
750 V4L2_FIELD_TOP,
751 sizeof(struct cx88_buffer),
752 dev);
753 err = dvb_register(dev);
6c5be74c 754 if (err != 0)
5772f813
TP
755 printk(KERN_ERR "%s/2: dvb_register failed (err = %d)\n",
756 core->name, err);
1da177e4 757
1da177e4 758 fail_core:
1da177e4
LT
759 return err;
760}
761
6c5be74c 762static int cx8802_dvb_remove(struct cx8802_driver *drv)
1da177e4 763{
6c5be74c 764 struct cx8802_dev *dev = drv->core->dvbdev;
611900c1 765
1da177e4
LT
766 /* dvb */
767 videobuf_dvb_unregister(&dev->dvb);
768
fc40b261 769 vp3054_i2c_remove(dev);
fc40b261 770
6c5be74c 771 return 0;
1da177e4
LT
772}
773
6c5be74c
ST
774static struct cx8802_driver cx8802_dvb_driver = {
775 .type_id = CX88_MPEG_DVB,
776 .hw_access = CX8802_DRVCTL_SHARED,
777 .probe = cx8802_dvb_probe,
778 .remove = cx8802_dvb_remove,
779 .advise_acquire = cx8802_dvb_advise_acquire,
780 .advise_release = cx8802_dvb_advise_release,
1da177e4
LT
781};
782
783static int dvb_init(void)
784{
5772f813 785 printk(KERN_INFO "cx88/2: cx2388x dvb driver version %d.%d.%d loaded\n",
1da177e4
LT
786 (CX88_VERSION_CODE >> 16) & 0xff,
787 (CX88_VERSION_CODE >> 8) & 0xff,
788 CX88_VERSION_CODE & 0xff);
789#ifdef SNAPSHOT
790 printk(KERN_INFO "cx2388x: snapshot date %04d-%02d-%02d\n",
791 SNAPSHOT/10000, (SNAPSHOT/100)%100, SNAPSHOT%100);
792#endif
6c5be74c 793 return cx8802_register_driver(&cx8802_dvb_driver);
1da177e4
LT
794}
795
796static void dvb_fini(void)
797{
6c5be74c 798 cx8802_unregister_driver(&cx8802_dvb_driver);
1da177e4
LT
799}
800
801module_init(dvb_init);
802module_exit(dvb_fini);
803
804/*
805 * Local variables:
806 * c-basic-offset: 8
807 * compile-command: "make DVB=1"
808 * End:
809 */