Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * |
3 | * device driver for Conexant 2388x based TV cards | |
4 | * MPEG Transport Stream (DVB) routines | |
5 | * | |
fc40b261 | 6 | * (c) 2004, 2005 Chris Pascoe <c.pascoe@itee.uq.edu.au> |
1da177e4 LT |
7 | * (c) 2004 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs] |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
22 | */ | |
23 | ||
24 | #include <linux/module.h> | |
25 | #include <linux/init.h> | |
26 | #include <linux/device.h> | |
27 | #include <linux/fs.h> | |
28 | #include <linux/kthread.h> | |
29 | #include <linux/file.h> | |
30 | #include <linux/suspend.h> | |
31 | ||
1da177e4 LT |
32 | #include "cx88.h" |
33 | #include "dvb-pll.h" | |
5e453dc7 | 34 | #include <media/v4l2-common.h> |
41ef7c1e | 35 | |
1f10c7af AQ |
36 | #include "mt352.h" |
37 | #include "mt352_priv.h" | |
ecf854df | 38 | #include "cx88-vp3054-i2c.h" |
1f10c7af AQ |
39 | #include "zl10353.h" |
40 | #include "cx22702.h" | |
41 | #include "or51132.h" | |
42 | #include "lgdt330x.h" | |
60464da8 ST |
43 | #include "s5h1409.h" |
44 | #include "xc5000.h" | |
1f10c7af AQ |
45 | #include "nxt200x.h" |
46 | #include "cx24123.h" | |
cd20ca9f | 47 | #include "isl6421.h" |
0df31f83 | 48 | #include "tuner-simple.h" |
827855d3 | 49 | #include "tda9887.h" |
d893d5dc | 50 | #include "s5h1411.h" |
e4aab64c IL |
51 | #include "stv0299.h" |
52 | #include "z0194a.h" | |
53 | #include "stv0288.h" | |
54 | #include "stb6000.h" | |
5bd1b663 | 55 | #include "cx24116.h" |
1da177e4 LT |
56 | |
57 | MODULE_DESCRIPTION("driver for cx2388x based DVB cards"); | |
58 | MODULE_AUTHOR("Chris Pascoe <c.pascoe@itee.uq.edu.au>"); | |
59 | MODULE_AUTHOR("Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]"); | |
60 | MODULE_LICENSE("GPL"); | |
61 | ||
ff699e6b | 62 | static unsigned int debug; |
1da177e4 LT |
63 | module_param(debug, int, 0644); |
64 | MODULE_PARM_DESC(debug,"enable debug messages [dvb]"); | |
65 | ||
78e92006 JG |
66 | DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); |
67 | ||
1da177e4 | 68 | #define dprintk(level,fmt, arg...) if (debug >= level) \ |
6c5be74c | 69 | printk(KERN_DEBUG "%s/2-dvb: " fmt, core->name, ## arg) |
1da177e4 LT |
70 | |
71 | /* ------------------------------------------------------------------ */ | |
72 | ||
73 | static int dvb_buf_setup(struct videobuf_queue *q, | |
74 | unsigned int *count, unsigned int *size) | |
75 | { | |
76 | struct cx8802_dev *dev = q->priv_data; | |
77 | ||
78 | dev->ts_packet_size = 188 * 4; | |
79 | dev->ts_packet_count = 32; | |
80 | ||
81 | *size = dev->ts_packet_size * dev->ts_packet_count; | |
82 | *count = 32; | |
83 | return 0; | |
84 | } | |
85 | ||
4a390558 MK |
86 | static int dvb_buf_prepare(struct videobuf_queue *q, |
87 | struct videobuf_buffer *vb, enum v4l2_field field) | |
1da177e4 LT |
88 | { |
89 | struct cx8802_dev *dev = q->priv_data; | |
c7b0ac05 | 90 | return cx8802_buf_prepare(q, dev, (struct cx88_buffer*)vb,field); |
1da177e4 LT |
91 | } |
92 | ||
93 | static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb) | |
94 | { | |
95 | struct cx8802_dev *dev = q->priv_data; | |
96 | cx8802_buf_queue(dev, (struct cx88_buffer*)vb); | |
97 | } | |
98 | ||
4a390558 MK |
99 | static void dvb_buf_release(struct videobuf_queue *q, |
100 | struct videobuf_buffer *vb) | |
1da177e4 | 101 | { |
c7b0ac05 | 102 | cx88_free_buffer(q, (struct cx88_buffer*)vb); |
1da177e4 LT |
103 | } |
104 | ||
408b664a | 105 | static struct videobuf_queue_ops dvb_qops = { |
1da177e4 LT |
106 | .buf_setup = dvb_buf_setup, |
107 | .buf_prepare = dvb_buf_prepare, | |
108 | .buf_queue = dvb_buf_queue, | |
109 | .buf_release = dvb_buf_release, | |
110 | }; | |
111 | ||
112 | /* ------------------------------------------------------------------ */ | |
22f3f17d MK |
113 | |
114 | static int cx88_dvb_bus_ctrl(struct dvb_frontend* fe, int acquire) | |
115 | { | |
116 | struct cx8802_dev *dev= fe->dvb->priv; | |
117 | struct cx8802_driver *drv = NULL; | |
118 | int ret = 0; | |
119 | ||
120 | drv = cx8802_get_driver(dev, CX88_MPEG_DVB); | |
121 | if (drv) { | |
4a390558 | 122 | if (acquire) |
22f3f17d MK |
123 | ret = drv->request_acquire(drv); |
124 | else | |
125 | ret = drv->request_release(drv); | |
126 | } | |
127 | ||
128 | return ret; | |
129 | } | |
130 | ||
131 | /* ------------------------------------------------------------------ */ | |
132 | ||
3d7d027a | 133 | static int dvico_fusionhdtv_demod_init(struct dvb_frontend* fe) |
1da177e4 LT |
134 | { |
135 | static u8 clock_config [] = { CLOCK_CTL, 0x38, 0x39 }; | |
136 | static u8 reset [] = { RESET, 0x80 }; | |
137 | static u8 adc_ctl_1_cfg [] = { ADC_CTL_1, 0x40 }; | |
138 | static u8 agc_cfg [] = { AGC_TARGET, 0x24, 0x20 }; | |
139 | static u8 gpp_ctl_cfg [] = { GPP_CTL, 0x33 }; | |
140 | static u8 capt_range_cfg[] = { CAPT_RANGE, 0x32 }; | |
141 | ||
142 | mt352_write(fe, clock_config, sizeof(clock_config)); | |
143 | udelay(200); | |
144 | mt352_write(fe, reset, sizeof(reset)); | |
145 | mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg)); | |
146 | ||
147 | mt352_write(fe, agc_cfg, sizeof(agc_cfg)); | |
148 | mt352_write(fe, gpp_ctl_cfg, sizeof(gpp_ctl_cfg)); | |
149 | mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg)); | |
150 | return 0; | |
151 | } | |
152 | ||
43eabb4e CP |
153 | static int dvico_dual_demod_init(struct dvb_frontend *fe) |
154 | { | |
155 | static u8 clock_config [] = { CLOCK_CTL, 0x38, 0x38 }; | |
156 | static u8 reset [] = { RESET, 0x80 }; | |
157 | static u8 adc_ctl_1_cfg [] = { ADC_CTL_1, 0x40 }; | |
158 | static u8 agc_cfg [] = { AGC_TARGET, 0x28, 0x20 }; | |
159 | static u8 gpp_ctl_cfg [] = { GPP_CTL, 0x33 }; | |
160 | static u8 capt_range_cfg[] = { CAPT_RANGE, 0x32 }; | |
161 | ||
162 | mt352_write(fe, clock_config, sizeof(clock_config)); | |
163 | udelay(200); | |
164 | mt352_write(fe, reset, sizeof(reset)); | |
165 | mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg)); | |
166 | ||
167 | mt352_write(fe, agc_cfg, sizeof(agc_cfg)); | |
168 | mt352_write(fe, gpp_ctl_cfg, sizeof(gpp_ctl_cfg)); | |
169 | mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg)); | |
170 | ||
171 | return 0; | |
172 | } | |
173 | ||
1da177e4 LT |
174 | static int dntv_live_dvbt_demod_init(struct dvb_frontend* fe) |
175 | { | |
176 | static u8 clock_config [] = { 0x89, 0x38, 0x39 }; | |
177 | static u8 reset [] = { 0x50, 0x80 }; | |
178 | static u8 adc_ctl_1_cfg [] = { 0x8E, 0x40 }; | |
179 | static u8 agc_cfg [] = { 0x67, 0x10, 0x23, 0x00, 0xFF, 0xFF, | |
f2421ca3 | 180 | 0x00, 0xFF, 0x00, 0x40, 0x40 }; |
1da177e4 LT |
181 | static u8 dntv_extra[] = { 0xB5, 0x7A }; |
182 | static u8 capt_range_cfg[] = { 0x75, 0x32 }; | |
183 | ||
184 | mt352_write(fe, clock_config, sizeof(clock_config)); | |
185 | udelay(2000); | |
186 | mt352_write(fe, reset, sizeof(reset)); | |
187 | mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg)); | |
188 | ||
189 | mt352_write(fe, agc_cfg, sizeof(agc_cfg)); | |
190 | udelay(2000); | |
191 | mt352_write(fe, dntv_extra, sizeof(dntv_extra)); | |
192 | mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg)); | |
193 | ||
194 | return 0; | |
195 | } | |
196 | ||
1da177e4 | 197 | static struct mt352_config dvico_fusionhdtv = { |
f7b54b10 | 198 | .demod_address = 0x0f, |
3d7d027a | 199 | .demod_init = dvico_fusionhdtv_demod_init, |
1da177e4 LT |
200 | }; |
201 | ||
202 | static struct mt352_config dntv_live_dvbt_config = { | |
203 | .demod_address = 0x0f, | |
204 | .demod_init = dntv_live_dvbt_demod_init, | |
1da177e4 | 205 | }; |
fc40b261 | 206 | |
43eabb4e | 207 | static struct mt352_config dvico_fusionhdtv_dual = { |
f7b54b10 | 208 | .demod_address = 0x0f, |
43eabb4e | 209 | .demod_init = dvico_dual_demod_init, |
43eabb4e CP |
210 | }; |
211 | ||
ecf854df | 212 | #if defined(CONFIG_VIDEO_CX88_VP3054) || (defined(CONFIG_VIDEO_CX88_VP3054_MODULE) && defined(MODULE)) |
3d7d027a CP |
213 | static int dntv_live_dvbt_pro_demod_init(struct dvb_frontend* fe) |
214 | { | |
215 | static u8 clock_config [] = { 0x89, 0x38, 0x38 }; | |
216 | static u8 reset [] = { 0x50, 0x80 }; | |
217 | static u8 adc_ctl_1_cfg [] = { 0x8E, 0x40 }; | |
218 | static u8 agc_cfg [] = { 0x67, 0x10, 0x20, 0x00, 0xFF, 0xFF, | |
219 | 0x00, 0xFF, 0x00, 0x40, 0x40 }; | |
220 | static u8 dntv_extra[] = { 0xB5, 0x7A }; | |
221 | static u8 capt_range_cfg[] = { 0x75, 0x32 }; | |
222 | ||
223 | mt352_write(fe, clock_config, sizeof(clock_config)); | |
224 | udelay(2000); | |
225 | mt352_write(fe, reset, sizeof(reset)); | |
226 | mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg)); | |
227 | ||
228 | mt352_write(fe, agc_cfg, sizeof(agc_cfg)); | |
229 | udelay(2000); | |
230 | mt352_write(fe, dntv_extra, sizeof(dntv_extra)); | |
231 | mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg)); | |
232 | ||
233 | return 0; | |
234 | } | |
235 | ||
fc40b261 CP |
236 | static struct mt352_config dntv_live_dvbt_pro_config = { |
237 | .demod_address = 0x0f, | |
238 | .no_tuner = 1, | |
3d7d027a | 239 | .demod_init = dntv_live_dvbt_pro_demod_init, |
fc40b261 CP |
240 | }; |
241 | #endif | |
1da177e4 | 242 | |
780dfef3 | 243 | static struct zl10353_config dvico_fusionhdtv_hybrid = { |
f7b54b10 | 244 | .demod_address = 0x0f, |
f54376e2 | 245 | .no_tuner = 1, |
780dfef3 CP |
246 | }; |
247 | ||
b3fb91d2 CP |
248 | static struct zl10353_config dvico_fusionhdtv_xc3028 = { |
249 | .demod_address = 0x0f, | |
250 | .if2 = 45600, | |
251 | .no_tuner = 1, | |
252 | }; | |
253 | ||
254 | static struct mt352_config dvico_fusionhdtv_mt352_xc3028 = { | |
255 | .demod_address = 0x0f, | |
256 | .if2 = 4560, | |
257 | .no_tuner = 1, | |
258 | .demod_init = dvico_fusionhdtv_demod_init, | |
259 | }; | |
260 | ||
780dfef3 | 261 | static struct zl10353_config dvico_fusionhdtv_plus_v1_1 = { |
f7b54b10 | 262 | .demod_address = 0x0f, |
780dfef3 | 263 | }; |
780dfef3 | 264 | |
1da177e4 LT |
265 | static struct cx22702_config connexant_refboard_config = { |
266 | .demod_address = 0x43, | |
38d84c3b | 267 | .output_mode = CX22702_SERIAL_OUTPUT, |
1da177e4 LT |
268 | }; |
269 | ||
ed355260 | 270 | static struct cx22702_config hauppauge_hvr_config = { |
aa481a65 ST |
271 | .demod_address = 0x63, |
272 | .output_mode = CX22702_SERIAL_OUTPUT, | |
273 | }; | |
1da177e4 | 274 | |
4a390558 | 275 | static int or51132_set_ts_param(struct dvb_frontend* fe, int is_punctured) |
1da177e4 LT |
276 | { |
277 | struct cx8802_dev *dev= fe->dvb->priv; | |
278 | dev->ts_gen_cntrl = is_punctured ? 0x04 : 0x00; | |
279 | return 0; | |
280 | } | |
281 | ||
408b664a | 282 | static struct or51132_config pchdtv_hd3000 = { |
f7b54b10 MK |
283 | .demod_address = 0x15, |
284 | .set_ts_params = or51132_set_ts_param, | |
1da177e4 | 285 | }; |
1da177e4 | 286 | |
6ddcc919 | 287 | static int lgdt330x_pll_rf_set(struct dvb_frontend* fe, int index) |
0ccef6db MK |
288 | { |
289 | struct cx8802_dev *dev= fe->dvb->priv; | |
290 | struct cx88_core *core = dev->core; | |
291 | ||
32d83efc | 292 | dprintk(1, "%s: index = %d\n", __func__, index); |
0ccef6db MK |
293 | if (index == 0) |
294 | cx_clear(MO_GP0_IO, 8); | |
295 | else | |
296 | cx_set(MO_GP0_IO, 8); | |
297 | return 0; | |
298 | } | |
299 | ||
6ddcc919 | 300 | static int lgdt330x_set_ts_param(struct dvb_frontend* fe, int is_punctured) |
f1798495 MK |
301 | { |
302 | struct cx8802_dev *dev= fe->dvb->priv; | |
303 | if (is_punctured) | |
304 | dev->ts_gen_cntrl |= 0x04; | |
305 | else | |
306 | dev->ts_gen_cntrl &= ~0x04; | |
307 | return 0; | |
308 | } | |
309 | ||
6ddcc919 | 310 | static struct lgdt330x_config fusionhdtv_3_gold = { |
f7b54b10 MK |
311 | .demod_address = 0x0e, |
312 | .demod_chip = LGDT3302, | |
313 | .serial_mpeg = 0x04, /* TPSERIAL for 3302 in TOP_CONTROL */ | |
314 | .set_ts_params = lgdt330x_set_ts_param, | |
0d723c09 | 315 | }; |
e52e98a7 MCC |
316 | |
317 | static struct lgdt330x_config fusionhdtv_5_gold = { | |
f7b54b10 MK |
318 | .demod_address = 0x0e, |
319 | .demod_chip = LGDT3303, | |
320 | .serial_mpeg = 0x40, /* TPSERIAL for 3303 in TOP_CONTROL */ | |
321 | .set_ts_params = lgdt330x_set_ts_param, | |
e52e98a7 | 322 | }; |
da215d22 RS |
323 | |
324 | static struct lgdt330x_config pchdtv_hd5500 = { | |
f7b54b10 MK |
325 | .demod_address = 0x59, |
326 | .demod_chip = LGDT3303, | |
327 | .serial_mpeg = 0x40, /* TPSERIAL for 3303 in TOP_CONTROL */ | |
328 | .set_ts_params = lgdt330x_set_ts_param, | |
da215d22 | 329 | }; |
f1798495 | 330 | |
4a390558 | 331 | static int nxt200x_set_ts_param(struct dvb_frontend* fe, int is_punctured) |
fde6d31e KL |
332 | { |
333 | struct cx8802_dev *dev= fe->dvb->priv; | |
334 | dev->ts_gen_cntrl = is_punctured ? 0x04 : 0x00; | |
335 | return 0; | |
336 | } | |
337 | ||
338 | static struct nxt200x_config ati_hdtvwonder = { | |
f7b54b10 | 339 | .demod_address = 0x0a, |
f7b54b10 | 340 | .set_ts_params = nxt200x_set_ts_param, |
fde6d31e | 341 | }; |
fde6d31e | 342 | |
0fa14aa6 ST |
343 | static int cx24123_set_ts_param(struct dvb_frontend* fe, |
344 | int is_punctured) | |
345 | { | |
346 | struct cx8802_dev *dev= fe->dvb->priv; | |
f7b54b10 | 347 | dev->ts_gen_cntrl = 0x02; |
0fa14aa6 ST |
348 | return 0; |
349 | } | |
350 | ||
f7b54b10 MK |
351 | static int kworld_dvbs_100_set_voltage(struct dvb_frontend* fe, |
352 | fe_sec_voltage_t voltage) | |
0e0351e3 VC |
353 | { |
354 | struct cx8802_dev *dev= fe->dvb->priv; | |
355 | struct cx88_core *core = dev->core; | |
356 | ||
4a390558 | 357 | if (voltage == SEC_VOLTAGE_OFF) |
f7b54b10 | 358 | cx_write(MO_GP0_IO, 0x000006fb); |
4a390558 | 359 | else |
cd20ca9f | 360 | cx_write(MO_GP0_IO, 0x000006f9); |
cd20ca9f AQ |
361 | |
362 | if (core->prev_set_voltage) | |
363 | return core->prev_set_voltage(fe, voltage); | |
364 | return 0; | |
0e0351e3 VC |
365 | } |
366 | ||
f7b54b10 MK |
367 | static int geniatech_dvbs_set_voltage(struct dvb_frontend *fe, |
368 | fe_sec_voltage_t voltage) | |
c02a34f4 SA |
369 | { |
370 | struct cx8802_dev *dev= fe->dvb->priv; | |
371 | struct cx88_core *core = dev->core; | |
372 | ||
373 | if (voltage == SEC_VOLTAGE_OFF) { | |
374 | dprintk(1,"LNB Voltage OFF\n"); | |
375 | cx_write(MO_GP0_IO, 0x0000efff); | |
376 | } | |
377 | ||
378 | if (core->prev_set_voltage) | |
379 | return core->prev_set_voltage(fe, voltage); | |
380 | return 0; | |
381 | } | |
382 | ||
af832623 IL |
383 | static int tevii_dvbs_set_voltage(struct dvb_frontend *fe, |
384 | fe_sec_voltage_t voltage) | |
385 | { | |
386 | struct cx8802_dev *dev= fe->dvb->priv; | |
387 | struct cx88_core *core = dev->core; | |
388 | ||
389 | switch (voltage) { | |
390 | case SEC_VOLTAGE_13: | |
391 | printk("LNB Voltage SEC_VOLTAGE_13\n"); | |
392 | cx_write(MO_GP0_IO, 0x00006040); | |
393 | break; | |
394 | case SEC_VOLTAGE_18: | |
395 | printk("LNB Voltage SEC_VOLTAGE_18\n"); | |
396 | cx_write(MO_GP0_IO, 0x00006060); | |
397 | break; | |
398 | case SEC_VOLTAGE_OFF: | |
399 | printk("LNB Voltage SEC_VOLTAGE_off\n"); | |
400 | break; | |
401 | } | |
402 | ||
403 | if (core->prev_set_voltage) | |
404 | return core->prev_set_voltage(fe, voltage); | |
405 | return 0; | |
406 | } | |
407 | ||
c02a34f4 | 408 | static struct cx24123_config geniatech_dvbs_config = { |
f7b54b10 MK |
409 | .demod_address = 0x55, |
410 | .set_ts_params = cx24123_set_ts_param, | |
c02a34f4 SA |
411 | }; |
412 | ||
0fa14aa6 | 413 | static struct cx24123_config hauppauge_novas_config = { |
f7b54b10 MK |
414 | .demod_address = 0x55, |
415 | .set_ts_params = cx24123_set_ts_param, | |
0e0351e3 VC |
416 | }; |
417 | ||
418 | static struct cx24123_config kworld_dvbs_100_config = { | |
f7b54b10 MK |
419 | .demod_address = 0x15, |
420 | .set_ts_params = cx24123_set_ts_param, | |
ef76856d | 421 | .lnb_polarity = 1, |
0fa14aa6 | 422 | }; |
0fa14aa6 | 423 | |
60464da8 ST |
424 | static struct s5h1409_config pinnacle_pctv_hd_800i_config = { |
425 | .demod_address = 0x32 >> 1, | |
426 | .output_mode = S5H1409_PARALLEL_OUTPUT, | |
427 | .gpio = S5H1409_GPIO_ON, | |
428 | .qam_if = 44000, | |
429 | .inversion = S5H1409_INVERSION_OFF, | |
430 | .status_mode = S5H1409_DEMODLOCKING, | |
4917019d | 431 | .mpeg_timing = S5H1409_MPEGTIMING_NONCONTINOUS_NONINVERTING_CLOCK, |
60464da8 ST |
432 | }; |
433 | ||
5c00fac0 ST |
434 | static struct s5h1409_config dvico_hdtv5_pci_nano_config = { |
435 | .demod_address = 0x32 >> 1, | |
436 | .output_mode = S5H1409_SERIAL_OUTPUT, | |
437 | .gpio = S5H1409_GPIO_OFF, | |
438 | .inversion = S5H1409_INVERSION_OFF, | |
439 | .status_mode = S5H1409_DEMODLOCKING, | |
440 | .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, | |
441 | }; | |
442 | ||
99e09eac MCC |
443 | static struct s5h1409_config kworld_atsc_120_config = { |
444 | .demod_address = 0x32 >> 1, | |
99e09eac MCC |
445 | .output_mode = S5H1409_SERIAL_OUTPUT, |
446 | .gpio = S5H1409_GPIO_OFF, | |
447 | .inversion = S5H1409_INVERSION_OFF, | |
448 | .status_mode = S5H1409_DEMODLOCKING, | |
449 | .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, | |
450 | }; | |
451 | ||
60464da8 ST |
452 | static struct xc5000_config pinnacle_pctv_hd_800i_tuner_config = { |
453 | .i2c_address = 0x64, | |
454 | .if_khz = 5380, | |
60464da8 ST |
455 | }; |
456 | ||
3f6014fc SV |
457 | static struct zl10353_config cx88_pinnacle_hybrid_pctv = { |
458 | .demod_address = (0x1e >> 1), | |
459 | .no_tuner = 1, | |
460 | .if2 = 45600, | |
461 | }; | |
462 | ||
9507901e MCC |
463 | static struct zl10353_config cx88_geniatech_x8000_mt = { |
464 | .demod_address = (0x1e >> 1), | |
465 | .no_tuner = 1, | |
466 | }; | |
467 | ||
d893d5dc ST |
468 | static struct s5h1411_config dvico_fusionhdtv7_config = { |
469 | .output_mode = S5H1411_SERIAL_OUTPUT, | |
470 | .gpio = S5H1411_GPIO_ON, | |
471 | .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, | |
472 | .qam_if = S5H1411_IF_44000, | |
473 | .vsb_if = S5H1411_IF_44000, | |
474 | .inversion = S5H1411_INVERSION_OFF, | |
475 | .status_mode = S5H1411_DEMODLOCKING | |
476 | }; | |
477 | ||
478 | static struct xc5000_config dvico_fusionhdtv7_tuner_config = { | |
479 | .i2c_address = 0xc2 >> 1, | |
480 | .if_khz = 5380, | |
d893d5dc ST |
481 | }; |
482 | ||
23fb348d MCC |
483 | static int attach_xc3028(u8 addr, struct cx8802_dev *dev) |
484 | { | |
485 | struct dvb_frontend *fe; | |
99e09eac | 486 | struct xc2028_ctrl ctl; |
23fb348d MCC |
487 | struct xc2028_config cfg = { |
488 | .i2c_adap = &dev->core->i2c_adap, | |
489 | .i2c_addr = addr, | |
99e09eac | 490 | .ctrl = &ctl, |
23fb348d MCC |
491 | }; |
492 | ||
ddd5441d MCC |
493 | if (!dev->dvb.frontend) { |
494 | printk(KERN_ERR "%s/2: dvb frontend not attached. " | |
495 | "Can't attach xc3028\n", | |
496 | dev->core->name); | |
497 | return -EINVAL; | |
498 | } | |
499 | ||
99e09eac MCC |
500 | /* |
501 | * Some xc3028 devices may be hidden by an I2C gate. This is known | |
502 | * to happen with some s5h1409-based devices. | |
503 | * Now that I2C gate is open, sets up xc3028 configuration | |
504 | */ | |
505 | cx88_setup_xc3028(dev->core, &ctl); | |
506 | ||
23fb348d MCC |
507 | fe = dvb_attach(xc2028_attach, dev->dvb.frontend, &cfg); |
508 | if (!fe) { | |
509 | printk(KERN_ERR "%s/2: xc3028 attach failed\n", | |
510 | dev->core->name); | |
23fb348d MCC |
511 | return -EINVAL; |
512 | } | |
513 | ||
514 | printk(KERN_INFO "%s/2: xc3028 attached\n", | |
515 | dev->core->name); | |
516 | ||
517 | return 0; | |
518 | } | |
9507901e | 519 | |
5bd1b663 ST |
520 | static int cx24116_set_ts_param(struct dvb_frontend *fe, |
521 | int is_punctured) | |
522 | { | |
523 | struct cx8802_dev *dev = fe->dvb->priv; | |
524 | dev->ts_gen_cntrl = 0x2; | |
525 | ||
526 | return 0; | |
527 | } | |
528 | ||
529 | static int cx24116_reset_device(struct dvb_frontend *fe) | |
530 | { | |
531 | struct cx8802_dev *dev = fe->dvb->priv; | |
532 | struct cx88_core *core = dev->core; | |
533 | ||
534 | /* Reset the part */ | |
535 | cx_write(MO_SRST_IO, 0); | |
536 | msleep(10); | |
537 | cx_write(MO_SRST_IO, 1); | |
538 | msleep(10); | |
539 | ||
540 | return 0; | |
541 | } | |
542 | ||
543 | static struct cx24116_config hauppauge_hvr4000_config = { | |
544 | .demod_address = 0x05, | |
545 | .set_ts_params = cx24116_set_ts_param, | |
546 | .reset_device = cx24116_reset_device, | |
547 | }; | |
548 | ||
af832623 IL |
549 | static struct cx24116_config tevii_s460_config = { |
550 | .demod_address = 0x55, | |
551 | .set_ts_params = cx24116_set_ts_param, | |
552 | .reset_device = cx24116_reset_device, | |
553 | }; | |
554 | ||
e4aab64c IL |
555 | static struct stv0299_config tevii_tuner_sharp_config = { |
556 | .demod_address = 0x68, | |
557 | .inittab = sharp_z0194a__inittab, | |
558 | .mclk = 88000000UL, | |
559 | .invert = 1, | |
560 | .skip_reinit = 0, | |
561 | .lock_output = 1, | |
562 | .volt13_op0_op1 = STV0299_VOLT13_OP1, | |
563 | .min_delay_ms = 100, | |
564 | .set_symbol_rate = sharp_z0194a__set_symbol_rate, | |
565 | .set_ts_params = cx24116_set_ts_param, | |
566 | }; | |
567 | ||
568 | static struct stv0288_config tevii_tuner_earda_config = { | |
569 | .demod_address = 0x68, | |
570 | .min_delay_ms = 100, | |
571 | .set_ts_params = cx24116_set_ts_param, | |
572 | }; | |
573 | ||
1da177e4 LT |
574 | static int dvb_register(struct cx8802_dev *dev) |
575 | { | |
0590d91c MCC |
576 | struct cx88_core *core = dev->core; |
577 | ||
1da177e4 | 578 | /* init struct videobuf_dvb */ |
0590d91c | 579 | dev->dvb.name = core->name; |
1da177e4 LT |
580 | dev->ts_gen_cntrl = 0x0c; |
581 | ||
582 | /* init frontend */ | |
0590d91c | 583 | switch (core->boardnr) { |
1da177e4 | 584 | case CX88_BOARD_HAUPPAUGE_DVB_T1: |
f7b54b10 | 585 | dev->dvb.frontend = dvb_attach(cx22702_attach, |
ed355260 | 586 | &connexant_refboard_config, |
0590d91c | 587 | &core->i2c_adap); |
f54376e2 | 588 | if (dev->dvb.frontend != NULL) { |
0590d91c MCC |
589 | if (!dvb_attach(dvb_pll_attach, dev->dvb.frontend, |
590 | 0x61, &core->i2c_adap, | |
591 | DVB_PLL_THOMSON_DTT759X)) | |
592 | goto frontend_detach; | |
f54376e2 | 593 | } |
1da177e4 | 594 | break; |
e057ee11 | 595 | case CX88_BOARD_TERRATEC_CINERGY_1400_DVB_T1: |
1da177e4 | 596 | case CX88_BOARD_CONEXANT_DVB_T1: |
f39624fd | 597 | case CX88_BOARD_KWORLD_DVB_T_CX22702: |
2b5200a7 | 598 | case CX88_BOARD_WINFAST_DTV1000: |
f7b54b10 MK |
599 | dev->dvb.frontend = dvb_attach(cx22702_attach, |
600 | &connexant_refboard_config, | |
0590d91c | 601 | &core->i2c_adap); |
f54376e2 | 602 | if (dev->dvb.frontend != NULL) { |
0590d91c MCC |
603 | if (!dvb_attach(dvb_pll_attach, dev->dvb.frontend, |
604 | 0x60, &core->i2c_adap, | |
605 | DVB_PLL_THOMSON_DTT7579)) | |
606 | goto frontend_detach; | |
f54376e2 | 607 | } |
1da177e4 | 608 | break; |
4bd6e9d9 | 609 | case CX88_BOARD_WINFAST_DTV2000H: |
611900c1 ST |
610 | case CX88_BOARD_HAUPPAUGE_HVR1100: |
611 | case CX88_BOARD_HAUPPAUGE_HVR1100LP: | |
a5a2ecfc TP |
612 | case CX88_BOARD_HAUPPAUGE_HVR1300: |
613 | case CX88_BOARD_HAUPPAUGE_HVR3000: | |
f7b54b10 | 614 | dev->dvb.frontend = dvb_attach(cx22702_attach, |
ed355260 | 615 | &hauppauge_hvr_config, |
0590d91c | 616 | &core->i2c_adap); |
f54376e2 | 617 | if (dev->dvb.frontend != NULL) { |
0590d91c MCC |
618 | if (!dvb_attach(simple_tuner_attach, dev->dvb.frontend, |
619 | &core->i2c_adap, 0x61, | |
620 | TUNER_PHILIPS_FMD1216ME_MK3)) | |
621 | goto frontend_detach; | |
f54376e2 | 622 | } |
611900c1 | 623 | break; |
780dfef3 | 624 | case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_PLUS: |
f7b54b10 MK |
625 | dev->dvb.frontend = dvb_attach(mt352_attach, |
626 | &dvico_fusionhdtv, | |
0590d91c | 627 | &core->i2c_adap); |
f54376e2 | 628 | if (dev->dvb.frontend != NULL) { |
0590d91c MCC |
629 | if (!dvb_attach(dvb_pll_attach, dev->dvb.frontend, |
630 | 0x60, NULL, DVB_PLL_THOMSON_DTT7579)) | |
631 | goto frontend_detach; | |
780dfef3 | 632 | break; |
f54376e2 | 633 | } |
780dfef3 | 634 | /* ZL10353 replaces MT352 on later cards */ |
f7b54b10 MK |
635 | dev->dvb.frontend = dvb_attach(zl10353_attach, |
636 | &dvico_fusionhdtv_plus_v1_1, | |
0590d91c | 637 | &core->i2c_adap); |
f54376e2 | 638 | if (dev->dvb.frontend != NULL) { |
0590d91c MCC |
639 | if (!dvb_attach(dvb_pll_attach, dev->dvb.frontend, |
640 | 0x60, NULL, DVB_PLL_THOMSON_DTT7579)) | |
641 | goto frontend_detach; | |
f54376e2 | 642 | } |
c2af3cd6 MK |
643 | break; |
644 | case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL: | |
c2af3cd6 MK |
645 | /* The tin box says DEE1601, but it seems to be DTT7579 |
646 | * compatible, with a slightly different MT352 AGC gain. */ | |
f7b54b10 MK |
647 | dev->dvb.frontend = dvb_attach(mt352_attach, |
648 | &dvico_fusionhdtv_dual, | |
0590d91c | 649 | &core->i2c_adap); |
c2af3cd6 | 650 | if (dev->dvb.frontend != NULL) { |
0590d91c MCC |
651 | if (!dvb_attach(dvb_pll_attach, dev->dvb.frontend, |
652 | 0x61, NULL, DVB_PLL_THOMSON_DTT7579)) | |
653 | goto frontend_detach; | |
c2af3cd6 MK |
654 | break; |
655 | } | |
c2af3cd6 | 656 | /* ZL10353 replaces MT352 on later cards */ |
f7b54b10 MK |
657 | dev->dvb.frontend = dvb_attach(zl10353_attach, |
658 | &dvico_fusionhdtv_plus_v1_1, | |
0590d91c | 659 | &core->i2c_adap); |
c2af3cd6 | 660 | if (dev->dvb.frontend != NULL) { |
0590d91c MCC |
661 | if (!dvb_attach(dvb_pll_attach, dev->dvb.frontend, |
662 | 0x61, NULL, DVB_PLL_THOMSON_DTT7579)) | |
663 | goto frontend_detach; | |
c2af3cd6 | 664 | } |
1da177e4 | 665 | break; |
780dfef3 | 666 | case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T1: |
f7b54b10 MK |
667 | dev->dvb.frontend = dvb_attach(mt352_attach, |
668 | &dvico_fusionhdtv, | |
0590d91c | 669 | &core->i2c_adap); |
f54376e2 | 670 | if (dev->dvb.frontend != NULL) { |
0590d91c MCC |
671 | if (!dvb_attach(dvb_pll_attach, dev->dvb.frontend, |
672 | 0x61, NULL, DVB_PLL_LG_Z201)) | |
673 | goto frontend_detach; | |
f54376e2 | 674 | } |
1da177e4 LT |
675 | break; |
676 | case CX88_BOARD_KWORLD_DVB_T: | |
677 | case CX88_BOARD_DNTV_LIVE_DVB_T: | |
a82decf6 | 678 | case CX88_BOARD_ADSTECH_DVB_T_PCI: |
f7b54b10 MK |
679 | dev->dvb.frontend = dvb_attach(mt352_attach, |
680 | &dntv_live_dvbt_config, | |
0590d91c | 681 | &core->i2c_adap); |
f54376e2 | 682 | if (dev->dvb.frontend != NULL) { |
0590d91c MCC |
683 | if (!dvb_attach(dvb_pll_attach, dev->dvb.frontend, |
684 | 0x61, NULL, DVB_PLL_UNKNOWN_1)) | |
685 | goto frontend_detach; | |
f54376e2 | 686 | } |
1da177e4 | 687 | break; |
fc40b261 | 688 | case CX88_BOARD_DNTV_LIVE_DVB_T_PRO: |
ecf854df | 689 | #if defined(CONFIG_VIDEO_CX88_VP3054) || (defined(CONFIG_VIDEO_CX88_VP3054_MODULE) && defined(MODULE)) |
f0ad9097 | 690 | /* MT352 is on a secondary I2C bus made from some GPIO lines */ |
2bfe031d | 691 | dev->dvb.frontend = dvb_attach(mt352_attach, &dntv_live_dvbt_pro_config, |
f0ad9097 | 692 | &dev->vp3054->adap); |
f54376e2 | 693 | if (dev->dvb.frontend != NULL) { |
0590d91c MCC |
694 | if (!dvb_attach(simple_tuner_attach, dev->dvb.frontend, |
695 | &core->i2c_adap, 0x61, | |
696 | TUNER_PHILIPS_FMD1216ME_MK3)) | |
697 | goto frontend_detach; | |
f54376e2 | 698 | } |
fc40b261 | 699 | #else |
0590d91c MCC |
700 | printk(KERN_ERR "%s/2: built without vp3054 support\n", |
701 | core->name); | |
fc40b261 CP |
702 | #endif |
703 | break; | |
780dfef3 | 704 | case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_HYBRID: |
f7b54b10 MK |
705 | dev->dvb.frontend = dvb_attach(zl10353_attach, |
706 | &dvico_fusionhdtv_hybrid, | |
0590d91c | 707 | &core->i2c_adap); |
f54376e2 | 708 | if (dev->dvb.frontend != NULL) { |
0590d91c MCC |
709 | if (!dvb_attach(simple_tuner_attach, dev->dvb.frontend, |
710 | &core->i2c_adap, 0x61, | |
711 | TUNER_THOMSON_FE6600)) | |
712 | goto frontend_detach; | |
f54376e2 | 713 | } |
780dfef3 | 714 | break; |
b3fb91d2 CP |
715 | case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_PRO: |
716 | dev->dvb.frontend = dvb_attach(zl10353_attach, | |
717 | &dvico_fusionhdtv_xc3028, | |
0590d91c | 718 | &core->i2c_adap); |
b3fb91d2 CP |
719 | if (dev->dvb.frontend == NULL) |
720 | dev->dvb.frontend = dvb_attach(mt352_attach, | |
721 | &dvico_fusionhdtv_mt352_xc3028, | |
0590d91c | 722 | &core->i2c_adap); |
8765561f CP |
723 | /* |
724 | * On this board, the demod provides the I2C bus pullup. | |
725 | * We must not permit gate_ctrl to be performed, or | |
726 | * the xc3028 cannot communicate on the bus. | |
727 | */ | |
728 | if (dev->dvb.frontend) | |
729 | dev->dvb.frontend->ops.i2c_gate_ctrl = NULL; | |
23fb348d MCC |
730 | if (attach_xc3028(0x61, dev) < 0) |
731 | return -EINVAL; | |
b3fb91d2 | 732 | break; |
1da177e4 | 733 | case CX88_BOARD_PCHDTV_HD3000: |
4a390558 | 734 | dev->dvb.frontend = dvb_attach(or51132_attach, &pchdtv_hd3000, |
0590d91c | 735 | &core->i2c_adap); |
f54376e2 | 736 | if (dev->dvb.frontend != NULL) { |
0590d91c MCC |
737 | if (!dvb_attach(simple_tuner_attach, dev->dvb.frontend, |
738 | &core->i2c_adap, 0x61, | |
739 | TUNER_THOMSON_DTT761X)) | |
740 | goto frontend_detach; | |
f54376e2 | 741 | } |
1da177e4 | 742 | break; |
f1798495 MK |
743 | case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_Q: |
744 | dev->ts_gen_cntrl = 0x08; | |
f1798495 | 745 | |
0590d91c | 746 | /* Do a hardware reset of chip before using it. */ |
f1798495 MK |
747 | cx_clear(MO_GP0_IO, 1); |
748 | mdelay(100); | |
0ccef6db | 749 | cx_set(MO_GP0_IO, 1); |
f1798495 | 750 | mdelay(200); |
0ccef6db MK |
751 | |
752 | /* Select RF connector callback */ | |
6ddcc919 | 753 | fusionhdtv_3_gold.pll_rf_set = lgdt330x_pll_rf_set; |
f7b54b10 MK |
754 | dev->dvb.frontend = dvb_attach(lgdt330x_attach, |
755 | &fusionhdtv_3_gold, | |
0590d91c | 756 | &core->i2c_adap); |
f54376e2 | 757 | if (dev->dvb.frontend != NULL) { |
0590d91c MCC |
758 | if (!dvb_attach(simple_tuner_attach, dev->dvb.frontend, |
759 | &core->i2c_adap, 0x61, | |
760 | TUNER_MICROTUNE_4042FI5)) | |
761 | goto frontend_detach; | |
f1798495 MK |
762 | } |
763 | break; | |
0d723c09 MK |
764 | case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_T: |
765 | dev->ts_gen_cntrl = 0x08; | |
0d723c09 | 766 | |
0590d91c | 767 | /* Do a hardware reset of chip before using it. */ |
0d723c09 MK |
768 | cx_clear(MO_GP0_IO, 1); |
769 | mdelay(100); | |
d975872c | 770 | cx_set(MO_GP0_IO, 9); |
0d723c09 | 771 | mdelay(200); |
f7b54b10 MK |
772 | dev->dvb.frontend = dvb_attach(lgdt330x_attach, |
773 | &fusionhdtv_3_gold, | |
0590d91c | 774 | &core->i2c_adap); |
f54376e2 | 775 | if (dev->dvb.frontend != NULL) { |
0590d91c MCC |
776 | if (!dvb_attach(simple_tuner_attach, dev->dvb.frontend, |
777 | &core->i2c_adap, 0x61, | |
778 | TUNER_THOMSON_DTT761X)) | |
779 | goto frontend_detach; | |
0d723c09 MK |
780 | } |
781 | break; | |
e52e98a7 MCC |
782 | case CX88_BOARD_DVICO_FUSIONHDTV_5_GOLD: |
783 | dev->ts_gen_cntrl = 0x08; | |
e52e98a7 | 784 | |
0590d91c | 785 | /* Do a hardware reset of chip before using it. */ |
e52e98a7 MCC |
786 | cx_clear(MO_GP0_IO, 1); |
787 | mdelay(100); | |
788 | cx_set(MO_GP0_IO, 1); | |
789 | mdelay(200); | |
f7b54b10 MK |
790 | dev->dvb.frontend = dvb_attach(lgdt330x_attach, |
791 | &fusionhdtv_5_gold, | |
0590d91c | 792 | &core->i2c_adap); |
f54376e2 | 793 | if (dev->dvb.frontend != NULL) { |
0590d91c MCC |
794 | if (!dvb_attach(simple_tuner_attach, dev->dvb.frontend, |
795 | &core->i2c_adap, 0x61, | |
796 | TUNER_LG_TDVS_H06XF)) | |
797 | goto frontend_detach; | |
798 | if (!dvb_attach(tda9887_attach, dev->dvb.frontend, | |
799 | &core->i2c_adap, 0x43)) | |
800 | goto frontend_detach; | |
e52e98a7 MCC |
801 | } |
802 | break; | |
da215d22 RS |
803 | case CX88_BOARD_PCHDTV_HD5500: |
804 | dev->ts_gen_cntrl = 0x08; | |
da215d22 | 805 | |
0590d91c | 806 | /* Do a hardware reset of chip before using it. */ |
da215d22 RS |
807 | cx_clear(MO_GP0_IO, 1); |
808 | mdelay(100); | |
809 | cx_set(MO_GP0_IO, 1); | |
810 | mdelay(200); | |
f7b54b10 MK |
811 | dev->dvb.frontend = dvb_attach(lgdt330x_attach, |
812 | &pchdtv_hd5500, | |
0590d91c | 813 | &core->i2c_adap); |
f54376e2 | 814 | if (dev->dvb.frontend != NULL) { |
0590d91c MCC |
815 | if (!dvb_attach(simple_tuner_attach, dev->dvb.frontend, |
816 | &core->i2c_adap, 0x61, | |
817 | TUNER_LG_TDVS_H06XF)) | |
818 | goto frontend_detach; | |
819 | if (!dvb_attach(tda9887_attach, dev->dvb.frontend, | |
820 | &core->i2c_adap, 0x43)) | |
821 | goto frontend_detach; | |
da215d22 RS |
822 | } |
823 | break; | |
fde6d31e | 824 | case CX88_BOARD_ATI_HDTVWONDER: |
f7b54b10 MK |
825 | dev->dvb.frontend = dvb_attach(nxt200x_attach, |
826 | &ati_hdtvwonder, | |
0590d91c | 827 | &core->i2c_adap); |
f54376e2 | 828 | if (dev->dvb.frontend != NULL) { |
0590d91c MCC |
829 | if (!dvb_attach(simple_tuner_attach, dev->dvb.frontend, |
830 | &core->i2c_adap, 0x61, | |
831 | TUNER_PHILIPS_TUV1236D)) | |
832 | goto frontend_detach; | |
f54376e2 | 833 | } |
0fa14aa6 | 834 | break; |
0fa14aa6 ST |
835 | case CX88_BOARD_HAUPPAUGE_NOVASPLUS_S1: |
836 | case CX88_BOARD_HAUPPAUGE_NOVASE2_S1: | |
f7b54b10 MK |
837 | dev->dvb.frontend = dvb_attach(cx24123_attach, |
838 | &hauppauge_novas_config, | |
0590d91c | 839 | &core->i2c_adap); |
cd20ca9f | 840 | if (dev->dvb.frontend) { |
0590d91c | 841 | if (!dvb_attach(isl6421_attach, dev->dvb.frontend, |
83fe92e7 | 842 | &core->i2c_adap, 0x08, ISL6421_DCL, 0x00)) |
0590d91c | 843 | goto frontend_detach; |
cd20ca9f | 844 | } |
0e0351e3 VC |
845 | break; |
846 | case CX88_BOARD_KWORLD_DVBS_100: | |
f7b54b10 MK |
847 | dev->dvb.frontend = dvb_attach(cx24123_attach, |
848 | &kworld_dvbs_100_config, | |
0590d91c | 849 | &core->i2c_adap); |
cd20ca9f | 850 | if (dev->dvb.frontend) { |
0590d91c | 851 | core->prev_set_voltage = dev->dvb.frontend->ops.set_voltage; |
dea74869 | 852 | dev->dvb.frontend->ops.set_voltage = kworld_dvbs_100_set_voltage; |
cd20ca9f | 853 | } |
fde6d31e | 854 | break; |
c02a34f4 | 855 | case CX88_BOARD_GENIATECH_DVBS: |
f7b54b10 MK |
856 | dev->dvb.frontend = dvb_attach(cx24123_attach, |
857 | &geniatech_dvbs_config, | |
0590d91c | 858 | &core->i2c_adap); |
c02a34f4 | 859 | if (dev->dvb.frontend) { |
0590d91c | 860 | core->prev_set_voltage = dev->dvb.frontend->ops.set_voltage; |
c02a34f4 SA |
861 | dev->dvb.frontend->ops.set_voltage = geniatech_dvbs_set_voltage; |
862 | } | |
863 | break; | |
60464da8 | 864 | case CX88_BOARD_PINNACLE_PCTV_HD_800i: |
60464da8 ST |
865 | dev->dvb.frontend = dvb_attach(s5h1409_attach, |
866 | &pinnacle_pctv_hd_800i_config, | |
0590d91c | 867 | &core->i2c_adap); |
60464da8 | 868 | if (dev->dvb.frontend != NULL) { |
0590d91c MCC |
869 | if (!dvb_attach(xc5000_attach, dev->dvb.frontend, |
870 | &core->i2c_adap, | |
30650961 | 871 | &pinnacle_pctv_hd_800i_tuner_config)) |
0590d91c | 872 | goto frontend_detach; |
60464da8 ST |
873 | } |
874 | break; | |
5c00fac0 ST |
875 | case CX88_BOARD_DVICO_FUSIONHDTV_5_PCI_NANO: |
876 | dev->dvb.frontend = dvb_attach(s5h1409_attach, | |
877 | &dvico_hdtv5_pci_nano_config, | |
0590d91c | 878 | &core->i2c_adap); |
5c00fac0 ST |
879 | if (dev->dvb.frontend != NULL) { |
880 | struct dvb_frontend *fe; | |
881 | struct xc2028_config cfg = { | |
0590d91c | 882 | .i2c_adap = &core->i2c_adap, |
5c00fac0 | 883 | .i2c_addr = 0x61, |
5c00fac0 ST |
884 | }; |
885 | static struct xc2028_ctrl ctl = { | |
ef80bfeb | 886 | .fname = XC2028_DEFAULT_FIRMWARE, |
5c00fac0 | 887 | .max_len = 64, |
33e53161 | 888 | .scode_table = XC3028_FE_OREN538, |
5c00fac0 ST |
889 | }; |
890 | ||
891 | fe = dvb_attach(xc2028_attach, | |
892 | dev->dvb.frontend, &cfg); | |
893 | if (fe != NULL && fe->ops.tuner_ops.set_config != NULL) | |
894 | fe->ops.tuner_ops.set_config(fe, &ctl); | |
895 | } | |
896 | break; | |
9507901e MCC |
897 | case CX88_BOARD_PINNACLE_HYBRID_PCTV: |
898 | dev->dvb.frontend = dvb_attach(zl10353_attach, | |
3f6014fc | 899 | &cx88_pinnacle_hybrid_pctv, |
0590d91c | 900 | &core->i2c_adap); |
3f6014fc SV |
901 | if (dev->dvb.frontend) { |
902 | dev->dvb.frontend->ops.i2c_gate_ctrl = NULL; | |
903 | if (attach_xc3028(0x61, dev) < 0) | |
904 | goto frontend_detach; | |
905 | } | |
9507901e MCC |
906 | break; |
907 | case CX88_BOARD_GENIATECH_X8000_MT: | |
99e09eac | 908 | dev->ts_gen_cntrl = 0x00; |
9507901e MCC |
909 | |
910 | dev->dvb.frontend = dvb_attach(zl10353_attach, | |
911 | &cx88_geniatech_x8000_mt, | |
0590d91c | 912 | &core->i2c_adap); |
23fb348d | 913 | if (attach_xc3028(0x61, dev) < 0) |
0590d91c | 914 | goto frontend_detach; |
9507901e | 915 | break; |
99e09eac MCC |
916 | case CX88_BOARD_KWORLD_ATSC_120: |
917 | dev->dvb.frontend = dvb_attach(s5h1409_attach, | |
918 | &kworld_atsc_120_config, | |
0590d91c | 919 | &core->i2c_adap); |
99e09eac | 920 | if (attach_xc3028(0x61, dev) < 0) |
0590d91c | 921 | goto frontend_detach; |
99e09eac | 922 | break; |
d893d5dc ST |
923 | case CX88_BOARD_DVICO_FUSIONHDTV_7_GOLD: |
924 | dev->dvb.frontend = dvb_attach(s5h1411_attach, | |
925 | &dvico_fusionhdtv7_config, | |
0590d91c | 926 | &core->i2c_adap); |
d893d5dc | 927 | if (dev->dvb.frontend != NULL) { |
0590d91c MCC |
928 | if (!dvb_attach(xc5000_attach, dev->dvb.frontend, |
929 | &core->i2c_adap, | |
30650961 | 930 | &dvico_fusionhdtv7_tuner_config)) |
0590d91c | 931 | goto frontend_detach; |
d893d5dc ST |
932 | } |
933 | break; | |
5bd1b663 ST |
934 | case CX88_BOARD_HAUPPAUGE_HVR4000: |
935 | case CX88_BOARD_HAUPPAUGE_HVR4000LITE: | |
936 | /* Support for DVB-S only, not DVB-T support */ | |
937 | dev->dvb.frontend = dvb_attach(cx24116_attach, | |
938 | &hauppauge_hvr4000_config, | |
939 | &dev->core->i2c_adap); | |
940 | if (dev->dvb.frontend) { | |
941 | dvb_attach(isl6421_attach, dev->dvb.frontend, | |
942 | &dev->core->i2c_adap, | |
7396d3ea | 943 | 0x08, ISL6421_DCL, 0x00); |
5bd1b663 ST |
944 | } |
945 | break; | |
e4aab64c IL |
946 | case CX88_BOARD_TEVII_S420: |
947 | dev->dvb.frontend = dvb_attach(stv0299_attach, | |
948 | &tevii_tuner_sharp_config, | |
949 | &core->i2c_adap); | |
950 | if (dev->dvb.frontend != NULL) { | |
951 | if (!dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x60, | |
952 | &core->i2c_adap, DVB_PLL_OPERA1)) | |
953 | goto frontend_detach; | |
954 | core->prev_set_voltage = dev->dvb.frontend->ops.set_voltage; | |
955 | dev->dvb.frontend->ops.set_voltage = tevii_dvbs_set_voltage; | |
956 | ||
957 | } else { | |
958 | dev->dvb.frontend = dvb_attach(stv0288_attach, | |
959 | &tevii_tuner_earda_config, | |
960 | &core->i2c_adap); | |
961 | if (dev->dvb.frontend != NULL) { | |
962 | if (!dvb_attach(stb6000_attach, dev->dvb.frontend, 0x61, | |
963 | &core->i2c_adap)) | |
964 | goto frontend_detach; | |
965 | core->prev_set_voltage = dev->dvb.frontend->ops.set_voltage; | |
966 | dev->dvb.frontend->ops.set_voltage = tevii_dvbs_set_voltage; | |
967 | ||
968 | } | |
969 | } | |
970 | break; | |
af832623 | 971 | case CX88_BOARD_TEVII_S460: |
83fe92e7 | 972 | dev->dvb.frontend = dvb_attach(cx24116_attach, |
af832623 IL |
973 | &tevii_s460_config, |
974 | &core->i2c_adap); | |
4cd7fb87 OR |
975 | if (dev->dvb.frontend != NULL) { |
976 | core->prev_set_voltage = dev->dvb.frontend->ops.set_voltage; | |
977 | dev->dvb.frontend->ops.set_voltage = tevii_dvbs_set_voltage; | |
978 | } | |
979 | break; | |
980 | case CX88_BOARD_OMICOM_SS4_PCI: | |
ee73042c | 981 | case CX88_BOARD_TBS_8920: |
57f51dbc | 982 | case CX88_BOARD_PROF_7300: |
ee73042c OR |
983 | dev->dvb.frontend = dvb_attach(cx24116_attach, |
984 | &hauppauge_hvr4000_config, | |
985 | &core->i2c_adap); | |
af832623 IL |
986 | if (dev->dvb.frontend != NULL) { |
987 | core->prev_set_voltage = dev->dvb.frontend->ops.set_voltage; | |
988 | dev->dvb.frontend->ops.set_voltage = tevii_dvbs_set_voltage; | |
989 | } | |
990 | break; | |
1da177e4 | 991 | default: |
5772f813 | 992 | printk(KERN_ERR "%s/2: The frontend of your DVB/ATSC card isn't supported yet\n", |
0590d91c | 993 | core->name); |
1da177e4 LT |
994 | break; |
995 | } | |
996 | if (NULL == dev->dvb.frontend) { | |
9507901e MCC |
997 | printk(KERN_ERR |
998 | "%s/2: frontend initialization failed\n", | |
0590d91c | 999 | core->name); |
23fb348d | 1000 | return -EINVAL; |
9507901e | 1001 | } |
d7cba043 MK |
1002 | /* define general-purpose callback pointer */ |
1003 | dev->dvb.frontend->callback = cx88_tuner_callback; | |
9507901e | 1004 | |
6c5be74c ST |
1005 | /* Ensure all frontends negotiate bus access */ |
1006 | dev->dvb.frontend->ops.ts_bus_ctrl = cx88_dvb_bus_ctrl; | |
1da177e4 | 1007 | |
93352f5c | 1008 | /* Put the analog decoder in standby to keep it quiet */ |
0590d91c | 1009 | cx88_call_i2c_clients(core, TUNER_SET_STANDBY, NULL); |
93352f5c | 1010 | |
1da177e4 | 1011 | /* register everything */ |
78e92006 JG |
1012 | return videobuf_dvb_register(&dev->dvb, THIS_MODULE, dev, |
1013 | &dev->pci->dev, adapter_nr); | |
0590d91c MCC |
1014 | |
1015 | frontend_detach: | |
1016 | if (dev->dvb.frontend) { | |
1017 | dvb_frontend_detach(dev->dvb.frontend); | |
1018 | dev->dvb.frontend = NULL; | |
1019 | } | |
1020 | return -EINVAL; | |
1da177e4 LT |
1021 | } |
1022 | ||
1023 | /* ----------------------------------------------------------- */ | |
1024 | ||
6c5be74c ST |
1025 | /* CX8802 MPEG -> mini driver - We have been given the hardware */ |
1026 | static int cx8802_dvb_advise_acquire(struct cx8802_driver *drv) | |
1da177e4 | 1027 | { |
6c5be74c ST |
1028 | struct cx88_core *core = drv->core; |
1029 | int err = 0; | |
32d83efc | 1030 | dprintk( 1, "%s\n", __func__); |
6c5be74c | 1031 | |
6a59d64c | 1032 | switch (core->boardnr) { |
6c5be74c ST |
1033 | case CX88_BOARD_HAUPPAUGE_HVR1300: |
1034 | /* We arrive here with either the cx23416 or the cx22702 | |
1035 | * on the bus. Take the bus from the cx23416 and enable the | |
1036 | * cx22702 demod | |
1037 | */ | |
1038 | cx_set(MO_GP0_IO, 0x00000080); /* cx22702 out of reset and enable */ | |
1039 | cx_clear(MO_GP0_IO, 0x00000004); | |
1040 | udelay(1000); | |
1041 | break; | |
1042 | default: | |
1043 | err = -ENODEV; | |
1044 | } | |
1045 | return err; | |
1046 | } | |
1047 | ||
1048 | /* CX8802 MPEG -> mini driver - We no longer have the hardware */ | |
1049 | static int cx8802_dvb_advise_release(struct cx8802_driver *drv) | |
1050 | { | |
1051 | struct cx88_core *core = drv->core; | |
1052 | int err = 0; | |
32d83efc | 1053 | dprintk( 1, "%s\n", __func__); |
6c5be74c | 1054 | |
6a59d64c | 1055 | switch (core->boardnr) { |
6c5be74c ST |
1056 | case CX88_BOARD_HAUPPAUGE_HVR1300: |
1057 | /* Do Nothing, leave the cx22702 on the bus. */ | |
1058 | break; | |
1059 | default: | |
1060 | err = -ENODEV; | |
1061 | } | |
1062 | return err; | |
1063 | } | |
1064 | ||
1065 | static int cx8802_dvb_probe(struct cx8802_driver *drv) | |
1066 | { | |
1067 | struct cx88_core *core = drv->core; | |
1068 | struct cx8802_dev *dev = drv->core->dvbdev; | |
1da177e4 LT |
1069 | int err; |
1070 | ||
32d83efc | 1071 | dprintk( 1, "%s\n", __func__); |
6c5be74c | 1072 | dprintk( 1, " ->being probed by Card=%d Name=%s, PCI %02x:%02x\n", |
6a59d64c | 1073 | core->boardnr, |
6c5be74c ST |
1074 | core->name, |
1075 | core->pci_bus, | |
1076 | core->pci_slot); | |
1da177e4 LT |
1077 | |
1078 | err = -ENODEV; | |
6a59d64c | 1079 | if (!(core->board.mpeg & CX88_MPEG_DVB)) |
1da177e4 LT |
1080 | goto fail_core; |
1081 | ||
ecf854df | 1082 | /* If vp3054 isn't enabled, a stub will just return 0 */ |
fc40b261 CP |
1083 | err = vp3054_i2c_probe(dev); |
1084 | if (0 != err) | |
6c5be74c | 1085 | goto fail_core; |
fc40b261 | 1086 | |
1da177e4 | 1087 | /* dvb stuff */ |
5772f813 | 1088 | printk(KERN_INFO "%s/2: cx2388x based DVB/ATSC card\n", core->name); |
0705135e GL |
1089 | videobuf_queue_sg_init(&dev->dvb.dvbq, &dvb_qops, |
1090 | &dev->pci->dev, &dev->slock, | |
1da177e4 LT |
1091 | V4L2_BUF_TYPE_VIDEO_CAPTURE, |
1092 | V4L2_FIELD_TOP, | |
1093 | sizeof(struct cx88_buffer), | |
1094 | dev); | |
1095 | err = dvb_register(dev); | |
6c5be74c | 1096 | if (err != 0) |
5772f813 TP |
1097 | printk(KERN_ERR "%s/2: dvb_register failed (err = %d)\n", |
1098 | core->name, err); | |
1da177e4 | 1099 | |
1da177e4 | 1100 | fail_core: |
1da177e4 LT |
1101 | return err; |
1102 | } | |
1103 | ||
6c5be74c | 1104 | static int cx8802_dvb_remove(struct cx8802_driver *drv) |
1da177e4 | 1105 | { |
6c5be74c | 1106 | struct cx8802_dev *dev = drv->core->dvbdev; |
611900c1 | 1107 | |
1da177e4 | 1108 | /* dvb */ |
9950c1b5 MCC |
1109 | if (dev->dvb.frontend) |
1110 | videobuf_dvb_unregister(&dev->dvb); | |
1da177e4 | 1111 | |
fc40b261 | 1112 | vp3054_i2c_remove(dev); |
fc40b261 | 1113 | |
6c5be74c | 1114 | return 0; |
1da177e4 LT |
1115 | } |
1116 | ||
6c5be74c ST |
1117 | static struct cx8802_driver cx8802_dvb_driver = { |
1118 | .type_id = CX88_MPEG_DVB, | |
1119 | .hw_access = CX8802_DRVCTL_SHARED, | |
1120 | .probe = cx8802_dvb_probe, | |
1121 | .remove = cx8802_dvb_remove, | |
1122 | .advise_acquire = cx8802_dvb_advise_acquire, | |
1123 | .advise_release = cx8802_dvb_advise_release, | |
1da177e4 LT |
1124 | }; |
1125 | ||
1126 | static int dvb_init(void) | |
1127 | { | |
5772f813 | 1128 | printk(KERN_INFO "cx88/2: cx2388x dvb driver version %d.%d.%d loaded\n", |
1da177e4 LT |
1129 | (CX88_VERSION_CODE >> 16) & 0xff, |
1130 | (CX88_VERSION_CODE >> 8) & 0xff, | |
1131 | CX88_VERSION_CODE & 0xff); | |
1132 | #ifdef SNAPSHOT | |
1133 | printk(KERN_INFO "cx2388x: snapshot date %04d-%02d-%02d\n", | |
1134 | SNAPSHOT/10000, (SNAPSHOT/100)%100, SNAPSHOT%100); | |
1135 | #endif | |
6c5be74c | 1136 | return cx8802_register_driver(&cx8802_dvb_driver); |
1da177e4 LT |
1137 | } |
1138 | ||
1139 | static void dvb_fini(void) | |
1140 | { | |
6c5be74c | 1141 | cx8802_unregister_driver(&cx8802_dvb_driver); |
1da177e4 LT |
1142 | } |
1143 | ||
1144 | module_init(dvb_init); | |
1145 | module_exit(dvb_fini); | |
1146 | ||
1147 | /* | |
1148 | * Local variables: | |
1149 | * c-basic-offset: 8 | |
1150 | * compile-command: "make DVB=1" | |
1151 | * End: | |
1152 | */ |