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V4L/DVB (8902): pvrusb2: Remove comment lines which refer to checkpatch's behavior
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / media / video / cx23885 / cx23885-417.c
CommitLineData
b1b81f1d
ST		 1/*
2 *
3 * Support for a cx23417 mpeg encoder via cx23885 host port.
4 *
5 * (c) 2004 Jelle Foks <jelle@foks.8m.com>
6 * (c) 2004 Gerd Knorr <kraxel@bytesex.org>
6d897616 7 * (c) 2008 Steven Toth <stoth@linuxtv.org>
b1b81f1d
ST		 8 * - CX23885/7/8 support
9 *
10 * Includes parts from the ivtv driver( http://ivtv.sourceforge.net/),
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27#include <linux/module.h>
28#include <linux/moduleparam.h>
29#include <linux/init.h>
30#include <linux/fs.h>
31#include <linux/delay.h>
32#include <linux/device.h>
33#include <linux/firmware.h>
34#include <media/v4l2-common.h>
35ea11ff 35#include <media/v4l2-ioctl.h>
b1b81f1d
ST		 36#include <media/cx2341x.h>
37
38#include "cx23885.h"
39#include "media/cx2341x.h"
40
41#define CX23885_FIRM_IMAGE_SIZE 376836
42#define CX23885_FIRM_IMAGE_NAME "v4l-cx23885-enc.fw"
43
44static unsigned int mpegbufs = 32;
45module_param(mpegbufs, int, 0644);
46MODULE_PARM_DESC(mpegbufs, "number of mpeg buffers, range 2-32");
47static unsigned int mpeglines = 32;
48module_param(mpeglines, int, 0644);
49MODULE_PARM_DESC(mpeglines, "number of lines in an MPEG buffer, range 2-32");
50static unsigned int mpeglinesize = 512;
51module_param(mpeglinesize, int, 0644);
52MODULE_PARM_DESC(mpeglinesize,
53 "number of bytes in each line of an MPEG buffer, range 512-1024");
54
55static unsigned int v4l_debug;
56module_param(v4l_debug, int, 0644);
57MODULE_PARM_DESC(v4l_debug, "enable V4L debug messages");
58
59#define dprintk(level, fmt, arg...)\
60 do { if (v4l_debug >= level) \
61 printk(KERN_DEBUG "%s: " fmt, dev->name , ## arg);\
62 } while (0)
63
64static struct cx23885_tvnorm cx23885_tvnorms[] = {
65 {
66 .name = "NTSC-M",
67 .id = V4L2_STD_NTSC_M,
68 }, {
69 .name = "NTSC-JP",
70 .id = V4L2_STD_NTSC_M_JP,
71 }, {
72 .name = "PAL-BG",
73 .id = V4L2_STD_PAL_BG,
74 }, {
75 .name = "PAL-DK",
76 .id = V4L2_STD_PAL_DK,
77 }, {
78 .name = "PAL-I",
79 .id = V4L2_STD_PAL_I,
80 }, {
81 .name = "PAL-M",
82 .id = V4L2_STD_PAL_M,
83 }, {
84 .name = "PAL-N",
85 .id = V4L2_STD_PAL_N,
86 }, {
87 .name = "PAL-Nc",
88 .id = V4L2_STD_PAL_Nc,
89 }, {
90 .name = "PAL-60",
91 .id = V4L2_STD_PAL_60,
92 }, {
93 .name = "SECAM-L",
94 .id = V4L2_STD_SECAM_L,
95 }, {
96 .name = "SECAM-DK",
97 .id = V4L2_STD_SECAM_DK,
98 }
99};
100
101/* ------------------------------------------------------------------ */
102enum cx23885_capture_type {
103 CX23885_MPEG_CAPTURE,
104 CX23885_RAW_CAPTURE,
105 CX23885_RAW_PASSTHRU_CAPTURE
106};
107enum cx23885_capture_bits {
108 CX23885_RAW_BITS_NONE = 0x00,
109 CX23885_RAW_BITS_YUV_CAPTURE = 0x01,
110 CX23885_RAW_BITS_PCM_CAPTURE = 0x02,
111 CX23885_RAW_BITS_VBI_CAPTURE = 0x04,
112 CX23885_RAW_BITS_PASSTHRU_CAPTURE = 0x08,
113 CX23885_RAW_BITS_TO_HOST_CAPTURE = 0x10
114};
115enum cx23885_capture_end {
116 CX23885_END_AT_GOP, /* stop at the end of gop, generate irq */
117 CX23885_END_NOW, /* stop immediately, no irq */
118};
119enum cx23885_framerate {
120 CX23885_FRAMERATE_NTSC_30, /* NTSC: 30fps */
121 CX23885_FRAMERATE_PAL_25 /* PAL: 25fps */
122};
123enum cx23885_stream_port {
124 CX23885_OUTPUT_PORT_MEMORY,
125 CX23885_OUTPUT_PORT_STREAMING,
126 CX23885_OUTPUT_PORT_SERIAL
127};
128enum cx23885_data_xfer_status {
129 CX23885_MORE_BUFFERS_FOLLOW,
130 CX23885_LAST_BUFFER,
131};
132enum cx23885_picture_mask {
133 CX23885_PICTURE_MASK_NONE,
134 CX23885_PICTURE_MASK_I_FRAMES,
135 CX23885_PICTURE_MASK_I_P_FRAMES = 0x3,
136 CX23885_PICTURE_MASK_ALL_FRAMES = 0x7,
137};
138enum cx23885_vbi_mode_bits {
139 CX23885_VBI_BITS_SLICED,
140 CX23885_VBI_BITS_RAW,
141};
142enum cx23885_vbi_insertion_bits {
143 CX23885_VBI_BITS_INSERT_IN_XTENSION_USR_DATA,
144 CX23885_VBI_BITS_INSERT_IN_PRIVATE_PACKETS = 0x1 << 1,
145 CX23885_VBI_BITS_SEPARATE_STREAM = 0x2 << 1,
146 CX23885_VBI_BITS_SEPARATE_STREAM_USR_DATA = 0x4 << 1,
147 CX23885_VBI_BITS_SEPARATE_STREAM_PRV_DATA = 0x5 << 1,
148};
149enum cx23885_dma_unit {
150 CX23885_DMA_BYTES,
151 CX23885_DMA_FRAMES,
152};
153enum cx23885_dma_transfer_status_bits {
154 CX23885_DMA_TRANSFER_BITS_DONE = 0x01,
155 CX23885_DMA_TRANSFER_BITS_ERROR = 0x04,
156 CX23885_DMA_TRANSFER_BITS_LL_ERROR = 0x10,
157};
158enum cx23885_pause {
159 CX23885_PAUSE_ENCODING,
160 CX23885_RESUME_ENCODING,
161};
162enum cx23885_copyright {
163 CX23885_COPYRIGHT_OFF,
164 CX23885_COPYRIGHT_ON,
165};
166enum cx23885_notification_type {
167 CX23885_NOTIFICATION_REFRESH,
168};
169enum cx23885_notification_status {
170 CX23885_NOTIFICATION_OFF,
171 CX23885_NOTIFICATION_ON,
172};
173enum cx23885_notification_mailbox {
174 CX23885_NOTIFICATION_NO_MAILBOX = -1,
175};
176enum cx23885_field1_lines {
177 CX23885_FIELD1_SAA7114 = 0x00EF, /* 239 */
178 CX23885_FIELD1_SAA7115 = 0x00F0, /* 240 */
179 CX23885_FIELD1_MICRONAS = 0x0105, /* 261 */
180};
181enum cx23885_field2_lines {
182 CX23885_FIELD2_SAA7114 = 0x00EF, /* 239 */
183 CX23885_FIELD2_SAA7115 = 0x00F0, /* 240 */
184 CX23885_FIELD2_MICRONAS = 0x0106, /* 262 */
185};
186enum cx23885_custom_data_type {
187 CX23885_CUSTOM_EXTENSION_USR_DATA,
188 CX23885_CUSTOM_PRIVATE_PACKET,
189};
190enum cx23885_mute {
191 CX23885_UNMUTE,
192 CX23885_MUTE,
193};
194enum cx23885_mute_video_mask {
195 CX23885_MUTE_VIDEO_V_MASK = 0x0000FF00,
196 CX23885_MUTE_VIDEO_U_MASK = 0x00FF0000,
197 CX23885_MUTE_VIDEO_Y_MASK = 0xFF000000,
198};
199enum cx23885_mute_video_shift {
200 CX23885_MUTE_VIDEO_V_SHIFT = 8,
201 CX23885_MUTE_VIDEO_U_SHIFT = 16,
202 CX23885_MUTE_VIDEO_Y_SHIFT = 24,
203};
204
205/* defines below are from ivtv-driver.h */
206#define IVTV_CMD_HW_BLOCKS_RST 0xFFFFFFFF
207
208/* Firmware API commands */
209#define IVTV_API_STD_TIMEOUT 500
210
211/* Registers */
212/* IVTV_REG_OFFSET */
213#define IVTV_REG_ENC_SDRAM_REFRESH (0x07F8)
214#define IVTV_REG_ENC_SDRAM_PRECHARGE (0x07FC)
215#define IVTV_REG_SPU (0x9050)
216#define IVTV_REG_HW_BLOCKS (0x9054)
217#define IVTV_REG_VPU (0x9058)
218#define IVTV_REG_APU (0xA064)
219
220/**** Bit definitions for MC417_RWD and MC417_OEN registers ***
221 bits 31-16
222+-----------+
223| Reserved |
224+-----------+
225 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
226+-------+-------+-------+-------+-------+-------+-------+-------+
227| MIWR# | MIRD# | MICS# |MIRDY# |MIADDR3|MIADDR2|MIADDR1|MIADDR0|
228+-------+-------+-------+-------+-------+-------+-------+-------+
229 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
230+-------+-------+-------+-------+-------+-------+-------+-------+
231|MIDATA7|MIDATA6|MIDATA5|MIDATA4|MIDATA3|MIDATA2|MIDATA1|MIDATA0|
232+-------+-------+-------+-------+-------+-------+-------+-------+
233***/
234#define MC417_MIWR 0x8000
235#define MC417_MIRD 0x4000
236#define MC417_MICS 0x2000
237#define MC417_MIRDY 0x1000
238#define MC417_MIADDR 0x0F00
239#define MC417_MIDATA 0x00FF
240
241/* MIADDR* nibble definitions */
242#define MCI_MEMORY_DATA_BYTE0 0x000
243#define MCI_MEMORY_DATA_BYTE1 0x100
244#define MCI_MEMORY_DATA_BYTE2 0x200
245#define MCI_MEMORY_DATA_BYTE3 0x300
246#define MCI_MEMORY_ADDRESS_BYTE2 0x400
247#define MCI_MEMORY_ADDRESS_BYTE1 0x500
248#define MCI_MEMORY_ADDRESS_BYTE0 0x600
249#define MCI_REGISTER_DATA_BYTE0 0x800
250#define MCI_REGISTER_DATA_BYTE1 0x900
251#define MCI_REGISTER_DATA_BYTE2 0xA00
252#define MCI_REGISTER_DATA_BYTE3 0xB00
253#define MCI_REGISTER_ADDRESS_BYTE0 0xC00
254#define MCI_REGISTER_ADDRESS_BYTE1 0xD00
255#define MCI_REGISTER_MODE 0xE00
256
257/* Read and write modes */
258#define MCI_MODE_REGISTER_READ 0
259#define MCI_MODE_REGISTER_WRITE 1
260#define MCI_MODE_MEMORY_READ 0
261#define MCI_MODE_MEMORY_WRITE 0x40
262
263/*** Bit definitions for MC417_CTL register ****
264 bits 31-6 bits 5-4 bit 3 bits 2-1 Bit 0
265+--------+-------------+--------+--------------+------------+
266|Reserved|MC417_SPD_CTL|Reserved|MC417_GPIO_SEL|UART_GPIO_EN|
267+--------+-------------+--------+--------------+------------+
268***/
269#define MC417_SPD_CTL(x) (((x) << 4) & 0x00000030)
270#define MC417_GPIO_SEL(x) (((x) << 1) & 0x00000006)
271#define MC417_UART_GPIO_EN 0x00000001
272
273/* Values for speed control */
274#define MC417_SPD_CTL_SLOW 0x1
275#define MC417_SPD_CTL_MEDIUM 0x0
276#define MC417_SPD_CTL_FAST 0x3 /* b'1x, but we use b'11 */
277
278/* Values for GPIO select */
279#define MC417_GPIO_SEL_GPIO3 0x3
280#define MC417_GPIO_SEL_GPIO2 0x2
281#define MC417_GPIO_SEL_GPIO1 0x1
282#define MC417_GPIO_SEL_GPIO0 0x0
283
284void cx23885_mc417_init(struct cx23885_dev *dev)
285{
286 u32 regval;
287
288 dprintk(2, "%s()\n", __func__);
289
290 /* Configure MC417_CTL register to defaults. */
291 regval = MC417_SPD_CTL(MC417_SPD_CTL_FAST) |
292 MC417_GPIO_SEL(MC417_GPIO_SEL_GPIO3) |
293 MC417_UART_GPIO_EN;
294 cx_write(MC417_CTL, regval);
295
296 /* Configure MC417_OEN to defaults. */
297 regval = MC417_MIRDY;
298 cx_write(MC417_OEN, regval);
299
300 /* Configure MC417_RWD to defaults. */
301 regval = MC417_MIWR | MC417_MIRD | MC417_MICS;
302 cx_write(MC417_RWD, regval);
303}
304
305static int mc417_wait_ready(struct cx23885_dev *dev)
306{
307 u32 mi_ready;
308 unsigned long timeout = jiffies + msecs_to_jiffies(1);
309
310 for (;;) {
311 mi_ready = cx_read(MC417_RWD) & MC417_MIRDY;
312 if (mi_ready != 0)
313 return 0;
314 if (time_after(jiffies, timeout))
315 return -1;
316 udelay(1);
317 }
318}
319
320static int mc417_register_write(struct cx23885_dev *dev, u16 address, u32 value)
321{
322 u32 regval;
323
324 /* Enable MC417 GPIO outputs except for MC417_MIRDY,
325 * which is an input.
326 */
327 cx_write(MC417_OEN, MC417_MIRDY);
328
329 /* Write data byte 0 */
330 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE0 |
331 (value & 0x000000FF);
332 cx_write(MC417_RWD, regval);
333
334 /* Transition CS/WR to effect write transaction across bus. */
335 regval |= MC417_MICS | MC417_MIWR;
336 cx_write(MC417_RWD, regval);
337
338 /* Write data byte 1 */
339 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE1 |
340 ((value >> 8) & 0x000000FF);
341 cx_write(MC417_RWD, regval);
342 regval |= MC417_MICS | MC417_MIWR;
343 cx_write(MC417_RWD, regval);
344
345 /* Write data byte 2 */
346 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE2 |
347 ((value >> 16) & 0x000000FF);
348 cx_write(MC417_RWD, regval);
349 regval |= MC417_MICS | MC417_MIWR;
350 cx_write(MC417_RWD, regval);
351
352 /* Write data byte 3 */
353 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE3 |
354 ((value >> 24) & 0x000000FF);
355 cx_write(MC417_RWD, regval);
356 regval |= MC417_MICS | MC417_MIWR;
357 cx_write(MC417_RWD, regval);
358
359 /* Write address byte 0 */
360 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE0 |
361 (address & 0xFF);
362 cx_write(MC417_RWD, regval);
363 regval |= MC417_MICS | MC417_MIWR;
364 cx_write(MC417_RWD, regval);
365
366 /* Write address byte 1 */
367 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE1 |
368 ((address >> 8) & 0xFF);
369 cx_write(MC417_RWD, regval);
370 regval |= MC417_MICS | MC417_MIWR;
371 cx_write(MC417_RWD, regval);
372
373 /* Indicate that this is a write. */
374 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_MODE |
375 MCI_MODE_REGISTER_WRITE;
376 cx_write(MC417_RWD, regval);
377 regval |= MC417_MICS | MC417_MIWR;
378 cx_write(MC417_RWD, regval);
379
380 /* Wait for the trans to complete (MC417_MIRDY asserted). */
381 return mc417_wait_ready(dev);
382}
383
384static int mc417_register_read(struct cx23885_dev *dev, u16 address, u32 *value)
385{
386 int retval;
387 u32 regval;
388 u32 tempval;
389 u32 dataval;
390
391 /* Enable MC417 GPIO outputs except for MC417_MIRDY,
392 * which is an input.
393 */
394 cx_write(MC417_OEN, MC417_MIRDY);
395
396 /* Write address byte 0 */
397 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE0 |
398 ((address & 0x00FF));
399 cx_write(MC417_RWD, regval);
400 regval |= MC417_MICS | MC417_MIWR;
401 cx_write(MC417_RWD, regval);
402
403 /* Write address byte 1 */
404 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE1 |
405 ((address >> 8) & 0xFF);
406 cx_write(MC417_RWD, regval);
407 regval |= MC417_MICS | MC417_MIWR;
408 cx_write(MC417_RWD, regval);
409
410 /* Indicate that this is a register read. */
411 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_MODE |
412 MCI_MODE_REGISTER_READ;
413 cx_write(MC417_RWD, regval);
414 regval |= MC417_MICS | MC417_MIWR;
415 cx_write(MC417_RWD, regval);
416
417 /* Wait for the trans to complete (MC417_MIRDY asserted). */
418 retval = mc417_wait_ready(dev);
419
420 /* switch the DAT0-7 GPIO[10:3] to input mode */
421 cx_write(MC417_OEN, MC417_MIRDY | MC417_MIDATA);
422
423 /* Read data byte 0 */
424 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE0;
425 cx_write(MC417_RWD, regval);
426
427 /* Transition RD to effect read transaction across bus.
428 * Transtion 0x5000 -> 0x9000 correct (RD/RDY -> WR/RDY)?
429 * Should it be 0x9000 -> 0xF000 (also why is RDY being set, its
430 * input only...)
431 */
432 regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE0;
433 cx_write(MC417_RWD, regval);
434
435 /* Collect byte */
436 tempval = cx_read(MC417_RWD);
437 dataval = tempval & 0x000000FF;
438
439 /* Bring CS and RD high. */
440 regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
441 cx_write(MC417_RWD, regval);
442
443 /* Read data byte 1 */
444 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE1;
445 cx_write(MC417_RWD, regval);
446 regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE1;
447 cx_write(MC417_RWD, regval);
448 tempval = cx_read(MC417_RWD);
449 dataval |= ((tempval & 0x000000FF) << 8);
450 regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
451 cx_write(MC417_RWD, regval);
452
453 /* Read data byte 2 */
454 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE2;
455 cx_write(MC417_RWD, regval);
456 regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE2;
457 cx_write(MC417_RWD, regval);
458 tempval = cx_read(MC417_RWD);
459 dataval |= ((tempval & 0x000000FF) << 16);
460 regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
461 cx_write(MC417_RWD, regval);
462
463 /* Read data byte 3 */
464 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE3;
465 cx_write(MC417_RWD, regval);
466 regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE3;
467 cx_write(MC417_RWD, regval);
468 tempval = cx_read(MC417_RWD);
469 dataval |= ((tempval & 0x000000FF) << 24);
470 regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
471 cx_write(MC417_RWD, regval);
472
473 *value = dataval;
474
475 return retval;
476}
477
478int mc417_memory_write(struct cx23885_dev *dev, u32 address, u32 value)
479{
480 u32 regval;
481
482 /* Enable MC417 GPIO outputs except for MC417_MIRDY,
483 * which is an input.
484 */
485 cx_write(MC417_OEN, MC417_MIRDY);
486
487 /* Write data byte 0 */
488 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE0 |
489 (value & 0x000000FF);
490 cx_write(MC417_RWD, regval);
491
492 /* Transition CS/WR to effect write transaction across bus. */
493 regval |= MC417_MICS | MC417_MIWR;
494 cx_write(MC417_RWD, regval);
495
496 /* Write data byte 1 */
497 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE1 |
498 ((value >> 8) & 0x000000FF);
499 cx_write(MC417_RWD, regval);
500 regval |= MC417_MICS | MC417_MIWR;
501 cx_write(MC417_RWD, regval);
502
503 /* Write data byte 2 */
504 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE2 |
505 ((value >> 16) & 0x000000FF);
506 cx_write(MC417_RWD, regval);
507 regval |= MC417_MICS | MC417_MIWR;
508 cx_write(MC417_RWD, regval);
509
510 /* Write data byte 3 */
511 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE3 |
512 ((value >> 24) & 0x000000FF);
513 cx_write(MC417_RWD, regval);
514 regval |= MC417_MICS | MC417_MIWR;
515 cx_write(MC417_RWD, regval);
516
517 /* Write address byte 2 */
518 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE2 |
519 MCI_MODE_MEMORY_WRITE | ((address >> 16) & 0x3F);
520 cx_write(MC417_RWD, regval);
521 regval |= MC417_MICS | MC417_MIWR;
522 cx_write(MC417_RWD, regval);
523
524 /* Write address byte 1 */
525 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE1 |
526 ((address >> 8) & 0xFF);
527 cx_write(MC417_RWD, regval);
528 regval |= MC417_MICS | MC417_MIWR;
529 cx_write(MC417_RWD, regval);
530
531 /* Write address byte 0 */
532 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE0 |
533 (address & 0xFF);
534 cx_write(MC417_RWD, regval);
535 regval |= MC417_MICS | MC417_MIWR;
536 cx_write(MC417_RWD, regval);
537
538 /* Wait for the trans to complete (MC417_MIRDY asserted). */
539 return mc417_wait_ready(dev);
540}
541
542int mc417_memory_read(struct cx23885_dev *dev, u32 address, u32 *value)
543{
544 int retval;
545 u32 regval;
546 u32 tempval;
547 u32 dataval;
548
549 /* Enable MC417 GPIO outputs except for MC417_MIRDY,
550 * which is an input.
551 */
552 cx_write(MC417_OEN, MC417_MIRDY);
553
554 /* Write address byte 2 */
555 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE2 |
556 MCI_MODE_MEMORY_READ | ((address >> 16) & 0x3F);
557 cx_write(MC417_RWD, regval);
558 regval |= MC417_MICS | MC417_MIWR;
559 cx_write(MC417_RWD, regval);
560
561 /* Write address byte 1 */
562 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE1 |
563 ((address >> 8) & 0xFF);
564 cx_write(MC417_RWD, regval);
565 regval |= MC417_MICS | MC417_MIWR;
566 cx_write(MC417_RWD, regval);
567
568 /* Write address byte 0 */
569 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE0 |
570 (address & 0xFF);
571 cx_write(MC417_RWD, regval);
572 regval |= MC417_MICS | MC417_MIWR;
573 cx_write(MC417_RWD, regval);
574
575 /* Wait for the trans to complete (MC417_MIRDY asserted). */
576 retval = mc417_wait_ready(dev);
577
578 /* switch the DAT0-7 GPIO[10:3] to input mode */
579 cx_write(MC417_OEN, MC417_MIRDY | MC417_MIDATA);
580
581 /* Read data byte 3 */
582 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE3;
583 cx_write(MC417_RWD, regval);
584
585 /* Transition RD to effect read transaction across bus. */
586 regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE3;
587 cx_write(MC417_RWD, regval);
588
589 /* Collect byte */
590 tempval = cx_read(MC417_RWD);
591 dataval = ((tempval & 0x000000FF) << 24);
592
593 /* Bring CS and RD high. */
594 regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
595 cx_write(MC417_RWD, regval);
596
597 /* Read data byte 2 */
598 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE2;
599 cx_write(MC417_RWD, regval);
600 regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE2;
601 cx_write(MC417_RWD, regval);
602 tempval = cx_read(MC417_RWD);
603 dataval |= ((tempval & 0x000000FF) << 16);
604 regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
605 cx_write(MC417_RWD, regval);
606
607 /* Read data byte 1 */
608 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE1;
609 cx_write(MC417_RWD, regval);
610 regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE1;
611 cx_write(MC417_RWD, regval);
612 tempval = cx_read(MC417_RWD);
613 dataval |= ((tempval & 0x000000FF) << 8);
614 regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
615 cx_write(MC417_RWD, regval);
616
617 /* Read data byte 0 */
618 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE0;
619 cx_write(MC417_RWD, regval);
620 regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE0;
621 cx_write(MC417_RWD, regval);
622 tempval = cx_read(MC417_RWD);
623 dataval |= (tempval & 0x000000FF);
624 regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
625 cx_write(MC417_RWD, regval);
626
627 *value = dataval;
628
629 return retval;
630}
631
632/* ------------------------------------------------------------------ */
633
634/* MPEG encoder API */
635char *cmd_to_str(int cmd)
636{
637 switch (cmd) {
638 case CX2341X_ENC_PING_FW:
639 return "PING_FW";
640 case CX2341X_ENC_START_CAPTURE:
641 return "START_CAPTURE";
642 case CX2341X_ENC_STOP_CAPTURE:
643 return "STOP_CAPTURE";
644 case CX2341X_ENC_SET_AUDIO_ID:
645 return "SET_AUDIO_ID";
646 case CX2341X_ENC_SET_VIDEO_ID:
647 return "SET_VIDEO_ID";
648 case CX2341X_ENC_SET_PCR_ID:
649 return "SET_PCR_PID";
650 case CX2341X_ENC_SET_FRAME_RATE:
651 return "SET_FRAME_RATE";
652 case CX2341X_ENC_SET_FRAME_SIZE:
653 return "SET_FRAME_SIZE";
654 case CX2341X_ENC_SET_BIT_RATE:
655 return "SET_BIT_RATE";
656 case CX2341X_ENC_SET_GOP_PROPERTIES:
657 return "SET_GOP_PROPERTIES";
658 case CX2341X_ENC_SET_ASPECT_RATIO:
659 return "SET_ASPECT_RATIO";
660 case CX2341X_ENC_SET_DNR_FILTER_MODE:
661 return "SET_DNR_FILTER_PROPS";
662 case CX2341X_ENC_SET_DNR_FILTER_PROPS:
663 return "SET_DNR_FILTER_PROPS";
664 case CX2341X_ENC_SET_CORING_LEVELS:
665 return "SET_CORING_LEVELS";
666 case CX2341X_ENC_SET_SPATIAL_FILTER_TYPE:
667 return "SET_SPATIAL_FILTER_TYPE";
668 case CX2341X_ENC_SET_VBI_LINE:
669 return "SET_VBI_LINE";
670 case CX2341X_ENC_SET_STREAM_TYPE:
671 return "SET_STREAM_TYPE";
672 case CX2341X_ENC_SET_OUTPUT_PORT:
673 return "SET_OUTPUT_PORT";
674 case CX2341X_ENC_SET_AUDIO_PROPERTIES:
675 return "SET_AUDIO_PROPERTIES";
676 case CX2341X_ENC_HALT_FW:
677 return "HALT_FW";
678 case CX2341X_ENC_GET_VERSION:
679 return "GET_VERSION";
680 case CX2341X_ENC_SET_GOP_CLOSURE:
681 return "SET_GOP_CLOSURE";
682 case CX2341X_ENC_GET_SEQ_END:
683 return "GET_SEQ_END";
684 case CX2341X_ENC_SET_PGM_INDEX_INFO:
685 return "SET_PGM_INDEX_INFO";
686 case CX2341X_ENC_SET_VBI_CONFIG:
687 return "SET_VBI_CONFIG";
688 case CX2341X_ENC_SET_DMA_BLOCK_SIZE:
689 return "SET_DMA_BLOCK_SIZE";
690 case CX2341X_ENC_GET_PREV_DMA_INFO_MB_10:
691 return "GET_PREV_DMA_INFO_MB_10";
692 case CX2341X_ENC_GET_PREV_DMA_INFO_MB_9:
693 return "GET_PREV_DMA_INFO_MB_9";
694 case CX2341X_ENC_SCHED_DMA_TO_HOST:
695 return "SCHED_DMA_TO_HOST";
696 case CX2341X_ENC_INITIALIZE_INPUT:
697 return "INITIALIZE_INPUT";
698 case CX2341X_ENC_SET_FRAME_DROP_RATE:
699 return "SET_FRAME_DROP_RATE";
700 case CX2341X_ENC_PAUSE_ENCODER:
701 return "PAUSE_ENCODER";
702 case CX2341X_ENC_REFRESH_INPUT:
703 return "REFRESH_INPUT";
704 case CX2341X_ENC_SET_COPYRIGHT:
705 return "SET_COPYRIGHT";
706 case CX2341X_ENC_SET_EVENT_NOTIFICATION:
707 return "SET_EVENT_NOTIFICATION";
708 case CX2341X_ENC_SET_NUM_VSYNC_LINES:
709 return "SET_NUM_VSYNC_LINES";
710 case CX2341X_ENC_SET_PLACEHOLDER:
711 return "SET_PLACEHOLDER";
712 case CX2341X_ENC_MUTE_VIDEO:
713 return "MUTE_VIDEO";
714 case CX2341X_ENC_MUTE_AUDIO:
715 return "MUTE_AUDIO";
716 case CX2341X_ENC_MISC:
717 return "MISC";
718 default:
719 return "UNKNOWN";
720 }
721}
722
723static int cx23885_mbox_func(void *priv,
724 u32 command,
725 int in,
726 int out,
727 u32 data[CX2341X_MBOX_MAX_DATA])
728{
729 struct cx23885_dev *dev = priv;
730 unsigned long timeout;
731 u32 value, flag, retval = 0;
732 int i;
733
734 dprintk(3, "%s: command(0x%X) = %s\n", __func__, command,
735 cmd_to_str(command));
736
737 /* this may not be 100% safe if we can't read any memory location
738 without side effects */
739 mc417_memory_read(dev, dev->cx23417_mailbox - 4, &value);
740 if (value != 0x12345678) {
741 printk(KERN_ERR
742 "Firmware and/or mailbox pointer not initialized "
743 "or corrupted, signature = 0x%x, cmd = %s\n", value,
744 cmd_to_str(command));
745 return -1;
746 }
747
748 /* This read looks at 32 bits, but flag is only 8 bits.
749 * Seems we also bail if CMD or TIMEOUT bytes are set???
750 */
751 mc417_memory_read(dev, dev->cx23417_mailbox, &flag);
752 if (flag) {
753 printk(KERN_ERR "ERROR: Mailbox appears to be in use "
754 "(%x), cmd = %s\n", flag, cmd_to_str(command));
755 return -1;
756 }
757
758 flag |= 1; /* tell 'em we're working on it */
759 mc417_memory_write(dev, dev->cx23417_mailbox, flag);
760
761 /* write command + args + fill remaining with zeros */
762 /* command code */
763 mc417_memory_write(dev, dev->cx23417_mailbox + 1, command);
764 mc417_memory_write(dev, dev->cx23417_mailbox + 3,
765 IVTV_API_STD_TIMEOUT); /* timeout */
766 for (i = 0; i < in; i++) {
767 mc417_memory_write(dev, dev->cx23417_mailbox + 4 + i, data[i]);
768 dprintk(3, "API Input %d = %d\n", i, data[i]);
769 }
770 for (; i < CX2341X_MBOX_MAX_DATA; i++)
771 mc417_memory_write(dev, dev->cx23417_mailbox + 4 + i, 0);
772
773 flag |= 3; /* tell 'em we're done writing */
774 mc417_memory_write(dev, dev->cx23417_mailbox, flag);
775
776 /* wait for firmware to handle the API command */
777 timeout = jiffies + msecs_to_jiffies(10);
778 for (;;) {
779 mc417_memory_read(dev, dev->cx23417_mailbox, &flag);
780 if (0 != (flag & 4))
781 break;
782 if (time_after(jiffies, timeout)) {
783 printk(KERN_ERR "ERROR: API Mailbox timeout\n");
784 return -1;
785 }
786 udelay(10);
787 }
788
789 /* read output values */
790 for (i = 0; i < out; i++) {
791 mc417_memory_read(dev, dev->cx23417_mailbox + 4 + i, data + i);
792 dprintk(3, "API Output %d = %d\n", i, data[i]);
793 }
794
795 mc417_memory_read(dev, dev->cx23417_mailbox + 2, &retval);
796 dprintk(3, "API result = %d\n", retval);
797
798 flag = 0;
799 mc417_memory_write(dev, dev->cx23417_mailbox, flag);
800
801 return retval;
802}
803
804/* We don't need to call the API often, so using just one
805 * mailbox will probably suffice
806 */
807static int cx23885_api_cmd(struct cx23885_dev *dev,
808 u32 command,
809 u32 inputcnt,
810 u32 outputcnt,
811 ...)
812{
813 u32 data[CX2341X_MBOX_MAX_DATA];
814 va_list vargs;
815 int i, err;
816
817 dprintk(3, "%s() cmds = 0x%08x\n", __func__, command);
818
819 va_start(vargs, outputcnt);
820 for (i = 0; i < inputcnt; i++)
821 data[i] = va_arg(vargs, int);
822
823 err = cx23885_mbox_func(dev, command, inputcnt, outputcnt, data);
824 for (i = 0; i < outputcnt; i++) {
825 int *vptr = va_arg(vargs, int *);
826 *vptr = data[i];
827 }
828 va_end(vargs);
829
830 return err;
831}
832
833static int cx23885_find_mailbox(struct cx23885_dev *dev)
834{
835 u32 signature[4] = {
836 0x12345678, 0x34567812, 0x56781234, 0x78123456
837 };
838 int signaturecnt = 0;
839 u32 value;
840 int i;
841
842 dprintk(2, "%s()\n", __func__);
843
844 for (i = 0; i < CX23885_FIRM_IMAGE_SIZE; i++) {
845 mc417_memory_read(dev, i, &value);
846 if (value == signature[signaturecnt])
847 signaturecnt++;
848 else
849 signaturecnt = 0;
850 if (4 == signaturecnt) {
851 dprintk(1, "Mailbox signature found at 0x%x\n", i+1);
852 return i+1;
853 }
854 }
855 printk(KERN_ERR "Mailbox signature values not found!\n");
856 return -1;
857}
858
859static int cx23885_load_firmware(struct cx23885_dev *dev)
860{
861 static const unsigned char magic[8] = {
862 0xa7, 0x0d, 0x00, 0x00, 0x66, 0xbb, 0x55, 0xaa
863 };
864 const struct firmware *firmware;
865 int i, retval = 0;
866 u32 value = 0;
867 u32 gpio_output = 0;
868 u32 checksum = 0;
869 u32 *dataptr;
870
871 dprintk(2, "%s()\n", __func__);
872
873 /* Save GPIO settings before reset of APU */
874 retval |= mc417_memory_read(dev, 0x9020, &gpio_output);
875 retval |= mc417_memory_read(dev, 0x900C, &value);
876
877 retval = mc417_register_write(dev,
878 IVTV_REG_VPU, 0xFFFFFFED);
879 retval |= mc417_register_write(dev,
880 IVTV_REG_HW_BLOCKS, IVTV_CMD_HW_BLOCKS_RST);
881 retval |= mc417_register_write(dev,
882 IVTV_REG_ENC_SDRAM_REFRESH, 0x80000800);
883 retval |= mc417_register_write(dev,
884 IVTV_REG_ENC_SDRAM_PRECHARGE, 0x1A);
885 retval |= mc417_register_write(dev,
886 IVTV_REG_APU, 0);
887
888 if (retval != 0) {
889 printk(KERN_ERR "%s: Error with mc417_register_write\n",
890 __func__);
891 return -1;
892 }
893
894 retval = request_firmware(&firmware, CX23885_FIRM_IMAGE_NAME,
895 &dev->pci->dev);
896
897 if (retval != 0) {
898 printk(KERN_ERR
899 "ERROR: Hotplug firmware request failed (%s).\n",
900 CX2341X_FIRM_ENC_FILENAME);
901 printk(KERN_ERR "Please fix your hotplug setup, the board will "
902 "not work without firmware loaded!\n");
903 return -1;
904 }
905
906 if (firmware->size != CX23885_FIRM_IMAGE_SIZE) {
907 printk(KERN_ERR "ERROR: Firmware size mismatch "
908 "(have %zd, expected %d)\n",
909 firmware->size, CX23885_FIRM_IMAGE_SIZE);
910 release_firmware(firmware);
911 return -1;
912 }
913
914 if (0 != memcmp(firmware->data, magic, 8)) {
915 printk(KERN_ERR
916 "ERROR: Firmware magic mismatch, wrong file?\n");
917 release_firmware(firmware);
918 return -1;
919 }
920
921 /* transfer to the chip */
922 dprintk(2, "Loading firmware ...\n");
923 dataptr = (u32 *)firmware->data;
924 for (i = 0; i < (firmware->size >> 2); i++) {
925 value = *dataptr;
926 checksum += ~value;
927 if (mc417_memory_write(dev, i, value) != 0) {
928 printk(KERN_ERR "ERROR: Loading firmware failed!\n");
929 release_firmware(firmware);
930 return -1;
931 }
932 dataptr++;
933 }
934
935 /* read back to verify with the checksum */
936 dprintk(1, "Verifying firmware ...\n");
937 for (i--; i >= 0; i--) {
938 if (mc417_memory_read(dev, i, &value) != 0) {
939 printk(KERN_ERR "ERROR: Reading firmware failed!\n");
940 release_firmware(firmware);
941 return -1;
942 }
943 checksum -= ~value;
944 }
945 if (checksum) {
946 printk(KERN_ERR
947 "ERROR: Firmware load failed (checksum mismatch).\n");
948 release_firmware(firmware);
949 return -1;
950 }
951 release_firmware(firmware);
952 dprintk(1, "Firmware upload successful.\n");
953
954 retval |= mc417_register_write(dev, IVTV_REG_HW_BLOCKS,
955 IVTV_CMD_HW_BLOCKS_RST);
956
957 /* Restore GPIO settings, make sure EIO14 is enabled as an output. */
958 dprintk(2, "%s: GPIO output EIO 0-15 was = 0x%x\n",
959 __func__, gpio_output);
960 /* Power-up seems to have GPIOs AFU. This was causing digital side
961 * to fail at power-up. Seems GPIOs should be set to 0x10ff0411 at
962 * power-up.
963 * gpio_output |= (1<<14);
964 */
965 /* Note: GPIO14 is specific to the HVR1800 here */
966 gpio_output = 0x10ff0411 | (1<<14);
967 retval |= mc417_register_write(dev, 0x9020, gpio_output | (1<<14));
968 dprintk(2, "%s: GPIO output EIO 0-15 now = 0x%x\n",
969 __func__, gpio_output);
970
971 dprintk(1, "%s: GPIO value EIO 0-15 was = 0x%x\n",
972 __func__, value);
973 value |= (1<<14);
974 dprintk(1, "%s: GPIO value EIO 0-15 now = 0x%x\n",
975 __func__, value);
976 retval |= mc417_register_write(dev, 0x900C, value);
977
978 retval |= mc417_register_read(dev, IVTV_REG_VPU, &value);
979 retval |= mc417_register_write(dev, IVTV_REG_VPU, value & 0xFFFFFFE8);
980
981 if (retval < 0)
982 printk(KERN_ERR "%s: Error with mc417_register_write\n",
983 __func__);
984 return 0;
985}
986
987void cx23885_417_check_encoder(struct cx23885_dev *dev)
988{
989 u32 status, seq;
990
991 status = seq = 0;
992 cx23885_api_cmd(dev, CX2341X_ENC_GET_SEQ_END, 0, 2, &status, &seq);
993 dprintk(1, "%s() status = %d, seq = %d\n", __func__, status, seq);
994}
995
996static void cx23885_codec_settings(struct cx23885_dev *dev)
997{
998 dprintk(1, "%s()\n", __func__);
999
1000 /* assign frame size */
1001 cx23885_api_cmd(dev, CX2341X_ENC_SET_FRAME_SIZE, 2, 0,
1002 dev->ts1.height, dev->ts1.width);
1003
1004 dev->mpeg_params.width = dev->ts1.width;
1005 dev->mpeg_params.height = dev->ts1.height;
1006 dev->mpeg_params.is_50hz =
1007 (dev->encodernorm.id & V4L2_STD_625_50) != 0;
1008
1009 cx2341x_update(dev, cx23885_mbox_func, NULL, &dev->mpeg_params);
1010
1011 cx23885_api_cmd(dev, CX2341X_ENC_MISC, 2, 0, 3, 1);
1012 cx23885_api_cmd(dev, CX2341X_ENC_MISC, 2, 0, 4, 1);
1013}
1014
1015static int cx23885_initialize_codec(struct cx23885_dev *dev)
1016{
1017 int version;
1018 int retval;
1019 u32 i, data[7];
1020
1021 dprintk(1, "%s()\n", __func__);
1022
1023 retval = cx23885_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0); /* ping */
1024 if (retval < 0) {
1025 dprintk(2, "%s() PING OK\n", __func__);
1026 retval = cx23885_load_firmware(dev);
1027 if (retval < 0) {
1028 printk(KERN_ERR "%s() f/w load failed\n", __func__);
1029 return retval;
1030 }
1031 dev->cx23417_mailbox = cx23885_find_mailbox(dev);
1032 if (dev->cx23417_mailbox < 0) {
1033 printk(KERN_ERR "%s() mailbox < 0, error\n",
1034 __func__);
1035 return -1;
1036 }
1037 retval = cx23885_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0);
1038 if (retval < 0) {
1039 printk(KERN_ERR
1040 "ERROR: cx23417 firmware ping failed!\n");
1041 return -1;
1042 }
1043 retval = cx23885_api_cmd(dev, CX2341X_ENC_GET_VERSION, 0, 1,
1044 &version);
1045 if (retval < 0) {
1046 printk(KERN_ERR "ERROR: cx23417 firmware get encoder :"
1047 "version failed!\n");
1048 return -1;
1049 }
1050 dprintk(1, "cx23417 firmware version is 0x%08x\n", version);
1051 msleep(200);
1052 }
1053
1054 cx23885_codec_settings(dev);
1055 msleep(60);
1056
1057 cx23885_api_cmd(dev, CX2341X_ENC_SET_NUM_VSYNC_LINES, 2, 0,
1058 CX23885_FIELD1_SAA7115, CX23885_FIELD2_SAA7115);
1059 cx23885_api_cmd(dev, CX2341X_ENC_SET_PLACEHOLDER, 12, 0,
1060 CX23885_CUSTOM_EXTENSION_USR_DATA, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1061 0, 0);
1062
1063 /* Setup to capture VBI */
1064 data[0] = 0x0001BD00;
1065 data[1] = 1; /* frames per interrupt */
1066 data[2] = 4; /* total bufs */
1067 data[3] = 0x91559155; /* start codes */
1068 data[4] = 0x206080C0; /* stop codes */
1069 data[5] = 6; /* lines */
1070 data[6] = 64; /* BPL */
1071
1072 cx23885_api_cmd(dev, CX2341X_ENC_SET_VBI_CONFIG, 7, 0, data[0], data[1],
1073 data[2], data[3], data[4], data[5], data[6]);
1074
1075 for (i = 2; i <= 24; i++) {
1076 int valid;
1077
1078 valid = ((i >= 19) && (i <= 21));
1079 cx23885_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0, i,
1080 valid, 0 , 0, 0);
1081 cx23885_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0,
1082 i | 0x80000000, valid, 0, 0, 0);
1083 }
1084
1085 cx23885_api_cmd(dev, CX2341X_ENC_MUTE_AUDIO, 1, 0, CX23885_UNMUTE);
1086 msleep(60);
1087
1088 /* initialize the video input */
1089 cx23885_api_cmd(dev, CX2341X_ENC_INITIALIZE_INPUT, 0, 0);
1090 msleep(60);
1091
1092 /* Enable VIP style pixel invalidation so we work with scaled mode */
1093 mc417_memory_write(dev, 2120, 0x00000080);
1094
1095 /* start capturing to the host interface */
1096 cx23885_api_cmd(dev, CX2341X_ENC_START_CAPTURE, 2, 0,
1097 CX23885_MPEG_CAPTURE, CX23885_RAW_BITS_NONE);
1098 msleep(10);
1099
1100 return 0;
1101}
1102
1103/* ------------------------------------------------------------------ */
1104
1105static int bb_buf_setup(struct videobuf_queue *q,
1106 unsigned int *count, unsigned int *size)
1107{
1108 struct cx23885_fh *fh = q->priv_data;
1109
1110 fh->dev->ts1.ts_packet_size = mpeglinesize;
1111 fh->dev->ts1.ts_packet_count = mpeglines;
1112
1113 *size = fh->dev->ts1.ts_packet_size * fh->dev->ts1.ts_packet_count;
1114 *count = mpegbufs;
1115
1116 return 0;
1117}
1118
1119static int bb_buf_prepare(struct videobuf_queue *q,
1120 struct videobuf_buffer *vb, enum v4l2_field field)
1121{
1122 struct cx23885_fh *fh = q->priv_data;
1123 return cx23885_buf_prepare(q, &fh->dev->ts1,
1124 (struct cx23885_buffer *)vb,
1125 field);
1126}
1127
1128static void bb_buf_queue(struct videobuf_queue *q,
1129 struct videobuf_buffer *vb)
1130{
1131 struct cx23885_fh *fh = q->priv_data;
1132 cx23885_buf_queue(&fh->dev->ts1, (struct cx23885_buffer *)vb);
1133}
1134
1135static void bb_buf_release(struct videobuf_queue *q,
1136 struct videobuf_buffer *vb)
1137{
1138 cx23885_free_buffer(q, (struct cx23885_buffer *)vb);
1139}
1140
1141static struct videobuf_queue_ops cx23885_qops = {
1142 .buf_setup = bb_buf_setup,
1143 .buf_prepare = bb_buf_prepare,
1144 .buf_queue = bb_buf_queue,
1145 .buf_release = bb_buf_release,
1146};
1147
1148/* ------------------------------------------------------------------ */
1149
1150static const u32 *ctrl_classes[] = {
1151 cx2341x_mpeg_ctrls,
1152 NULL
1153};
1154
1155static int cx23885_queryctrl(struct cx23885_dev *dev,
1156 struct v4l2_queryctrl *qctrl)
1157{
1158 qctrl->id = v4l2_ctrl_next(ctrl_classes, qctrl->id);
1159 if (qctrl->id == 0)
1160 return -EINVAL;
1161
1162 /* MPEG V4L2 controls */
1163 if (cx2341x_ctrl_query(&dev->mpeg_params, qctrl))
1164 qctrl->flags |= V4L2_CTRL_FLAG_DISABLED;
1165
1166 return 0;
1167}
1168
1169static int cx23885_querymenu(struct cx23885_dev *dev,
1170 struct v4l2_querymenu *qmenu)
1171{
1172 struct v4l2_queryctrl qctrl;
1173
1174 qctrl.id = qmenu->id;
1175 cx23885_queryctrl(dev, &qctrl);
1176 return v4l2_ctrl_query_menu(qmenu, &qctrl,
e0e31cdb 1177 cx2341x_ctrl_get_menu(&dev->mpeg_params, qmenu->id));
b1b81f1d
ST		 1178}
1179
305519c9 1180static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id *id)
b1b81f1d 1181{
305519c9
DSL		 1182 struct cx23885_fh *fh = file->private_data;
1183 struct cx23885_dev *dev = fh->dev;
1184 unsigned int i;
b1b81f1d 1185
305519c9
DSL		 1186 for (i = 0; i < ARRAY_SIZE(cx23885_tvnorms); i++)
1187 if (*id & cx23885_tvnorms[i].id)
1188 break;
1189 if (i == ARRAY_SIZE(cx23885_tvnorms))
1190 return -EINVAL;
1191 dev->encodernorm = cx23885_tvnorms[i];
1192 return 0;
1193}
b1b81f1d 1194
305519c9
DSL		 1195static int vidioc_enum_input(struct file *file, void *priv,
1196 struct v4l2_input *i)
1197{
1198 struct cx23885_fh *fh = file->private_data;
1199 struct cx23885_dev *dev = fh->dev;
1200 struct cx23885_input *input;
1201 unsigned int n;
b1b81f1d 1202
305519c9 1203 n = i->index;
b1b81f1d 1204
305519c9
DSL		 1205 if (n >= 4)
1206 return -EINVAL;
b1b81f1d 1207
305519c9 1208 input = &cx23885_boards[dev->board].input[n];
b1b81f1d 1209
305519c9
DSL		 1210 if (input->type == 0)
1211 return -EINVAL;
b1b81f1d 1212
305519c9
DSL		 1213 memset(i, 0, sizeof(*i));
1214 i->index = n;
b1b81f1d 1215
305519c9
DSL		 1216 /* FIXME
1217 * strcpy(i->name, input->name); */
1218 strcpy(i->name, "unset");
b1b81f1d 1219
305519c9
DSL		 1220 if (input->type == CX23885_VMUX_TELEVISION ||
1221 input->type == CX23885_VMUX_CABLE)
1222 i->type = V4L2_INPUT_TYPE_TUNER;
1223 else
1224 i->type = V4L2_INPUT_TYPE_CAMERA;
b1b81f1d 1225
305519c9
DSL		 1226 for (n = 0; n < ARRAY_SIZE(cx23885_tvnorms); n++)
1227 i->std |= cx23885_tvnorms[n].id;
1228 return 0;
1229}
b1b81f1d 1230
305519c9
DSL		 1231static int vidioc_g_input(struct file *file, void *priv, unsigned int *i)
1232{
1233 struct cx23885_fh *fh = file->private_data;
1234 struct cx23885_dev *dev = fh->dev;
b1b81f1d 1235
305519c9
DSL		 1236 *i = dev->input;
1237 return 0;
1238}
b1b81f1d 1239
305519c9
DSL		 1240static int vidioc_s_input(struct file *file, void *priv, unsigned int i)
1241{
1242 if (i >= 4)
1243 return -EINVAL;
b1b81f1d 1244
305519c9
DSL		 1245 return 0;
1246}
b1b81f1d 1247
305519c9
DSL		 1248static int vidioc_g_tuner(struct file *file, void *priv,
1249 struct v4l2_tuner *t)
1250{
1251 struct cx23885_fh *fh = file->private_data;
1252 struct cx23885_dev *dev = fh->dev;
b1b81f1d 1253
305519c9
DSL		 1254 if (UNSET == dev->tuner_type)
1255 return -EINVAL;
1256 if (0 != t->index)
1257 return -EINVAL;
1258 memset(t, 0, sizeof(*t));
1259 strcpy(t->name, "Television");
1260 cx23885_call_i2c_clients(&dev->i2c_bus[2], VIDIOC_G_TUNER, t);
1261 cx23885_call_i2c_clients(&dev->i2c_bus[1], VIDIOC_G_TUNER, t);
b1b81f1d 1262
305519c9 1263 dprintk(1, "VIDIOC_G_TUNER: tuner type %d\n", t->type);
b1b81f1d 1264
305519c9
DSL		 1265 return 0;
1266}
b1b81f1d 1267
305519c9
DSL		 1268static int vidioc_s_tuner(struct file *file, void *priv,
1269 struct v4l2_tuner *t)
1270{
1271 struct cx23885_fh *fh = file->private_data;
1272 struct cx23885_dev *dev = fh->dev;
1273
1274 if (UNSET == dev->tuner_type)
1275 return -EINVAL;
1276
1277 /* Update the A/V core */
1278 cx23885_call_i2c_clients(&dev->i2c_bus[2], VIDIOC_S_TUNER, t);
1279
1280 return 0;
1281}
1282
1283static int vidioc_g_frequency(struct file *file, void *priv,
1284 struct v4l2_frequency *f)
1285{
1286 struct cx23885_fh *fh = file->private_data;
1287 struct cx23885_dev *dev = fh->dev;
1288
1289 memset(f, 0, sizeof(*f));
1290 if (UNSET == dev->tuner_type)
1291 return -EINVAL;
1292 f->type = V4L2_TUNER_ANALOG_TV;
1293 f->frequency = dev->freq;
1294
1295 /* Assumption that tuner is always on bus 1 */
1296 cx23885_call_i2c_clients(&dev->i2c_bus[1], VIDIOC_G_FREQUENCY, f);
1297
1298 return 0;
1299}
1300
1301static int vidioc_s_frequency(struct file *file, void *priv,
1302 struct v4l2_frequency *f)
1303{
1304 struct cx23885_fh *fh = file->private_data;
1305 struct cx23885_dev *dev = fh->dev;
1306
1307 cx23885_api_cmd(fh->dev, CX2341X_ENC_STOP_CAPTURE, 3, 0,
1308 CX23885_END_NOW, CX23885_MPEG_CAPTURE,
1309 CX23885_RAW_BITS_NONE);
1310
1311 dprintk(1, "VIDIOC_S_FREQUENCY: dev type %d, f\n",
1312 dev->tuner_type);
1313 dprintk(1, "VIDIOC_S_FREQUENCY: f tuner %d, f type %d\n",
1314 f->tuner, f->type);
1315 if (UNSET == dev->tuner_type)
1316 return -EINVAL;
1317 if (f->tuner != 0)
1318 return -EINVAL;
1319 if (f->type != V4L2_TUNER_ANALOG_TV)
1320 return -EINVAL;
1321 dev->freq = f->frequency;
1322
1323 /* Assumption that tuner is always on bus 1 */
1324 cx23885_call_i2c_clients(&dev->i2c_bus[1], VIDIOC_S_FREQUENCY, f);
1325
1326 cx23885_initialize_codec(dev);
b1b81f1d
ST		 1327
1328 return 0;
1329}
1330
305519c9
DSL		 1331static int vidioc_s_ctrl(struct file *file, void *priv,
1332 struct v4l2_control *ctl)
1333{
1334 struct cx23885_fh *fh = file->private_data;
1335 struct cx23885_dev *dev = fh->dev;
1336
1337 /* Update the A/V core */
1338 cx23885_call_i2c_clients(&dev->i2c_bus[2], VIDIOC_S_CTRL, ctl);
1339 return 0;
1340}
1341
1342static int vidioc_querycap(struct file *file, void *priv,
1343 struct v4l2_capability *cap)
b1b81f1d
ST		 1344{
1345 struct cx23885_fh *fh = file->private_data;
1346 struct cx23885_dev *dev = fh->dev;
1347 struct cx23885_tsport *tsport = &dev->ts1;
1348
305519c9
DSL		 1349 memset(cap, 0, sizeof(*cap));
1350 strcpy(cap->driver, dev->name);
1351 strlcpy(cap->card, cx23885_boards[tsport->dev->board].name,
1352 sizeof(cap->card));
1353 sprintf(cap->bus_info, "PCI:%s", pci_name(dev->pci));
1354 cap->version = CX23885_VERSION_CODE;
1355 cap->capabilities =
1356 V4L2_CAP_VIDEO_CAPTURE |
1357 V4L2_CAP_READWRITE |
1358 V4L2_CAP_STREAMING |
1359 0;
1360 if (UNSET != dev->tuner_type)
1361 cap->capabilities |= V4L2_CAP_TUNER;
b1b81f1d 1362
305519c9
DSL		 1363 return 0;
1364}
b1b81f1d 1365
305519c9
DSL		 1366static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv,
1367 struct v4l2_fmtdesc *f)
1368{
1369 int index;
b1b81f1d 1370
305519c9
DSL		 1371 index = f->index;
1372 if (index != 0)
1373 return -EINVAL;
b1b81f1d 1374
305519c9
DSL		 1375 memset(f, 0, sizeof(*f));
1376 f->index = index;
1377 strlcpy(f->description, "MPEG", sizeof(f->description));
1378 f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1379 f->pixelformat = V4L2_PIX_FMT_MPEG;
b1b81f1d 1380
305519c9
DSL		 1381 return 0;
1382}
b1b81f1d 1383
305519c9
DSL		 1384static int vidioc_g_fmt_vid_cap(struct file *file, void *priv,
1385 struct v4l2_format *f)
1386{
1387 struct cx23885_fh *fh = file->private_data;
1388 struct cx23885_dev *dev = fh->dev;
b1b81f1d 1389
305519c9
DSL		 1390 memset(f, 0, sizeof(*f));
1391 f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1392 f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG;
1393 f->fmt.pix.bytesperline = 0;
1394 f->fmt.pix.sizeimage =
1395 dev->ts1.ts_packet_size * dev->ts1.ts_packet_count;
1396 f->fmt.pix.colorspace = 0;
1397 f->fmt.pix.width = dev->ts1.width;
1398 f->fmt.pix.height = dev->ts1.height;
1399 f->fmt.pix.field = fh->mpegq.field;
1400 dprintk(1, "VIDIOC_G_FMT: w: %d, h: %d, f: %d\n",
1401 dev->ts1.width, dev->ts1.height, fh->mpegq.field);
1402 return 0;
1403}
b1b81f1d 1404
305519c9
DSL		 1405static int vidioc_try_fmt_vid_cap(struct file *file, void *priv,
1406 struct v4l2_format *f)
1407{
1408 struct cx23885_fh *fh = file->private_data;
1409 struct cx23885_dev *dev = fh->dev;
b1b81f1d 1410
305519c9
DSL		 1411 f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1412 f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG;
1413 f->fmt.pix.bytesperline = 0;
1414 f->fmt.pix.sizeimage =
1415 dev->ts1.ts_packet_size * dev->ts1.ts_packet_count;
1416 f->fmt.pix.sizeimage =
1417 f->fmt.pix.colorspace = 0;
1418 dprintk(1, "VIDIOC_TRY_FMT: w: %d, h: %d, f: %d\n",
1419 dev->ts1.width, dev->ts1.height, fh->mpegq.field);
1420 return 0;
1421}
b1b81f1d 1422
305519c9
DSL		 1423static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
1424 struct v4l2_format *f)
1425{
1426 struct cx23885_fh *fh = file->private_data;
1427 struct cx23885_dev *dev = fh->dev;
b1b81f1d 1428
305519c9
DSL		 1429 f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1430 f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG;
1431 f->fmt.pix.bytesperline = 0;
1432 f->fmt.pix.sizeimage =
1433 dev->ts1.ts_packet_size * dev->ts1.ts_packet_count;
1434 f->fmt.pix.colorspace = 0;
1435 dprintk(1, "VIDIOC_S_FMT: w: %d, h: %d, f: %d\n",
1436 f->fmt.pix.width, f->fmt.pix.height, f->fmt.pix.field);
1437 return 0;
1438}
b1b81f1d 1439
305519c9
DSL		 1440static int vidioc_reqbufs(struct file *file, void *priv,
1441 struct v4l2_requestbuffers *p)
1442{
1443 struct cx23885_fh *fh = file->private_data;
b1b81f1d 1444
305519c9
DSL		 1445 return videobuf_reqbufs(&fh->mpegq, p);
1446}
1447
1448static int vidioc_querybuf(struct file *file, void *priv,
1449 struct v4l2_buffer *p)
1450{
1451 struct cx23885_fh *fh = file->private_data;
1452
1453 return videobuf_querybuf(&fh->mpegq, p);
1454}
1455
1456static int vidioc_qbuf(struct file *file, void *priv,
1457 struct v4l2_buffer *p)
1458{
1459 struct cx23885_fh *fh = file->private_data;
1460
1461 return videobuf_qbuf(&fh->mpegq, p);
1462}
1463
1464static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *b)
1465{
1466 struct cx23885_fh *fh = priv;
1467
1468 return videobuf_dqbuf(&fh->mpegq, b, file->f_flags & O_NONBLOCK);
1469}
1470
1471
1472static int vidioc_streamon(struct file *file, void *priv,
1473 enum v4l2_buf_type i)
1474{
1475 struct cx23885_fh *fh = file->private_data;
1476
1477 return videobuf_streamon(&fh->mpegq);
1478}
1479
1480static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i)
1481{
1482 struct cx23885_fh *fh = file->private_data;
1483
1484 return videobuf_streamoff(&fh->mpegq);
1485}
1486
1487static int vidioc_g_ext_ctrls(struct file *file, void *priv,
1488 struct v4l2_ext_controls *f)
1489{
1490 struct cx23885_fh *fh = priv;
1491 struct cx23885_dev *dev = fh->dev;
1492
1493 if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG)
1494 return -EINVAL;
1495 return cx2341x_ext_ctrls(&dev->mpeg_params, 0, f, VIDIOC_G_EXT_CTRLS);
1496}
1497
1498static int vidioc_s_ext_ctrls(struct file *file, void *priv,
1499 struct v4l2_ext_controls *f)
1500{
1501 struct cx23885_fh *fh = priv;
1502 struct cx23885_dev *dev = fh->dev;
1503 struct cx2341x_mpeg_params p;
1504 int err;
1505
1506 if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG)
1507 return -EINVAL;
1508
1509 p = dev->mpeg_params;
1510 err = cx2341x_ext_ctrls(&p, 0, f, VIDIOC_S_EXT_CTRLS);
1511
1512 if (err == 0) {
1513 err = cx2341x_update(dev, cx23885_mbox_func,
1514 &dev->mpeg_params, &p);
1515 dev->mpeg_params = p;
b1b81f1d 1516 }
305519c9
DSL		 1517 return err;
1518}
1519
1520static int vidioc_try_ext_ctrls(struct file *file, void *priv,
1521 struct v4l2_ext_controls *f)
1522{
1523 struct cx23885_fh *fh = priv;
1524 struct cx23885_dev *dev = fh->dev;
1525 struct cx2341x_mpeg_params p;
1526 int err;
1527
1528 if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG)
1529 return -EINVAL;
1530
1531 p = dev->mpeg_params;
1532 err = cx2341x_ext_ctrls(&p, 0, f, VIDIOC_TRY_EXT_CTRLS);
1533 return err;
1534}
1535
1536static int vidioc_log_status(struct file *file, void *priv)
1537{
1538 struct cx23885_fh *fh = priv;
1539 struct cx23885_dev *dev = fh->dev;
1540 char name[32 + 2];
1541
1542 snprintf(name, sizeof(name), "%s/2", dev->name);
1543 printk(KERN_INFO
1544 "%s/2: ============ START LOG STATUS ============\n",
1545 dev->name);
1546 cx23885_call_i2c_clients(&dev->i2c_bus[0], VIDIOC_LOG_STATUS,
1547 NULL);
1548 cx23885_call_i2c_clients(&dev->i2c_bus[1], VIDIOC_LOG_STATUS,
1549 NULL);
1550 cx23885_call_i2c_clients(&dev->i2c_bus[2], VIDIOC_LOG_STATUS,
1551 NULL);
1552 cx2341x_log_status(&dev->mpeg_params, name);
1553 printk(KERN_INFO
1554 "%s/2: ============= END LOG STATUS =============\n",
1555 dev->name);
b1b81f1d
ST		 1556 return 0;
1557}
1558
305519c9
DSL		 1559static int vidioc_querymenu(struct file *file, void *priv,
1560 struct v4l2_querymenu *a)
1561{
1562 struct cx23885_fh *fh = priv;
1563 struct cx23885_dev *dev = fh->dev;
1564
1565 return cx23885_querymenu(dev, a);
1566}
1567
1568static int vidioc_queryctrl(struct file *file, void *priv,
1569 struct v4l2_queryctrl *c)
b1b81f1d 1570{
305519c9
DSL		 1571 struct cx23885_fh *fh = priv;
1572 struct cx23885_dev *dev = fh->dev;
1573
1574 return cx23885_queryctrl(dev, c);
b1b81f1d
ST		 1575}
1576
1577static int mpeg_open(struct inode *inode, struct file *file)
1578{
1579 int minor = iminor(inode);
1580 struct cx23885_dev *h, *dev = NULL;
1581 struct list_head *list;
1582 struct cx23885_fh *fh;
1583
1584 dprintk(2, "%s()\n", __func__);
1585
d56dc612 1586 lock_kernel();
b1b81f1d
ST		 1587 list_for_each(list, &cx23885_devlist) {
1588 h = list_entry(list, struct cx23885_dev, devlist);
1589 if (h->v4l_device->minor == minor) {
1590 dev = h;
1591 break;
1592 }
1593 }
1594
d56dc612
HV		 1595 if (dev == NULL) {
1596 unlock_kernel();
b1b81f1d 1597 return -ENODEV;
d56dc612 1598 }
b1b81f1d
ST		 1599
1600 /* allocate + initialize per filehandle data */
1601 fh = kzalloc(sizeof(*fh), GFP_KERNEL);
d56dc612
HV		 1602 if (NULL == fh) {
1603 unlock_kernel();
b1b81f1d 1604 return -ENOMEM;
d56dc612 1605 }
b1b81f1d
ST		 1606
1607 file->private_data = fh;
1608 fh->dev = dev;
1609
1610 videobuf_queue_sg_init(&fh->mpegq, &cx23885_qops,
1611 &dev->pci->dev, &dev->ts1.slock,
1612 V4L2_BUF_TYPE_VIDEO_CAPTURE,
1613 V4L2_FIELD_INTERLACED,
1614 sizeof(struct cx23885_buffer),
1615 fh);
d56dc612 1616 unlock_kernel();
b1b81f1d
ST		 1617
1618 return 0;
1619}
1620
1621static int mpeg_release(struct inode *inode, struct file *file)
1622{
1623 struct cx23885_fh *fh = file->private_data;
1624 struct cx23885_dev *dev = fh->dev;
1625
1626 dprintk(2, "%s()\n", __func__);
1627
1628 /* FIXME: Review this crap */
1629 /* Shut device down on last close */
1630 if (atomic_cmpxchg(&fh->v4l_reading, 1, 0) == 1) {
1631 if (atomic_dec_return(&dev->v4l_reader_count) == 0) {
1632 /* stop mpeg capture */
1633 cx23885_api_cmd(fh->dev, CX2341X_ENC_STOP_CAPTURE, 3, 0,
1634 CX23885_END_NOW, CX23885_MPEG_CAPTURE,
1635 CX23885_RAW_BITS_NONE);
1636
1637 msleep(500);
1638 cx23885_417_check_encoder(dev);
1639
1640 cx23885_cancel_buffers(&fh->dev->ts1);
1641 }
1642 }
1643
1644 if (fh->mpegq.streaming)
1645 videobuf_streamoff(&fh->mpegq);
1646 if (fh->mpegq.reading)
1647 videobuf_read_stop(&fh->mpegq);
1648
1649 videobuf_mmap_free(&fh->mpegq);
1650 file->private_data = NULL;
1651 kfree(fh);
1652
1653 return 0;
1654}
1655
1656static ssize_t mpeg_read(struct file *file, char __user *data,
1657 size_t count, loff_t *ppos)
1658{
1659 struct cx23885_fh *fh = file->private_data;
1660 struct cx23885_dev *dev = fh->dev;
1661
1662 dprintk(2, "%s()\n", __func__);
1663
1664 /* Deal w/ A/V decoder * and mpeg encoder sync issues. */
1665 /* Start mpeg encoder on first read. */
1666 if (atomic_cmpxchg(&fh->v4l_reading, 0, 1) == 0) {
1667 if (atomic_inc_return(&dev->v4l_reader_count) == 1) {
1668 if (cx23885_initialize_codec(dev) < 0)
1669 return -EINVAL;
1670 }
1671 }
1672
1673 return videobuf_read_stream(&fh->mpegq, data, count, ppos, 0,
1674 file->f_flags & O_NONBLOCK);
1675}
1676
1677static unsigned int mpeg_poll(struct file *file,
1678 struct poll_table_struct *wait)
1679{
1680 struct cx23885_fh *fh = file->private_data;
1681 struct cx23885_dev *dev = fh->dev;
1682
1683 dprintk(2, "%s\n", __func__);
1684
1685 return videobuf_poll_stream(file, &fh->mpegq, wait);
1686}
1687
1688static int mpeg_mmap(struct file *file, struct vm_area_struct *vma)
1689{
1690 struct cx23885_fh *fh = file->private_data;
1691 struct cx23885_dev *dev = fh->dev;
1692
1693 dprintk(2, "%s()\n", __func__);
1694
1695 return videobuf_mmap_mapper(&fh->mpegq, vma);
1696}
1697
1698static struct file_operations mpeg_fops = {
1699 .owner = THIS_MODULE,
1700 .open = mpeg_open,
1701 .release = mpeg_release,
1702 .read = mpeg_read,
1703 .poll = mpeg_poll,
1704 .mmap = mpeg_mmap,
305519c9 1705 .ioctl = video_ioctl2,
b1b81f1d
ST		 1706 .llseek = no_llseek,
1707};
1708
a399810c 1709static const struct v4l2_ioctl_ops mpeg_ioctl_ops = {
305519c9
DSL		 1710 .vidioc_s_std = vidioc_s_std,
1711 .vidioc_enum_input = vidioc_enum_input,
1712 .vidioc_g_input = vidioc_g_input,
1713 .vidioc_s_input = vidioc_s_input,
1714 .vidioc_g_tuner = vidioc_g_tuner,
1715 .vidioc_s_tuner = vidioc_s_tuner,
1716 .vidioc_g_frequency = vidioc_g_frequency,
1717 .vidioc_s_frequency = vidioc_s_frequency,
1718 .vidioc_s_ctrl = vidioc_s_ctrl,
1719 .vidioc_querycap = vidioc_querycap,
1720 .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
1721 .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap,
1722 .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
1723 .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
1724 .vidioc_reqbufs = vidioc_reqbufs,
1725 .vidioc_querybuf = vidioc_querybuf,
1726 .vidioc_qbuf = vidioc_qbuf,
1727 .vidioc_dqbuf = vidioc_dqbuf,
1728 .vidioc_streamon = vidioc_streamon,
1729 .vidioc_streamoff = vidioc_streamoff,
1730 .vidioc_g_ext_ctrls = vidioc_g_ext_ctrls,
1731 .vidioc_s_ext_ctrls = vidioc_s_ext_ctrls,
1732 .vidioc_try_ext_ctrls = vidioc_try_ext_ctrls,
1733 .vidioc_log_status = vidioc_log_status,
1734 .vidioc_querymenu = vidioc_querymenu,
1735 .vidioc_queryctrl = vidioc_queryctrl,
b1b81f1d
ST		 1736};
1737
a399810c
HV		 1738static struct video_device cx23885_mpeg_template = {
1739 .name = "cx23885",
a399810c
HV		 1740 .fops = &mpeg_fops,
1741 .ioctl_ops = &mpeg_ioctl_ops,
1742 .minor = -1,
1743};
1744
b1b81f1d
ST		 1745void cx23885_417_unregister(struct cx23885_dev *dev)
1746{
1747 dprintk(1, "%s()\n", __func__);
1748
1749 if (dev->v4l_device) {
1750 if (-1 != dev->v4l_device->minor)
1751 video_unregister_device(dev->v4l_device);
1752 else
1753 video_device_release(dev->v4l_device);
1754 dev->v4l_device = NULL;
1755 }
1756}
1757
1758static struct video_device *cx23885_video_dev_alloc(
1759 struct cx23885_tsport *tsport,
1760 struct pci_dev *pci,
1761 struct video_device *template,
1762 char *type)
1763{
1764 struct video_device *vfd;
1765 struct cx23885_dev *dev = tsport->dev;
1766
1767 dprintk(1, "%s()\n", __func__);
1768
1769 vfd = video_device_alloc();
1770 if (NULL == vfd)
1771 return NULL;
1772 *vfd = *template;
1773 vfd->minor = -1;
1774 snprintf(vfd->name, sizeof(vfd->name), "%s %s (%s)", dev->name,
1775 type, cx23885_boards[tsport->dev->board].name);
5e85e732 1776 vfd->parent = &pci->dev;
b1b81f1d
ST		 1777 vfd->release = video_device_release;
1778 return vfd;
1779}
1780
1781int cx23885_417_register(struct cx23885_dev *dev)
1782{
1783 /* FIXME: Port1 hardcoded here */
1784 int err = -ENODEV;
1785 struct cx23885_tsport *tsport = &dev->ts1;
1786
1787 dprintk(1, "%s()\n", __func__);
1788
1789 if (cx23885_boards[dev->board].portb != CX23885_MPEG_ENCODER)
1790 return err;
1791
1792 /* Set default TV standard */
1793 dev->encodernorm = cx23885_tvnorms[0];
1794
1795 if (dev->encodernorm.id & V4L2_STD_525_60)
1796 tsport->height = 480;
1797 else
1798 tsport->height = 576;
1799
1800 tsport->width = 720;
1801 cx2341x_fill_defaults(&dev->mpeg_params);
1802
1803 dev->mpeg_params.port = CX2341X_PORT_SERIAL;
1804
1805 /* Allocate and initialize V4L video device */
1806 dev->v4l_device = cx23885_video_dev_alloc(tsport,
1807 dev->pci, &cx23885_mpeg_template, "mpeg");
1808 err = video_register_device(dev->v4l_device,
1809 VFL_TYPE_GRABBER, -1);
1810 if (err < 0) {
1811 printk(KERN_INFO "%s: can't register mpeg device\n", dev->name);
1812 return err;
1813 }
1814
1815 /* Initialize MC417 registers */
1816 cx23885_mc417_init(dev);
1817
1818 printk(KERN_INFO "%s: registered device video%d [mpeg]\n",
1819 dev->name, dev->v4l_device->minor & 0x1f);
1820
1821 return 0;
1822}
kernel source for telekom puls (alcatel/mediatek)