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Merge git://git.kernel.org/pub/scm/linux/kernel/git/pkl/squashfs-linus
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / media / video / cx23885 / altera-ci.c
CommitLineData
349bcf02
IL		 1/*
2 * altera-ci.c
3 *
4 * CI driver in conjunction with NetUp Dual DVB-T/C RF CI card
5 *
6 * Copyright (C) 2010,2011 NetUP Inc.
7 * Copyright (C) 2010,2011 Igor M. Liplianin <liplianin@netup.ru>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 *
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25/*
26 * currently cx23885 GPIO's used.
27 * GPIO-0 ~INT in
28 * GPIO-1 TMS out
29 * GPIO-2 ~reset chips out
30 * GPIO-3 to GPIO-10 data/addr for CA in/out
31 * GPIO-11 ~CS out
32 * GPIO-12 AD_RG out
33 * GPIO-13 ~WR out
34 * GPIO-14 ~RD out
35 * GPIO-15 ~RDY in
36 * GPIO-16 TCK out
37 * GPIO-17 TDO in
38 * GPIO-18 TDI out
39 */
40/*
41 * Bit definitions for MC417_RWD and MC417_OEN registers
42 * bits 31-16
43 * +-----------+
44 * | Reserved |
45 * +-----------+
46 * bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
47 * +-------+-------+-------+-------+-------+-------+-------+-------+
48 * | TDI | TDO | TCK | RDY# | #RD | #WR | AD_RG | #CS |
49 * +-------+-------+-------+-------+-------+-------+-------+-------+
50 * bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
51 * +-------+-------+-------+-------+-------+-------+-------+-------+
52 * | DATA7| DATA6| DATA5| DATA4| DATA3| DATA2| DATA1| DATA0|
53 * +-------+-------+-------+-------+-------+-------+-------+-------+
54 */
55#include <linux/version.h>
56#include <media/videobuf-dma-sg.h>
57#include <media/videobuf-dvb.h>
58#include "altera-ci.h"
59#include "dvb_ca_en50221.h"
60
61/* FPGA regs */
62#define NETUP_CI_INT_CTRL 0x00
63#define NETUP_CI_BUSCTRL2 0x01
64#define NETUP_CI_ADDR0 0x04
65#define NETUP_CI_ADDR1 0x05
66#define NETUP_CI_DATA 0x06
67#define NETUP_CI_BUSCTRL 0x07
68#define NETUP_CI_PID_ADDR0 0x08
69#define NETUP_CI_PID_ADDR1 0x09
70#define NETUP_CI_PID_DATA 0x0a
71#define NETUP_CI_TSA_DIV 0x0c
72#define NETUP_CI_TSB_DIV 0x0d
73#define NETUP_CI_REVISION 0x0f
74
75/* const for ci op */
76#define NETUP_CI_FLG_CTL 1
77#define NETUP_CI_FLG_RD 1
78#define NETUP_CI_FLG_AD 1
79
80static unsigned int ci_dbg;
81module_param(ci_dbg, int, 0644);
82MODULE_PARM_DESC(ci_dbg, "Enable CI debugging");
83
84static unsigned int pid_dbg;
85module_param(pid_dbg, int, 0644);
86MODULE_PARM_DESC(pid_dbg, "Enable PID filtering debugging");
87
88MODULE_DESCRIPTION("altera FPGA CI module");
89MODULE_AUTHOR("Igor M. Liplianin <liplianin@netup.ru>");
90MODULE_LICENSE("GPL");
91
92#define ci_dbg_print(args...) \
93 do { \
94 if (ci_dbg) \
95 printk(KERN_DEBUG args); \
96 } while (0)
97
98#define pid_dbg_print(args...) \
99 do { \
100 if (pid_dbg) \
101 printk(KERN_DEBUG args); \
102 } while (0)
103
104struct altera_ci_state;
105struct netup_hw_pid_filter;
106
107struct fpga_internal {
108 void *dev;
109 struct mutex fpga_mutex;/* two CI's on the same fpga */
110 struct netup_hw_pid_filter *pid_filt[2];
111 struct altera_ci_state *state[2];
112 struct work_struct work;
113 int (*fpga_rw) (void *dev, int flag, int data, int rw);
114 int cis_used;
115 int filts_used;
116 int strt_wrk;
117};
118
119/* stores all private variables for communication with CI */
120struct altera_ci_state {
121 struct fpga_internal *internal;
122 struct dvb_ca_en50221 ca;
123 int status;
124 int nr;
125};
126
127/* stores all private variables for hardware pid filtering */
128struct netup_hw_pid_filter {
129 struct fpga_internal *internal;
130 struct dvb_demux *demux;
131 /* save old functions */
132 int (*start_feed)(struct dvb_demux_feed *feed);
133 int (*stop_feed)(struct dvb_demux_feed *feed);
134
135 int status;
136 int nr;
137};
138
139/* internal params node */
140struct fpga_inode {
141 /* pointer for internal params, one for each pair of CI's */
142 struct fpga_internal *internal;
143 struct fpga_inode *next_inode;
144};
145
146/* first internal params */
147static struct fpga_inode *fpga_first_inode;
148
149/* find chip by dev */
150static struct fpga_inode *find_inode(void *dev)
151{
152 struct fpga_inode *temp_chip = fpga_first_inode;
153
154 if (temp_chip == NULL)
155 return temp_chip;
156
157 /*
158 Search for the last fpga CI chip or
159 find it by dev */
160 while ((temp_chip != NULL) &&
161 (temp_chip->internal->dev != dev))
162 temp_chip = temp_chip->next_inode;
163
164 return temp_chip;
165}
166/* check demux */
167static struct fpga_internal *check_filter(struct fpga_internal *temp_int,
168 void *demux_dev, int filt_nr)
169{
170 if (temp_int == NULL)
171 return NULL;
172
173 if ((temp_int->pid_filt[filt_nr]) == NULL)
174 return NULL;
175
176 if (temp_int->pid_filt[filt_nr]->demux == demux_dev)
177 return temp_int;
178
179 return NULL;
180}
181
182/* find chip by demux */
183static struct fpga_inode *find_dinode(void *demux_dev)
184{
185 struct fpga_inode *temp_chip = fpga_first_inode;
186 struct fpga_internal *temp_int;
187
188 /*
189 * Search of the last fpga CI chip or
190 * find it by demux
191 */
192 while (temp_chip != NULL) {
193 if (temp_chip->internal != NULL) {
194 temp_int = temp_chip->internal;
195 if (check_filter(temp_int, demux_dev, 0))
196 break;
197 if (check_filter(temp_int, demux_dev, 1))
198 break;
199 }
200
201 temp_chip = temp_chip->next_inode;
202 }
203
204 return temp_chip;
205}
206
207/* deallocating chip */
208static void remove_inode(struct fpga_internal *internal)
209{
210 struct fpga_inode *prev_node = fpga_first_inode;
211 struct fpga_inode *del_node = find_inode(internal->dev);
212
213 if (del_node != NULL) {
214 if (del_node == fpga_first_inode) {
215 fpga_first_inode = del_node->next_inode;
216 } else {
217 while (prev_node->next_inode != del_node)
218 prev_node = prev_node->next_inode;
219
220 if (del_node->next_inode == NULL)
221 prev_node->next_inode = NULL;
222 else
223 prev_node->next_inode =
224 prev_node->next_inode->next_inode;
225 }
226
227 kfree(del_node);
228 }
229}
230
231/* allocating new chip */
232static struct fpga_inode *append_internal(struct fpga_internal *internal)
233{
234 struct fpga_inode *new_node = fpga_first_inode;
235
236 if (new_node == NULL) {
237 new_node = kmalloc(sizeof(struct fpga_inode), GFP_KERNEL);
238 fpga_first_inode = new_node;
239 } else {
240 while (new_node->next_inode != NULL)
241 new_node = new_node->next_inode;
242
243 new_node->next_inode =
244 kmalloc(sizeof(struct fpga_inode), GFP_KERNEL);
245 if (new_node->next_inode != NULL)
246 new_node = new_node->next_inode;
247 else
248 new_node = NULL;
249 }
250
251 if (new_node != NULL) {
252 new_node->internal = internal;
253 new_node->next_inode = NULL;
254 }
255
256 return new_node;
257}
258
259static int netup_fpga_op_rw(struct fpga_internal *inter, int addr,
260 u8 val, u8 read)
261{
262 inter->fpga_rw(inter->dev, NETUP_CI_FLG_AD, addr, 0);
263 return inter->fpga_rw(inter->dev, 0, val, read);
264}
265
266/* flag - mem/io, read - read/write */
267int altera_ci_op_cam(struct dvb_ca_en50221 *en50221, int slot,
268 u8 flag, u8 read, int addr, u8 val)
269{
270
271 struct altera_ci_state *state = en50221->data;
272 struct fpga_internal *inter = state->internal;
273
274 u8 store;
275 int mem = 0;
276
277 if (0 != slot)
278 return -EINVAL;
279
280 mutex_lock(&inter->fpga_mutex);
281
282 netup_fpga_op_rw(inter, NETUP_CI_ADDR0, ((addr << 1) & 0xfe), 0);
283 netup_fpga_op_rw(inter, NETUP_CI_ADDR1, ((addr >> 7) & 0x7f), 0);
284 store = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, 0, NETUP_CI_FLG_RD);
285
8af81ddb 286 store &= 0x0f;
349bcf02
IL		 287 store |= ((state->nr << 7) | (flag << 6));
288
289 netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, store, 0);
290 mem = netup_fpga_op_rw(inter, NETUP_CI_DATA, val, read);
291
292 mutex_unlock(&inter->fpga_mutex);
293
294 ci_dbg_print("%s: %s: addr=[0x%02x], %s=%x\n", __func__,
295 (read) ? "read" : "write", addr,
296 (flag == NETUP_CI_FLG_CTL) ? "ctl" : "mem",
297 (read) ? mem : val);
298
299 return mem;
300}
301
302int altera_ci_read_attribute_mem(struct dvb_ca_en50221 *en50221,
303 int slot, int addr)
304{
305 return altera_ci_op_cam(en50221, slot, 0, NETUP_CI_FLG_RD, addr, 0);
306}
307
308int altera_ci_write_attribute_mem(struct dvb_ca_en50221 *en50221,
309 int slot, int addr, u8 data)
310{
311 return altera_ci_op_cam(en50221, slot, 0, 0, addr, data);
312}
313
314int altera_ci_read_cam_ctl(struct dvb_ca_en50221 *en50221, int slot, u8 addr)
315{
316 return altera_ci_op_cam(en50221, slot, NETUP_CI_FLG_CTL,
317 NETUP_CI_FLG_RD, addr, 0);
318}
319
320int altera_ci_write_cam_ctl(struct dvb_ca_en50221 *en50221, int slot,
321 u8 addr, u8 data)
322{
323 return altera_ci_op_cam(en50221, slot, NETUP_CI_FLG_CTL, 0, addr, data);
324}
325
326int altera_ci_slot_reset(struct dvb_ca_en50221 *en50221, int slot)
327{
328 struct altera_ci_state *state = en50221->data;
329 struct fpga_internal *inter = state->internal;
330 /* reasonable timeout for CI reset is 10 seconds */
331 unsigned long t_out = jiffies + msecs_to_jiffies(9999);
332 int ret;
333
334 ci_dbg_print("%s\n", __func__);
335
336 if (0 != slot)
337 return -EINVAL;
338
339 mutex_lock(&inter->fpga_mutex);
340
341 ret = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, 0, NETUP_CI_FLG_RD);
342 netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL,
8af81ddb
AO		 343 (ret & 0xcf) | (1 << (5 - state->nr)), 0);
344
345 mutex_unlock(&inter->fpga_mutex);
349bcf02
IL		 346
347 for (;;) {
348 mdelay(50);
8af81ddb
AO		 349
350 mutex_lock(&inter->fpga_mutex);
351
349bcf02
IL		 352 ret = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL,
353 0, NETUP_CI_FLG_RD);
8af81ddb
AO		 354 mutex_unlock(&inter->fpga_mutex);
355
349bcf02
IL		 356 if ((ret & (1 << (5 - state->nr))) == 0)
357 break;
358 if (time_after(jiffies, t_out))
359 break;
360 }
361
349bcf02
IL		 362
363 ci_dbg_print("%s: %d msecs\n", __func__,
364 jiffies_to_msecs(jiffies + msecs_to_jiffies(9999) - t_out));
365
366 return 0;
367}
368
369int altera_ci_slot_shutdown(struct dvb_ca_en50221 *en50221, int slot)
370{
371 /* not implemented */
372 return 0;
373}
374
375int altera_ci_slot_ts_ctl(struct dvb_ca_en50221 *en50221, int slot)
376{
377 struct altera_ci_state *state = en50221->data;
378 struct fpga_internal *inter = state->internal;
379 int ret;
380
381 ci_dbg_print("%s\n", __func__);
382
383 if (0 != slot)
384 return -EINVAL;
385
386 mutex_lock(&inter->fpga_mutex);
387
388 ret = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, 0, NETUP_CI_FLG_RD);
389 netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL,
8af81ddb 390 (ret & 0x0f) | (1 << (3 - state->nr)), 0);
349bcf02
IL		 391
392 mutex_unlock(&inter->fpga_mutex);
393
394 return 0;
395}
396
397/* work handler */
398static void netup_read_ci_status(struct work_struct *work)
399{
400 struct fpga_internal *inter =
401 container_of(work, struct fpga_internal, work);
402 int ret;
403
404 ci_dbg_print("%s\n", __func__);
405
406 mutex_lock(&inter->fpga_mutex);
407 /* ack' irq */
408 ret = netup_fpga_op_rw(inter, NETUP_CI_INT_CTRL, 0, NETUP_CI_FLG_RD);
409 ret = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, 0, NETUP_CI_FLG_RD);
410
411 mutex_unlock(&inter->fpga_mutex);
412
413 if (inter->state[1] != NULL) {
414 inter->state[1]->status =
415 ((ret & 1) == 0 ?
416 DVB_CA_EN50221_POLL_CAM_PRESENT |
417 DVB_CA_EN50221_POLL_CAM_READY : 0);
418 ci_dbg_print("%s: setting CI[1] status = 0x%x\n",
419 __func__, inter->state[1]->status);
420 };
421
422 if (inter->state[0] != NULL) {
423 inter->state[0]->status =
424 ((ret & 2) == 0 ?
425 DVB_CA_EN50221_POLL_CAM_PRESENT |
426 DVB_CA_EN50221_POLL_CAM_READY : 0);
427 ci_dbg_print("%s: setting CI[0] status = 0x%x\n",
428 __func__, inter->state[0]->status);
429 };
430}
431
432/* CI irq handler */
433int altera_ci_irq(void *dev)
434{
435 struct fpga_inode *temp_int = NULL;
436 struct fpga_internal *inter = NULL;
437
438 ci_dbg_print("%s\n", __func__);
439
440 if (dev != NULL) {
441 temp_int = find_inode(dev);
442 if (temp_int != NULL) {
443 inter = temp_int->internal;
444 schedule_work(&inter->work);
445 }
446 }
447
448 return 1;
449}
450EXPORT_SYMBOL(altera_ci_irq);
451
452int altera_poll_ci_slot_status(struct dvb_ca_en50221 *en50221, int slot,
453 int open)
454{
455 struct altera_ci_state *state = en50221->data;
456
457 if (0 != slot)
458 return -EINVAL;
459
460 return state->status;
461}
462
463void altera_hw_filt_release(void *main_dev, int filt_nr)
464{
465 struct fpga_inode *temp_int = find_inode(main_dev);
466 struct netup_hw_pid_filter *pid_filt = NULL;
467
468 ci_dbg_print("%s\n", __func__);
469
470 if (temp_int != NULL) {
471 pid_filt = temp_int->internal->pid_filt[filt_nr - 1];
472 /* stored old feed controls */
473 pid_filt->demux->start_feed = pid_filt->start_feed;
474 pid_filt->demux->stop_feed = pid_filt->stop_feed;
475
476 if (((--(temp_int->internal->filts_used)) <= 0) &&
477 ((temp_int->internal->cis_used) <= 0)) {
478
479 ci_dbg_print("%s: Actually removing\n", __func__);
480
481 remove_inode(temp_int->internal);
482 kfree(pid_filt->internal);
483 }
484
485 kfree(pid_filt);
486
487 }
488
489}
490EXPORT_SYMBOL(altera_hw_filt_release);
491
492void altera_ci_release(void *dev, int ci_nr)
493{
494 struct fpga_inode *temp_int = find_inode(dev);
495 struct altera_ci_state *state = NULL;
496
497 ci_dbg_print("%s\n", __func__);
498
499 if (temp_int != NULL) {
500 state = temp_int->internal->state[ci_nr - 1];
501 altera_hw_filt_release(dev, ci_nr);
502
503
504 if (((temp_int->internal->filts_used) <= 0) &&
505 ((--(temp_int->internal->cis_used)) <= 0)) {
506
507 ci_dbg_print("%s: Actually removing\n", __func__);
508
509 remove_inode(temp_int->internal);
510 kfree(state->internal);
511 }
512
513 if (state != NULL) {
514 if (state->ca.data != NULL)
515 dvb_ca_en50221_release(&state->ca);
516
517 kfree(state);
518 }
519 }
520
521}
522EXPORT_SYMBOL(altera_ci_release);
523
524static void altera_pid_control(struct netup_hw_pid_filter *pid_filt,
525 u16 pid, int onoff)
526{
527 struct fpga_internal *inter = pid_filt->internal;
528 u8 store = 0;
529
2f2710bd
IL		 530 /* pid 0-0x1f always enabled, don't touch them */
531 if ((pid == 0x2000) || (pid < 0x20))
349bcf02
IL		 532 return;
533
534 mutex_lock(&inter->fpga_mutex);
535
536 netup_fpga_op_rw(inter, NETUP_CI_PID_ADDR0, (pid >> 3) & 0xff, 0);
537 netup_fpga_op_rw(inter, NETUP_CI_PID_ADDR1,
538 ((pid >> 11) & 0x03) | (pid_filt->nr << 2), 0);
539
540 store = netup_fpga_op_rw(inter, NETUP_CI_PID_DATA, 0, NETUP_CI_FLG_RD);
541
542 if (onoff)/* 0 - on, 1 - off */
543 store |= (1 << (pid & 7));
544 else
545 store &= ~(1 << (pid & 7));
546
547 netup_fpga_op_rw(inter, NETUP_CI_PID_DATA, store, 0);
548
549 mutex_unlock(&inter->fpga_mutex);
550
551 pid_dbg_print("%s: (%d) set pid: %5d 0x%04x '%s'\n", __func__,
552 pid_filt->nr, pid, pid, onoff ? "off" : "on");
553}
554
555static void altera_toggle_fullts_streaming(struct netup_hw_pid_filter *pid_filt,
556 int filt_nr, int onoff)
557{
558 struct fpga_internal *inter = pid_filt->internal;
559 u8 store = 0;
560 int i;
561
562 pid_dbg_print("%s: pid_filt->nr[%d] now %s\n", __func__, pid_filt->nr,
563 onoff ? "off" : "on");
564
565 if (onoff)/* 0 - on, 1 - off */
566 store = 0xff;/* ignore pid */
567 else
568 store = 0;/* enable pid */
569
570 mutex_lock(&inter->fpga_mutex);
571
572 for (i = 0; i < 1024; i++) {
573 netup_fpga_op_rw(inter, NETUP_CI_PID_ADDR0, i & 0xff, 0);
574
575 netup_fpga_op_rw(inter, NETUP_CI_PID_ADDR1,
576 ((i >> 8) & 0x03) | (pid_filt->nr << 2), 0);
2f2710bd
IL		 577 /* pid 0-0x1f always enabled */
578 netup_fpga_op_rw(inter, NETUP_CI_PID_DATA,
579 (i > 3 ? store : 0), 0);
349bcf02
IL		 580 }
581
582 mutex_unlock(&inter->fpga_mutex);
583}
584
585int altera_pid_feed_control(void *demux_dev, int filt_nr,
586 struct dvb_demux_feed *feed, int onoff)
587{
588 struct fpga_inode *temp_int = find_dinode(demux_dev);
589 struct fpga_internal *inter = temp_int->internal;
590 struct netup_hw_pid_filter *pid_filt = inter->pid_filt[filt_nr - 1];
591
592 altera_pid_control(pid_filt, feed->pid, onoff ? 0 : 1);
593 /* call old feed proc's */
594 if (onoff)
595 pid_filt->start_feed(feed);
596 else
597 pid_filt->stop_feed(feed);
598
599 if (feed->pid == 0x2000)
600 altera_toggle_fullts_streaming(pid_filt, filt_nr,
601 onoff ? 0 : 1);
602
603 return 0;
604}
605EXPORT_SYMBOL(altera_pid_feed_control);
606
607int altera_ci_start_feed(struct dvb_demux_feed *feed, int num)
608{
609 altera_pid_feed_control(feed->demux, num, feed, 1);
610
611 return 0;
612}
613
614int altera_ci_stop_feed(struct dvb_demux_feed *feed, int num)
615{
616 altera_pid_feed_control(feed->demux, num, feed, 0);
617
618 return 0;
619}
620
621int altera_ci_start_feed_1(struct dvb_demux_feed *feed)
622{
623 return altera_ci_start_feed(feed, 1);
624}
625
626int altera_ci_stop_feed_1(struct dvb_demux_feed *feed)
627{
628 return altera_ci_stop_feed(feed, 1);
629}
630
631int altera_ci_start_feed_2(struct dvb_demux_feed *feed)
632{
633 return altera_ci_start_feed(feed, 2);
634}
635
636int altera_ci_stop_feed_2(struct dvb_demux_feed *feed)
637{
638 return altera_ci_stop_feed(feed, 2);
639}
640
641int altera_hw_filt_init(struct altera_ci_config *config, int hw_filt_nr)
642{
643 struct netup_hw_pid_filter *pid_filt = NULL;
644 struct fpga_inode *temp_int = find_inode(config->dev);
645 struct fpga_internal *inter = NULL;
646 int ret = 0;
647
648 pid_filt = kzalloc(sizeof(struct netup_hw_pid_filter), GFP_KERNEL);
649
650 ci_dbg_print("%s\n", __func__);
651
652 if (!pid_filt) {
653 ret = -ENOMEM;
654 goto err;
655 }
656
657 if (temp_int != NULL) {
658 inter = temp_int->internal;
659 (inter->filts_used)++;
660 ci_dbg_print("%s: Find Internal Structure!\n", __func__);
661 } else {
662 inter = kzalloc(sizeof(struct fpga_internal), GFP_KERNEL);
663 if (!inter) {
664 ret = -ENOMEM;
665 goto err;
666 }
667
668 temp_int = append_internal(inter);
669 inter->filts_used = 1;
670 inter->dev = config->dev;
671 inter->fpga_rw = config->fpga_rw;
672 mutex_init(&inter->fpga_mutex);
673 inter->strt_wrk = 1;
674 ci_dbg_print("%s: Create New Internal Structure!\n", __func__);
675 }
676
3920d6b3
HV		 677 ci_dbg_print("%s: setting hw pid filter = %p for ci = %d\n", __func__,
678 pid_filt, hw_filt_nr - 1);
349bcf02
IL		 679 inter->pid_filt[hw_filt_nr - 1] = pid_filt;
680 pid_filt->demux = config->demux;
681 pid_filt->internal = inter;
682 pid_filt->nr = hw_filt_nr - 1;
683 /* store old feed controls */
684 pid_filt->start_feed = config->demux->start_feed;
685 pid_filt->stop_feed = config->demux->stop_feed;
686 /* replace with new feed controls */
687 if (hw_filt_nr == 1) {
688 pid_filt->demux->start_feed = altera_ci_start_feed_1;
689 pid_filt->demux->stop_feed = altera_ci_stop_feed_1;
690 } else if (hw_filt_nr == 2) {
691 pid_filt->demux->start_feed = altera_ci_start_feed_2;
692 pid_filt->demux->stop_feed = altera_ci_stop_feed_2;
693 }
694
695 altera_toggle_fullts_streaming(pid_filt, 0, 1);
696
697 return 0;
698err:
699 ci_dbg_print("%s: Can't init hardware filter: Error %d\n",
700 __func__, ret);
701
702 kfree(pid_filt);
703
704 return ret;
705}
706EXPORT_SYMBOL(altera_hw_filt_init);
707
708int altera_ci_init(struct altera_ci_config *config, int ci_nr)
709{
710 struct altera_ci_state *state;
711 struct fpga_inode *temp_int = find_inode(config->dev);
712 struct fpga_internal *inter = NULL;
713 int ret = 0;
714 u8 store = 0;
715
716 state = kzalloc(sizeof(struct altera_ci_state), GFP_KERNEL);
717
718 ci_dbg_print("%s\n", __func__);
719
720 if (!state) {
721 ret = -ENOMEM;
722 goto err;
723 }
724
725 if (temp_int != NULL) {
726 inter = temp_int->internal;
727 (inter->cis_used)++;
728 ci_dbg_print("%s: Find Internal Structure!\n", __func__);
729 } else {
730 inter = kzalloc(sizeof(struct fpga_internal), GFP_KERNEL);
731 if (!inter) {
732 ret = -ENOMEM;
733 goto err;
734 }
735
736 temp_int = append_internal(inter);
737 inter->cis_used = 1;
738 inter->dev = config->dev;
739 inter->fpga_rw = config->fpga_rw;
740 mutex_init(&inter->fpga_mutex);
741 inter->strt_wrk = 1;
742 ci_dbg_print("%s: Create New Internal Structure!\n", __func__);
743 }
744
3920d6b3
HV		 745 ci_dbg_print("%s: setting state = %p for ci = %d\n", __func__,
746 state, ci_nr - 1);
349bcf02
IL		 747 inter->state[ci_nr - 1] = state;
748 state->internal = inter;
749 state->nr = ci_nr - 1;
750
751 state->ca.owner = THIS_MODULE;
752 state->ca.read_attribute_mem = altera_ci_read_attribute_mem;
753 state->ca.write_attribute_mem = altera_ci_write_attribute_mem;
754 state->ca.read_cam_control = altera_ci_read_cam_ctl;
755 state->ca.write_cam_control = altera_ci_write_cam_ctl;
756 state->ca.slot_reset = altera_ci_slot_reset;
757 state->ca.slot_shutdown = altera_ci_slot_shutdown;
758 state->ca.slot_ts_enable = altera_ci_slot_ts_ctl;
759 state->ca.poll_slot_status = altera_poll_ci_slot_status;
760 state->ca.data = state;
761
762 ret = dvb_ca_en50221_init(config->adapter,
763 &state->ca,
764 /* flags */ 0,
765 /* n_slots */ 1);
766 if (0 != ret)
767 goto err;
768
769 altera_hw_filt_init(config, ci_nr);
770
771 if (inter->strt_wrk) {
772 INIT_WORK(&inter->work, netup_read_ci_status);
773 inter->strt_wrk = 0;
774 }
775
776 ci_dbg_print("%s: CI initialized!\n", __func__);
777
778 mutex_lock(&inter->fpga_mutex);
779
780 /* Enable div */
781 netup_fpga_op_rw(inter, NETUP_CI_TSA_DIV, 0x0, 0);
782 netup_fpga_op_rw(inter, NETUP_CI_TSB_DIV, 0x0, 0);
783
784 /* enable TS out */
785 store = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL2, 0, NETUP_CI_FLG_RD);
786 store |= (3 << 4);
787 netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL2, store, 0);
788
789 ret = netup_fpga_op_rw(inter, NETUP_CI_REVISION, 0, NETUP_CI_FLG_RD);
790 /* enable irq */
791 netup_fpga_op_rw(inter, NETUP_CI_INT_CTRL, 0x44, 0);
792
793 mutex_unlock(&inter->fpga_mutex);
794
795 ci_dbg_print("%s: NetUP CI Revision = 0x%x\n", __func__, ret);
796
797 schedule_work(&inter->work);
798
799 return 0;
800err:
801 ci_dbg_print("%s: Cannot initialize CI: Error %d.\n", __func__, ret);
802
803 kfree(state);
804
805 return ret;
806}
807EXPORT_SYMBOL(altera_ci_init);
808
809int altera_ci_tuner_reset(void *dev, int ci_nr)
810{
811 struct fpga_inode *temp_int = find_inode(dev);
812 struct fpga_internal *inter = NULL;
813 u8 store;
814
815 ci_dbg_print("%s\n", __func__);
816
817 if (temp_int == NULL)
818 return -1;
819
820 if (temp_int->internal == NULL)
821 return -1;
822
823 inter = temp_int->internal;
824
825 mutex_lock(&inter->fpga_mutex);
826
827 store = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL2, 0, NETUP_CI_FLG_RD);
828 store &= ~(4 << (2 - ci_nr));
829 netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL2, store, 0);
830 msleep(100);
831 store |= (4 << (2 - ci_nr));
832 netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL2, store, 0);
833
834 mutex_unlock(&inter->fpga_mutex);
835
836 return 0;
837}
838EXPORT_SYMBOL(altera_ci_tuner_reset);
kernel source for telekom puls (alcatel/mediatek)