Commit | Line | Data |
---|---|---|
1c1e45d1 HV |
1 | /* |
2 | * cx18 init/start/stop/exit stream functions | |
3 | * | |
4 | * Derived from ivtv-streams.c | |
5 | * | |
6 | * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl> | |
6afdeaf8 | 7 | * Copyright (C) 2008 Andy Walls <awalls@md.metrocast.net> |
1c1e45d1 HV |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA | |
22 | * 02111-1307 USA | |
23 | */ | |
24 | ||
25 | #include "cx18-driver.h" | |
b1526421 | 26 | #include "cx18-io.h" |
1c1e45d1 HV |
27 | #include "cx18-fileops.h" |
28 | #include "cx18-mailbox.h" | |
29 | #include "cx18-i2c.h" | |
30 | #include "cx18-queue.h" | |
31 | #include "cx18-ioctl.h" | |
32 | #include "cx18-streams.h" | |
33 | #include "cx18-cards.h" | |
34 | #include "cx18-scb.h" | |
1c1e45d1 HV |
35 | #include "cx18-dvb.h" |
36 | ||
37 | #define CX18_DSP0_INTERRUPT_MASK 0xd0004C | |
38 | ||
bec43661 | 39 | static struct v4l2_file_operations cx18_v4l2_enc_fops = { |
daf20d95 HV |
40 | .owner = THIS_MODULE, |
41 | .read = cx18_v4l2_read, | |
42 | .open = cx18_v4l2_open, | |
3b6fe58f | 43 | /* FIXME change to video_ioctl2 if serialization lock can be removed */ |
78b055be | 44 | .unlocked_ioctl = cx18_v4l2_ioctl, |
daf20d95 HV |
45 | .release = cx18_v4l2_close, |
46 | .poll = cx18_v4l2_enc_poll, | |
b7101de3 | 47 | .mmap = cx18_v4l2_mmap, |
1c1e45d1 HV |
48 | }; |
49 | ||
50 | /* offset from 0 to register ts v4l2 minors on */ | |
51 | #define CX18_V4L2_ENC_TS_OFFSET 16 | |
52 | /* offset from 0 to register pcm v4l2 minors on */ | |
53 | #define CX18_V4L2_ENC_PCM_OFFSET 24 | |
54 | /* offset from 0 to register yuv v4l2 minors on */ | |
55 | #define CX18_V4L2_ENC_YUV_OFFSET 32 | |
56 | ||
57 | static struct { | |
58 | const char *name; | |
59 | int vfl_type; | |
dd89601d | 60 | int num_offset; |
1c1e45d1 HV |
61 | int dma; |
62 | enum v4l2_buf_type buf_type; | |
1c1e45d1 HV |
63 | } cx18_stream_info[] = { |
64 | { /* CX18_ENC_STREAM_TYPE_MPG */ | |
65 | "encoder MPEG", | |
66 | VFL_TYPE_GRABBER, 0, | |
67 | PCI_DMA_FROMDEVICE, V4L2_BUF_TYPE_VIDEO_CAPTURE, | |
1c1e45d1 HV |
68 | }, |
69 | { /* CX18_ENC_STREAM_TYPE_TS */ | |
70 | "TS", | |
71 | VFL_TYPE_GRABBER, -1, | |
72 | PCI_DMA_FROMDEVICE, V4L2_BUF_TYPE_VIDEO_CAPTURE, | |
1c1e45d1 HV |
73 | }, |
74 | { /* CX18_ENC_STREAM_TYPE_YUV */ | |
75 | "encoder YUV", | |
76 | VFL_TYPE_GRABBER, CX18_V4L2_ENC_YUV_OFFSET, | |
77 | PCI_DMA_FROMDEVICE, V4L2_BUF_TYPE_VIDEO_CAPTURE, | |
1c1e45d1 HV |
78 | }, |
79 | { /* CX18_ENC_STREAM_TYPE_VBI */ | |
80 | "encoder VBI", | |
81 | VFL_TYPE_VBI, 0, | |
82 | PCI_DMA_FROMDEVICE, V4L2_BUF_TYPE_VBI_CAPTURE, | |
1c1e45d1 HV |
83 | }, |
84 | { /* CX18_ENC_STREAM_TYPE_PCM */ | |
85 | "encoder PCM audio", | |
86 | VFL_TYPE_GRABBER, CX18_V4L2_ENC_PCM_OFFSET, | |
87 | PCI_DMA_FROMDEVICE, V4L2_BUF_TYPE_PRIVATE, | |
1c1e45d1 HV |
88 | }, |
89 | { /* CX18_ENC_STREAM_TYPE_IDX */ | |
90 | "encoder IDX", | |
91 | VFL_TYPE_GRABBER, -1, | |
92 | PCI_DMA_FROMDEVICE, V4L2_BUF_TYPE_VIDEO_CAPTURE, | |
1c1e45d1 HV |
93 | }, |
94 | { /* CX18_ENC_STREAM_TYPE_RAD */ | |
95 | "encoder radio", | |
96 | VFL_TYPE_RADIO, 0, | |
97 | PCI_DMA_NONE, V4L2_BUF_TYPE_PRIVATE, | |
1c1e45d1 HV |
98 | }, |
99 | }; | |
100 | ||
1bf5842f SF |
101 | |
102 | void cx18_dma_free(struct videobuf_queue *q, | |
103 | struct cx18_stream *s, struct cx18_videobuf_buffer *buf) | |
104 | { | |
105 | videobuf_waiton(q, &buf->vb, 0, 0); | |
106 | videobuf_vmalloc_free(&buf->vb); | |
107 | buf->vb.state = VIDEOBUF_NEEDS_INIT; | |
108 | } | |
109 | ||
110 | static int cx18_prepare_buffer(struct videobuf_queue *q, | |
111 | struct cx18_stream *s, | |
112 | struct cx18_videobuf_buffer *buf, | |
113 | u32 pixelformat, | |
114 | unsigned int width, unsigned int height, | |
115 | enum v4l2_field field) | |
116 | { | |
117 | struct cx18 *cx = s->cx; | |
118 | int rc = 0; | |
119 | ||
120 | /* check settings */ | |
121 | buf->bytes_used = 0; | |
122 | ||
123 | if ((width < 48) || (height < 32)) | |
124 | return -EINVAL; | |
125 | ||
126 | buf->vb.size = (width * height * 2); | |
127 | if ((buf->vb.baddr != 0) && (buf->vb.bsize < buf->vb.size)) | |
128 | return -EINVAL; | |
129 | ||
130 | /* alloc + fill struct (if changed) */ | |
131 | if (buf->vb.width != width || buf->vb.height != height || | |
132 | buf->vb.field != field || s->pixelformat != pixelformat || | |
133 | buf->tvnorm != cx->std) { | |
134 | ||
135 | buf->vb.width = width; | |
136 | buf->vb.height = height; | |
137 | buf->vb.field = field; | |
138 | buf->tvnorm = cx->std; | |
139 | s->pixelformat = pixelformat; | |
140 | ||
141 | cx18_dma_free(q, s, buf); | |
142 | } | |
143 | ||
144 | if ((buf->vb.baddr != 0) && (buf->vb.bsize < buf->vb.size)) | |
145 | return -EINVAL; | |
146 | ||
147 | if (buf->vb.field == 0) | |
148 | buf->vb.field = V4L2_FIELD_INTERLACED; | |
149 | ||
150 | if (VIDEOBUF_NEEDS_INIT == buf->vb.state) { | |
151 | buf->vb.width = width; | |
152 | buf->vb.height = height; | |
153 | buf->vb.field = field; | |
154 | buf->tvnorm = cx->std; | |
155 | s->pixelformat = pixelformat; | |
156 | ||
157 | rc = videobuf_iolock(q, &buf->vb, NULL); | |
158 | if (rc != 0) | |
159 | goto fail; | |
160 | } | |
161 | buf->vb.state = VIDEOBUF_PREPARED; | |
162 | return 0; | |
163 | ||
164 | fail: | |
165 | cx18_dma_free(q, s, buf); | |
166 | return rc; | |
167 | ||
168 | } | |
169 | ||
170 | /* VB_MIN_BUFSIZE is lcm(1440 * 480, 1440 * 576) | |
171 | 1440 is a single line of 4:2:2 YUV at 720 luma samples wide | |
172 | */ | |
173 | #define VB_MIN_BUFFERS 32 | |
174 | #define VB_MIN_BUFSIZE 4147200 | |
175 | ||
176 | static int buffer_setup(struct videobuf_queue *q, | |
177 | unsigned int *count, unsigned int *size) | |
178 | { | |
179 | struct cx18_stream *s = q->priv_data; | |
180 | struct cx18 *cx = s->cx; | |
181 | ||
182 | *size = 2 * cx->cxhdl.width * cx->cxhdl.height; | |
183 | if (*count == 0) | |
184 | *count = VB_MIN_BUFFERS; | |
185 | ||
186 | while (*size * *count > VB_MIN_BUFFERS * VB_MIN_BUFSIZE) | |
187 | (*count)--; | |
188 | ||
189 | q->field = V4L2_FIELD_INTERLACED; | |
190 | q->last = V4L2_FIELD_INTERLACED; | |
191 | ||
192 | return 0; | |
193 | } | |
194 | ||
195 | static int buffer_prepare(struct videobuf_queue *q, | |
196 | struct videobuf_buffer *vb, | |
197 | enum v4l2_field field) | |
198 | { | |
199 | struct cx18_videobuf_buffer *buf = | |
200 | container_of(vb, struct cx18_videobuf_buffer, vb); | |
201 | struct cx18_stream *s = q->priv_data; | |
202 | struct cx18 *cx = s->cx; | |
203 | ||
204 | return cx18_prepare_buffer(q, s, buf, s->pixelformat, | |
205 | cx->cxhdl.width, cx->cxhdl.height, field); | |
206 | } | |
207 | ||
208 | static void buffer_release(struct videobuf_queue *q, | |
209 | struct videobuf_buffer *vb) | |
210 | { | |
211 | struct cx18_videobuf_buffer *buf = | |
212 | container_of(vb, struct cx18_videobuf_buffer, vb); | |
213 | struct cx18_stream *s = q->priv_data; | |
214 | ||
215 | cx18_dma_free(q, s, buf); | |
216 | } | |
217 | ||
218 | static void buffer_queue(struct videobuf_queue *q, struct videobuf_buffer *vb) | |
219 | { | |
220 | struct cx18_videobuf_buffer *buf = | |
221 | container_of(vb, struct cx18_videobuf_buffer, vb); | |
222 | struct cx18_stream *s = q->priv_data; | |
223 | ||
224 | buf->vb.state = VIDEOBUF_QUEUED; | |
225 | ||
226 | list_add_tail(&buf->vb.queue, &s->vb_capture); | |
227 | } | |
228 | ||
229 | static struct videobuf_queue_ops cx18_videobuf_qops = { | |
230 | .buf_setup = buffer_setup, | |
231 | .buf_prepare = buffer_prepare, | |
232 | .buf_queue = buffer_queue, | |
233 | .buf_release = buffer_release, | |
234 | }; | |
235 | ||
1c1e45d1 HV |
236 | static void cx18_stream_init(struct cx18 *cx, int type) |
237 | { | |
238 | struct cx18_stream *s = &cx->streams[type]; | |
3d05913d | 239 | struct video_device *video_dev = s->video_dev; |
1c1e45d1 | 240 | |
3d05913d | 241 | /* we need to keep video_dev, so restore it afterwards */ |
1c1e45d1 | 242 | memset(s, 0, sizeof(*s)); |
3d05913d | 243 | s->video_dev = video_dev; |
1c1e45d1 HV |
244 | |
245 | /* initialize cx18_stream fields */ | |
754f9969 | 246 | s->dvb = NULL; |
1c1e45d1 HV |
247 | s->cx = cx; |
248 | s->type = type; | |
249 | s->name = cx18_stream_info[type].name; | |
d3c5e707 | 250 | s->handle = CX18_INVALID_TASK_HANDLE; |
1c1e45d1 HV |
251 | |
252 | s->dma = cx18_stream_info[type].dma; | |
6ecd86dc | 253 | s->buffers = cx->stream_buffers[type]; |
1c1e45d1 | 254 | s->buf_size = cx->stream_buf_size[type]; |
52fcb3ec AW |
255 | INIT_LIST_HEAD(&s->buf_pool); |
256 | s->bufs_per_mdl = 1; | |
257 | s->mdl_size = s->buf_size * s->bufs_per_mdl; | |
6ecd86dc | 258 | |
1c1e45d1 HV |
259 | init_waitqueue_head(&s->waitq); |
260 | s->id = -1; | |
40c5520f | 261 | spin_lock_init(&s->q_free.lock); |
1c1e45d1 | 262 | cx18_queue_init(&s->q_free); |
40c5520f | 263 | spin_lock_init(&s->q_busy.lock); |
66c2a6b0 | 264 | cx18_queue_init(&s->q_busy); |
40c5520f | 265 | spin_lock_init(&s->q_full.lock); |
1c1e45d1 | 266 | cx18_queue_init(&s->q_full); |
52fcb3ec AW |
267 | spin_lock_init(&s->q_idle.lock); |
268 | cx18_queue_init(&s->q_idle); | |
21a278b8 AW |
269 | |
270 | INIT_WORK(&s->out_work_order, cx18_out_work_handler); | |
b7101de3 ST |
271 | |
272 | INIT_LIST_HEAD(&s->vb_capture); | |
273 | s->vb_timeout.function = cx18_vb_timeout; | |
274 | s->vb_timeout.data = (unsigned long)s; | |
275 | init_timer(&s->vb_timeout); | |
276 | spin_lock_init(&s->vb_lock); | |
1bf5842f | 277 | if (type == CX18_ENC_STREAM_TYPE_YUV) { |
612031c0 SF |
278 | spin_lock_init(&s->vbuf_q_lock); |
279 | ||
1bf5842f SF |
280 | s->vb_type = V4L2_BUF_TYPE_VIDEO_CAPTURE; |
281 | videobuf_queue_vmalloc_init(&s->vbuf_q, &cx18_videobuf_qops, | |
282 | &cx->pci_dev->dev, &s->vbuf_q_lock, | |
283 | V4L2_BUF_TYPE_VIDEO_CAPTURE, | |
284 | V4L2_FIELD_INTERLACED, | |
285 | sizeof(struct cx18_videobuf_buffer), | |
286 | s, &cx->serialize_lock); | |
287 | ||
288 | /* Assume the previous pixel default */ | |
289 | s->pixelformat = V4L2_PIX_FMT_HM12; | |
290 | } | |
1c1e45d1 HV |
291 | } |
292 | ||
293 | static int cx18_prep_dev(struct cx18 *cx, int type) | |
294 | { | |
295 | struct cx18_stream *s = &cx->streams[type]; | |
296 | u32 cap = cx->v4l2_cap; | |
dd89601d | 297 | int num_offset = cx18_stream_info[type].num_offset; |
5811cf99 | 298 | int num = cx->instance + cx18_first_minor + num_offset; |
1c1e45d1 | 299 | |
754f9969 AW |
300 | /* |
301 | * These five fields are always initialized. | |
302 | * For analog capture related streams, if video_dev == NULL then the | |
303 | * stream is not in use. | |
304 | * For the TS stream, if dvb == NULL then the stream is not in use. | |
305 | * In those cases no other fields but these four can be used. | |
306 | */ | |
3d05913d | 307 | s->video_dev = NULL; |
754f9969 | 308 | s->dvb = NULL; |
1c1e45d1 HV |
309 | s->cx = cx; |
310 | s->type = type; | |
311 | s->name = cx18_stream_info[type].name; | |
312 | ||
313 | /* Check whether the radio is supported */ | |
314 | if (type == CX18_ENC_STREAM_TYPE_RAD && !(cap & V4L2_CAP_RADIO)) | |
315 | return 0; | |
316 | ||
317 | /* Check whether VBI is supported */ | |
318 | if (type == CX18_ENC_STREAM_TYPE_VBI && | |
319 | !(cap & (V4L2_CAP_VBI_CAPTURE | V4L2_CAP_SLICED_VBI_CAPTURE))) | |
320 | return 0; | |
321 | ||
1c1e45d1 HV |
322 | /* User explicitly selected 0 buffers for these streams, so don't |
323 | create them. */ | |
324 | if (cx18_stream_info[type].dma != PCI_DMA_NONE && | |
6ecd86dc | 325 | cx->stream_buffers[type] == 0) { |
1c1e45d1 HV |
326 | CX18_INFO("Disabled %s device\n", cx18_stream_info[type].name); |
327 | return 0; | |
328 | } | |
329 | ||
330 | cx18_stream_init(cx, type); | |
331 | ||
754f9969 AW |
332 | /* Allocate the cx18_dvb struct only for the TS on cards with DTV */ |
333 | if (type == CX18_ENC_STREAM_TYPE_TS) { | |
334 | if (cx->card->hw_all & CX18_HW_DVB) { | |
335 | s->dvb = kzalloc(sizeof(struct cx18_dvb), GFP_KERNEL); | |
336 | if (s->dvb == NULL) { | |
337 | CX18_ERR("Couldn't allocate cx18_dvb structure" | |
338 | " for %s\n", s->name); | |
339 | return -ENOMEM; | |
340 | } | |
341 | } else { | |
342 | /* Don't need buffers for the TS, if there is no DVB */ | |
343 | s->buffers = 0; | |
344 | } | |
345 | } | |
346 | ||
dd89601d | 347 | if (num_offset == -1) |
1c1e45d1 HV |
348 | return 0; |
349 | ||
350 | /* allocate and initialize the v4l2 video device structure */ | |
3d05913d AW |
351 | s->video_dev = video_device_alloc(); |
352 | if (s->video_dev == NULL) { | |
1c1e45d1 HV |
353 | CX18_ERR("Couldn't allocate v4l2 video_device for %s\n", |
354 | s->name); | |
355 | return -ENOMEM; | |
356 | } | |
357 | ||
5811cf99 AW |
358 | snprintf(s->video_dev->name, sizeof(s->video_dev->name), "%s %s", |
359 | cx->v4l2_dev.name, s->name); | |
1c1e45d1 | 360 | |
3d05913d | 361 | s->video_dev->num = num; |
5811cf99 | 362 | s->video_dev->v4l2_dev = &cx->v4l2_dev; |
3d05913d AW |
363 | s->video_dev->fops = &cx18_v4l2_enc_fops; |
364 | s->video_dev->release = video_device_release; | |
365 | s->video_dev->tvnorms = V4L2_STD_ALL; | |
b1a873a3 | 366 | set_bit(V4L2_FL_USE_FH_PRIO, &s->video_dev->flags); |
3d05913d | 367 | cx18_set_funcs(s->video_dev); |
1c1e45d1 HV |
368 | return 0; |
369 | } | |
370 | ||
371 | /* Initialize v4l2 variables and register v4l2 devices */ | |
372 | int cx18_streams_setup(struct cx18 *cx) | |
373 | { | |
9b4a7c8a | 374 | int type, ret; |
1c1e45d1 HV |
375 | |
376 | /* Setup V4L2 Devices */ | |
377 | for (type = 0; type < CX18_MAX_STREAMS; type++) { | |
378 | /* Prepare device */ | |
9b4a7c8a AW |
379 | ret = cx18_prep_dev(cx, type); |
380 | if (ret < 0) | |
1c1e45d1 HV |
381 | break; |
382 | ||
383 | /* Allocate Stream */ | |
9b4a7c8a AW |
384 | ret = cx18_stream_alloc(&cx->streams[type]); |
385 | if (ret < 0) | |
1c1e45d1 HV |
386 | break; |
387 | } | |
388 | if (type == CX18_MAX_STREAMS) | |
389 | return 0; | |
390 | ||
391 | /* One or more streams could not be initialized. Clean 'em all up. */ | |
3f98387e | 392 | cx18_streams_cleanup(cx, 0); |
9b4a7c8a | 393 | return ret; |
1c1e45d1 HV |
394 | } |
395 | ||
396 | static int cx18_reg_dev(struct cx18 *cx, int type) | |
397 | { | |
398 | struct cx18_stream *s = &cx->streams[type]; | |
399 | int vfl_type = cx18_stream_info[type].vfl_type; | |
38c7c036 | 400 | const char *name; |
9b4a7c8a | 401 | int num, ret; |
1c1e45d1 | 402 | |
754f9969 | 403 | if (type == CX18_ENC_STREAM_TYPE_TS && s->dvb != NULL) { |
9b4a7c8a AW |
404 | ret = cx18_dvb_register(s); |
405 | if (ret < 0) { | |
1c1e45d1 | 406 | CX18_ERR("DVB failed to register\n"); |
9b4a7c8a | 407 | return ret; |
1c1e45d1 HV |
408 | } |
409 | } | |
410 | ||
3d05913d | 411 | if (s->video_dev == NULL) |
1c1e45d1 HV |
412 | return 0; |
413 | ||
3d05913d | 414 | num = s->video_dev->num; |
dd89601d HV |
415 | /* card number + user defined offset + device offset */ |
416 | if (type != CX18_ENC_STREAM_TYPE_MPG) { | |
417 | struct cx18_stream *s_mpg = &cx->streams[CX18_ENC_STREAM_TYPE_MPG]; | |
418 | ||
3d05913d AW |
419 | if (s_mpg->video_dev) |
420 | num = s_mpg->video_dev->num | |
421 | + cx18_stream_info[type].num_offset; | |
dd89601d | 422 | } |
5811cf99 | 423 | video_set_drvdata(s->video_dev, s); |
1c1e45d1 HV |
424 | |
425 | /* Register device. First try the desired minor, then any free one. */ | |
6b5270d2 | 426 | ret = video_register_device_no_warn(s->video_dev, vfl_type, num); |
9b4a7c8a | 427 | if (ret < 0) { |
581644d9 | 428 | CX18_ERR("Couldn't register v4l2 device for %s (device node number %d)\n", |
dd89601d | 429 | s->name, num); |
3d05913d AW |
430 | video_device_release(s->video_dev); |
431 | s->video_dev = NULL; | |
9b4a7c8a | 432 | return ret; |
1c1e45d1 | 433 | } |
38c7c036 LP |
434 | |
435 | name = video_device_node_name(s->video_dev); | |
1c1e45d1 HV |
436 | |
437 | switch (vfl_type) { | |
438 | case VFL_TYPE_GRABBER: | |
38c7c036 LP |
439 | CX18_INFO("Registered device %s for %s (%d x %d.%02d kB)\n", |
440 | name, s->name, cx->stream_buffers[type], | |
22dce188 AW |
441 | cx->stream_buf_size[type] / 1024, |
442 | (cx->stream_buf_size[type] * 100 / 1024) % 100); | |
1c1e45d1 HV |
443 | break; |
444 | ||
445 | case VFL_TYPE_RADIO: | |
38c7c036 | 446 | CX18_INFO("Registered device %s for %s\n", name, s->name); |
1c1e45d1 HV |
447 | break; |
448 | ||
449 | case VFL_TYPE_VBI: | |
6ecd86dc | 450 | if (cx->stream_buffers[type]) |
38c7c036 | 451 | CX18_INFO("Registered device %s for %s " |
6ecd86dc | 452 | "(%d x %d bytes)\n", |
38c7c036 | 453 | name, s->name, cx->stream_buffers[type], |
6ecd86dc | 454 | cx->stream_buf_size[type]); |
1c1e45d1 | 455 | else |
38c7c036 LP |
456 | CX18_INFO("Registered device %s for %s\n", |
457 | name, s->name); | |
1c1e45d1 HV |
458 | break; |
459 | } | |
460 | ||
461 | return 0; | |
462 | } | |
463 | ||
464 | /* Register v4l2 devices */ | |
465 | int cx18_streams_register(struct cx18 *cx) | |
466 | { | |
467 | int type; | |
9b4a7c8a AW |
468 | int err; |
469 | int ret = 0; | |
1c1e45d1 HV |
470 | |
471 | /* Register V4L2 devices */ | |
9b4a7c8a AW |
472 | for (type = 0; type < CX18_MAX_STREAMS; type++) { |
473 | err = cx18_reg_dev(cx, type); | |
474 | if (err && ret == 0) | |
475 | ret = err; | |
476 | } | |
1c1e45d1 | 477 | |
9b4a7c8a | 478 | if (ret == 0) |
1c1e45d1 HV |
479 | return 0; |
480 | ||
481 | /* One or more streams could not be initialized. Clean 'em all up. */ | |
3f98387e | 482 | cx18_streams_cleanup(cx, 1); |
9b4a7c8a | 483 | return ret; |
1c1e45d1 HV |
484 | } |
485 | ||
486 | /* Unregister v4l2 devices */ | |
3f98387e | 487 | void cx18_streams_cleanup(struct cx18 *cx, int unregister) |
1c1e45d1 HV |
488 | { |
489 | struct video_device *vdev; | |
490 | int type; | |
491 | ||
492 | /* Teardown all streams */ | |
493 | for (type = 0; type < CX18_MAX_STREAMS; type++) { | |
7b1dde03 | 494 | |
754f9969 | 495 | /* The TS has a cx18_dvb structure, not a video_device */ |
7b1dde03 | 496 | if (type == CX18_ENC_STREAM_TYPE_TS) { |
754f9969 AW |
497 | if (cx->streams[type].dvb != NULL) { |
498 | if (unregister) | |
499 | cx18_dvb_unregister(&cx->streams[type]); | |
500 | kfree(cx->streams[type].dvb); | |
501 | cx->streams[type].dvb = NULL; | |
7b1dde03 AW |
502 | cx18_stream_free(&cx->streams[type]); |
503 | } | |
504 | continue; | |
505 | } | |
506 | ||
507 | /* No struct video_device, but can have buffers allocated */ | |
508 | if (type == CX18_ENC_STREAM_TYPE_IDX) { | |
0f890ab1 | 509 | /* If the module params didn't inhibit IDX ... */ |
7b1dde03 AW |
510 | if (cx->stream_buffers[type] != 0) { |
511 | cx->stream_buffers[type] = 0; | |
0f890ab1 AW |
512 | /* |
513 | * Before calling cx18_stream_free(), | |
514 | * check if the IDX stream was actually set up. | |
515 | * Needed, since the cx18_probe() error path | |
516 | * exits through here as well as normal clean up | |
517 | */ | |
518 | if (cx->streams[type].buffers != 0) | |
519 | cx18_stream_free(&cx->streams[type]); | |
7b1dde03 AW |
520 | } |
521 | continue; | |
fac3639d | 522 | } |
1c1e45d1 | 523 | |
7b1dde03 | 524 | /* If struct video_device exists, can have buffers allocated */ |
3d05913d | 525 | vdev = cx->streams[type].video_dev; |
1c1e45d1 | 526 | |
3d05913d | 527 | cx->streams[type].video_dev = NULL; |
1c1e45d1 HV |
528 | if (vdev == NULL) |
529 | continue; | |
530 | ||
1bf5842f SF |
531 | if (type == CX18_ENC_STREAM_TYPE_YUV) |
532 | videobuf_mmap_free(&cx->streams[type].vbuf_q); | |
533 | ||
1c1e45d1 HV |
534 | cx18_stream_free(&cx->streams[type]); |
535 | ||
3f98387e HV |
536 | /* Unregister or release device */ |
537 | if (unregister) | |
538 | video_unregister_device(vdev); | |
539 | else | |
540 | video_device_release(vdev); | |
1c1e45d1 HV |
541 | } |
542 | } | |
543 | ||
544 | static void cx18_vbi_setup(struct cx18_stream *s) | |
545 | { | |
546 | struct cx18 *cx = s->cx; | |
dd073434 | 547 | int raw = cx18_raw_vbi(cx); |
1c1e45d1 HV |
548 | u32 data[CX2341X_MBOX_MAX_DATA]; |
549 | int lines; | |
550 | ||
551 | if (cx->is_60hz) { | |
552 | cx->vbi.count = 12; | |
553 | cx->vbi.start[0] = 10; | |
554 | cx->vbi.start[1] = 273; | |
555 | } else { /* PAL/SECAM */ | |
556 | cx->vbi.count = 18; | |
557 | cx->vbi.start[0] = 6; | |
558 | cx->vbi.start[1] = 318; | |
559 | } | |
560 | ||
561 | /* setup VBI registers */ | |
add632cd HV |
562 | if (raw) |
563 | v4l2_subdev_call(cx->sd_av, vbi, s_raw_fmt, &cx->vbi.in.fmt.vbi); | |
564 | else | |
565 | v4l2_subdev_call(cx->sd_av, vbi, s_sliced_fmt, &cx->vbi.in.fmt.sliced); | |
1c1e45d1 | 566 | |
dcc0ef88 AW |
567 | /* |
568 | * Send the CX18_CPU_SET_RAW_VBI_PARAM API command to setup Encoder Raw | |
569 | * VBI when the first analog capture channel starts, as once it starts | |
570 | * (e.g. MPEG), we can't effect any change in the Encoder Raw VBI setup | |
571 | * (i.e. for the VBI capture channels). We also send it for each | |
572 | * analog capture channel anyway just to make sure we get the proper | |
573 | * behavior | |
574 | */ | |
1c1e45d1 HV |
575 | if (raw) { |
576 | lines = cx->vbi.count * 2; | |
577 | } else { | |
812b1f9d AW |
578 | /* |
579 | * For 525/60 systems, according to the VIP 2 & BT.656 std: | |
580 | * The EAV RP code's Field bit toggles on line 4, a few lines | |
581 | * after the Vertcal Blank bit has already toggled. | |
582 | * Tell the encoder to capture 21-4+1=18 lines per field, | |
583 | * since we want lines 10 through 21. | |
584 | * | |
5ab74052 AW |
585 | * For 625/50 systems, according to the VIP 2 & BT.656 std: |
586 | * The EAV RP code's Field bit toggles on line 1, a few lines | |
587 | * after the Vertcal Blank bit has already toggled. | |
929a3ad1 AW |
588 | * (We've actually set the digitizer so that the Field bit |
589 | * toggles on line 2.) Tell the encoder to capture 23-2+1=22 | |
590 | * lines per field, since we want lines 6 through 23. | |
812b1f9d | 591 | */ |
929a3ad1 | 592 | lines = cx->is_60hz ? (21 - 4 + 1) * 2 : (23 - 2 + 1) * 2; |
1c1e45d1 HV |
593 | } |
594 | ||
1c1e45d1 HV |
595 | data[0] = s->handle; |
596 | /* Lines per field */ | |
597 | data[1] = (lines / 2) | ((lines / 2) << 16); | |
598 | /* bytes per line */ | |
302df970 AW |
599 | data[2] = (raw ? vbi_active_samples |
600 | : (cx->is_60hz ? vbi_hblank_samples_60Hz | |
601 | : vbi_hblank_samples_50Hz)); | |
1c1e45d1 HV |
602 | /* Every X number of frames a VBI interrupt arrives |
603 | (frames as in 25 or 30 fps) */ | |
604 | data[3] = 1; | |
302df970 AW |
605 | /* |
606 | * Set the SAV/EAV RP codes to look for as start/stop points | |
607 | * when in VIP-1.1 mode | |
608 | */ | |
1c1e45d1 | 609 | if (raw) { |
302df970 AW |
610 | /* |
611 | * Start codes for beginning of "active" line in vertical blank | |
612 | * 0x20 ( VerticalBlank ) | |
613 | * 0x60 ( EvenField VerticalBlank ) | |
614 | */ | |
1c1e45d1 | 615 | data[4] = 0x20602060; |
302df970 AW |
616 | /* |
617 | * End codes for end of "active" raw lines and regular lines | |
618 | * 0x30 ( VerticalBlank HorizontalBlank) | |
619 | * 0x70 ( EvenField VerticalBlank HorizontalBlank) | |
620 | * 0x90 (Task HorizontalBlank) | |
621 | * 0xd0 (Task EvenField HorizontalBlank) | |
622 | */ | |
af009cf6 | 623 | data[5] = 0x307090d0; |
1c1e45d1 | 624 | } else { |
302df970 AW |
625 | /* |
626 | * End codes for active video, we want data in the hblank region | |
627 | * 0xb0 (Task 0 VerticalBlank HorizontalBlank) | |
628 | * 0xf0 (Task EvenField VerticalBlank HorizontalBlank) | |
629 | * | |
630 | * Since the V bit is only allowed to toggle in the EAV RP code, | |
631 | * just before the first active region line, these two | |
812b1f9d | 632 | * are problematic: |
302df970 AW |
633 | * 0x90 (Task HorizontalBlank) |
634 | * 0xd0 (Task EvenField HorizontalBlank) | |
812b1f9d | 635 | * |
af7c58b1 AW |
636 | * We have set the digitzer such that we don't have to worry |
637 | * about these problem codes. | |
302df970 | 638 | */ |
1c1e45d1 | 639 | data[4] = 0xB0F0B0F0; |
302df970 AW |
640 | /* |
641 | * Start codes for beginning of active line in vertical blank | |
642 | * 0xa0 (Task VerticalBlank ) | |
643 | * 0xe0 (Task EvenField VerticalBlank ) | |
644 | */ | |
1c1e45d1 HV |
645 | data[5] = 0xA0E0A0E0; |
646 | } | |
647 | ||
648 | CX18_DEBUG_INFO("Setup VBI h: %d lines %x bpl %d fr %d %x %x\n", | |
649 | data[0], data[1], data[2], data[3], data[4], data[5]); | |
650 | ||
dcc0ef88 | 651 | cx18_api(cx, CX18_CPU_SET_RAW_VBI_PARAM, 6, data); |
1c1e45d1 HV |
652 | } |
653 | ||
ef991797 AW |
654 | void cx18_stream_rotate_idx_mdls(struct cx18 *cx) |
655 | { | |
656 | struct cx18_stream *s = &cx->streams[CX18_ENC_STREAM_TYPE_IDX]; | |
657 | struct cx18_mdl *mdl; | |
658 | ||
659 | if (!cx18_stream_enabled(s)) | |
660 | return; | |
661 | ||
662 | /* Return if the firmware is not running low on MDLs */ | |
663 | if ((atomic_read(&s->q_free.depth) + atomic_read(&s->q_busy.depth)) >= | |
664 | CX18_ENC_STREAM_TYPE_IDX_FW_MDL_MIN) | |
665 | return; | |
666 | ||
667 | /* Return if there are no MDLs to rotate back to the firmware */ | |
668 | if (atomic_read(&s->q_full.depth) < 2) | |
669 | return; | |
670 | ||
671 | /* | |
672 | * Take the oldest IDX MDL still holding data, and discard its index | |
673 | * entries by scheduling the MDL to go back to the firmware | |
674 | */ | |
675 | mdl = cx18_dequeue(s, &s->q_full); | |
676 | if (mdl != NULL) | |
677 | cx18_enqueue(s, mdl, &s->q_free); | |
678 | } | |
679 | ||
87116159 | 680 | static |
52fcb3ec AW |
681 | struct cx18_queue *_cx18_stream_put_mdl_fw(struct cx18_stream *s, |
682 | struct cx18_mdl *mdl) | |
66c2a6b0 AW |
683 | { |
684 | struct cx18 *cx = s->cx; | |
685 | struct cx18_queue *q; | |
686 | ||
687 | /* Don't give it to the firmware, if we're not running a capture */ | |
688 | if (s->handle == CX18_INVALID_TASK_HANDLE || | |
87116159 | 689 | test_bit(CX18_F_S_STOPPING, &s->s_flags) || |
66c2a6b0 | 690 | !test_bit(CX18_F_S_STREAMING, &s->s_flags)) |
52fcb3ec | 691 | return cx18_enqueue(s, mdl, &s->q_free); |
66c2a6b0 | 692 | |
52fcb3ec | 693 | q = cx18_enqueue(s, mdl, &s->q_busy); |
66c2a6b0 | 694 | if (q != &s->q_busy) |
52fcb3ec | 695 | return q; /* The firmware has the max MDLs it can handle */ |
66c2a6b0 | 696 | |
52fcb3ec | 697 | cx18_mdl_sync_for_device(s, mdl); |
66c2a6b0 | 698 | cx18_vapi(cx, CX18_CPU_DE_SET_MDL, 5, s->handle, |
52fcb3ec AW |
699 | (void __iomem *) &cx->scb->cpu_mdl[mdl->id] - cx->enc_mem, |
700 | s->bufs_per_mdl, mdl->id, s->mdl_size); | |
66c2a6b0 AW |
701 | return q; |
702 | } | |
703 | ||
87116159 AW |
704 | static |
705 | void _cx18_stream_load_fw_queue(struct cx18_stream *s) | |
66c2a6b0 | 706 | { |
abb096de | 707 | struct cx18_queue *q; |
52fcb3ec | 708 | struct cx18_mdl *mdl; |
66c2a6b0 | 709 | |
c37b11bf AW |
710 | if (atomic_read(&s->q_free.depth) == 0 || |
711 | atomic_read(&s->q_busy.depth) >= CX18_MAX_FW_MDLS_PER_STREAM) | |
abb096de AW |
712 | return; |
713 | ||
714 | /* Move from q_free to q_busy notifying the firmware, until the limit */ | |
715 | do { | |
52fcb3ec AW |
716 | mdl = cx18_dequeue(s, &s->q_free); |
717 | if (mdl == NULL) | |
abb096de | 718 | break; |
52fcb3ec | 719 | q = _cx18_stream_put_mdl_fw(s, mdl); |
c37b11bf | 720 | } while (atomic_read(&s->q_busy.depth) < CX18_MAX_FW_MDLS_PER_STREAM |
0ef02892 | 721 | && q == &s->q_busy); |
66c2a6b0 AW |
722 | } |
723 | ||
87116159 AW |
724 | void cx18_out_work_handler(struct work_struct *work) |
725 | { | |
21a278b8 AW |
726 | struct cx18_stream *s = |
727 | container_of(work, struct cx18_stream, out_work_order); | |
87116159 | 728 | |
21a278b8 | 729 | _cx18_stream_load_fw_queue(s); |
87116159 AW |
730 | } |
731 | ||
52fcb3ec AW |
732 | static void cx18_stream_configure_mdls(struct cx18_stream *s) |
733 | { | |
734 | cx18_unload_queues(s); | |
735 | ||
22dce188 AW |
736 | switch (s->type) { |
737 | case CX18_ENC_STREAM_TYPE_YUV: | |
738 | /* | |
739 | * Height should be a multiple of 32 lines. | |
740 | * Set the MDL size to the exact size needed for one frame. | |
741 | * Use enough buffers per MDL to cover the MDL size | |
742 | */ | |
1bf5842f SF |
743 | if (s->pixelformat == V4L2_PIX_FMT_HM12) |
744 | s->mdl_size = 720 * s->cx->cxhdl.height * 3 / 2; | |
745 | else | |
746 | s->mdl_size = 720 * s->cx->cxhdl.height * 2; | |
22dce188 AW |
747 | s->bufs_per_mdl = s->mdl_size / s->buf_size; |
748 | if (s->mdl_size % s->buf_size) | |
749 | s->bufs_per_mdl++; | |
750 | break; | |
127ce5f0 AW |
751 | case CX18_ENC_STREAM_TYPE_VBI: |
752 | s->bufs_per_mdl = 1; | |
753 | if (cx18_raw_vbi(s->cx)) { | |
754 | s->mdl_size = (s->cx->is_60hz ? 12 : 18) | |
755 | * 2 * vbi_active_samples; | |
756 | } else { | |
757 | /* | |
758 | * See comment in cx18_vbi_setup() below about the | |
759 | * extra lines we capture in sliced VBI mode due to | |
760 | * the lines on which EAV RP codes toggle. | |
761 | */ | |
762 | s->mdl_size = s->cx->is_60hz | |
763 | ? (21 - 4 + 1) * 2 * vbi_hblank_samples_60Hz | |
764 | : (23 - 2 + 1) * 2 * vbi_hblank_samples_50Hz; | |
765 | } | |
766 | break; | |
22dce188 AW |
767 | default: |
768 | s->bufs_per_mdl = 1; | |
769 | s->mdl_size = s->buf_size * s->bufs_per_mdl; | |
770 | break; | |
771 | } | |
52fcb3ec AW |
772 | |
773 | cx18_load_queues(s); | |
774 | } | |
775 | ||
1c1e45d1 HV |
776 | int cx18_start_v4l2_encode_stream(struct cx18_stream *s) |
777 | { | |
778 | u32 data[MAX_MB_ARGUMENTS]; | |
779 | struct cx18 *cx = s->cx; | |
1c1e45d1 | 780 | int captype = 0; |
e46c54a8 | 781 | struct cx18_stream *s_idx; |
1c1e45d1 | 782 | |
540bab93 | 783 | if (!cx18_stream_enabled(s)) |
1c1e45d1 HV |
784 | return -EINVAL; |
785 | ||
786 | CX18_DEBUG_INFO("Start encoder stream %s\n", s->name); | |
787 | ||
788 | switch (s->type) { | |
789 | case CX18_ENC_STREAM_TYPE_MPG: | |
790 | captype = CAPTURE_CHANNEL_TYPE_MPEG; | |
791 | cx->mpg_data_received = cx->vbi_data_inserted = 0; | |
792 | cx->dualwatch_jiffies = jiffies; | |
a75b9be1 | 793 | cx->dualwatch_stereo_mode = v4l2_ctrl_g_ctrl(cx->cxhdl.audio_mode); |
1c1e45d1 HV |
794 | cx->search_pack_header = 0; |
795 | break; | |
796 | ||
e46c54a8 AW |
797 | case CX18_ENC_STREAM_TYPE_IDX: |
798 | captype = CAPTURE_CHANNEL_TYPE_INDEX; | |
799 | break; | |
1c1e45d1 HV |
800 | case CX18_ENC_STREAM_TYPE_TS: |
801 | captype = CAPTURE_CHANNEL_TYPE_TS; | |
1c1e45d1 HV |
802 | break; |
803 | case CX18_ENC_STREAM_TYPE_YUV: | |
804 | captype = CAPTURE_CHANNEL_TYPE_YUV; | |
805 | break; | |
806 | case CX18_ENC_STREAM_TYPE_PCM: | |
807 | captype = CAPTURE_CHANNEL_TYPE_PCM; | |
808 | break; | |
809 | case CX18_ENC_STREAM_TYPE_VBI: | |
dcc0ef88 | 810 | #ifdef CX18_ENCODER_PARSES_SLICED |
dd073434 AW |
811 | captype = cx18_raw_vbi(cx) ? |
812 | CAPTURE_CHANNEL_TYPE_VBI : CAPTURE_CHANNEL_TYPE_SLICED_VBI; | |
dcc0ef88 AW |
813 | #else |
814 | /* | |
815 | * Currently we set things up so that Sliced VBI from the | |
816 | * digitizer is handled as Raw VBI by the encoder | |
817 | */ | |
818 | captype = CAPTURE_CHANNEL_TYPE_VBI; | |
819 | #endif | |
1c1e45d1 HV |
820 | cx->vbi.frame = 0; |
821 | cx->vbi.inserted_frame = 0; | |
822 | memset(cx->vbi.sliced_mpeg_size, | |
823 | 0, sizeof(cx->vbi.sliced_mpeg_size)); | |
824 | break; | |
825 | default: | |
826 | return -EINVAL; | |
827 | } | |
1c1e45d1 | 828 | |
1c1e45d1 HV |
829 | /* Clear Streamoff flags in case left from last capture */ |
830 | clear_bit(CX18_F_S_STREAMOFF, &s->s_flags); | |
831 | ||
832 | cx18_vapi_result(cx, data, CX18_CREATE_TASK, 1, CPU_CMD_MASK_CAPTURE); | |
833 | s->handle = data[0]; | |
834 | cx18_vapi(cx, CX18_CPU_SET_CHANNEL_TYPE, 2, s->handle, captype); | |
835 | ||
dcc0ef88 AW |
836 | /* |
837 | * For everything but CAPTURE_CHANNEL_TYPE_TS, play it safe and | |
838 | * set up all the parameters, as it is not obvious which parameters the | |
839 | * firmware shares across capture channel types and which it does not. | |
840 | * | |
841 | * Some of the cx18_vapi() calls below apply to only certain capture | |
842 | * channel types. We're hoping there's no harm in calling most of them | |
843 | * anyway, as long as the values are all consistent. Setting some | |
844 | * shared parameters will have no effect once an analog capture channel | |
845 | * has started streaming. | |
846 | */ | |
847 | if (captype != CAPTURE_CHANNEL_TYPE_TS) { | |
1c1e45d1 HV |
848 | cx18_vapi(cx, CX18_CPU_SET_VER_CROP_LINE, 2, s->handle, 0); |
849 | cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 3, s->handle, 3, 1); | |
850 | cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 3, s->handle, 8, 0); | |
851 | cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 3, s->handle, 4, 1); | |
1c1e45d1 | 852 | |
dcc0ef88 AW |
853 | /* |
854 | * Audio related reset according to | |
855 | * Documentation/video4linux/cx2341x/fw-encoder-api.txt | |
856 | */ | |
857 | if (atomic_read(&cx->ana_capturing) == 0) | |
858 | cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 2, | |
859 | s->handle, 12); | |
860 | ||
861 | /* | |
862 | * Number of lines for Field 1 & Field 2 according to | |
863 | * Documentation/video4linux/cx2341x/fw-encoder-api.txt | |
f37aa511 AW |
864 | * Field 1 is 312 for 625 line systems in BT.656 |
865 | * Field 2 is 313 for 625 line systems in BT.656 | |
dcc0ef88 | 866 | */ |
1c1e45d1 | 867 | cx18_vapi(cx, CX18_CPU_SET_CAPTURE_LINE_NO, 3, |
f37aa511 | 868 | s->handle, 312, 313); |
1c1e45d1 | 869 | |
1c1e45d1 HV |
870 | if (cx->v4l2_cap & V4L2_CAP_VBI_CAPTURE) |
871 | cx18_vbi_setup(s); | |
872 | ||
dcc0ef88 | 873 | /* |
e46c54a8 AW |
874 | * Select to receive I, P, and B frame index entries, if the |
875 | * index stream is enabled. Otherwise disable index entry | |
876 | * generation. | |
dcc0ef88 | 877 | */ |
e46c54a8 | 878 | s_idx = &cx->streams[CX18_ENC_STREAM_TYPE_IDX]; |
5ada5773 AW |
879 | cx18_vapi_result(cx, data, CX18_CPU_SET_INDEXTABLE, 2, |
880 | s->handle, cx18_stream_enabled(s_idx) ? 7 : 0); | |
1c1e45d1 | 881 | |
dcc0ef88 | 882 | /* Call out to the common CX2341x API setup for user controls */ |
a75b9be1 HV |
883 | cx->cxhdl.priv = s; |
884 | cx2341x_handler_setup(&cx->cxhdl); | |
dcc0ef88 AW |
885 | |
886 | /* | |
887 | * When starting a capture and we're set for radio, | |
888 | * ensure the video is muted, despite the user control. | |
889 | */ | |
a75b9be1 | 890 | if (!cx->cxhdl.video_mute && |
dcc0ef88 AW |
891 | test_bit(CX18_F_I_RADIO_USER, &cx->i_flags)) |
892 | cx18_vapi(cx, CX18_CPU_SET_VIDEO_MUTE, 2, s->handle, | |
a75b9be1 | 893 | (v4l2_ctrl_g_ctrl(cx->cxhdl.video_mute_yuv) << 8) | 1); |
b7101de3 ST |
894 | |
895 | /* Enable the Video Format Converter for UYVY 4:2:2 support, | |
896 | * rather than the default HM12 Macroblovk 4:2:0 support. | |
897 | */ | |
898 | if (captype == CAPTURE_CHANNEL_TYPE_YUV) { | |
1bf5842f | 899 | if (s->pixelformat == V4L2_PIX_FMT_UYVY) |
b7101de3 ST |
900 | cx18_vapi(cx, CX18_CPU_SET_VFC_PARAM, 2, |
901 | s->handle, 1); | |
902 | else | |
903 | /* If in doubt, default to HM12 */ | |
904 | cx18_vapi(cx, CX18_CPU_SET_VFC_PARAM, 2, | |
905 | s->handle, 0); | |
906 | } | |
1c1e45d1 HV |
907 | } |
908 | ||
31554ae5 | 909 | if (atomic_read(&cx->tot_capturing) == 0) { |
a75b9be1 | 910 | cx2341x_handler_set_busy(&cx->cxhdl, 1); |
1c1e45d1 | 911 | clear_bit(CX18_F_I_EOS, &cx->i_flags); |
b1526421 | 912 | cx18_write_reg(cx, 7, CX18_DSP0_INTERRUPT_MASK); |
1c1e45d1 HV |
913 | } |
914 | ||
915 | cx18_vapi(cx, CX18_CPU_DE_SET_MDL_ACK, 3, s->handle, | |
990c81c8 AV |
916 | (void __iomem *)&cx->scb->cpu_mdl_ack[s->type][0] - cx->enc_mem, |
917 | (void __iomem *)&cx->scb->cpu_mdl_ack[s->type][1] - cx->enc_mem); | |
1c1e45d1 | 918 | |
66c2a6b0 | 919 | /* Init all the cpu_mdls for this stream */ |
52fcb3ec | 920 | cx18_stream_configure_mdls(s); |
87116159 | 921 | _cx18_stream_load_fw_queue(s); |
66c2a6b0 | 922 | |
1c1e45d1 HV |
923 | /* begin_capture */ |
924 | if (cx18_vapi(cx, CX18_CPU_CAPTURE_START, 1, s->handle)) { | |
925 | CX18_DEBUG_WARN("Error starting capture!\n"); | |
3b5df8ea | 926 | /* Ensure we're really not capturing before releasing MDLs */ |
87116159 | 927 | set_bit(CX18_F_S_STOPPING, &s->s_flags); |
3b5df8ea AW |
928 | if (s->type == CX18_ENC_STREAM_TYPE_MPG) |
929 | cx18_vapi(cx, CX18_CPU_CAPTURE_STOP, 2, s->handle, 1); | |
930 | else | |
931 | cx18_vapi(cx, CX18_CPU_CAPTURE_STOP, 1, s->handle); | |
66c2a6b0 AW |
932 | clear_bit(CX18_F_S_STREAMING, &s->s_flags); |
933 | /* FIXME - CX18_F_S_STREAMOFF as well? */ | |
3b5df8ea | 934 | cx18_vapi(cx, CX18_CPU_DE_RELEASE_MDL, 1, s->handle); |
1c1e45d1 | 935 | cx18_vapi(cx, CX18_DESTROY_TASK, 1, s->handle); |
66c2a6b0 | 936 | s->handle = CX18_INVALID_TASK_HANDLE; |
87116159 | 937 | clear_bit(CX18_F_S_STOPPING, &s->s_flags); |
66c2a6b0 AW |
938 | if (atomic_read(&cx->tot_capturing) == 0) { |
939 | set_bit(CX18_F_I_EOS, &cx->i_flags); | |
940 | cx18_write_reg(cx, 5, CX18_DSP0_INTERRUPT_MASK); | |
941 | } | |
1c1e45d1 HV |
942 | return -EINVAL; |
943 | } | |
944 | ||
945 | /* you're live! sit back and await interrupts :) */ | |
dcc0ef88 | 946 | if (captype != CAPTURE_CHANNEL_TYPE_TS) |
31554ae5 HV |
947 | atomic_inc(&cx->ana_capturing); |
948 | atomic_inc(&cx->tot_capturing); | |
1c1e45d1 HV |
949 | return 0; |
950 | } | |
0f4cf676 | 951 | EXPORT_SYMBOL(cx18_start_v4l2_encode_stream); |
1c1e45d1 HV |
952 | |
953 | void cx18_stop_all_captures(struct cx18 *cx) | |
954 | { | |
955 | int i; | |
956 | ||
957 | for (i = CX18_MAX_STREAMS - 1; i >= 0; i--) { | |
958 | struct cx18_stream *s = &cx->streams[i]; | |
959 | ||
540bab93 | 960 | if (!cx18_stream_enabled(s)) |
1c1e45d1 HV |
961 | continue; |
962 | if (test_bit(CX18_F_S_STREAMING, &s->s_flags)) | |
963 | cx18_stop_v4l2_encode_stream(s, 0); | |
964 | } | |
965 | } | |
966 | ||
967 | int cx18_stop_v4l2_encode_stream(struct cx18_stream *s, int gop_end) | |
968 | { | |
969 | struct cx18 *cx = s->cx; | |
970 | unsigned long then; | |
971 | ||
540bab93 | 972 | if (!cx18_stream_enabled(s)) |
1c1e45d1 HV |
973 | return -EINVAL; |
974 | ||
975 | /* This function assumes that you are allowed to stop the capture | |
976 | and that we are actually capturing */ | |
977 | ||
978 | CX18_DEBUG_INFO("Stop Capture\n"); | |
979 | ||
31554ae5 | 980 | if (atomic_read(&cx->tot_capturing) == 0) |
1c1e45d1 HV |
981 | return 0; |
982 | ||
87116159 | 983 | set_bit(CX18_F_S_STOPPING, &s->s_flags); |
1c1e45d1 HV |
984 | if (s->type == CX18_ENC_STREAM_TYPE_MPG) |
985 | cx18_vapi(cx, CX18_CPU_CAPTURE_STOP, 2, s->handle, !gop_end); | |
986 | else | |
987 | cx18_vapi(cx, CX18_CPU_CAPTURE_STOP, 1, s->handle); | |
988 | ||
989 | then = jiffies; | |
990 | ||
991 | if (s->type == CX18_ENC_STREAM_TYPE_MPG && gop_end) { | |
992 | CX18_INFO("ignoring gop_end: not (yet?) supported by the firmware\n"); | |
993 | } | |
994 | ||
31554ae5 HV |
995 | if (s->type != CX18_ENC_STREAM_TYPE_TS) |
996 | atomic_dec(&cx->ana_capturing); | |
997 | atomic_dec(&cx->tot_capturing); | |
1c1e45d1 HV |
998 | |
999 | /* Clear capture and no-read bits */ | |
1000 | clear_bit(CX18_F_S_STREAMING, &s->s_flags); | |
1001 | ||
f68d0cf5 AW |
1002 | /* Tell the CX23418 it can't use our buffers anymore */ |
1003 | cx18_vapi(cx, CX18_CPU_DE_RELEASE_MDL, 1, s->handle); | |
1004 | ||
1c1e45d1 | 1005 | cx18_vapi(cx, CX18_DESTROY_TASK, 1, s->handle); |
d3c5e707 | 1006 | s->handle = CX18_INVALID_TASK_HANDLE; |
87116159 | 1007 | clear_bit(CX18_F_S_STOPPING, &s->s_flags); |
1c1e45d1 | 1008 | |
31554ae5 | 1009 | if (atomic_read(&cx->tot_capturing) > 0) |
1c1e45d1 HV |
1010 | return 0; |
1011 | ||
a75b9be1 | 1012 | cx2341x_handler_set_busy(&cx->cxhdl, 0); |
b1526421 | 1013 | cx18_write_reg(cx, 5, CX18_DSP0_INTERRUPT_MASK); |
1c1e45d1 HV |
1014 | wake_up(&s->waitq); |
1015 | ||
1016 | return 0; | |
1017 | } | |
0f4cf676 | 1018 | EXPORT_SYMBOL(cx18_stop_v4l2_encode_stream); |
1c1e45d1 HV |
1019 | |
1020 | u32 cx18_find_handle(struct cx18 *cx) | |
1021 | { | |
1022 | int i; | |
1023 | ||
1024 | /* find first available handle to be used for global settings */ | |
1025 | for (i = 0; i < CX18_MAX_STREAMS; i++) { | |
1026 | struct cx18_stream *s = &cx->streams[i]; | |
1027 | ||
3d05913d | 1028 | if (s->video_dev && (s->handle != CX18_INVALID_TASK_HANDLE)) |
1c1e45d1 HV |
1029 | return s->handle; |
1030 | } | |
d3c5e707 | 1031 | return CX18_INVALID_TASK_HANDLE; |
1c1e45d1 | 1032 | } |
ee2d64f5 AW |
1033 | |
1034 | struct cx18_stream *cx18_handle_to_stream(struct cx18 *cx, u32 handle) | |
1035 | { | |
1036 | int i; | |
1037 | struct cx18_stream *s; | |
1038 | ||
1039 | if (handle == CX18_INVALID_TASK_HANDLE) | |
1040 | return NULL; | |
1041 | ||
1042 | for (i = 0; i < CX18_MAX_STREAMS; i++) { | |
1043 | s = &cx->streams[i]; | |
1044 | if (s->handle != handle) | |
1045 | continue; | |
540bab93 | 1046 | if (cx18_stream_enabled(s)) |
ee2d64f5 AW |
1047 | return s; |
1048 | } | |
1049 | return NULL; | |
1050 | } |