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V4L/DVB: zoran: remove V4L1 videodev.h include
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / media / video / arv.c
CommitLineData
1da177e4
LT		 1/*
2 * Colour AR M64278(VGA) driver for Video4Linux
3 *
4 * Copyright (C) 2003 Takeo Takahashi <takahashi.takeo@renesas.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 * Some code is taken from AR driver sample program for M3T-M32700UT.
12 *
13 * AR driver sample (M32R SDK):
14 * Copyright (c) 2003 RENESAS TECHNOROGY CORPORATION
15 * AND RENESAS SOLUTIONS CORPORATION
16 * All Rights Reserved.
17 *
18 * 2003-09-01: Support w3cam by Takeo Takahashi
19 */
20
1da177e4 21#include <linux/init.h>
1da177e4 22#include <linux/module.h>
1da177e4
LT		 23#include <linux/delay.h>
24#include <linux/errno.h>
25#include <linux/fs.h>
1da177e4
LT		 26#include <linux/kernel.h>
27#include <linux/slab.h>
28#include <linux/mm.h>
29#include <linux/sched.h>
30#include <linux/videodev.h>
5e87efa3 31#include <media/v4l2-common.h>
dfb9aff0 32#include <media/v4l2-ioctl.h>
3593cab5 33#include <linux/mutex.h>
1da177e4 34
1da177e4
LT		 35#include <asm/uaccess.h>
36#include <asm/m32r.h>
37#include <asm/io.h>
38#include <asm/dma.h>
39#include <asm/byteorder.h>
40
41#if 0
88f44234 42#define DEBUG(n, args...) printk(KERN_INFO args)
1da177e4
LT		 43#define CHECK_LOST 1
44#else
45#define DEBUG(n, args...)
46#define CHECK_LOST 0
47#endif
48
49/*
50 * USE_INT is always 0, interrupt mode is not available
51 * on linux due to lack of speed
52 */
53#define USE_INT 0 /* Don't modify */
54
55#define VERSION "0.03"
56
57#define ar_inl(addr) inl((unsigned long)(addr))
88f44234 58#define ar_outl(val, addr) outl((unsigned long)(val), (unsigned long)(addr))
1da177e4
LT		 59
60extern struct cpuinfo_m32r boot_cpu_data;
61
62/*
63 * CCD pixel size
64 * Note that M32700UT does not support CIF mode, but QVGA is
65 * supported by M32700UT hardware using VGA mode of AR LSI.
66 *
67 * Supported: VGA (Normal mode, Interlace mode)
68 * QVGA (Always Interlace mode of VGA)
69 *
70 */
71#define AR_WIDTH_VGA 640
72#define AR_HEIGHT_VGA 480
73#define AR_WIDTH_QVGA 320
74#define AR_HEIGHT_QVGA 240
75#define MIN_AR_WIDTH AR_WIDTH_QVGA
76#define MIN_AR_HEIGHT AR_HEIGHT_QVGA
77#define MAX_AR_WIDTH AR_WIDTH_VGA
78#define MAX_AR_HEIGHT AR_HEIGHT_VGA
79
80/* bits & bytes per pixel */
81#define AR_BITS_PER_PIXEL 16
82#define AR_BYTES_PER_PIXEL (AR_BITS_PER_PIXEL/8)
83
84/* line buffer size */
85#define AR_LINE_BYTES_VGA (AR_WIDTH_VGA * AR_BYTES_PER_PIXEL)
86#define AR_LINE_BYTES_QVGA (AR_WIDTH_QVGA * AR_BYTES_PER_PIXEL)
87#define MAX_AR_LINE_BYTES AR_LINE_BYTES_VGA
88
89/* frame size & type */
90#define AR_FRAME_BYTES_VGA \
91 (AR_WIDTH_VGA * AR_HEIGHT_VGA * AR_BYTES_PER_PIXEL)
92#define AR_FRAME_BYTES_QVGA \
93 (AR_WIDTH_QVGA * AR_HEIGHT_QVGA * AR_BYTES_PER_PIXEL)
94#define MAX_AR_FRAME_BYTES \
95 (MAX_AR_WIDTH * MAX_AR_HEIGHT * AR_BYTES_PER_PIXEL)
96
97#define AR_MAX_FRAME 15
98
99/* capture size */
100#define AR_SIZE_VGA 0
101#define AR_SIZE_QVGA 1
102
103/* capture mode */
104#define AR_MODE_INTERLACE 0
105#define AR_MODE_NORMAL 1
106
107struct ar_device {
108 struct video_device *vdev;
109 unsigned int start_capture; /* duaring capture in INT. mode. */
110#if USE_INT
111 unsigned char *line_buff; /* DMA line buffer */
112#endif
113 unsigned char *frame[MAX_AR_HEIGHT]; /* frame data */
114 short size; /* capture size */
115 short mode; /* capture mode */
116 int width, height;
117 int frame_bytes, line_bytes;
118 wait_queue_head_t wait;
7d43cd53 119 unsigned long in_use;
3593cab5 120 struct mutex lock;
1da177e4
LT		 121};
122
123static int video_nr = -1; /* video device number (first free) */
124static unsigned char yuv[MAX_AR_FRAME_BYTES];
125
126/* module parameters */
127/* default frequency */
128#define DEFAULT_FREQ 50 /* 50 or 75 (MHz) is available as BCLK */
129static int freq = DEFAULT_FREQ; /* BCLK: available 50 or 70 (MHz) */
ff699e6b
DSL		 130static int vga; /* default mode(0:QVGA mode, other:VGA mode) */
131static int vga_interlace; /* 0 is normal mode for, else interlace mode */
9b565eb7
ES		 132module_param(freq, int, 0);
133module_param(vga, int, 0);
134module_param(vga_interlace, int, 0);
1da177e4
LT		 135
136static int ar_initialize(struct video_device *dev);
137
138static inline void wait_for_vsync(void)
139{
140 while (ar_inl(ARVCR0) & ARVCR0_VDS) /* wait for VSYNC */
141 cpu_relax();
142 while (!(ar_inl(ARVCR0) & ARVCR0_VDS)) /* wait for VSYNC */
143 cpu_relax();
144}
145
146static inline void wait_acknowledge(void)
147{
148 int i;
149
150 for (i = 0; i < 1000; i++)
151 cpu_relax();
152 while (ar_inl(PLDI2CSTS) & PLDI2CSTS_NOACK)
153 cpu_relax();
154}
155
156/*******************************************************************
157 * I2C functions
158 *******************************************************************/
159void iic(int n, unsigned long addr, unsigned long data1, unsigned long data2,
160 unsigned long data3)
161{
162 int i;
163
d56410e0
MCC		 164 /* Slave Address */
165 ar_outl(addr, PLDI2CDATA);
1da177e4
LT		 166 wait_for_vsync();
167
d56410e0
MCC		 168 /* Start */
169 ar_outl(1, PLDI2CCND);
1da177e4
LT		 170 wait_acknowledge();
171
172 /* Transfer data 1 */
d56410e0 173 ar_outl(data1, PLDI2CDATA);
1da177e4 174 wait_for_vsync();
d56410e0 175 ar_outl(PLDI2CSTEN_STEN, PLDI2CSTEN);
1da177e4
LT		 176 wait_acknowledge();
177
178 /* Transfer data 2 */
d56410e0 179 ar_outl(data2, PLDI2CDATA);
1da177e4 180 wait_for_vsync();
d56410e0 181 ar_outl(PLDI2CSTEN_STEN, PLDI2CSTEN);
1da177e4
LT		 182 wait_acknowledge();
183
184 if (n == 3) {
185 /* Transfer data 3 */
d56410e0 186 ar_outl(data3, PLDI2CDATA);
1da177e4 187 wait_for_vsync();
d56410e0 188 ar_outl(PLDI2CSTEN_STEN, PLDI2CSTEN);
1da177e4 189 wait_acknowledge();
d56410e0 190 }
1da177e4 191
d56410e0 192 /* Stop */
1da177e4
LT		 193 for (i = 0; i < 100; i++)
194 cpu_relax();
d56410e0
MCC		 195 ar_outl(2, PLDI2CCND);
196 ar_outl(2, PLDI2CCND);
1da177e4
LT		 197
198 while (ar_inl(PLDI2CSTS) & PLDI2CSTS_BB)
199 cpu_relax();
200}
201
202
203void init_iic(void)
204{
205 DEBUG(1, "init_iic:\n");
206
d56410e0 207 /*
1da177e4
LT		 208 * ICU Setting (iic)
209 */
d56410e0
MCC		 210 /* I2C Setting */
211 ar_outl(0x0, PLDI2CCR); /* I2CCR Disable */
212 ar_outl(0x0300, PLDI2CMOD); /* I2CMOD ACK/8b-data/7b-addr/auto */
213 ar_outl(0x1, PLDI2CACK); /* I2CACK ACK */
1da177e4 214
657de3cd 215 /* I2C CLK */
d56410e0 216 /* 50MH-100k */
88f44234 217 if (freq == 75)
d56410e0 218 ar_outl(369, PLDI2CFREQ); /* BCLK = 75MHz */
88f44234 219 else if (freq == 50)
1da177e4 220 ar_outl(244, PLDI2CFREQ); /* BCLK = 50MHz */
88f44234 221 else
1da177e4 222 ar_outl(244, PLDI2CFREQ); /* default: BCLK = 50MHz */
d56410e0 223 ar_outl(0x1, PLDI2CCR); /* I2CCR Enable */
1da177e4
LT		 224}
225
226/**************************************************************************
227 *
228 * Video4Linux Interface functions
229 *
230 **************************************************************************/
231
232static inline void disable_dma(void)
233{
234 ar_outl(0x8000, M32R_DMAEN_PORTL); /* disable DMA0 */
235}
236
237static inline void enable_dma(void)
238{
239 ar_outl(0x8080, M32R_DMAEN_PORTL); /* enable DMA0 */
240}
241
242static inline void clear_dma_status(void)
243{
244 ar_outl(0x8000, M32R_DMAEDET_PORTL); /* clear status */
245}
246
247static inline void wait_for_vertical_sync(int exp_line)
248{
249#if CHECK_LOST
250 int tmout = 10000; /* FIXME */
251 int l;
252
253 /*
254 * check HCOUNT because we cannot check vertical sync.
d56410e0 255 */
1da177e4
LT		 256 for (; tmout >= 0; tmout--) {
257 l = ar_inl(ARVHCOUNT);
258 if (l == exp_line)
259 break;
260 }
261 if (tmout < 0)
88f44234 262 printk(KERN_ERR "arv: lost %d -> %d\n", exp_line, l);
1da177e4
LT		 263#else
264 while (ar_inl(ARVHCOUNT) != exp_line)
265 cpu_relax();
266#endif
267}
268
269static ssize_t ar_read(struct file *file, char *buf, size_t count, loff_t *ppos)
270{
271 struct video_device *v = video_devdata(file);
601e9444 272 struct ar_device *ar = video_get_drvdata(v);
1da177e4
LT		 273 long ret = ar->frame_bytes; /* return read bytes */
274 unsigned long arvcr1 = 0;
275 unsigned long flags;
276 unsigned char *p;
277 int h, w;
278 unsigned char *py, *pu, *pv;
88f44234 279#if !USE_INT
1da177e4
LT		 280 int l;
281#endif
282
283 DEBUG(1, "ar_read()\n");
284
285 if (ar->size == AR_SIZE_QVGA)
286 arvcr1 |= ARVCR1_QVGA;
287 if (ar->mode == AR_MODE_NORMAL)
288 arvcr1 |= ARVCR1_NORMAL;
289
3593cab5 290 mutex_lock(&ar->lock);
1da177e4
LT		 291
292#if USE_INT
293 local_irq_save(flags);
294 disable_dma();
295 ar_outl(0xa1871300, M32R_DMA0CR0_PORTL);
296 ar_outl(0x01000000, M32R_DMA0CR1_PORTL);
297
298 /* set AR FIFO address as source(BSEL5) */
299 ar_outl(ARDATA32, M32R_DMA0CSA_PORTL);
300 ar_outl(ARDATA32, M32R_DMA0RSA_PORTL);
301 ar_outl(ar->line_buff, M32R_DMA0CDA_PORTL); /* destination addr. */
302 ar_outl(ar->line_buff, M32R_DMA0RDA_PORTL); /* reload address */
303 ar_outl(ar->line_bytes, M32R_DMA0CBCUT_PORTL); /* byte count (bytes) */
304 ar_outl(ar->line_bytes, M32R_DMA0RBCUT_PORTL); /* reload count (bytes) */
305
306 /*
307 * Okey , kicks AR LSI to invoke an interrupt
308 */
309 ar->start_capture = 0;
310 ar_outl(arvcr1 | ARVCR1_HIEN, ARVCR1);
311 local_irq_restore(flags);
312 /* .... AR interrupts .... */
313 interruptible_sleep_on(&ar->wait);
314 if (signal_pending(current)) {
88f44234 315 printk(KERN_ERR "arv: interrupted while get frame data.\n");
1da177e4
LT		 316 ret = -EINTR;
317 goto out_up;
318 }
319#else /* ! USE_INT */
320 /* polling */
321 ar_outl(arvcr1, ARVCR1);
322 disable_dma();
323 ar_outl(0x8000, M32R_DMAEDET_PORTL);
324 ar_outl(0xa0861300, M32R_DMA0CR0_PORTL);
325 ar_outl(0x01000000, M32R_DMA0CR1_PORTL);
326 ar_outl(ARDATA32, M32R_DMA0CSA_PORTL);
327 ar_outl(ARDATA32, M32R_DMA0RSA_PORTL);
328 ar_outl(ar->line_bytes, M32R_DMA0CBCUT_PORTL);
329 ar_outl(ar->line_bytes, M32R_DMA0RBCUT_PORTL);
330
331 local_irq_save(flags);
332 while (ar_inl(ARVHCOUNT) != 0) /* wait for 0 */
333 cpu_relax();
334 if (ar->mode == AR_MODE_INTERLACE && ar->size == AR_SIZE_VGA) {
335 for (h = 0; h < ar->height; h++) {
336 wait_for_vertical_sync(h);
337 if (h < (AR_HEIGHT_VGA/2))
338 l = h << 1;
339 else
340 l = (((h - (AR_HEIGHT_VGA/2)) << 1) + 1);
341 ar_outl(virt_to_phys(ar->frame[l]), M32R_DMA0CDA_PORTL);
342 enable_dma();
343 while (!(ar_inl(M32R_DMAEDET_PORTL) & 0x8000))
344 cpu_relax();
345 disable_dma();
346 clear_dma_status();
347 ar_outl(0xa0861300, M32R_DMA0CR0_PORTL);
348 }
349 } else {
350 for (h = 0; h < ar->height; h++) {
351 wait_for_vertical_sync(h);
352 ar_outl(virt_to_phys(ar->frame[h]), M32R_DMA0CDA_PORTL);
353 enable_dma();
354 while (!(ar_inl(M32R_DMAEDET_PORTL) & 0x8000))
355 cpu_relax();
356 disable_dma();
357 clear_dma_status();
358 ar_outl(0xa0861300, M32R_DMA0CR0_PORTL);
359 }
360 }
361 local_irq_restore(flags);
362#endif /* ! USE_INT */
363
364 /*
365 * convert YUV422 to YUV422P
366 * +--------------------+
367 * | Y0,Y1,... |
368 * | ..............Yn |
369 * +--------------------+
370 * | U0,U1,........Un |
371 * +--------------------+
372 * | V0,V1,........Vn |
373 * +--------------------+
374 */
375 py = yuv;
376 pu = py + (ar->frame_bytes / 2);
377 pv = pu + (ar->frame_bytes / 4);
378 for (h = 0; h < ar->height; h++) {
379 p = ar->frame[h];
380 for (w = 0; w < ar->line_bytes; w += 4) {
381 *py++ = *p++;
382 *pu++ = *p++;
383 *py++ = *p++;
384 *pv++ = *p++;
385 }
386 }
387 if (copy_to_user(buf, yuv, ar->frame_bytes)) {
88f44234 388 printk(KERN_ERR "arv: failed while copy_to_user yuv.\n");
1da177e4
LT		 389 ret = -EFAULT;
390 goto out_up;
391 }
392 DEBUG(1, "ret = %d\n", ret);
393out_up:
3593cab5 394 mutex_unlock(&ar->lock);
1da177e4
LT		 395 return ret;
396}
397
069b7479 398static long ar_do_ioctl(struct file *file, unsigned int cmd, void *arg)
1da177e4
LT		 399{
400 struct video_device *dev = video_devdata(file);
601e9444 401 struct ar_device *ar = video_get_drvdata(dev);
1da177e4
LT		 402
403 DEBUG(1, "ar_ioctl()\n");
88f44234 404 switch (cmd) {
1da177e4
LT		 405 case VIDIOCGCAP:
406 {
407 struct video_capability *b = arg;
408 DEBUG(1, "VIDIOCGCAP:\n");
409 strcpy(b->name, ar->vdev->name);
410 b->type = VID_TYPE_CAPTURE;
411 b->channels = 0;
412 b->audios = 0;
413 b->maxwidth = MAX_AR_WIDTH;
414 b->maxheight = MAX_AR_HEIGHT;
415 b->minwidth = MIN_AR_WIDTH;
416 b->minheight = MIN_AR_HEIGHT;
417 return 0;
418 }
419 case VIDIOCGCHAN:
420 DEBUG(1, "VIDIOCGCHAN:\n");
421 return 0;
422 case VIDIOCSCHAN:
423 DEBUG(1, "VIDIOCSCHAN:\n");
424 return 0;
425 case VIDIOCGTUNER:
426 DEBUG(1, "VIDIOCGTUNER:\n");
427 return 0;
428 case VIDIOCSTUNER:
429 DEBUG(1, "VIDIOCSTUNER:\n");
430 return 0;
431 case VIDIOCGPICT:
432 DEBUG(1, "VIDIOCGPICT:\n");
433 return 0;
434 case VIDIOCSPICT:
435 DEBUG(1, "VIDIOCSPICT:\n");
436 return 0;
437 case VIDIOCCAPTURE:
438 DEBUG(1, "VIDIOCCAPTURE:\n");
439 return -EINVAL;
440 case VIDIOCGWIN:
441 {
442 struct video_window *w = arg;
443 DEBUG(1, "VIDIOCGWIN:\n");
8509a29e 444 memset(w, 0, sizeof(*w));
1da177e4
LT		 445 w->width = ar->width;
446 w->height = ar->height;
447 return 0;
448 }
449 case VIDIOCSWIN:
450 {
451 struct video_window *w = arg;
452 DEBUG(1, "VIDIOCSWIN:\n");
453 if ((w->width != AR_WIDTH_VGA || w->height != AR_HEIGHT_VGA) &&
454 (w->width != AR_WIDTH_QVGA || w->height != AR_HEIGHT_QVGA))
455 return -EINVAL;
456
3593cab5 457 mutex_lock(&ar->lock);
1da177e4
LT		 458 ar->width = w->width;
459 ar->height = w->height;
460 if (ar->width == AR_WIDTH_VGA) {
461 ar->size = AR_SIZE_VGA;
462 ar->frame_bytes = AR_FRAME_BYTES_VGA;
463 ar->line_bytes = AR_LINE_BYTES_VGA;
464 if (vga_interlace)
465 ar->mode = AR_MODE_INTERLACE;
466 else
467 ar->mode = AR_MODE_NORMAL;
468 } else {
469 ar->size = AR_SIZE_QVGA;
470 ar->frame_bytes = AR_FRAME_BYTES_QVGA;
471 ar->line_bytes = AR_LINE_BYTES_QVGA;
472 ar->mode = AR_MODE_INTERLACE;
473 }
3593cab5 474 mutex_unlock(&ar->lock);
1da177e4
LT		 475 return 0;
476 }
477 case VIDIOCGFBUF:
478 DEBUG(1, "VIDIOCGFBUF:\n");
479 return -EINVAL;
480 case VIDIOCSFBUF:
481 DEBUG(1, "VIDIOCSFBUF:\n");
482 return -EINVAL;
483 case VIDIOCKEY:
484 DEBUG(1, "VIDIOCKEY:\n");
485 return 0;
486 case VIDIOCGFREQ:
487 DEBUG(1, "VIDIOCGFREQ:\n");
488 return -EINVAL;
489 case VIDIOCSFREQ:
490 DEBUG(1, "VIDIOCSFREQ:\n");
491 return -EINVAL;
492 case VIDIOCGAUDIO:
493 DEBUG(1, "VIDIOCGAUDIO:\n");
494 return -EINVAL;
495 case VIDIOCSAUDIO:
496 DEBUG(1, "VIDIOCSAUDIO:\n");
497 return -EINVAL;
498 case VIDIOCSYNC:
499 DEBUG(1, "VIDIOCSYNC:\n");
500 return -EINVAL;
501 case VIDIOCMCAPTURE:
502 DEBUG(1, "VIDIOCMCAPTURE:\n");
503 return -EINVAL;
504 case VIDIOCGMBUF:
505 DEBUG(1, "VIDIOCGMBUF:\n");
506 return -EINVAL;
507 case VIDIOCGUNIT:
508 DEBUG(1, "VIDIOCGUNIT:\n");
509 return -EINVAL;
510 case VIDIOCGCAPTURE:
511 DEBUG(1, "VIDIOCGCAPTURE:\n");
512 return -EINVAL;
513 case VIDIOCSCAPTURE:
514 DEBUG(1, "VIDIOCSCAPTURE:\n");
515 return -EINVAL;
516 case VIDIOCSPLAYMODE:
517 DEBUG(1, "VIDIOCSPLAYMODE:\n");
518 return -EINVAL;
519 case VIDIOCSWRITEMODE:
520 DEBUG(1, "VIDIOCSWRITEMODE:\n");
521 return -EINVAL;
522 case VIDIOCGPLAYINFO:
523 DEBUG(1, "VIDIOCGPLAYINFO:\n");
524 return -EINVAL;
525 case VIDIOCSMICROCODE:
526 DEBUG(1, "VIDIOCSMICROCODE:\n");
527 return -EINVAL;
528 case VIDIOCGVBIFMT:
529 DEBUG(1, "VIDIOCGVBIFMT:\n");
530 return -EINVAL;
531 case VIDIOCSVBIFMT:
532 DEBUG(1, "VIDIOCSVBIFMT:\n");
533 return -EINVAL;
534 default:
535 DEBUG(1, "Unknown ioctl(0x%08x)\n", cmd);
536 return -ENOIOCTLCMD;
537 }
538 return 0;
539}
540
069b7479 541static long ar_ioctl(struct file *file, unsigned int cmd,
1da177e4
LT		 542 unsigned long arg)
543{
f473bf76 544 return video_usercopy(file, cmd, arg, ar_do_ioctl);
1da177e4
LT		 545}
546
547#if USE_INT
548/*
549 * Interrupt handler
550 */
7d12e780 551static void ar_interrupt(int irq, void *dev)
1da177e4
LT		 552{
553 struct ar_device *ar = dev;
554 unsigned int line_count;
555 unsigned int line_number;
556 unsigned int arvcr1;
557
558 line_count = ar_inl(ARVHCOUNT); /* line number */
559 if (ar->mode == AR_MODE_INTERLACE && ar->size == AR_SIZE_VGA) {
560 /* operations for interlace mode */
88f44234 561 if (line_count < (AR_HEIGHT_VGA / 2)) /* even line */
1da177e4 562 line_number = (line_count << 1);
d56410e0
MCC		 563 else /* odd line */
564 line_number =
88f44234 565 (((line_count - (AR_HEIGHT_VGA / 2)) << 1) + 1);
1da177e4
LT		 566 } else {
567 line_number = line_count;
568 }
569
570 if (line_number == 0) {
571 /*
572 * It is an interrupt for line 0.
573 * we have to start capture.
574 */
575 disable_dma();
576#if 0
577 ar_outl(ar->line_buff, M32R_DMA0CDA_PORTL); /* needless? */
578#endif
579 memcpy(ar->frame[0], ar->line_buff, ar->line_bytes);
580#if 0
581 ar_outl(0xa1861300, M32R_DMA0CR0_PORTL);
582#endif
583 enable_dma();
584 ar->start_capture = 1; /* during capture */
585 return;
586 }
587
588 if (ar->start_capture == 1 && line_number <= (ar->height - 1)) {
589 disable_dma();
590 memcpy(ar->frame[line_number], ar->line_buff, ar->line_bytes);
591
592 /*
593 * if captured all line of a frame, disable AR interrupt
594 * and wake a process up.
595 */
596 if (line_number == (ar->height - 1)) { /* end of line */
597
598 ar->start_capture = 0;
599
600 /* disable AR interrupt request */
601 arvcr1 = ar_inl(ARVCR1);
602 arvcr1 &= ~ARVCR1_HIEN; /* clear int. flag */
603 ar_outl(arvcr1, ARVCR1); /* disable */
604 wake_up_interruptible(&ar->wait);
605 } else {
606#if 0
607 ar_outl(ar->line_buff, M32R_DMA0CDA_PORTL);
608 ar_outl(0xa1861300, M32R_DMA0CR0_PORTL);
609#endif
610 enable_dma();
611 }
612 }
613}
614#endif
615
616/*
617 * ar_initialize()
618 * ar_initialize() is called by video_register_device() and
619 * initializes AR LSI and peripherals.
620 *
621 * -1 is returned in all failures.
622 * 0 is returned in success.
623 *
624 */
625static int ar_initialize(struct video_device *dev)
626{
601e9444 627 struct ar_device *ar = video_get_drvdata(dev);
1da177e4 628 unsigned long cr = 0;
88f44234 629 int i, found = 0;
1da177e4
LT		 630
631 DEBUG(1, "ar_initialize:\n");
632
633 /*
634 * initialize AR LSI
635 */
636 ar_outl(0, ARVCR0); /* assert reset of AR LSI */
637 for (i = 0; i < 0x18; i++) /* wait for over 10 cycles @ 27MHz */
638 cpu_relax();
639 ar_outl(ARVCR0_RST, ARVCR0); /* negate reset of AR LSI (enable) */
640 for (i = 0; i < 0x40d; i++) /* wait for over 420 cycles @ 27MHz */
641 cpu_relax();
642
643 /* AR uses INT3 of CPU as interrupt pin. */
644 ar_outl(ARINTSEL_INT3, ARINTSEL);
645
646 if (ar->size == AR_SIZE_QVGA)
647 cr |= ARVCR1_QVGA;
648 if (ar->mode == AR_MODE_NORMAL)
649 cr |= ARVCR1_NORMAL;
650 ar_outl(cr, ARVCR1);
651
d56410e0 652 /*
1da177e4
LT		 653 * Initialize IIC so that CPU can communicate with AR LSI,
654 * and send boot commands to AR LSI.
655 */
656 init_iic();
657
658 for (i = 0; i < 0x100000; i++) { /* > 0xa1d10, 56ms */
659 if ((ar_inl(ARVCR0) & ARVCR0_VDS)) { /* VSYNC */
660 found = 1;
661 break;
662 }
663 }
664
665 if (found == 0)
666 return -ENODEV;
667
88f44234
HV		 668 printk(KERN_INFO "arv: Initializing ");
669
670 iic(2, 0x78, 0x11, 0x01, 0x00); /* start */
671 iic(3, 0x78, 0x12, 0x00, 0x06);
672 iic(3, 0x78, 0x12, 0x12, 0x30);
673 iic(3, 0x78, 0x12, 0x15, 0x58);
674 iic(3, 0x78, 0x12, 0x17, 0x30);
675 printk(KERN_CONT ".");
676 iic(3, 0x78, 0x12, 0x1a, 0x97);
677 iic(3, 0x78, 0x12, 0x1b, 0xff);
678 iic(3, 0x78, 0x12, 0x1c, 0xff);
679 iic(3, 0x78, 0x12, 0x26, 0x10);
680 iic(3, 0x78, 0x12, 0x27, 0x00);
681 printk(KERN_CONT ".");
682 iic(2, 0x78, 0x34, 0x02, 0x00);
683 iic(2, 0x78, 0x7a, 0x10, 0x00);
684 iic(2, 0x78, 0x80, 0x39, 0x00);
685 iic(2, 0x78, 0x81, 0xe6, 0x00);
686 iic(2, 0x78, 0x8d, 0x00, 0x00);
687 printk(KERN_CONT ".");
688 iic(2, 0x78, 0x8e, 0x0c, 0x00);
689 iic(2, 0x78, 0x8f, 0x00, 0x00);
1da177e4 690#if 0
88f44234 691 iic(2, 0x78, 0x90, 0x00, 0x00); /* AWB on=1 off=0 */
1da177e4 692#endif
88f44234
HV		 693 iic(2, 0x78, 0x93, 0x01, 0x00);
694 iic(2, 0x78, 0x94, 0xcd, 0x00);
695 iic(2, 0x78, 0x95, 0x00, 0x00);
696 printk(KERN_CONT ".");
697 iic(2, 0x78, 0x96, 0xa0, 0x00);
698 iic(2, 0x78, 0x97, 0x00, 0x00);
699 iic(2, 0x78, 0x98, 0x60, 0x00);
700 iic(2, 0x78, 0x99, 0x01, 0x00);
701 iic(2, 0x78, 0x9a, 0x19, 0x00);
702 printk(KERN_CONT ".");
703 iic(2, 0x78, 0x9b, 0x02, 0x00);
704 iic(2, 0x78, 0x9c, 0xe8, 0x00);
705 iic(2, 0x78, 0x9d, 0x02, 0x00);
706 iic(2, 0x78, 0x9e, 0x2e, 0x00);
707 iic(2, 0x78, 0xb8, 0x78, 0x00);
708 iic(2, 0x78, 0xba, 0x05, 0x00);
1da177e4 709#if 0
88f44234 710 iic(2, 0x78, 0x83, 0x8c, 0x00); /* brightness */
1da177e4 711#endif
88f44234 712 printk(KERN_CONT ".");
1da177e4
LT		 713
714 /* color correction */
88f44234
HV		 715 iic(3, 0x78, 0x49, 0x00, 0x95); /* a */
716 iic(3, 0x78, 0x49, 0x01, 0x96); /* b */
717 iic(3, 0x78, 0x49, 0x03, 0x85); /* c */
718 iic(3, 0x78, 0x49, 0x04, 0x97); /* d */
719 iic(3, 0x78, 0x49, 0x02, 0x7e); /* e(Lo) */
720 iic(3, 0x78, 0x49, 0x05, 0xa4); /* f(Lo) */
721 iic(3, 0x78, 0x49, 0x06, 0x04); /* e(Hi) */
722 iic(3, 0x78, 0x49, 0x07, 0x04); /* e(Hi) */
723 iic(2, 0x78, 0x48, 0x01, 0x00); /* on=1 off=0 */
724
725 printk(KERN_CONT ".");
726 iic(2, 0x78, 0x11, 0x00, 0x00); /* end */
727 printk(KERN_CONT " done\n");
1da177e4
LT		 728 return 0;
729}
730
731
732void ar_release(struct video_device *vfd)
733{
601e9444 734 struct ar_device *ar = video_get_drvdata(vfd);
3593cab5 735 mutex_lock(&ar->lock);
1da177e4
LT		 736 video_device_release(vfd);
737}
738
739/****************************************************************************
740 *
741 * Video4Linux Module functions
742 *
743 ****************************************************************************/
7d43cd53
HV		 744static struct ar_device ardev;
745
bec43661 746static int ar_exclusive_open(struct file *file)
7d43cd53
HV		 747{
748 return test_and_set_bit(0, &ardev.in_use) ? -EBUSY : 0;
749}
750
bec43661 751static int ar_exclusive_release(struct file *file)
7d43cd53
HV		 752{
753 clear_bit(0, &ardev.in_use);
754 return 0;
755}
756
bec43661 757static const struct v4l2_file_operations ar_fops = {
1da177e4 758 .owner = THIS_MODULE,
7d43cd53
HV		 759 .open = ar_exclusive_open,
760 .release = ar_exclusive_release,
1da177e4
LT		 761 .read = ar_read,
762 .ioctl = ar_ioctl,
1da177e4
LT		 763};
764
765static struct video_device ar_template = {
1da177e4 766 .name = "Colour AR VGA",
1da177e4
LT		 767 .fops = &ar_fops,
768 .release = ar_release,
1da177e4
LT		 769};
770
771#define ALIGN4(x) ((((int)(x)) & 0x3) == 0)
1da177e4
LT		 772
773static int __init ar_init(void)
774{
775 struct ar_device *ar;
776 int ret;
777 int i;
778
779 DEBUG(1, "ar_init:\n");
780 ret = -EIO;
781 printk(KERN_INFO "arv: Colour AR VGA driver %s\n", VERSION);
782
783 ar = &ardev;
784 memset(ar, 0, sizeof(struct ar_device));
785
786#if USE_INT
787 /* allocate a DMA buffer for 1 line. */
788 ar->line_buff = kmalloc(MAX_AR_LINE_BYTES, GFP_KERNEL | GFP_DMA);
88f44234
HV		 789 if (ar->line_buff == NULL || !ALIGN4(ar->line_buff)) {
790 printk(KERN_ERR "arv: buffer allocation failed for DMA.\n");
1da177e4
LT		 791 ret = -ENOMEM;
792 goto out_end;
793 }
794#endif
795 /* allocate buffers for a frame */
796 for (i = 0; i < MAX_AR_HEIGHT; i++) {
797 ar->frame[i] = kmalloc(MAX_AR_LINE_BYTES, GFP_KERNEL);
88f44234
HV		 798 if (ar->frame[i] == NULL || !ALIGN4(ar->frame[i])) {
799 printk(KERN_ERR "arv: buffer allocation failed for frame.\n");
1da177e4
LT		 800 ret = -ENOMEM;
801 goto out_line_buff;
802 }
803 }
804
805 ar->vdev = video_device_alloc();
806 if (!ar->vdev) {
807 printk(KERN_ERR "arv: video_device_alloc() failed\n");
808 return -ENOMEM;
809 }
810 memcpy(ar->vdev, &ar_template, sizeof(ar_template));
601e9444 811 video_set_drvdata(ar->vdev, ar);
1da177e4
LT		 812
813 if (vga) {
814 ar->width = AR_WIDTH_VGA;
815 ar->height = AR_HEIGHT_VGA;
816 ar->size = AR_SIZE_VGA;
817 ar->frame_bytes = AR_FRAME_BYTES_VGA;
818 ar->line_bytes = AR_LINE_BYTES_VGA;
819 if (vga_interlace)
820 ar->mode = AR_MODE_INTERLACE;
821 else
822 ar->mode = AR_MODE_NORMAL;
823 } else {
824 ar->width = AR_WIDTH_QVGA;
825 ar->height = AR_HEIGHT_QVGA;
826 ar->size = AR_SIZE_QVGA;
827 ar->frame_bytes = AR_FRAME_BYTES_QVGA;
828 ar->line_bytes = AR_LINE_BYTES_QVGA;
829 ar->mode = AR_MODE_INTERLACE;
830 }
3593cab5 831 mutex_init(&ar->lock);
1da177e4
LT		 832 init_waitqueue_head(&ar->wait);
833
834#if USE_INT
835 if (request_irq(M32R_IRQ_INT3, ar_interrupt, 0, "arv", ar)) {
88f44234 836 printk(KERN_ERR "arv: request_irq(%d) failed.\n", M32R_IRQ_INT3);
1da177e4
LT		 837 ret = -EIO;
838 goto out_irq;
839 }
840#endif
841
842 if (ar_initialize(ar->vdev) != 0) {
88f44234 843 printk(KERN_ERR "arv: M64278 not found.\n");
1da177e4
LT		 844 ret = -ENODEV;
845 goto out_dev;
846 }
847
848 /*
849 * ok, we can initialize h/w according to parameters,
850 * so register video device as a frame grabber type.
851 * device is named "video[0-64]".
852 * video_register_device() initializes h/w using ar_initialize().
d56410e0 853 */
1da177e4
LT		 854 if (video_register_device(ar->vdev, VFL_TYPE_GRABBER, video_nr) != 0) {
855 /* return -1, -ENFILE(full) or others */
88f44234 856 printk(KERN_ERR "arv: register video (Colour AR) failed.\n");
1da177e4
LT		 857 ret = -ENODEV;
858 goto out_dev;
859 }
860
88f44234 861 printk(KERN_INFO "%s: Found M64278 VGA (IRQ %d, Freq %dMHz).\n",
38c7c036 862 video_device_node_name(ar->vdev), M32R_IRQ_INT3, freq);
1da177e4
LT		 863
864 return 0;
865
866out_dev:
867#if USE_INT
868 free_irq(M32R_IRQ_INT3, ar);
869
870out_irq:
871#endif
2ea75330
JJ		 872 for (i = 0; i < MAX_AR_HEIGHT; i++)
873 kfree(ar->frame[i]);
1da177e4
LT		 874
875out_line_buff:
876#if USE_INT
877 kfree(ar->line_buff);
878
879out_end:
880#endif
881 return ret;
882}
883
884
885static int __init ar_init_module(void)
886{
887 freq = (boot_cpu_data.bus_clock / 1000000);
88f44234 888 printk(KERN_INFO "arv: Bus clock %d\n", freq);
1da177e4
LT		 889 if (freq != 50 && freq != 75)
890 freq = DEFAULT_FREQ;
891 return ar_init();
892}
893
894static void __exit ar_cleanup_module(void)
895{
896 struct ar_device *ar;
897 int i;
898
899 ar = &ardev;
900 video_unregister_device(ar->vdev);
901#if USE_INT
902 free_irq(M32R_IRQ_INT3, ar);
903#endif
2ea75330
JJ		 904 for (i = 0; i < MAX_AR_HEIGHT; i++)
905 kfree(ar->frame[i]);
1da177e4
LT		 906#if USE_INT
907 kfree(ar->line_buff);
908#endif
909}
910
911module_init(ar_init_module);
912module_exit(ar_cleanup_module);
913
914MODULE_AUTHOR("Takeo Takahashi <takahashi.takeo@renesas.com>");
915MODULE_DESCRIPTION("Colour AR M64278(VGA) for Video4Linux");
916MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)