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1da177e4 LT |
1 | /* |
2 | * Colour AR M64278(VGA) driver for Video4Linux | |
3 | * | |
4 | * Copyright (C) 2003 Takeo Takahashi <takahashi.takeo@renesas.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * Some code is taken from AR driver sample program for M3T-M32700UT. | |
12 | * | |
13 | * AR driver sample (M32R SDK): | |
14 | * Copyright (c) 2003 RENESAS TECHNOROGY CORPORATION | |
15 | * AND RENESAS SOLUTIONS CORPORATION | |
16 | * All Rights Reserved. | |
17 | * | |
18 | * 2003-09-01: Support w3cam by Takeo Takahashi | |
19 | */ | |
20 | ||
1da177e4 | 21 | #include <linux/init.h> |
1da177e4 | 22 | #include <linux/module.h> |
1da177e4 LT |
23 | #include <linux/delay.h> |
24 | #include <linux/errno.h> | |
25 | #include <linux/fs.h> | |
26 | #include <linux/init.h> | |
27 | #include <linux/kernel.h> | |
28 | #include <linux/slab.h> | |
29 | #include <linux/mm.h> | |
30 | #include <linux/sched.h> | |
31 | #include <linux/videodev.h> | |
5e87efa3 | 32 | #include <media/v4l2-common.h> |
3593cab5 | 33 | #include <linux/mutex.h> |
1da177e4 | 34 | |
1da177e4 LT |
35 | #include <asm/uaccess.h> |
36 | #include <asm/m32r.h> | |
37 | #include <asm/io.h> | |
38 | #include <asm/dma.h> | |
39 | #include <asm/byteorder.h> | |
40 | ||
41 | #if 0 | |
42 | #define DEBUG(n, args...) printk(args) | |
43 | #define CHECK_LOST 1 | |
44 | #else | |
45 | #define DEBUG(n, args...) | |
46 | #define CHECK_LOST 0 | |
47 | #endif | |
48 | ||
49 | /* | |
50 | * USE_INT is always 0, interrupt mode is not available | |
51 | * on linux due to lack of speed | |
52 | */ | |
53 | #define USE_INT 0 /* Don't modify */ | |
54 | ||
55 | #define VERSION "0.03" | |
56 | ||
57 | #define ar_inl(addr) inl((unsigned long)(addr)) | |
58 | #define ar_outl(val, addr) outl((unsigned long)(val),(unsigned long)(addr)) | |
59 | ||
60 | extern struct cpuinfo_m32r boot_cpu_data; | |
61 | ||
62 | /* | |
63 | * CCD pixel size | |
64 | * Note that M32700UT does not support CIF mode, but QVGA is | |
65 | * supported by M32700UT hardware using VGA mode of AR LSI. | |
66 | * | |
67 | * Supported: VGA (Normal mode, Interlace mode) | |
68 | * QVGA (Always Interlace mode of VGA) | |
69 | * | |
70 | */ | |
71 | #define AR_WIDTH_VGA 640 | |
72 | #define AR_HEIGHT_VGA 480 | |
73 | #define AR_WIDTH_QVGA 320 | |
74 | #define AR_HEIGHT_QVGA 240 | |
75 | #define MIN_AR_WIDTH AR_WIDTH_QVGA | |
76 | #define MIN_AR_HEIGHT AR_HEIGHT_QVGA | |
77 | #define MAX_AR_WIDTH AR_WIDTH_VGA | |
78 | #define MAX_AR_HEIGHT AR_HEIGHT_VGA | |
79 | ||
80 | /* bits & bytes per pixel */ | |
81 | #define AR_BITS_PER_PIXEL 16 | |
82 | #define AR_BYTES_PER_PIXEL (AR_BITS_PER_PIXEL/8) | |
83 | ||
84 | /* line buffer size */ | |
85 | #define AR_LINE_BYTES_VGA (AR_WIDTH_VGA * AR_BYTES_PER_PIXEL) | |
86 | #define AR_LINE_BYTES_QVGA (AR_WIDTH_QVGA * AR_BYTES_PER_PIXEL) | |
87 | #define MAX_AR_LINE_BYTES AR_LINE_BYTES_VGA | |
88 | ||
89 | /* frame size & type */ | |
90 | #define AR_FRAME_BYTES_VGA \ | |
91 | (AR_WIDTH_VGA * AR_HEIGHT_VGA * AR_BYTES_PER_PIXEL) | |
92 | #define AR_FRAME_BYTES_QVGA \ | |
93 | (AR_WIDTH_QVGA * AR_HEIGHT_QVGA * AR_BYTES_PER_PIXEL) | |
94 | #define MAX_AR_FRAME_BYTES \ | |
95 | (MAX_AR_WIDTH * MAX_AR_HEIGHT * AR_BYTES_PER_PIXEL) | |
96 | ||
97 | #define AR_MAX_FRAME 15 | |
98 | ||
99 | /* capture size */ | |
100 | #define AR_SIZE_VGA 0 | |
101 | #define AR_SIZE_QVGA 1 | |
102 | ||
103 | /* capture mode */ | |
104 | #define AR_MODE_INTERLACE 0 | |
105 | #define AR_MODE_NORMAL 1 | |
106 | ||
107 | struct ar_device { | |
108 | struct video_device *vdev; | |
109 | unsigned int start_capture; /* duaring capture in INT. mode. */ | |
110 | #if USE_INT | |
111 | unsigned char *line_buff; /* DMA line buffer */ | |
112 | #endif | |
113 | unsigned char *frame[MAX_AR_HEIGHT]; /* frame data */ | |
114 | short size; /* capture size */ | |
115 | short mode; /* capture mode */ | |
116 | int width, height; | |
117 | int frame_bytes, line_bytes; | |
118 | wait_queue_head_t wait; | |
3593cab5 | 119 | struct mutex lock; |
1da177e4 LT |
120 | }; |
121 | ||
122 | static int video_nr = -1; /* video device number (first free) */ | |
123 | static unsigned char yuv[MAX_AR_FRAME_BYTES]; | |
124 | ||
125 | /* module parameters */ | |
126 | /* default frequency */ | |
127 | #define DEFAULT_FREQ 50 /* 50 or 75 (MHz) is available as BCLK */ | |
128 | static int freq = DEFAULT_FREQ; /* BCLK: available 50 or 70 (MHz) */ | |
129 | static int vga = 0; /* default mode(0:QVGA mode, other:VGA mode) */ | |
130 | static int vga_interlace = 0; /* 0 is normal mode for, else interlace mode */ | |
9b565eb7 ES |
131 | module_param(freq, int, 0); |
132 | module_param(vga, int, 0); | |
133 | module_param(vga_interlace, int, 0); | |
1da177e4 LT |
134 | |
135 | static int ar_initialize(struct video_device *dev); | |
136 | ||
137 | static inline void wait_for_vsync(void) | |
138 | { | |
139 | while (ar_inl(ARVCR0) & ARVCR0_VDS) /* wait for VSYNC */ | |
140 | cpu_relax(); | |
141 | while (!(ar_inl(ARVCR0) & ARVCR0_VDS)) /* wait for VSYNC */ | |
142 | cpu_relax(); | |
143 | } | |
144 | ||
145 | static inline void wait_acknowledge(void) | |
146 | { | |
147 | int i; | |
148 | ||
149 | for (i = 0; i < 1000; i++) | |
150 | cpu_relax(); | |
151 | while (ar_inl(PLDI2CSTS) & PLDI2CSTS_NOACK) | |
152 | cpu_relax(); | |
153 | } | |
154 | ||
155 | /******************************************************************* | |
156 | * I2C functions | |
157 | *******************************************************************/ | |
158 | void iic(int n, unsigned long addr, unsigned long data1, unsigned long data2, | |
159 | unsigned long data3) | |
160 | { | |
161 | int i; | |
162 | ||
d56410e0 MCC |
163 | /* Slave Address */ |
164 | ar_outl(addr, PLDI2CDATA); | |
1da177e4 LT |
165 | wait_for_vsync(); |
166 | ||
d56410e0 MCC |
167 | /* Start */ |
168 | ar_outl(1, PLDI2CCND); | |
1da177e4 LT |
169 | wait_acknowledge(); |
170 | ||
171 | /* Transfer data 1 */ | |
d56410e0 | 172 | ar_outl(data1, PLDI2CDATA); |
1da177e4 | 173 | wait_for_vsync(); |
d56410e0 | 174 | ar_outl(PLDI2CSTEN_STEN, PLDI2CSTEN); |
1da177e4 LT |
175 | wait_acknowledge(); |
176 | ||
177 | /* Transfer data 2 */ | |
d56410e0 | 178 | ar_outl(data2, PLDI2CDATA); |
1da177e4 | 179 | wait_for_vsync(); |
d56410e0 | 180 | ar_outl(PLDI2CSTEN_STEN, PLDI2CSTEN); |
1da177e4 LT |
181 | wait_acknowledge(); |
182 | ||
183 | if (n == 3) { | |
184 | /* Transfer data 3 */ | |
d56410e0 | 185 | ar_outl(data3, PLDI2CDATA); |
1da177e4 | 186 | wait_for_vsync(); |
d56410e0 | 187 | ar_outl(PLDI2CSTEN_STEN, PLDI2CSTEN); |
1da177e4 | 188 | wait_acknowledge(); |
d56410e0 | 189 | } |
1da177e4 | 190 | |
d56410e0 | 191 | /* Stop */ |
1da177e4 LT |
192 | for (i = 0; i < 100; i++) |
193 | cpu_relax(); | |
d56410e0 MCC |
194 | ar_outl(2, PLDI2CCND); |
195 | ar_outl(2, PLDI2CCND); | |
1da177e4 LT |
196 | |
197 | while (ar_inl(PLDI2CSTS) & PLDI2CSTS_BB) | |
198 | cpu_relax(); | |
199 | } | |
200 | ||
201 | ||
202 | void init_iic(void) | |
203 | { | |
204 | DEBUG(1, "init_iic:\n"); | |
205 | ||
d56410e0 | 206 | /* |
1da177e4 LT |
207 | * ICU Setting (iic) |
208 | */ | |
d56410e0 MCC |
209 | /* I2C Setting */ |
210 | ar_outl(0x0, PLDI2CCR); /* I2CCR Disable */ | |
211 | ar_outl(0x0300, PLDI2CMOD); /* I2CMOD ACK/8b-data/7b-addr/auto */ | |
212 | ar_outl(0x1, PLDI2CACK); /* I2CACK ACK */ | |
1da177e4 | 213 | |
657de3cd | 214 | /* I2C CLK */ |
d56410e0 | 215 | /* 50MH-100k */ |
1da177e4 | 216 | if (freq == 75) { |
d56410e0 | 217 | ar_outl(369, PLDI2CFREQ); /* BCLK = 75MHz */ |
1da177e4 LT |
218 | } else if (freq == 50) { |
219 | ar_outl(244, PLDI2CFREQ); /* BCLK = 50MHz */ | |
220 | } else { | |
221 | ar_outl(244, PLDI2CFREQ); /* default: BCLK = 50MHz */ | |
222 | } | |
d56410e0 | 223 | ar_outl(0x1, PLDI2CCR); /* I2CCR Enable */ |
1da177e4 LT |
224 | } |
225 | ||
226 | /************************************************************************** | |
227 | * | |
228 | * Video4Linux Interface functions | |
229 | * | |
230 | **************************************************************************/ | |
231 | ||
232 | static inline void disable_dma(void) | |
233 | { | |
234 | ar_outl(0x8000, M32R_DMAEN_PORTL); /* disable DMA0 */ | |
235 | } | |
236 | ||
237 | static inline void enable_dma(void) | |
238 | { | |
239 | ar_outl(0x8080, M32R_DMAEN_PORTL); /* enable DMA0 */ | |
240 | } | |
241 | ||
242 | static inline void clear_dma_status(void) | |
243 | { | |
244 | ar_outl(0x8000, M32R_DMAEDET_PORTL); /* clear status */ | |
245 | } | |
246 | ||
247 | static inline void wait_for_vertical_sync(int exp_line) | |
248 | { | |
249 | #if CHECK_LOST | |
250 | int tmout = 10000; /* FIXME */ | |
251 | int l; | |
252 | ||
253 | /* | |
254 | * check HCOUNT because we cannot check vertical sync. | |
d56410e0 | 255 | */ |
1da177e4 LT |
256 | for (; tmout >= 0; tmout--) { |
257 | l = ar_inl(ARVHCOUNT); | |
258 | if (l == exp_line) | |
259 | break; | |
260 | } | |
261 | if (tmout < 0) | |
262 | printk("arv: lost %d -> %d\n", exp_line, l); | |
263 | #else | |
264 | while (ar_inl(ARVHCOUNT) != exp_line) | |
265 | cpu_relax(); | |
266 | #endif | |
267 | } | |
268 | ||
269 | static ssize_t ar_read(struct file *file, char *buf, size_t count, loff_t *ppos) | |
270 | { | |
271 | struct video_device *v = video_devdata(file); | |
272 | struct ar_device *ar = v->priv; | |
273 | long ret = ar->frame_bytes; /* return read bytes */ | |
274 | unsigned long arvcr1 = 0; | |
275 | unsigned long flags; | |
276 | unsigned char *p; | |
277 | int h, w; | |
278 | unsigned char *py, *pu, *pv; | |
279 | #if ! USE_INT | |
280 | int l; | |
281 | #endif | |
282 | ||
283 | DEBUG(1, "ar_read()\n"); | |
284 | ||
285 | if (ar->size == AR_SIZE_QVGA) | |
286 | arvcr1 |= ARVCR1_QVGA; | |
287 | if (ar->mode == AR_MODE_NORMAL) | |
288 | arvcr1 |= ARVCR1_NORMAL; | |
289 | ||
3593cab5 | 290 | mutex_lock(&ar->lock); |
1da177e4 LT |
291 | |
292 | #if USE_INT | |
293 | local_irq_save(flags); | |
294 | disable_dma(); | |
295 | ar_outl(0xa1871300, M32R_DMA0CR0_PORTL); | |
296 | ar_outl(0x01000000, M32R_DMA0CR1_PORTL); | |
297 | ||
298 | /* set AR FIFO address as source(BSEL5) */ | |
299 | ar_outl(ARDATA32, M32R_DMA0CSA_PORTL); | |
300 | ar_outl(ARDATA32, M32R_DMA0RSA_PORTL); | |
301 | ar_outl(ar->line_buff, M32R_DMA0CDA_PORTL); /* destination addr. */ | |
302 | ar_outl(ar->line_buff, M32R_DMA0RDA_PORTL); /* reload address */ | |
303 | ar_outl(ar->line_bytes, M32R_DMA0CBCUT_PORTL); /* byte count (bytes) */ | |
304 | ar_outl(ar->line_bytes, M32R_DMA0RBCUT_PORTL); /* reload count (bytes) */ | |
305 | ||
306 | /* | |
307 | * Okey , kicks AR LSI to invoke an interrupt | |
308 | */ | |
309 | ar->start_capture = 0; | |
310 | ar_outl(arvcr1 | ARVCR1_HIEN, ARVCR1); | |
311 | local_irq_restore(flags); | |
312 | /* .... AR interrupts .... */ | |
313 | interruptible_sleep_on(&ar->wait); | |
314 | if (signal_pending(current)) { | |
315 | printk("arv: interrupted while get frame data.\n"); | |
316 | ret = -EINTR; | |
317 | goto out_up; | |
318 | } | |
319 | #else /* ! USE_INT */ | |
320 | /* polling */ | |
321 | ar_outl(arvcr1, ARVCR1); | |
322 | disable_dma(); | |
323 | ar_outl(0x8000, M32R_DMAEDET_PORTL); | |
324 | ar_outl(0xa0861300, M32R_DMA0CR0_PORTL); | |
325 | ar_outl(0x01000000, M32R_DMA0CR1_PORTL); | |
326 | ar_outl(ARDATA32, M32R_DMA0CSA_PORTL); | |
327 | ar_outl(ARDATA32, M32R_DMA0RSA_PORTL); | |
328 | ar_outl(ar->line_bytes, M32R_DMA0CBCUT_PORTL); | |
329 | ar_outl(ar->line_bytes, M32R_DMA0RBCUT_PORTL); | |
330 | ||
331 | local_irq_save(flags); | |
332 | while (ar_inl(ARVHCOUNT) != 0) /* wait for 0 */ | |
333 | cpu_relax(); | |
334 | if (ar->mode == AR_MODE_INTERLACE && ar->size == AR_SIZE_VGA) { | |
335 | for (h = 0; h < ar->height; h++) { | |
336 | wait_for_vertical_sync(h); | |
337 | if (h < (AR_HEIGHT_VGA/2)) | |
338 | l = h << 1; | |
339 | else | |
340 | l = (((h - (AR_HEIGHT_VGA/2)) << 1) + 1); | |
341 | ar_outl(virt_to_phys(ar->frame[l]), M32R_DMA0CDA_PORTL); | |
342 | enable_dma(); | |
343 | while (!(ar_inl(M32R_DMAEDET_PORTL) & 0x8000)) | |
344 | cpu_relax(); | |
345 | disable_dma(); | |
346 | clear_dma_status(); | |
347 | ar_outl(0xa0861300, M32R_DMA0CR0_PORTL); | |
348 | } | |
349 | } else { | |
350 | for (h = 0; h < ar->height; h++) { | |
351 | wait_for_vertical_sync(h); | |
352 | ar_outl(virt_to_phys(ar->frame[h]), M32R_DMA0CDA_PORTL); | |
353 | enable_dma(); | |
354 | while (!(ar_inl(M32R_DMAEDET_PORTL) & 0x8000)) | |
355 | cpu_relax(); | |
356 | disable_dma(); | |
357 | clear_dma_status(); | |
358 | ar_outl(0xa0861300, M32R_DMA0CR0_PORTL); | |
359 | } | |
360 | } | |
361 | local_irq_restore(flags); | |
362 | #endif /* ! USE_INT */ | |
363 | ||
364 | /* | |
365 | * convert YUV422 to YUV422P | |
366 | * +--------------------+ | |
367 | * | Y0,Y1,... | | |
368 | * | ..............Yn | | |
369 | * +--------------------+ | |
370 | * | U0,U1,........Un | | |
371 | * +--------------------+ | |
372 | * | V0,V1,........Vn | | |
373 | * +--------------------+ | |
374 | */ | |
375 | py = yuv; | |
376 | pu = py + (ar->frame_bytes / 2); | |
377 | pv = pu + (ar->frame_bytes / 4); | |
378 | for (h = 0; h < ar->height; h++) { | |
379 | p = ar->frame[h]; | |
380 | for (w = 0; w < ar->line_bytes; w += 4) { | |
381 | *py++ = *p++; | |
382 | *pu++ = *p++; | |
383 | *py++ = *p++; | |
384 | *pv++ = *p++; | |
385 | } | |
386 | } | |
387 | if (copy_to_user(buf, yuv, ar->frame_bytes)) { | |
388 | printk("arv: failed while copy_to_user yuv.\n"); | |
389 | ret = -EFAULT; | |
390 | goto out_up; | |
391 | } | |
392 | DEBUG(1, "ret = %d\n", ret); | |
393 | out_up: | |
3593cab5 | 394 | mutex_unlock(&ar->lock); |
1da177e4 LT |
395 | return ret; |
396 | } | |
397 | ||
398 | static int ar_do_ioctl(struct inode *inode, struct file *file, | |
399 | unsigned int cmd, void *arg) | |
400 | { | |
401 | struct video_device *dev = video_devdata(file); | |
402 | struct ar_device *ar = dev->priv; | |
403 | ||
404 | DEBUG(1, "ar_ioctl()\n"); | |
405 | switch(cmd) { | |
406 | case VIDIOCGCAP: | |
407 | { | |
408 | struct video_capability *b = arg; | |
409 | DEBUG(1, "VIDIOCGCAP:\n"); | |
410 | strcpy(b->name, ar->vdev->name); | |
411 | b->type = VID_TYPE_CAPTURE; | |
412 | b->channels = 0; | |
413 | b->audios = 0; | |
414 | b->maxwidth = MAX_AR_WIDTH; | |
415 | b->maxheight = MAX_AR_HEIGHT; | |
416 | b->minwidth = MIN_AR_WIDTH; | |
417 | b->minheight = MIN_AR_HEIGHT; | |
418 | return 0; | |
419 | } | |
420 | case VIDIOCGCHAN: | |
421 | DEBUG(1, "VIDIOCGCHAN:\n"); | |
422 | return 0; | |
423 | case VIDIOCSCHAN: | |
424 | DEBUG(1, "VIDIOCSCHAN:\n"); | |
425 | return 0; | |
426 | case VIDIOCGTUNER: | |
427 | DEBUG(1, "VIDIOCGTUNER:\n"); | |
428 | return 0; | |
429 | case VIDIOCSTUNER: | |
430 | DEBUG(1, "VIDIOCSTUNER:\n"); | |
431 | return 0; | |
432 | case VIDIOCGPICT: | |
433 | DEBUG(1, "VIDIOCGPICT:\n"); | |
434 | return 0; | |
435 | case VIDIOCSPICT: | |
436 | DEBUG(1, "VIDIOCSPICT:\n"); | |
437 | return 0; | |
438 | case VIDIOCCAPTURE: | |
439 | DEBUG(1, "VIDIOCCAPTURE:\n"); | |
440 | return -EINVAL; | |
441 | case VIDIOCGWIN: | |
442 | { | |
443 | struct video_window *w = arg; | |
444 | DEBUG(1, "VIDIOCGWIN:\n"); | |
445 | memset(w, 0, sizeof(w)); | |
446 | w->width = ar->width; | |
447 | w->height = ar->height; | |
448 | return 0; | |
449 | } | |
450 | case VIDIOCSWIN: | |
451 | { | |
452 | struct video_window *w = arg; | |
453 | DEBUG(1, "VIDIOCSWIN:\n"); | |
454 | if ((w->width != AR_WIDTH_VGA || w->height != AR_HEIGHT_VGA) && | |
455 | (w->width != AR_WIDTH_QVGA || w->height != AR_HEIGHT_QVGA)) | |
456 | return -EINVAL; | |
457 | ||
3593cab5 | 458 | mutex_lock(&ar->lock); |
1da177e4 LT |
459 | ar->width = w->width; |
460 | ar->height = w->height; | |
461 | if (ar->width == AR_WIDTH_VGA) { | |
462 | ar->size = AR_SIZE_VGA; | |
463 | ar->frame_bytes = AR_FRAME_BYTES_VGA; | |
464 | ar->line_bytes = AR_LINE_BYTES_VGA; | |
465 | if (vga_interlace) | |
466 | ar->mode = AR_MODE_INTERLACE; | |
467 | else | |
468 | ar->mode = AR_MODE_NORMAL; | |
469 | } else { | |
470 | ar->size = AR_SIZE_QVGA; | |
471 | ar->frame_bytes = AR_FRAME_BYTES_QVGA; | |
472 | ar->line_bytes = AR_LINE_BYTES_QVGA; | |
473 | ar->mode = AR_MODE_INTERLACE; | |
474 | } | |
3593cab5 | 475 | mutex_unlock(&ar->lock); |
1da177e4 LT |
476 | return 0; |
477 | } | |
478 | case VIDIOCGFBUF: | |
479 | DEBUG(1, "VIDIOCGFBUF:\n"); | |
480 | return -EINVAL; | |
481 | case VIDIOCSFBUF: | |
482 | DEBUG(1, "VIDIOCSFBUF:\n"); | |
483 | return -EINVAL; | |
484 | case VIDIOCKEY: | |
485 | DEBUG(1, "VIDIOCKEY:\n"); | |
486 | return 0; | |
487 | case VIDIOCGFREQ: | |
488 | DEBUG(1, "VIDIOCGFREQ:\n"); | |
489 | return -EINVAL; | |
490 | case VIDIOCSFREQ: | |
491 | DEBUG(1, "VIDIOCSFREQ:\n"); | |
492 | return -EINVAL; | |
493 | case VIDIOCGAUDIO: | |
494 | DEBUG(1, "VIDIOCGAUDIO:\n"); | |
495 | return -EINVAL; | |
496 | case VIDIOCSAUDIO: | |
497 | DEBUG(1, "VIDIOCSAUDIO:\n"); | |
498 | return -EINVAL; | |
499 | case VIDIOCSYNC: | |
500 | DEBUG(1, "VIDIOCSYNC:\n"); | |
501 | return -EINVAL; | |
502 | case VIDIOCMCAPTURE: | |
503 | DEBUG(1, "VIDIOCMCAPTURE:\n"); | |
504 | return -EINVAL; | |
505 | case VIDIOCGMBUF: | |
506 | DEBUG(1, "VIDIOCGMBUF:\n"); | |
507 | return -EINVAL; | |
508 | case VIDIOCGUNIT: | |
509 | DEBUG(1, "VIDIOCGUNIT:\n"); | |
510 | return -EINVAL; | |
511 | case VIDIOCGCAPTURE: | |
512 | DEBUG(1, "VIDIOCGCAPTURE:\n"); | |
513 | return -EINVAL; | |
514 | case VIDIOCSCAPTURE: | |
515 | DEBUG(1, "VIDIOCSCAPTURE:\n"); | |
516 | return -EINVAL; | |
517 | case VIDIOCSPLAYMODE: | |
518 | DEBUG(1, "VIDIOCSPLAYMODE:\n"); | |
519 | return -EINVAL; | |
520 | case VIDIOCSWRITEMODE: | |
521 | DEBUG(1, "VIDIOCSWRITEMODE:\n"); | |
522 | return -EINVAL; | |
523 | case VIDIOCGPLAYINFO: | |
524 | DEBUG(1, "VIDIOCGPLAYINFO:\n"); | |
525 | return -EINVAL; | |
526 | case VIDIOCSMICROCODE: | |
527 | DEBUG(1, "VIDIOCSMICROCODE:\n"); | |
528 | return -EINVAL; | |
529 | case VIDIOCGVBIFMT: | |
530 | DEBUG(1, "VIDIOCGVBIFMT:\n"); | |
531 | return -EINVAL; | |
532 | case VIDIOCSVBIFMT: | |
533 | DEBUG(1, "VIDIOCSVBIFMT:\n"); | |
534 | return -EINVAL; | |
535 | default: | |
536 | DEBUG(1, "Unknown ioctl(0x%08x)\n", cmd); | |
537 | return -ENOIOCTLCMD; | |
538 | } | |
539 | return 0; | |
540 | } | |
541 | ||
542 | static int ar_ioctl(struct inode *inode, struct file *file, unsigned int cmd, | |
543 | unsigned long arg) | |
544 | { | |
545 | return video_usercopy(inode, file, cmd, arg, ar_do_ioctl); | |
546 | } | |
547 | ||
548 | #if USE_INT | |
549 | /* | |
550 | * Interrupt handler | |
551 | */ | |
552 | static void ar_interrupt(int irq, void *dev, struct pt_regs *regs) | |
553 | { | |
554 | struct ar_device *ar = dev; | |
555 | unsigned int line_count; | |
556 | unsigned int line_number; | |
557 | unsigned int arvcr1; | |
558 | ||
559 | line_count = ar_inl(ARVHCOUNT); /* line number */ | |
560 | if (ar->mode == AR_MODE_INTERLACE && ar->size == AR_SIZE_VGA) { | |
561 | /* operations for interlace mode */ | |
562 | if ( line_count < (AR_HEIGHT_VGA/2) ) /* even line */ | |
563 | line_number = (line_count << 1); | |
d56410e0 MCC |
564 | else /* odd line */ |
565 | line_number = | |
1da177e4 LT |
566 | (((line_count - (AR_HEIGHT_VGA/2)) << 1) + 1); |
567 | } else { | |
568 | line_number = line_count; | |
569 | } | |
570 | ||
571 | if (line_number == 0) { | |
572 | /* | |
573 | * It is an interrupt for line 0. | |
574 | * we have to start capture. | |
575 | */ | |
576 | disable_dma(); | |
577 | #if 0 | |
578 | ar_outl(ar->line_buff, M32R_DMA0CDA_PORTL); /* needless? */ | |
579 | #endif | |
580 | memcpy(ar->frame[0], ar->line_buff, ar->line_bytes); | |
581 | #if 0 | |
582 | ar_outl(0xa1861300, M32R_DMA0CR0_PORTL); | |
583 | #endif | |
584 | enable_dma(); | |
585 | ar->start_capture = 1; /* during capture */ | |
586 | return; | |
587 | } | |
588 | ||
589 | if (ar->start_capture == 1 && line_number <= (ar->height - 1)) { | |
590 | disable_dma(); | |
591 | memcpy(ar->frame[line_number], ar->line_buff, ar->line_bytes); | |
592 | ||
593 | /* | |
594 | * if captured all line of a frame, disable AR interrupt | |
595 | * and wake a process up. | |
596 | */ | |
597 | if (line_number == (ar->height - 1)) { /* end of line */ | |
598 | ||
599 | ar->start_capture = 0; | |
600 | ||
601 | /* disable AR interrupt request */ | |
602 | arvcr1 = ar_inl(ARVCR1); | |
603 | arvcr1 &= ~ARVCR1_HIEN; /* clear int. flag */ | |
604 | ar_outl(arvcr1, ARVCR1); /* disable */ | |
605 | wake_up_interruptible(&ar->wait); | |
606 | } else { | |
607 | #if 0 | |
608 | ar_outl(ar->line_buff, M32R_DMA0CDA_PORTL); | |
609 | ar_outl(0xa1861300, M32R_DMA0CR0_PORTL); | |
610 | #endif | |
611 | enable_dma(); | |
612 | } | |
613 | } | |
614 | } | |
615 | #endif | |
616 | ||
617 | /* | |
618 | * ar_initialize() | |
619 | * ar_initialize() is called by video_register_device() and | |
620 | * initializes AR LSI and peripherals. | |
621 | * | |
622 | * -1 is returned in all failures. | |
623 | * 0 is returned in success. | |
624 | * | |
625 | */ | |
626 | static int ar_initialize(struct video_device *dev) | |
627 | { | |
628 | struct ar_device *ar = dev->priv; | |
629 | unsigned long cr = 0; | |
630 | int i,found=0; | |
631 | ||
632 | DEBUG(1, "ar_initialize:\n"); | |
633 | ||
634 | /* | |
635 | * initialize AR LSI | |
636 | */ | |
637 | ar_outl(0, ARVCR0); /* assert reset of AR LSI */ | |
638 | for (i = 0; i < 0x18; i++) /* wait for over 10 cycles @ 27MHz */ | |
639 | cpu_relax(); | |
640 | ar_outl(ARVCR0_RST, ARVCR0); /* negate reset of AR LSI (enable) */ | |
641 | for (i = 0; i < 0x40d; i++) /* wait for over 420 cycles @ 27MHz */ | |
642 | cpu_relax(); | |
643 | ||
644 | /* AR uses INT3 of CPU as interrupt pin. */ | |
645 | ar_outl(ARINTSEL_INT3, ARINTSEL); | |
646 | ||
647 | if (ar->size == AR_SIZE_QVGA) | |
648 | cr |= ARVCR1_QVGA; | |
649 | if (ar->mode == AR_MODE_NORMAL) | |
650 | cr |= ARVCR1_NORMAL; | |
651 | ar_outl(cr, ARVCR1); | |
652 | ||
d56410e0 | 653 | /* |
1da177e4 LT |
654 | * Initialize IIC so that CPU can communicate with AR LSI, |
655 | * and send boot commands to AR LSI. | |
656 | */ | |
657 | init_iic(); | |
658 | ||
659 | for (i = 0; i < 0x100000; i++) { /* > 0xa1d10, 56ms */ | |
660 | if ((ar_inl(ARVCR0) & ARVCR0_VDS)) { /* VSYNC */ | |
661 | found = 1; | |
662 | break; | |
663 | } | |
664 | } | |
665 | ||
666 | if (found == 0) | |
667 | return -ENODEV; | |
668 | ||
669 | printk("arv: Initializing "); | |
670 | ||
671 | iic(2,0x78,0x11,0x01,0x00); /* start */ | |
672 | iic(3,0x78,0x12,0x00,0x06); | |
673 | iic(3,0x78,0x12,0x12,0x30); | |
674 | iic(3,0x78,0x12,0x15,0x58); | |
675 | iic(3,0x78,0x12,0x17,0x30); | |
676 | printk("."); | |
677 | iic(3,0x78,0x12,0x1a,0x97); | |
678 | iic(3,0x78,0x12,0x1b,0xff); | |
679 | iic(3,0x78,0x12,0x1c,0xff); | |
680 | iic(3,0x78,0x12,0x26,0x10); | |
681 | iic(3,0x78,0x12,0x27,0x00); | |
682 | printk("."); | |
683 | iic(2,0x78,0x34,0x02,0x00); | |
684 | iic(2,0x78,0x7a,0x10,0x00); | |
685 | iic(2,0x78,0x80,0x39,0x00); | |
686 | iic(2,0x78,0x81,0xe6,0x00); | |
687 | iic(2,0x78,0x8d,0x00,0x00); | |
688 | printk("."); | |
689 | iic(2,0x78,0x8e,0x0c,0x00); | |
690 | iic(2,0x78,0x8f,0x00,0x00); | |
691 | #if 0 | |
692 | iic(2,0x78,0x90,0x00,0x00); /* AWB on=1 off=0 */ | |
693 | #endif | |
694 | iic(2,0x78,0x93,0x01,0x00); | |
695 | iic(2,0x78,0x94,0xcd,0x00); | |
696 | iic(2,0x78,0x95,0x00,0x00); | |
697 | printk("."); | |
698 | iic(2,0x78,0x96,0xa0,0x00); | |
699 | iic(2,0x78,0x97,0x00,0x00); | |
700 | iic(2,0x78,0x98,0x60,0x00); | |
701 | iic(2,0x78,0x99,0x01,0x00); | |
702 | iic(2,0x78,0x9a,0x19,0x00); | |
703 | printk("."); | |
704 | iic(2,0x78,0x9b,0x02,0x00); | |
705 | iic(2,0x78,0x9c,0xe8,0x00); | |
706 | iic(2,0x78,0x9d,0x02,0x00); | |
707 | iic(2,0x78,0x9e,0x2e,0x00); | |
708 | iic(2,0x78,0xb8,0x78,0x00); | |
709 | iic(2,0x78,0xba,0x05,0x00); | |
710 | #if 0 | |
711 | iic(2,0x78,0x83,0x8c,0x00); /* brightness */ | |
712 | #endif | |
713 | printk("."); | |
714 | ||
715 | /* color correction */ | |
716 | iic(3,0x78,0x49,0x00,0x95); /* a */ | |
717 | iic(3,0x78,0x49,0x01,0x96); /* b */ | |
718 | iic(3,0x78,0x49,0x03,0x85); /* c */ | |
719 | iic(3,0x78,0x49,0x04,0x97); /* d */ | |
720 | iic(3,0x78,0x49,0x02,0x7e); /* e(Lo) */ | |
721 | iic(3,0x78,0x49,0x05,0xa4); /* f(Lo) */ | |
722 | iic(3,0x78,0x49,0x06,0x04); /* e(Hi) */ | |
723 | iic(3,0x78,0x49,0x07,0x04); /* e(Hi) */ | |
724 | iic(2,0x78,0x48,0x01,0x00); /* on=1 off=0 */ | |
725 | ||
726 | printk("."); | |
727 | iic(2,0x78,0x11,0x00,0x00); /* end */ | |
728 | printk(" done\n"); | |
729 | return 0; | |
730 | } | |
731 | ||
732 | ||
733 | void ar_release(struct video_device *vfd) | |
734 | { | |
735 | struct ar_device *ar = vfd->priv; | |
3593cab5 | 736 | mutex_lock(&ar->lock); |
1da177e4 LT |
737 | video_device_release(vfd); |
738 | } | |
739 | ||
740 | /**************************************************************************** | |
741 | * | |
742 | * Video4Linux Module functions | |
743 | * | |
744 | ****************************************************************************/ | |
745 | static struct file_operations ar_fops = { | |
746 | .owner = THIS_MODULE, | |
747 | .open = video_exclusive_open, | |
748 | .release = video_exclusive_release, | |
749 | .read = ar_read, | |
750 | .ioctl = ar_ioctl, | |
0d0fbf81 | 751 | .compat_ioctl = v4l_compat_ioctl32, |
1da177e4 LT |
752 | .llseek = no_llseek, |
753 | }; | |
754 | ||
755 | static struct video_device ar_template = { | |
756 | .owner = THIS_MODULE, | |
757 | .name = "Colour AR VGA", | |
758 | .type = VID_TYPE_CAPTURE, | |
759 | .hardware = VID_HARDWARE_ARV, | |
760 | .fops = &ar_fops, | |
761 | .release = ar_release, | |
762 | .minor = -1, | |
763 | }; | |
764 | ||
765 | #define ALIGN4(x) ((((int)(x)) & 0x3) == 0) | |
766 | static struct ar_device ardev; | |
767 | ||
768 | static int __init ar_init(void) | |
769 | { | |
770 | struct ar_device *ar; | |
771 | int ret; | |
772 | int i; | |
773 | ||
774 | DEBUG(1, "ar_init:\n"); | |
775 | ret = -EIO; | |
776 | printk(KERN_INFO "arv: Colour AR VGA driver %s\n", VERSION); | |
777 | ||
778 | ar = &ardev; | |
779 | memset(ar, 0, sizeof(struct ar_device)); | |
780 | ||
781 | #if USE_INT | |
782 | /* allocate a DMA buffer for 1 line. */ | |
783 | ar->line_buff = kmalloc(MAX_AR_LINE_BYTES, GFP_KERNEL | GFP_DMA); | |
784 | if (ar->line_buff == NULL || ! ALIGN4(ar->line_buff)) { | |
785 | printk("arv: buffer allocation failed for DMA.\n"); | |
786 | ret = -ENOMEM; | |
787 | goto out_end; | |
788 | } | |
789 | #endif | |
790 | /* allocate buffers for a frame */ | |
791 | for (i = 0; i < MAX_AR_HEIGHT; i++) { | |
792 | ar->frame[i] = kmalloc(MAX_AR_LINE_BYTES, GFP_KERNEL); | |
793 | if (ar->frame[i] == NULL || ! ALIGN4(ar->frame[i])) { | |
794 | printk("arv: buffer allocation failed for frame.\n"); | |
795 | ret = -ENOMEM; | |
796 | goto out_line_buff; | |
797 | } | |
798 | } | |
799 | ||
800 | ar->vdev = video_device_alloc(); | |
801 | if (!ar->vdev) { | |
802 | printk(KERN_ERR "arv: video_device_alloc() failed\n"); | |
803 | return -ENOMEM; | |
804 | } | |
805 | memcpy(ar->vdev, &ar_template, sizeof(ar_template)); | |
806 | ar->vdev->priv = ar; | |
807 | ||
808 | if (vga) { | |
809 | ar->width = AR_WIDTH_VGA; | |
810 | ar->height = AR_HEIGHT_VGA; | |
811 | ar->size = AR_SIZE_VGA; | |
812 | ar->frame_bytes = AR_FRAME_BYTES_VGA; | |
813 | ar->line_bytes = AR_LINE_BYTES_VGA; | |
814 | if (vga_interlace) | |
815 | ar->mode = AR_MODE_INTERLACE; | |
816 | else | |
817 | ar->mode = AR_MODE_NORMAL; | |
818 | } else { | |
819 | ar->width = AR_WIDTH_QVGA; | |
820 | ar->height = AR_HEIGHT_QVGA; | |
821 | ar->size = AR_SIZE_QVGA; | |
822 | ar->frame_bytes = AR_FRAME_BYTES_QVGA; | |
823 | ar->line_bytes = AR_LINE_BYTES_QVGA; | |
824 | ar->mode = AR_MODE_INTERLACE; | |
825 | } | |
3593cab5 | 826 | mutex_init(&ar->lock); |
1da177e4 LT |
827 | init_waitqueue_head(&ar->wait); |
828 | ||
829 | #if USE_INT | |
830 | if (request_irq(M32R_IRQ_INT3, ar_interrupt, 0, "arv", ar)) { | |
831 | printk("arv: request_irq(%d) failed.\n", M32R_IRQ_INT3); | |
832 | ret = -EIO; | |
833 | goto out_irq; | |
834 | } | |
835 | #endif | |
836 | ||
837 | if (ar_initialize(ar->vdev) != 0) { | |
838 | printk("arv: M64278 not found.\n"); | |
839 | ret = -ENODEV; | |
840 | goto out_dev; | |
841 | } | |
842 | ||
843 | /* | |
844 | * ok, we can initialize h/w according to parameters, | |
845 | * so register video device as a frame grabber type. | |
846 | * device is named "video[0-64]". | |
847 | * video_register_device() initializes h/w using ar_initialize(). | |
d56410e0 | 848 | */ |
1da177e4 LT |
849 | if (video_register_device(ar->vdev, VFL_TYPE_GRABBER, video_nr) != 0) { |
850 | /* return -1, -ENFILE(full) or others */ | |
851 | printk("arv: register video (Colour AR) failed.\n"); | |
852 | ret = -ENODEV; | |
853 | goto out_dev; | |
854 | } | |
855 | ||
856 | printk("video%d: Found M64278 VGA (IRQ %d, Freq %dMHz).\n", | |
857 | ar->vdev->minor, M32R_IRQ_INT3, freq); | |
858 | ||
859 | return 0; | |
860 | ||
861 | out_dev: | |
862 | #if USE_INT | |
863 | free_irq(M32R_IRQ_INT3, ar); | |
864 | ||
865 | out_irq: | |
866 | #endif | |
2ea75330 JJ |
867 | for (i = 0; i < MAX_AR_HEIGHT; i++) |
868 | kfree(ar->frame[i]); | |
1da177e4 LT |
869 | |
870 | out_line_buff: | |
871 | #if USE_INT | |
872 | kfree(ar->line_buff); | |
873 | ||
874 | out_end: | |
875 | #endif | |
876 | return ret; | |
877 | } | |
878 | ||
879 | ||
880 | static int __init ar_init_module(void) | |
881 | { | |
882 | freq = (boot_cpu_data.bus_clock / 1000000); | |
883 | printk("arv: Bus clock %d\n", freq); | |
884 | if (freq != 50 && freq != 75) | |
885 | freq = DEFAULT_FREQ; | |
886 | return ar_init(); | |
887 | } | |
888 | ||
889 | static void __exit ar_cleanup_module(void) | |
890 | { | |
891 | struct ar_device *ar; | |
892 | int i; | |
893 | ||
894 | ar = &ardev; | |
895 | video_unregister_device(ar->vdev); | |
896 | #if USE_INT | |
897 | free_irq(M32R_IRQ_INT3, ar); | |
898 | #endif | |
2ea75330 JJ |
899 | for (i = 0; i < MAX_AR_HEIGHT; i++) |
900 | kfree(ar->frame[i]); | |
1da177e4 LT |
901 | #if USE_INT |
902 | kfree(ar->line_buff); | |
903 | #endif | |
904 | } | |
905 | ||
906 | module_init(ar_init_module); | |
907 | module_exit(ar_cleanup_module); | |
908 | ||
909 | MODULE_AUTHOR("Takeo Takahashi <takahashi.takeo@renesas.com>"); | |
910 | MODULE_DESCRIPTION("Colour AR M64278(VGA) for Video4Linux"); | |
911 | MODULE_LICENSE("GPL"); |