[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / media / video / adv7343_regs.h

/*
 * ADV7343 encoder related structure and register definitions
 *
 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation version 2.
 *
 * This program is distributed .as is. WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#ifndef ADV7343_REG_H
#define ADV7343_REGS_H

struct adv7343_std_info {
	u32 standard_val3;
	u32 fsc_val;
	v4l2_std_id stdid;
};

/* Register offset macros */
#define ADV7343_POWER_MODE_REG		(0x00)
#define ADV7343_MODE_SELECT_REG		(0x01)
#define ADV7343_MODE_REG0		(0x02)

#define ADV7343_DAC2_OUTPUT_LEVEL	(0x0b)

#define ADV7343_SOFT_RESET		(0x17)

#define ADV7343_HD_MODE_REG1		(0x30)
#define ADV7343_HD_MODE_REG2		(0x31)
#define ADV7343_HD_MODE_REG3		(0x32)
#define ADV7343_HD_MODE_REG4		(0x33)
#define ADV7343_HD_MODE_REG5		(0x34)
#define ADV7343_HD_MODE_REG6		(0x35)

#define ADV7343_HD_MODE_REG7		(0x39)

#define ADV7343_SD_MODE_REG1		(0x80)
#define ADV7343_SD_MODE_REG2		(0x82)
#define ADV7343_SD_MODE_REG3		(0x83)
#define ADV7343_SD_MODE_REG4		(0x84)
#define ADV7343_SD_MODE_REG5		(0x86)
#define ADV7343_SD_MODE_REG6		(0x87)
#define ADV7343_SD_MODE_REG7		(0x88)
#define ADV7343_SD_MODE_REG8		(0x89)

#define ADV7343_FSC_REG0		(0x8C)
#define ADV7343_FSC_REG1		(0x8D)
#define ADV7343_FSC_REG2		(0x8E)
#define ADV7343_FSC_REG3		(0x8F)

#define ADV7343_SD_CGMS_WSS0		(0x99)

#define ADV7343_SD_HUE_REG		(0xA0)
#define ADV7343_SD_BRIGHTNESS_WSS	(0xA1)

/* Default values for the registers */
#define ADV7343_POWER_MODE_REG_DEFAULT		(0x10)
#define ADV7343_HD_MODE_REG1_DEFAULT		(0x3C)	/* Changed Default
							   720p EAVSAV code*/
#define ADV7343_HD_MODE_REG2_DEFAULT		(0x01)	/* Changed Pixel data
							   valid */
#define ADV7343_HD_MODE_REG3_DEFAULT		(0x00)	/* Color delay 0 clks */
#define ADV7343_HD_MODE_REG4_DEFAULT		(0xE8)	/* Changed */
#define ADV7343_HD_MODE_REG5_DEFAULT		(0x08)
#define ADV7343_HD_MODE_REG6_DEFAULT		(0x00)
#define ADV7343_HD_MODE_REG7_DEFAULT		(0x00)
#define ADV7343_SD_MODE_REG8_DEFAULT		(0x00)
#define ADV7343_SOFT_RESET_DEFAULT		(0x02)
#define ADV7343_COMPOSITE_POWER_VALUE		(0x80)
#define ADV7343_COMPONENT_POWER_VALUE		(0x1C)
#define ADV7343_SVIDEO_POWER_VALUE		(0x60)
#define ADV7343_SD_HUE_REG_DEFAULT		(127)
#define ADV7343_SD_BRIGHTNESS_WSS_DEFAULT	(0x03)

#define ADV7343_SD_CGMS_WSS0_DEFAULT		(0x10)

#define ADV7343_SD_MODE_REG1_DEFAULT		(0x00)
#define ADV7343_SD_MODE_REG2_DEFAULT		(0xC9)
#define ADV7343_SD_MODE_REG3_DEFAULT		(0x10)
#define ADV7343_SD_MODE_REG4_DEFAULT		(0x01)
#define ADV7343_SD_MODE_REG5_DEFAULT		(0x02)
#define ADV7343_SD_MODE_REG6_DEFAULT		(0x0C)
#define ADV7343_SD_MODE_REG7_DEFAULT		(0x04)
#define ADV7343_SD_MODE_REG8_DEFAULT		(0x00)

/* Bit masks for Mode Select Register */
#define INPUT_MODE_MASK			(0x70)
#define SD_INPUT_MODE			(0x00)
#define HD_720P_INPUT_MODE		(0x10)
#define HD_1080I_INPUT_MODE		(0x10)

/* Bit masks for Mode Register 0 */
#define TEST_PATTERN_BLACK_BAR_EN	(0x04)
#define YUV_OUTPUT_SELECT		(0x20)
#define RGB_OUTPUT_SELECT		(0xDF)

/* Bit masks for DAC output levels */
#define DAC_OUTPUT_LEVEL_MASK		(0xFF)

/* Bit masks for soft reset register */
#define SOFT_RESET			(0x02)

/* Bit masks for HD Mode Register 1 */
#define OUTPUT_STD_MASK		(0x03)
#define OUTPUT_STD_SHIFT	(0)
#define OUTPUT_STD_EIA0_2	(0x00)
#define OUTPUT_STD_EIA0_1	(0x01)
#define OUTPUT_STD_FULL		(0x02)
#define EMBEDDED_SYNC		(0x04)
#define EXTERNAL_SYNC		(0xFB)
#define STD_MODE_SHIFT		(3)
#define STD_MODE_MASK		(0x1F)
#define STD_MODE_720P		(0x05)
#define STD_MODE_720P_25	(0x08)
#define STD_MODE_720P_30	(0x07)
#define STD_MODE_720P_50	(0x06)
#define STD_MODE_1080I		(0x0D)
#define STD_MODE_1080I_25fps	(0x0E)
#define STD_MODE_1080P_24	(0x12)
#define STD_MODE_1080P_25	(0x10)
#define STD_MODE_1080P_30	(0x0F)
#define STD_MODE_525P		(0x00)
#define STD_MODE_625P		(0x03)

/* Bit masks for SD Mode Register 1 */
#define SD_STD_MASK		(0x03)
#define SD_STD_NTSC		(0x00)
#define SD_STD_PAL_BDGHI	(0x01)
#define SD_STD_PAL_M		(0x02)
#define SD_STD_PAL_N		(0x03)
#define SD_LUMA_FLTR_MASK	(0x7)
#define SD_LUMA_FLTR_SHIFT	(0x2)
#define SD_CHROMA_FLTR_MASK	(0x7)
#define SD_CHROMA_FLTR_SHIFT	(0x5)

/* Bit masks for SD Mode Register 2 */
#define SD_PBPR_SSAF_EN		(0x01)
#define SD_PBPR_SSAF_DI		(0xFE)
#define SD_DAC_1_DI		(0xFD)
#define SD_DAC_2_DI		(0xFB)
#define SD_PEDESTAL_EN		(0x08)
#define SD_PEDESTAL_DI		(0xF7)
#define SD_SQUARE_PIXEL_EN	(0x10)
#define SD_SQUARE_PIXEL_DI	(0xEF)
#define SD_PIXEL_DATA_VALID	(0x40)
#define SD_ACTIVE_EDGE_EN	(0x80)
#define SD_ACTIVE_EDGE_DI	(0x7F)

/* Bit masks for HD Mode Register 6 */
#define HD_RGB_INPUT_EN		(0x02)
#define HD_RGB_INPUT_DI		(0xFD)
#define HD_PBPR_SYNC_EN		(0x04)
#define HD_PBPR_SYNC_DI		(0xFB)
#define HD_DAC_SWAP_EN		(0x08)
#define HD_DAC_SWAP_DI		(0xF7)
#define HD_GAMMA_CURVE_A	(0xEF)
#define HD_GAMMA_CURVE_B	(0x10)
#define HD_GAMMA_EN		(0x20)
#define HD_GAMMA_DI		(0xDF)
#define HD_ADPT_FLTR_MODEB	(0x40)
#define HD_ADPT_FLTR_MODEA	(0xBF)
#define HD_ADPT_FLTR_EN		(0x80)
#define HD_ADPT_FLTR_DI		(0x7F)

#define ADV7343_BRIGHTNESS_MAX	(127)
#define ADV7343_BRIGHTNESS_MIN	(0)
#define ADV7343_BRIGHTNESS_DEF	(3)
#define ADV7343_HUE_MAX		(255)
#define ADV7343_HUE_MIN		(0)
#define ADV7343_HUE_DEF		(127)
#define ADV7343_GAIN_MAX	(64)
#define ADV7343_GAIN_MIN	(-64)
#define ADV7343_GAIN_DEF	(0)

#endif
Commit	Line	Data
06e61f8d C	1	/*
	2	* ADV7343 encoder related structure and register definitions
	3	*
	4	* Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License as
	8	* published by the Free Software Foundation version 2.
	9	*
	10	* This program is distributed .as is. WITHOUT ANY WARRANTY of any
	11	* kind, whether express or implied; without even the implied warranty
	12	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*/
	15
	16	#ifndef ADV7343_REG_H
	17	#define ADV7343_REGS_H
	18
	19	struct adv7343_std_info {
	20	u32 standard_val3;
	21	u32 fsc_val;
	22	v4l2_std_id stdid;
	23	};
	24
	25	/* Register offset macros */
	26	#define ADV7343_POWER_MODE_REG (0x00)
	27	#define ADV7343_MODE_SELECT_REG (0x01)
	28	#define ADV7343_MODE_REG0 (0x02)
	29
	30	#define ADV7343_DAC2_OUTPUT_LEVEL (0x0b)
	31
	32	#define ADV7343_SOFT_RESET (0x17)
	33
	34	#define ADV7343_HD_MODE_REG1 (0x30)
	35	#define ADV7343_HD_MODE_REG2 (0x31)
	36	#define ADV7343_HD_MODE_REG3 (0x32)
	37	#define ADV7343_HD_MODE_REG4 (0x33)
	38	#define ADV7343_HD_MODE_REG5 (0x34)
	39	#define ADV7343_HD_MODE_REG6 (0x35)
	40
	41	#define ADV7343_HD_MODE_REG7 (0x39)
	42
	43	#define ADV7343_SD_MODE_REG1 (0x80)
	44	#define ADV7343_SD_MODE_REG2 (0x82)
	45	#define ADV7343_SD_MODE_REG3 (0x83)
	46	#define ADV7343_SD_MODE_REG4 (0x84)
	47	#define ADV7343_SD_MODE_REG5 (0x86)
	48	#define ADV7343_SD_MODE_REG6 (0x87)
	49	#define ADV7343_SD_MODE_REG7 (0x88)
	50	#define ADV7343_SD_MODE_REG8 (0x89)
	51
	52	#define ADV7343_FSC_REG0 (0x8C)
	53	#define ADV7343_FSC_REG1 (0x8D)
	54	#define ADV7343_FSC_REG2 (0x8E)
	55	#define ADV7343_FSC_REG3 (0x8F)
	56
	57	#define ADV7343_SD_CGMS_WSS0 (0x99)
	58
	59	#define ADV7343_SD_HUE_REG (0xA0)
	60	#define ADV7343_SD_BRIGHTNESS_WSS (0xA1)
	61
	62	/* Default values for the registers */
	63	#define ADV7343_POWER_MODE_REG_DEFAULT (0x10)
	64	#define ADV7343_HD_MODE_REG1_DEFAULT (0x3C) /* Changed Default
65	720p EAVSAV code*/
66	#define ADV7343_HD_MODE_REG2_DEFAULT (0x01) /* Changed Pixel data
67	valid */
68	#define ADV7343_HD_MODE_REG3_DEFAULT (0x00) /* Color delay 0 clks */
69	#define ADV7343_HD_MODE_REG4_DEFAULT (0xE8) /* Changed */
70	#define ADV7343_HD_MODE_REG5_DEFAULT (0x08)
71	#define ADV7343_HD_MODE_REG6_DEFAULT (0x00)
72	#define ADV7343_HD_MODE_REG7_DEFAULT (0x00)
73	#define ADV7343_SD_MODE_REG8_DEFAULT (0x00)
74	#define ADV7343_SOFT_RESET_DEFAULT (0x02)
75	#define ADV7343_COMPOSITE_POWER_VALUE (0x80)
76	#define ADV7343_COMPONENT_POWER_VALUE (0x1C)
77	#define ADV7343_SVIDEO_POWER_VALUE (0x60)
78	#define ADV7343_SD_HUE_REG_DEFAULT (127)
79	#define ADV7343_SD_BRIGHTNESS_WSS_DEFAULT (0x03)
80
81	#define ADV7343_SD_CGMS_WSS0_DEFAULT (0x10)
82
83	#define ADV7343_SD_MODE_REG1_DEFAULT (0x00)
84	#define ADV7343_SD_MODE_REG2_DEFAULT (0xC9)
85	#define ADV7343_SD_MODE_REG3_DEFAULT (0x10)
86	#define ADV7343_SD_MODE_REG4_DEFAULT (0x01)
87	#define ADV7343_SD_MODE_REG5_DEFAULT (0x02)
88	#define ADV7343_SD_MODE_REG6_DEFAULT (0x0C)
89	#define ADV7343_SD_MODE_REG7_DEFAULT (0x04)
90	#define ADV7343_SD_MODE_REG8_DEFAULT (0x00)
91
92	/* Bit masks for Mode Select Register */
93	#define INPUT_MODE_MASK (0x70)
94	#define SD_INPUT_MODE (0x00)
95	#define HD_720P_INPUT_MODE (0x10)
96	#define HD_1080I_INPUT_MODE (0x10)
97
98	/* Bit masks for Mode Register 0 */
99	#define TEST_PATTERN_BLACK_BAR_EN (0x04)
100	#define YUV_OUTPUT_SELECT (0x20)
101	#define RGB_OUTPUT_SELECT (0xDF)
102
103	/* Bit masks for DAC output levels */
104	#define DAC_OUTPUT_LEVEL_MASK (0xFF)
06e61f8d C	105
	106	/* Bit masks for soft reset register */
	107	#define SOFT_RESET (0x02)
	108
	109	/* Bit masks for HD Mode Register 1 */
	110	#define OUTPUT_STD_MASK (0x03)
	111	#define OUTPUT_STD_SHIFT (0)
	112	#define OUTPUT_STD_EIA0_2 (0x00)
	113	#define OUTPUT_STD_EIA0_1 (0x01)
	114	#define OUTPUT_STD_FULL (0x02)
	115	#define EMBEDDED_SYNC (0x04)
	116	#define EXTERNAL_SYNC (0xFB)
	117	#define STD_MODE_SHIFT (3)
	118	#define STD_MODE_MASK (0x1F)
	119	#define STD_MODE_720P (0x05)
	120	#define STD_MODE_720P_25 (0x08)
	121	#define STD_MODE_720P_30 (0x07)
	122	#define STD_MODE_720P_50 (0x06)
	123	#define STD_MODE_1080I (0x0D)
	124	#define STD_MODE_1080I_25fps (0x0E)
	125	#define STD_MODE_1080P_24 (0x12)
	126	#define STD_MODE_1080P_25 (0x10)
	127	#define STD_MODE_1080P_30 (0x0F)
	128	#define STD_MODE_525P (0x00)
	129	#define STD_MODE_625P (0x03)
	130
	131	/* Bit masks for SD Mode Register 1 */
	132	#define SD_STD_MASK (0x03)
	133	#define SD_STD_NTSC (0x00)
	134	#define SD_STD_PAL_BDGHI (0x01)
	135	#define SD_STD_PAL_M (0x02)
	136	#define SD_STD_PAL_N (0x03)
	137	#define SD_LUMA_FLTR_MASK (0x7)
	138	#define SD_LUMA_FLTR_SHIFT (0x2)
	139	#define SD_CHROMA_FLTR_MASK (0x7)
	140	#define SD_CHROMA_FLTR_SHIFT (0x5)
	141
	142	/* Bit masks for SD Mode Register 2 */
	143	#define SD_PBPR_SSAF_EN (0x01)
	144	#define SD_PBPR_SSAF_DI (0xFE)
	145	#define SD_DAC_1_DI (0xFD)
	146	#define SD_DAC_2_DI (0xFB)
	147	#define SD_PEDESTAL_EN (0x08)
	148	#define SD_PEDESTAL_DI (0xF7)
	149	#define SD_SQUARE_PIXEL_EN (0x10)
	150	#define SD_SQUARE_PIXEL_DI (0xEF)
	151	#define SD_PIXEL_DATA_VALID (0x40)
	152	#define SD_ACTIVE_EDGE_EN (0x80)
	153	#define SD_ACTIVE_EDGE_DI (0x7F)
	154
	155	/* Bit masks for HD Mode Register 6 */
	156	#define HD_RGB_INPUT_EN (0x02)
	157	#define HD_RGB_INPUT_DI (0xFD)
	158	#define HD_PBPR_SYNC_EN (0x04)
	159	#define HD_PBPR_SYNC_DI (0xFB)
	160	#define HD_DAC_SWAP_EN (0x08)
	161	#define HD_DAC_SWAP_DI (0xF7)
	162	#define HD_GAMMA_CURVE_A (0xEF)
	163	#define HD_GAMMA_CURVE_B (0x10)
	164	#define HD_GAMMA_EN (0x20)
	165	#define HD_GAMMA_DI (0xDF)
	166	#define HD_ADPT_FLTR_MODEB (0x40)
	167	#define HD_ADPT_FLTR_MODEA (0xBF)
	168	#define HD_ADPT_FLTR_EN (0x80)
169	#define HD_ADPT_FLTR_DI (0x7F)
170
171	#define ADV7343_BRIGHTNESS_MAX (127)
172	#define ADV7343_BRIGHTNESS_MIN (0)
173	#define ADV7343_BRIGHTNESS_DEF (3)
174	#define ADV7343_HUE_MAX (255)
175	#define ADV7343_HUE_MIN (0)
176	#define ADV7343_HUE_DEF (127)
ceed52d6 HV	177	#define ADV7343_GAIN_MAX (64)
ceed52d6 HV	178	#define ADV7343_GAIN_MIN (-64)
06e61f8d C	179	#define ADV7343_GAIN_DEF (0)
	180
	181	#endif