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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mason/btrfs...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / media / rc / nuvoton-cir.c
CommitLineData
6d2f5c27
JW		 1/*
2 * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR
3 *
4 * Copyright (C) 2010 Jarod Wilson <jarod@redhat.com>
5 * Copyright (C) 2009 Nuvoton PS Team
6 *
7 * Special thanks to Nuvoton for providing hardware, spec sheets and
8 * sample code upon which portions of this driver are based. Indirect
9 * thanks also to Maxim Levitsky, whose ene_ir driver this driver is
10 * modeled after.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
25 * USA
26 */
27
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/pnp.h>
31#include <linux/io.h>
32#include <linux/interrupt.h>
33#include <linux/sched.h>
34#include <linux/slab.h>
6bda9644 35#include <media/rc-core.h>
6d2f5c27
JW		 36#include <linux/pci_ids.h>
37
38#include "nuvoton-cir.h"
39
6d2f5c27
JW		 40/* write val to config reg */
41static inline void nvt_cr_write(struct nvt_dev *nvt, u8 val, u8 reg)
42{
43 outb(reg, nvt->cr_efir);
44 outb(val, nvt->cr_efdr);
45}
46
47/* read val from config reg */
48static inline u8 nvt_cr_read(struct nvt_dev *nvt, u8 reg)
49{
50 outb(reg, nvt->cr_efir);
51 return inb(nvt->cr_efdr);
52}
53
54/* update config register bit without changing other bits */
55static inline void nvt_set_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
56{
57 u8 tmp = nvt_cr_read(nvt, reg) | val;
58 nvt_cr_write(nvt, tmp, reg);
59}
60
61/* clear config register bit without changing other bits */
62static inline void nvt_clear_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
63{
64 u8 tmp = nvt_cr_read(nvt, reg) & ~val;
65 nvt_cr_write(nvt, tmp, reg);
66}
67
68/* enter extended function mode */
69static inline void nvt_efm_enable(struct nvt_dev *nvt)
70{
71 /* Enabling Extended Function Mode explicitly requires writing 2x */
72 outb(EFER_EFM_ENABLE, nvt->cr_efir);
73 outb(EFER_EFM_ENABLE, nvt->cr_efir);
74}
75
76/* exit extended function mode */
77static inline void nvt_efm_disable(struct nvt_dev *nvt)
78{
79 outb(EFER_EFM_DISABLE, nvt->cr_efir);
80}
81
82/*
83 * When you want to address a specific logical device, write its logical
84 * device number to CR_LOGICAL_DEV_SEL, then enable/disable by writing
85 * 0x1/0x0 respectively to CR_LOGICAL_DEV_EN.
86 */
87static inline void nvt_select_logical_dev(struct nvt_dev *nvt, u8 ldev)
88{
89 outb(CR_LOGICAL_DEV_SEL, nvt->cr_efir);
90 outb(ldev, nvt->cr_efdr);
91}
92
93/* write val to cir config register */
94static inline void nvt_cir_reg_write(struct nvt_dev *nvt, u8 val, u8 offset)
95{
96 outb(val, nvt->cir_addr + offset);
97}
98
99/* read val from cir config register */
100static u8 nvt_cir_reg_read(struct nvt_dev *nvt, u8 offset)
101{
102 u8 val;
103
104 val = inb(nvt->cir_addr + offset);
105
106 return val;
107}
108
109/* write val to cir wake register */
110static inline void nvt_cir_wake_reg_write(struct nvt_dev *nvt,
111 u8 val, u8 offset)
112{
113 outb(val, nvt->cir_wake_addr + offset);
114}
115
116/* read val from cir wake config register */
117static u8 nvt_cir_wake_reg_read(struct nvt_dev *nvt, u8 offset)
118{
119 u8 val;
120
121 val = inb(nvt->cir_wake_addr + offset);
122
123 return val;
124}
125
4e6e29ad
JW		 126#define pr_reg(text, ...) \
127 printk(KERN_INFO KBUILD_MODNAME ": " text, ## __VA_ARGS__)
128
6d2f5c27
JW		 129/* dump current cir register contents */
130static void cir_dump_regs(struct nvt_dev *nvt)
131{
132 nvt_efm_enable(nvt);
133 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
134
4e6e29ad
JW		 135 pr_reg("%s: Dump CIR logical device registers:\n", NVT_DRIVER_NAME);
136 pr_reg(" * CR CIR ACTIVE : 0x%x\n",
6d2f5c27 137 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
4e6e29ad 138 pr_reg(" * CR CIR BASE ADDR: 0x%x\n",
6d2f5c27
JW		 139 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
140 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
4e6e29ad 141 pr_reg(" * CR CIR IRQ NUM: 0x%x\n",
6d2f5c27
JW		 142 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
143
144 nvt_efm_disable(nvt);
145
4e6e29ad
JW		 146 pr_reg("%s: Dump CIR registers:\n", NVT_DRIVER_NAME);
147 pr_reg(" * IRCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRCON));
148 pr_reg(" * IRSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRSTS));
149 pr_reg(" * IREN: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IREN));
150 pr_reg(" * RXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_RXFCONT));
151 pr_reg(" * CP: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CP));
152 pr_reg(" * CC: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CC));
153 pr_reg(" * SLCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCH));
154 pr_reg(" * SLCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCL));
155 pr_reg(" * FIFOCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FIFOCON));
156 pr_reg(" * IRFIFOSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFIFOSTS));
157 pr_reg(" * SRXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SRXFIFO));
158 pr_reg(" * TXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_TXFCONT));
159 pr_reg(" * STXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_STXFIFO));
160 pr_reg(" * FCCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCH));
161 pr_reg(" * FCCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCL));
162 pr_reg(" * IRFSM: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFSM));
6d2f5c27
JW		 163}
164
165/* dump current cir wake register contents */
166static void cir_wake_dump_regs(struct nvt_dev *nvt)
167{
168 u8 i, fifo_len;
169
170 nvt_efm_enable(nvt);
171 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
172
4e6e29ad 173 pr_reg("%s: Dump CIR WAKE logical device registers:\n",
6d2f5c27 174 NVT_DRIVER_NAME);
4e6e29ad 175 pr_reg(" * CR CIR WAKE ACTIVE : 0x%x\n",
6d2f5c27 176 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
4e6e29ad 177 pr_reg(" * CR CIR WAKE BASE ADDR: 0x%x\n",
6d2f5c27 178 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
4e6e29ad
JW		 179 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
180 pr_reg(" * CR CIR WAKE IRQ NUM: 0x%x\n",
6d2f5c27
JW		 181 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
182
183 nvt_efm_disable(nvt);
184
4e6e29ad
JW		 185 pr_reg("%s: Dump CIR WAKE registers\n", NVT_DRIVER_NAME);
186 pr_reg(" * IRCON: 0x%x\n",
6d2f5c27 187 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON));
4e6e29ad 188 pr_reg(" * IRSTS: 0x%x\n",
6d2f5c27 189 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS));
4e6e29ad 190 pr_reg(" * IREN: 0x%x\n",
6d2f5c27 191 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN));
4e6e29ad 192 pr_reg(" * FIFO CMP DEEP: 0x%x\n",
6d2f5c27 193 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_DEEP));
4e6e29ad 194 pr_reg(" * FIFO CMP TOL: 0x%x\n",
6d2f5c27 195 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_TOL));
4e6e29ad 196 pr_reg(" * FIFO COUNT: 0x%x\n",
6d2f5c27 197 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT));
4e6e29ad 198 pr_reg(" * SLCH: 0x%x\n",
6d2f5c27 199 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCH));
4e6e29ad 200 pr_reg(" * SLCL: 0x%x\n",
6d2f5c27 201 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCL));
4e6e29ad 202 pr_reg(" * FIFOCON: 0x%x\n",
6d2f5c27 203 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON));
4e6e29ad 204 pr_reg(" * SRXFSTS: 0x%x\n",
6d2f5c27 205 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SRXFSTS));
4e6e29ad 206 pr_reg(" * SAMPLE RX FIFO: 0x%x\n",
6d2f5c27 207 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SAMPLE_RX_FIFO));
4e6e29ad 208 pr_reg(" * WR FIFO DATA: 0x%x\n",
6d2f5c27 209 nvt_cir_wake_reg_read(nvt, CIR_WAKE_WR_FIFO_DATA));
4e6e29ad 210 pr_reg(" * RD FIFO ONLY: 0x%x\n",
6d2f5c27 211 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
4e6e29ad 212 pr_reg(" * RD FIFO ONLY IDX: 0x%x\n",
6d2f5c27 213 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX));
4e6e29ad 214 pr_reg(" * FIFO IGNORE: 0x%x\n",
6d2f5c27 215 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_IGNORE));
4e6e29ad 216 pr_reg(" * IRFSM: 0x%x\n",
6d2f5c27
JW		 217 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRFSM));
218
219 fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT);
4e6e29ad
JW		 220 pr_reg("%s: Dump CIR WAKE FIFO (len %d)\n", NVT_DRIVER_NAME, fifo_len);
221 pr_reg("* Contents = ");
6d2f5c27 222 for (i = 0; i < fifo_len; i++)
4e6e29ad 223 printk(KERN_CONT "%02x ",
6d2f5c27 224 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
4e6e29ad 225 printk(KERN_CONT "\n");
6d2f5c27
JW		 226}
227
228/* detect hardware features */
229static int nvt_hw_detect(struct nvt_dev *nvt)
230{
231 unsigned long flags;
232 u8 chip_major, chip_minor;
233 int ret = 0;
362d3a3a
JW		 234 char chip_id[12];
235 bool chip_unknown = false;
6d2f5c27
JW		 236
237 nvt_efm_enable(nvt);
238
239 /* Check if we're wired for the alternate EFER setup */
240 chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
241 if (chip_major == 0xff) {
242 nvt->cr_efir = CR_EFIR2;
243 nvt->cr_efdr = CR_EFDR2;
244 nvt_efm_enable(nvt);
245 chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
246 }
247
248 chip_minor = nvt_cr_read(nvt, CR_CHIP_ID_LO);
6d2f5c27 249
362d3a3a
JW		 250 /* these are the known working chip revisions... */
251 switch (chip_major) {
252 case CHIP_ID_HIGH_667:
253 strcpy(chip_id, "w83667hg\0");
254 if (chip_minor != CHIP_ID_LOW_667)
255 chip_unknown = true;
256 break;
257 case CHIP_ID_HIGH_677B:
258 strcpy(chip_id, "w83677hg\0");
259 if (chip_minor != CHIP_ID_LOW_677B2 &&
260 chip_minor != CHIP_ID_LOW_677B3)
261 chip_unknown = true;
262 break;
263 case CHIP_ID_HIGH_677C:
264 strcpy(chip_id, "w83677hg-c\0");
265 if (chip_minor != CHIP_ID_LOW_677C)
266 chip_unknown = true;
267 break;
268 default:
269 strcpy(chip_id, "w836x7hg\0");
270 chip_unknown = true;
271 break;
5df465df 272 }
6d2f5c27 273
362d3a3a
JW		 274 /* warn, but still let the driver load, if we don't know this chip */
275 if (chip_unknown)
276 nvt_pr(KERN_WARNING, "%s: unknown chip, id: 0x%02x 0x%02x, "
277 "it may not work...", chip_id, chip_major, chip_minor);
278 else
279 nvt_dbg("%s: chip id: 0x%02x 0x%02x",
280 chip_id, chip_major, chip_minor);
281
6d2f5c27
JW		 282 nvt_efm_disable(nvt);
283
284 spin_lock_irqsave(&nvt->nvt_lock, flags);
285 nvt->chip_major = chip_major;
286 nvt->chip_minor = chip_minor;
287 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
288
289 return ret;
290}
291
292static void nvt_cir_ldev_init(struct nvt_dev *nvt)
293{
39381d4f
JW		 294 u8 val, psreg, psmask, psval;
295
296 if (nvt->chip_major == CHIP_ID_HIGH_667) {
297 psreg = CR_MULTIFUNC_PIN_SEL;
298 psmask = MULTIFUNC_PIN_SEL_MASK;
299 psval = MULTIFUNC_ENABLE_CIR | MULTIFUNC_ENABLE_CIRWB;
300 } else {
301 psreg = CR_OUTPUT_PIN_SEL;
302 psmask = OUTPUT_PIN_SEL_MASK;
303 psval = OUTPUT_ENABLE_CIR | OUTPUT_ENABLE_CIRWB;
304 }
6d2f5c27 305
39381d4f
JW		 306 /* output pin selection: enable CIR, with WB sensor enabled */
307 val = nvt_cr_read(nvt, psreg);
308 val &= psmask;
309 val |= psval;
310 nvt_cr_write(nvt, val, psreg);
6d2f5c27
JW		 311
312 /* Select CIR logical device and enable */
313 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
314 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
315
316 nvt_cr_write(nvt, nvt->cir_addr >> 8, CR_CIR_BASE_ADDR_HI);
317 nvt_cr_write(nvt, nvt->cir_addr & 0xff, CR_CIR_BASE_ADDR_LO);
318
319 nvt_cr_write(nvt, nvt->cir_irq, CR_CIR_IRQ_RSRC);
320
321 nvt_dbg("CIR initialized, base io port address: 0x%lx, irq: %d",
322 nvt->cir_addr, nvt->cir_irq);
323}
324
325static void nvt_cir_wake_ldev_init(struct nvt_dev *nvt)
326{
327 /* Select ACPI logical device, enable it and CIR Wake */
328 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
329 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
330
331 /* Enable CIR Wake via PSOUT# (Pin60) */
332 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
333
334 /* enable cir interrupt of mouse/keyboard IRQ event */
335 nvt_set_reg_bit(nvt, CIR_INTR_MOUSE_IRQ_BIT, CR_ACPI_IRQ_EVENTS);
336
337 /* enable pme interrupt of cir wakeup event */
338 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
339
340 /* Select CIR Wake logical device and enable */
341 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
342 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
343
344 nvt_cr_write(nvt, nvt->cir_wake_addr >> 8, CR_CIR_BASE_ADDR_HI);
345 nvt_cr_write(nvt, nvt->cir_wake_addr & 0xff, CR_CIR_BASE_ADDR_LO);
346
347 nvt_cr_write(nvt, nvt->cir_wake_irq, CR_CIR_IRQ_RSRC);
348
349 nvt_dbg("CIR Wake initialized, base io port address: 0x%lx, irq: %d",
350 nvt->cir_wake_addr, nvt->cir_wake_irq);
351}
352
353/* clear out the hardware's cir rx fifo */
354static void nvt_clear_cir_fifo(struct nvt_dev *nvt)
355{
356 u8 val;
357
358 val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
359 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON);
360}
361
362/* clear out the hardware's cir wake rx fifo */
363static void nvt_clear_cir_wake_fifo(struct nvt_dev *nvt)
364{
365 u8 val;
366
367 val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON);
368 nvt_cir_wake_reg_write(nvt, val | CIR_WAKE_FIFOCON_RXFIFOCLR,
369 CIR_WAKE_FIFOCON);
370}
371
372/* clear out the hardware's cir tx fifo */
373static void nvt_clear_tx_fifo(struct nvt_dev *nvt)
374{
375 u8 val;
376
377 val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
378 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_TXFIFOCLR, CIR_FIFOCON);
379}
380
fbdc781c
JW		 381/* enable RX Trigger Level Reach and Packet End interrupts */
382static void nvt_set_cir_iren(struct nvt_dev *nvt)
383{
384 u8 iren;
385
386 iren = CIR_IREN_RTR | CIR_IREN_PE;
387 nvt_cir_reg_write(nvt, iren, CIR_IREN);
388}
389
6d2f5c27
JW		 390static void nvt_cir_regs_init(struct nvt_dev *nvt)
391{
392 /* set sample limit count (PE interrupt raised when reached) */
393 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_SLCH);
394 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_SLCL);
395
396 /* set fifo irq trigger levels */
397 nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV |
398 CIR_FIFOCON_RX_TRIGGER_LEV, CIR_FIFOCON);
399
400 /*
401 * Enable TX and RX, specify carrier on = low, off = high, and set
402 * sample period (currently 50us)
403 */
4e6e29ad
JW		 404 nvt_cir_reg_write(nvt,
405 CIR_IRCON_TXEN | CIR_IRCON_RXEN |
406 CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL,
407 CIR_IRCON);
6d2f5c27
JW		 408
409 /* clear hardware rx and tx fifos */
410 nvt_clear_cir_fifo(nvt);
411 nvt_clear_tx_fifo(nvt);
412
413 /* clear any and all stray interrupts */
414 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
415
fbdc781c
JW		 416 /* and finally, enable interrupts */
417 nvt_set_cir_iren(nvt);
6d2f5c27
JW		 418}
419
420static void nvt_cir_wake_regs_init(struct nvt_dev *nvt)
421{
3198ed16
JW		 422 /* set number of bytes needed for wake from s3 (default 65) */
423 nvt_cir_wake_reg_write(nvt, CIR_WAKE_FIFO_CMP_BYTES,
424 CIR_WAKE_FIFO_CMP_DEEP);
6d2f5c27
JW		 425
426 /* set tolerance/variance allowed per byte during wake compare */
427 nvt_cir_wake_reg_write(nvt, CIR_WAKE_CMP_TOLERANCE,
428 CIR_WAKE_FIFO_CMP_TOL);
429
430 /* set sample limit count (PE interrupt raised when reached) */
431 nvt_cir_wake_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_WAKE_SLCH);
432 nvt_cir_wake_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_WAKE_SLCL);
433
434 /* set cir wake fifo rx trigger level (currently 67) */
435 nvt_cir_wake_reg_write(nvt, CIR_WAKE_FIFOCON_RX_TRIGGER_LEV,
436 CIR_WAKE_FIFOCON);
437
438 /*
439 * Enable TX and RX, specific carrier on = low, off = high, and set
440 * sample period (currently 50us)
441 */
442 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN |
443 CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
444 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL,
445 CIR_WAKE_IRCON);
446
447 /* clear cir wake rx fifo */
448 nvt_clear_cir_wake_fifo(nvt);
449
450 /* clear any and all stray interrupts */
451 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
452}
453
454static void nvt_enable_wake(struct nvt_dev *nvt)
455{
456 nvt_efm_enable(nvt);
457
458 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
459 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
460 nvt_set_reg_bit(nvt, CIR_INTR_MOUSE_IRQ_BIT, CR_ACPI_IRQ_EVENTS);
461 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
462
463 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
464 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
465
466 nvt_efm_disable(nvt);
467
468 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN |
469 CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
4e6e29ad
JW		 470 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL,
471 CIR_WAKE_IRCON);
6d2f5c27
JW		 472 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
473 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN);
474}
475
476/* rx carrier detect only works in learning mode, must be called w/nvt_lock */
477static u32 nvt_rx_carrier_detect(struct nvt_dev *nvt)
478{
479 u32 count, carrier, duration = 0;
480 int i;
481
482 count = nvt_cir_reg_read(nvt, CIR_FCCL) |
483 nvt_cir_reg_read(nvt, CIR_FCCH) << 8;
484
485 for (i = 0; i < nvt->pkts; i++) {
486 if (nvt->buf[i] & BUF_PULSE_BIT)
487 duration += nvt->buf[i] & BUF_LEN_MASK;
488 }
489
490 duration *= SAMPLE_PERIOD;
491
492 if (!count || !duration) {
493 nvt_pr(KERN_NOTICE, "Unable to determine carrier! (c:%u, d:%u)",
494 count, duration);
495 return 0;
496 }
497
b4608fae 498 carrier = MS_TO_NS(count) / duration;
6d2f5c27
JW		 499
500 if ((carrier > MAX_CARRIER) || (carrier < MIN_CARRIER))
501 nvt_dbg("WTF? Carrier frequency out of range!");
502
503 nvt_dbg("Carrier frequency: %u (count %u, duration %u)",
504 carrier, count, duration);
505
506 return carrier;
507}
508
509/*
510 * set carrier frequency
511 *
512 * set carrier on 2 registers: CP & CC
513 * always set CP as 0x81
514 * set CC by SPEC, CC = 3MHz/carrier - 1
515 */
d8b4b582 516static int nvt_set_tx_carrier(struct rc_dev *dev, u32 carrier)
6d2f5c27 517{
d8b4b582 518 struct nvt_dev *nvt = dev->priv;
6d2f5c27
JW		 519 u16 val;
520
521 nvt_cir_reg_write(nvt, 1, CIR_CP);
522 val = 3000000 / (carrier) - 1;
523 nvt_cir_reg_write(nvt, val & 0xff, CIR_CC);
524
525 nvt_dbg("cp: 0x%x cc: 0x%x\n",
526 nvt_cir_reg_read(nvt, CIR_CP), nvt_cir_reg_read(nvt, CIR_CC));
527
528 return 0;
529}
530
531/*
532 * nvt_tx_ir
533 *
534 * 1) clean TX fifo first (handled by AP)
535 * 2) copy data from user space
536 * 3) disable RX interrupts, enable TX interrupts: TTR & TFU
537 * 4) send 9 packets to TX FIFO to open TTR
538 * in interrupt_handler:
539 * 5) send all data out
540 * go back to write():
541 * 6) disable TX interrupts, re-enable RX interupts
542 *
543 * The key problem of this function is user space data may larger than
544 * driver's data buf length. So nvt_tx_ir() will only copy TX_BUF_LEN data to
545 * buf, and keep current copied data buf num in cur_buf_num. But driver's buf
546 * number may larger than TXFCONT (0xff). So in interrupt_handler, it has to
547 * set TXFCONT as 0xff, until buf_count less than 0xff.
548 */
d8b4b582 549static int nvt_tx_ir(struct rc_dev *dev, int *txbuf, u32 n)
6d2f5c27 550{
d8b4b582 551 struct nvt_dev *nvt = dev->priv;
6d2f5c27
JW		 552 unsigned long flags;
553 size_t cur_count;
554 unsigned int i;
555 u8 iren;
556 int ret;
557
558 spin_lock_irqsave(&nvt->tx.lock, flags);
559
560 if (n >= TX_BUF_LEN) {
561 nvt->tx.buf_count = cur_count = TX_BUF_LEN;
562 ret = TX_BUF_LEN;
563 } else {
564 nvt->tx.buf_count = cur_count = n;
565 ret = n;
566 }
567
568 memcpy(nvt->tx.buf, txbuf, nvt->tx.buf_count);
569
570 nvt->tx.cur_buf_num = 0;
571
572 /* save currently enabled interrupts */
573 iren = nvt_cir_reg_read(nvt, CIR_IREN);
574
575 /* now disable all interrupts, save TFU & TTR */
576 nvt_cir_reg_write(nvt, CIR_IREN_TFU | CIR_IREN_TTR, CIR_IREN);
577
578 nvt->tx.tx_state = ST_TX_REPLY;
579
580 nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV_8 |
581 CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON);
582
583 /* trigger TTR interrupt by writing out ones, (yes, it's ugly) */
584 for (i = 0; i < 9; i++)
585 nvt_cir_reg_write(nvt, 0x01, CIR_STXFIFO);
586
587 spin_unlock_irqrestore(&nvt->tx.lock, flags);
588
589 wait_event(nvt->tx.queue, nvt->tx.tx_state == ST_TX_REQUEST);
590
591 spin_lock_irqsave(&nvt->tx.lock, flags);
592 nvt->tx.tx_state = ST_TX_NONE;
593 spin_unlock_irqrestore(&nvt->tx.lock, flags);
594
595 /* restore enabled interrupts to prior state */
596 nvt_cir_reg_write(nvt, iren, CIR_IREN);
597
598 return ret;
599}
600
601/* dump contents of the last rx buffer we got from the hw rx fifo */
602static void nvt_dump_rx_buf(struct nvt_dev *nvt)
603{
604 int i;
605
4e6e29ad 606 printk(KERN_DEBUG "%s (len %d): ", __func__, nvt->pkts);
6d2f5c27 607 for (i = 0; (i < nvt->pkts) && (i < RX_BUF_LEN); i++)
4e6e29ad
JW		 608 printk(KERN_CONT "0x%02x ", nvt->buf[i]);
609 printk(KERN_CONT "\n");
6d2f5c27
JW		 610}
611
612/*
613 * Process raw data in rx driver buffer, store it in raw IR event kfifo,
614 * trigger decode when appropriate.
615 *
616 * We get IR data samples one byte at a time. If the msb is set, its a pulse,
617 * otherwise its a space. The lower 7 bits are the count of SAMPLE_PERIOD
618 * (default 50us) intervals for that pulse/space. A discrete signal is
619 * followed by a series of 0x7f packets, then either 0x7<something> or 0x80
620 * to signal more IR coming (repeats) or end of IR, respectively. We store
621 * sample data in the raw event kfifo until we see 0x7<something> (except f)
622 * or 0x80, at which time, we trigger a decode operation.
623 */
624static void nvt_process_rx_ir_data(struct nvt_dev *nvt)
625{
4651918a 626 DEFINE_IR_RAW_EVENT(rawir);
6d2f5c27
JW		 627 unsigned int count;
628 u32 carrier;
629 u8 sample;
630 int i;
631
632 nvt_dbg_verbose("%s firing", __func__);
633
634 if (debug)
635 nvt_dump_rx_buf(nvt);
636
637 if (nvt->carrier_detect_enabled)
638 carrier = nvt_rx_carrier_detect(nvt);
639
640 count = nvt->pkts;
641 nvt_dbg_verbose("Processing buffer of len %d", count);
642
b7582815
JW		 643 init_ir_raw_event(&rawir);
644
6d2f5c27
JW		 645 for (i = 0; i < count; i++) {
646 nvt->pkts--;
647 sample = nvt->buf[i];
648
649 rawir.pulse = ((sample & BUF_PULSE_BIT) != 0);
b4608fae
JW		 650 rawir.duration = US_TO_NS((sample & BUF_LEN_MASK)
651 * SAMPLE_PERIOD);
6d2f5c27
JW		 652
653 if ((sample & BUF_LEN_MASK) == BUF_LEN_MASK) {
654 if (nvt->rawir.pulse == rawir.pulse)
655 nvt->rawir.duration += rawir.duration;
656 else {
657 nvt->rawir.duration = rawir.duration;
658 nvt->rawir.pulse = rawir.pulse;
659 }
660 continue;
661 }
662
663 rawir.duration += nvt->rawir.duration;
4651918a
ML		 664
665 init_ir_raw_event(&nvt->rawir);
6d2f5c27
JW		 666 nvt->rawir.duration = 0;
667 nvt->rawir.pulse = rawir.pulse;
668
669 if (sample == BUF_PULSE_BIT)
670 rawir.pulse = false;
671
672 if (rawir.duration) {
673 nvt_dbg("Storing %s with duration %d",
674 rawir.pulse ? "pulse" : "space",
675 rawir.duration);
676
46872d27 677 ir_raw_event_store_with_filter(nvt->rdev, &rawir);
6d2f5c27
JW		 678 }
679
680 /*
681 * BUF_PULSE_BIT indicates end of IR data, BUF_REPEAT_BYTE
682 * indicates end of IR signal, but new data incoming. In both
683 * cases, it means we're ready to call ir_raw_event_handle
684 */
b7582815
JW		 685 if ((sample == BUF_PULSE_BIT) && nvt->pkts) {
686 nvt_dbg("Calling ir_raw_event_handle (signal end)\n");
6d2f5c27 687 ir_raw_event_handle(nvt->rdev);
b7582815 688 }
6d2f5c27
JW		 689 }
690
b7582815
JW		 691 nvt_dbg("Calling ir_raw_event_handle (buffer empty)\n");
692 ir_raw_event_handle(nvt->rdev);
693
6d2f5c27
JW		 694 if (nvt->pkts) {
695 nvt_dbg("Odd, pkts should be 0 now... (its %u)", nvt->pkts);
696 nvt->pkts = 0;
697 }
698
699 nvt_dbg_verbose("%s done", __func__);
700}
701
fbdc781c
JW		 702static void nvt_handle_rx_fifo_overrun(struct nvt_dev *nvt)
703{
704 nvt_pr(KERN_WARNING, "RX FIFO overrun detected, flushing data!");
705
706 nvt->pkts = 0;
707 nvt_clear_cir_fifo(nvt);
708 ir_raw_event_reset(nvt->rdev);
709}
710
6d2f5c27
JW		 711/* copy data from hardware rx fifo into driver buffer */
712static void nvt_get_rx_ir_data(struct nvt_dev *nvt)
713{
714 unsigned long flags;
715 u8 fifocount, val;
716 unsigned int b_idx;
fbdc781c 717 bool overrun = false;
6d2f5c27
JW		 718 int i;
719
720 /* Get count of how many bytes to read from RX FIFO */
721 fifocount = nvt_cir_reg_read(nvt, CIR_RXFCONT);
722 /* if we get 0xff, probably means the logical dev is disabled */
723 if (fifocount == 0xff)
724 return;
fbdc781c 725 /* watch out for a fifo overrun condition */
6d2f5c27 726 else if (fifocount > RX_BUF_LEN) {
fbdc781c
JW		 727 overrun = true;
728 fifocount = RX_BUF_LEN;
6d2f5c27
JW		 729 }
730
731 nvt_dbg("attempting to fetch %u bytes from hw rx fifo", fifocount);
732
733 spin_lock_irqsave(&nvt->nvt_lock, flags);
734
735 b_idx = nvt->pkts;
736
737 /* This should never happen, but lets check anyway... */
738 if (b_idx + fifocount > RX_BUF_LEN) {
739 nvt_process_rx_ir_data(nvt);
740 b_idx = 0;
741 }
742
743 /* Read fifocount bytes from CIR Sample RX FIFO register */
744 for (i = 0; i < fifocount; i++) {
745 val = nvt_cir_reg_read(nvt, CIR_SRXFIFO);
746 nvt->buf[b_idx + i] = val;
747 }
748
749 nvt->pkts += fifocount;
750 nvt_dbg("%s: pkts now %d", __func__, nvt->pkts);
751
752 nvt_process_rx_ir_data(nvt);
753
fbdc781c
JW		 754 if (overrun)
755 nvt_handle_rx_fifo_overrun(nvt);
756
6d2f5c27
JW		 757 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
758}
759
760static void nvt_cir_log_irqs(u8 status, u8 iren)
761{
762 nvt_pr(KERN_INFO, "IRQ 0x%02x (IREN 0x%02x) :%s%s%s%s%s%s%s%s%s",
763 status, iren,
764 status & CIR_IRSTS_RDR ? " RDR" : "",
765 status & CIR_IRSTS_RTR ? " RTR" : "",
766 status & CIR_IRSTS_PE ? " PE" : "",
767 status & CIR_IRSTS_RFO ? " RFO" : "",
768 status & CIR_IRSTS_TE ? " TE" : "",
769 status & CIR_IRSTS_TTR ? " TTR" : "",
770 status & CIR_IRSTS_TFU ? " TFU" : "",
771 status & CIR_IRSTS_GH ? " GH" : "",
772 status & ~(CIR_IRSTS_RDR | CIR_IRSTS_RTR | CIR_IRSTS_PE |
773 CIR_IRSTS_RFO | CIR_IRSTS_TE | CIR_IRSTS_TTR |
774 CIR_IRSTS_TFU | CIR_IRSTS_GH) ? " ?" : "");
775}
776
777static bool nvt_cir_tx_inactive(struct nvt_dev *nvt)
778{
779 unsigned long flags;
780 bool tx_inactive;
781 u8 tx_state;
782
783 spin_lock_irqsave(&nvt->tx.lock, flags);
784 tx_state = nvt->tx.tx_state;
785 spin_unlock_irqrestore(&nvt->tx.lock, flags);
786
787 tx_inactive = (tx_state == ST_TX_NONE);
788
789 return tx_inactive;
790}
791
792/* interrupt service routine for incoming and outgoing CIR data */
793static irqreturn_t nvt_cir_isr(int irq, void *data)
794{
795 struct nvt_dev *nvt = data;
796 u8 status, iren, cur_state;
797 unsigned long flags;
798
799 nvt_dbg_verbose("%s firing", __func__);
800
801 nvt_efm_enable(nvt);
802 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
803 nvt_efm_disable(nvt);
804
805 /*
806 * Get IR Status register contents. Write 1 to ack/clear
807 *
808 * bit: reg name - description
809 * 7: CIR_IRSTS_RDR - RX Data Ready
810 * 6: CIR_IRSTS_RTR - RX FIFO Trigger Level Reach
811 * 5: CIR_IRSTS_PE - Packet End
812 * 4: CIR_IRSTS_RFO - RX FIFO Overrun (RDR will also be set)
813 * 3: CIR_IRSTS_TE - TX FIFO Empty
814 * 2: CIR_IRSTS_TTR - TX FIFO Trigger Level Reach
815 * 1: CIR_IRSTS_TFU - TX FIFO Underrun
816 * 0: CIR_IRSTS_GH - Min Length Detected
817 */
818 status = nvt_cir_reg_read(nvt, CIR_IRSTS);
819 if (!status) {
820 nvt_dbg_verbose("%s exiting, IRSTS 0x0", __func__);
821 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
822 return IRQ_RETVAL(IRQ_NONE);
823 }
824
825 /* ack/clear all irq flags we've got */
826 nvt_cir_reg_write(nvt, status, CIR_IRSTS);
827 nvt_cir_reg_write(nvt, 0, CIR_IRSTS);
828
829 /* Interrupt may be shared with CIR Wake, bail if CIR not enabled */
830 iren = nvt_cir_reg_read(nvt, CIR_IREN);
831 if (!iren) {
832 nvt_dbg_verbose("%s exiting, CIR not enabled", __func__);
833 return IRQ_RETVAL(IRQ_NONE);
834 }
835
836 if (debug)
837 nvt_cir_log_irqs(status, iren);
838
839 if (status & CIR_IRSTS_RTR) {
840 /* FIXME: add code for study/learn mode */
841 /* We only do rx if not tx'ing */
842 if (nvt_cir_tx_inactive(nvt))
843 nvt_get_rx_ir_data(nvt);
844 }
845
846 if (status & CIR_IRSTS_PE) {
847 if (nvt_cir_tx_inactive(nvt))
848 nvt_get_rx_ir_data(nvt);
849
850 spin_lock_irqsave(&nvt->nvt_lock, flags);
851
852 cur_state = nvt->study_state;
853
854 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
855
856 if (cur_state == ST_STUDY_NONE)
857 nvt_clear_cir_fifo(nvt);
858 }
859
860 if (status & CIR_IRSTS_TE)
861 nvt_clear_tx_fifo(nvt);
862
863 if (status & CIR_IRSTS_TTR) {
864 unsigned int pos, count;
865 u8 tmp;
866
867 spin_lock_irqsave(&nvt->tx.lock, flags);
868
869 pos = nvt->tx.cur_buf_num;
870 count = nvt->tx.buf_count;
871
872 /* Write data into the hardware tx fifo while pos < count */
873 if (pos < count) {
874 nvt_cir_reg_write(nvt, nvt->tx.buf[pos], CIR_STXFIFO);
875 nvt->tx.cur_buf_num++;
876 /* Disable TX FIFO Trigger Level Reach (TTR) interrupt */
877 } else {
878 tmp = nvt_cir_reg_read(nvt, CIR_IREN);
879 nvt_cir_reg_write(nvt, tmp & ~CIR_IREN_TTR, CIR_IREN);
880 }
881
882 spin_unlock_irqrestore(&nvt->tx.lock, flags);
883
884 }
885
886 if (status & CIR_IRSTS_TFU) {
887 spin_lock_irqsave(&nvt->tx.lock, flags);
888 if (nvt->tx.tx_state == ST_TX_REPLY) {
889 nvt->tx.tx_state = ST_TX_REQUEST;
890 wake_up(&nvt->tx.queue);
891 }
892 spin_unlock_irqrestore(&nvt->tx.lock, flags);
893 }
894
895 nvt_dbg_verbose("%s done", __func__);
896 return IRQ_RETVAL(IRQ_HANDLED);
897}
898
899/* Interrupt service routine for CIR Wake */
900static irqreturn_t nvt_cir_wake_isr(int irq, void *data)
901{
902 u8 status, iren, val;
903 struct nvt_dev *nvt = data;
904 unsigned long flags;
905
906 nvt_dbg_wake("%s firing", __func__);
907
908 status = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS);
909 if (!status)
910 return IRQ_RETVAL(IRQ_NONE);
911
912 if (status & CIR_WAKE_IRSTS_IR_PENDING)
913 nvt_clear_cir_wake_fifo(nvt);
914
915 nvt_cir_wake_reg_write(nvt, status, CIR_WAKE_IRSTS);
916 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IRSTS);
917
918 /* Interrupt may be shared with CIR, bail if Wake not enabled */
919 iren = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN);
920 if (!iren) {
921 nvt_dbg_wake("%s exiting, wake not enabled", __func__);
922 return IRQ_RETVAL(IRQ_HANDLED);
923 }
924
925 if ((status & CIR_WAKE_IRSTS_PE) &&
926 (nvt->wake_state == ST_WAKE_START)) {
927 while (nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX)) {
928 val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY);
929 nvt_dbg("setting wake up key: 0x%x", val);
930 }
931
932 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN);
933 spin_lock_irqsave(&nvt->nvt_lock, flags);
934 nvt->wake_state = ST_WAKE_FINISH;
935 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
936 }
937
938 nvt_dbg_wake("%s done", __func__);
939 return IRQ_RETVAL(IRQ_HANDLED);
940}
941
942static void nvt_enable_cir(struct nvt_dev *nvt)
943{
944 /* set function enable flags */
945 nvt_cir_reg_write(nvt, CIR_IRCON_TXEN | CIR_IRCON_RXEN |
946 CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL,
947 CIR_IRCON);
948
949 nvt_efm_enable(nvt);
950
951 /* enable the CIR logical device */
952 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
953 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
954
955 nvt_efm_disable(nvt);
956
957 /* clear all pending interrupts */
958 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
959
960 /* enable interrupts */
fbdc781c 961 nvt_set_cir_iren(nvt);
6d2f5c27
JW		 962}
963
964static void nvt_disable_cir(struct nvt_dev *nvt)
965{
966 /* disable CIR interrupts */
967 nvt_cir_reg_write(nvt, 0, CIR_IREN);
968
969 /* clear any and all pending interrupts */
970 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
971
972 /* clear all function enable flags */
973 nvt_cir_reg_write(nvt, 0, CIR_IRCON);
974
975 /* clear hardware rx and tx fifos */
976 nvt_clear_cir_fifo(nvt);
977 nvt_clear_tx_fifo(nvt);
978
979 nvt_efm_enable(nvt);
980
981 /* disable the CIR logical device */
982 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
983 nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN);
984
985 nvt_efm_disable(nvt);
986}
987
d8b4b582 988static int nvt_open(struct rc_dev *dev)
6d2f5c27 989{
d8b4b582 990 struct nvt_dev *nvt = dev->priv;
6d2f5c27
JW		 991 unsigned long flags;
992
993 spin_lock_irqsave(&nvt->nvt_lock, flags);
994 nvt->in_use = true;
995 nvt_enable_cir(nvt);
996 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
997
998 return 0;
999}
1000
d8b4b582 1001static void nvt_close(struct rc_dev *dev)
6d2f5c27 1002{
d8b4b582 1003 struct nvt_dev *nvt = dev->priv;
6d2f5c27
JW		 1004 unsigned long flags;
1005
1006 spin_lock_irqsave(&nvt->nvt_lock, flags);
1007 nvt->in_use = false;
1008 nvt_disable_cir(nvt);
1009 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1010}
1011
1012/* Allocate memory, probe hardware, and initialize everything */
1013static int nvt_probe(struct pnp_dev *pdev, const struct pnp_device_id *dev_id)
1014{
d8b4b582
DH		 1015 struct nvt_dev *nvt;
1016 struct rc_dev *rdev;
6d2f5c27
JW		 1017 int ret = -ENOMEM;
1018
1019 nvt = kzalloc(sizeof(struct nvt_dev), GFP_KERNEL);
1020 if (!nvt)
1021 return ret;
1022
6d2f5c27 1023 /* input device for IR remote (and tx) */
d8b4b582 1024 rdev = rc_allocate_device();
6d2f5c27
JW		 1025 if (!rdev)
1026 goto failure;
1027
1028 ret = -ENODEV;
1029 /* validate pnp resources */
1030 if (!pnp_port_valid(pdev, 0) ||
1031 pnp_port_len(pdev, 0) < CIR_IOREG_LENGTH) {
1032 dev_err(&pdev->dev, "IR PNP Port not valid!\n");
1033 goto failure;
1034 }
1035
1036 if (!pnp_irq_valid(pdev, 0)) {
1037 dev_err(&pdev->dev, "PNP IRQ not valid!\n");
1038 goto failure;
1039 }
1040
1041 if (!pnp_port_valid(pdev, 1) ||
1042 pnp_port_len(pdev, 1) < CIR_IOREG_LENGTH) {
1043 dev_err(&pdev->dev, "Wake PNP Port not valid!\n");
1044 goto failure;
1045 }
1046
1047 nvt->cir_addr = pnp_port_start(pdev, 0);
1048 nvt->cir_irq = pnp_irq(pdev, 0);
1049
1050 nvt->cir_wake_addr = pnp_port_start(pdev, 1);
1051 /* irq is always shared between cir and cir wake */
1052 nvt->cir_wake_irq = nvt->cir_irq;
1053
1054 nvt->cr_efir = CR_EFIR;
1055 nvt->cr_efdr = CR_EFDR;
1056
1057 spin_lock_init(&nvt->nvt_lock);
1058 spin_lock_init(&nvt->tx.lock);
4651918a 1059 init_ir_raw_event(&nvt->rawir);
6d2f5c27
JW		 1060
1061 ret = -EBUSY;
1062 /* now claim resources */
1063 if (!request_region(nvt->cir_addr,
1064 CIR_IOREG_LENGTH, NVT_DRIVER_NAME))
1065 goto failure;
1066
1067 if (request_irq(nvt->cir_irq, nvt_cir_isr, IRQF_SHARED,
1068 NVT_DRIVER_NAME, (void *)nvt))
1069 goto failure;
1070
1071 if (!request_region(nvt->cir_wake_addr,
1072 CIR_IOREG_LENGTH, NVT_DRIVER_NAME))
1073 goto failure;
1074
1075 if (request_irq(nvt->cir_wake_irq, nvt_cir_wake_isr, IRQF_SHARED,
1076 NVT_DRIVER_NAME, (void *)nvt))
1077 goto failure;
1078
1079 pnp_set_drvdata(pdev, nvt);
1080 nvt->pdev = pdev;
1081
1082 init_waitqueue_head(&nvt->tx.queue);
1083
1084 ret = nvt_hw_detect(nvt);
1085 if (ret)
1086 goto failure;
1087
1088 /* Initialize CIR & CIR Wake Logical Devices */
1089 nvt_efm_enable(nvt);
1090 nvt_cir_ldev_init(nvt);
1091 nvt_cir_wake_ldev_init(nvt);
1092 nvt_efm_disable(nvt);
1093
1094 /* Initialize CIR & CIR Wake Config Registers */
1095 nvt_cir_regs_init(nvt);
1096 nvt_cir_wake_regs_init(nvt);
1097
d8b4b582
DH		 1098 /* Set up the rc device */
1099 rdev->priv = nvt;
1100 rdev->driver_type = RC_DRIVER_IR_RAW;
52b66144 1101 rdev->allowed_protos = RC_TYPE_ALL;
d8b4b582
DH		 1102 rdev->open = nvt_open;
1103 rdev->close = nvt_close;
1104 rdev->tx_ir = nvt_tx_ir;
1105 rdev->s_tx_carrier = nvt_set_tx_carrier;
1106 rdev->input_name = "Nuvoton w836x7hg Infrared Remote Transceiver";
46872d27 1107 rdev->input_phys = "nuvoton/cir0";
d8b4b582
DH		 1108 rdev->input_id.bustype = BUS_HOST;
1109 rdev->input_id.vendor = PCI_VENDOR_ID_WINBOND2;
1110 rdev->input_id.product = nvt->chip_major;
1111 rdev->input_id.version = nvt->chip_minor;
46872d27 1112 rdev->dev.parent = &pdev->dev;
d8b4b582
DH		 1113 rdev->driver_name = NVT_DRIVER_NAME;
1114 rdev->map_name = RC_MAP_RC6_MCE;
46872d27
JW		 1115 rdev->timeout = US_TO_NS(1000);
1116 /* rx resolution is hardwired to 50us atm, 1, 25, 100 also possible */
1117 rdev->rx_resolution = US_TO_NS(CIR_SAMPLE_PERIOD);
6d2f5c27 1118#if 0
d8b4b582
DH		 1119 rdev->min_timeout = XYZ;
1120 rdev->max_timeout = XYZ;
6d2f5c27 1121 /* tx bits */
d8b4b582 1122 rdev->tx_resolution = XYZ;
6d2f5c27 1123#endif
6d2f5c27 1124
d8b4b582 1125 ret = rc_register_device(rdev);
6d2f5c27
JW		 1126 if (ret)
1127 goto failure;
1128
46872d27 1129 device_init_wakeup(&pdev->dev, true);
d8b4b582 1130 nvt->rdev = rdev;
6d2f5c27
JW		 1131 nvt_pr(KERN_NOTICE, "driver has been successfully loaded\n");
1132 if (debug) {
1133 cir_dump_regs(nvt);
1134 cir_wake_dump_regs(nvt);
1135 }
1136
1137 return 0;
1138
1139failure:
1140 if (nvt->cir_irq)
1141 free_irq(nvt->cir_irq, nvt);
1142 if (nvt->cir_addr)
1143 release_region(nvt->cir_addr, CIR_IOREG_LENGTH);
1144
1145 if (nvt->cir_wake_irq)
1146 free_irq(nvt->cir_wake_irq, nvt);
1147 if (nvt->cir_wake_addr)
1148 release_region(nvt->cir_wake_addr, CIR_IOREG_LENGTH);
1149
d8b4b582 1150 rc_free_device(rdev);
6d2f5c27
JW		 1151 kfree(nvt);
1152
1153 return ret;
1154}
1155
1156static void __devexit nvt_remove(struct pnp_dev *pdev)
1157{
1158 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1159 unsigned long flags;
1160
1161 spin_lock_irqsave(&nvt->nvt_lock, flags);
1162 /* disable CIR */
1163 nvt_cir_reg_write(nvt, 0, CIR_IREN);
1164 nvt_disable_cir(nvt);
1165 /* enable CIR Wake (for IR power-on) */
1166 nvt_enable_wake(nvt);
1167 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1168
1169 /* free resources */
1170 free_irq(nvt->cir_irq, nvt);
1171 free_irq(nvt->cir_wake_irq, nvt);
1172 release_region(nvt->cir_addr, CIR_IOREG_LENGTH);
1173 release_region(nvt->cir_wake_addr, CIR_IOREG_LENGTH);
1174
d8b4b582 1175 rc_unregister_device(nvt->rdev);
6d2f5c27 1176
6d2f5c27
JW		 1177 kfree(nvt);
1178}
1179
1180static int nvt_suspend(struct pnp_dev *pdev, pm_message_t state)
1181{
1182 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1183 unsigned long flags;
1184
1185 nvt_dbg("%s called", __func__);
1186
1187 /* zero out misc state tracking */
1188 spin_lock_irqsave(&nvt->nvt_lock, flags);
1189 nvt->study_state = ST_STUDY_NONE;
1190 nvt->wake_state = ST_WAKE_NONE;
1191 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1192
1193 spin_lock_irqsave(&nvt->tx.lock, flags);
1194 nvt->tx.tx_state = ST_TX_NONE;
1195 spin_unlock_irqrestore(&nvt->tx.lock, flags);
1196
1197 /* disable all CIR interrupts */
1198 nvt_cir_reg_write(nvt, 0, CIR_IREN);
1199
1200 nvt_efm_enable(nvt);
1201
1202 /* disable cir logical dev */
1203 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
1204 nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN);
1205
1206 nvt_efm_disable(nvt);
1207
1208 /* make sure wake is enabled */
1209 nvt_enable_wake(nvt);
1210
1211 return 0;
1212}
1213
1214static int nvt_resume(struct pnp_dev *pdev)
1215{
1216 int ret = 0;
1217 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1218
1219 nvt_dbg("%s called", __func__);
1220
1221 /* open interrupt */
fbdc781c 1222 nvt_set_cir_iren(nvt);
6d2f5c27
JW		 1223
1224 /* Enable CIR logical device */
1225 nvt_efm_enable(nvt);
1226 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
1227 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
1228
1229 nvt_efm_disable(nvt);
1230
1231 nvt_cir_regs_init(nvt);
1232 nvt_cir_wake_regs_init(nvt);
1233
1234 return ret;
1235}
1236
1237static void nvt_shutdown(struct pnp_dev *pdev)
1238{
1239 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1240 nvt_enable_wake(nvt);
1241}
1242
1243static const struct pnp_device_id nvt_ids[] = {
1244 { "WEC0530", 0 }, /* CIR */
1245 { "NTN0530", 0 }, /* CIR for new chip's pnp id*/
1246 { "", 0 },
1247};
1248
1249static struct pnp_driver nvt_driver = {
1250 .name = NVT_DRIVER_NAME,
1251 .id_table = nvt_ids,
1252 .flags = PNP_DRIVER_RES_DO_NOT_CHANGE,
1253 .probe = nvt_probe,
1254 .remove = __devexit_p(nvt_remove),
1255 .suspend = nvt_suspend,
1256 .resume = nvt_resume,
1257 .shutdown = nvt_shutdown,
1258};
1259
1260int nvt_init(void)
1261{
1262 return pnp_register_driver(&nvt_driver);
1263}
1264
1265void nvt_exit(void)
1266{
1267 pnp_unregister_driver(&nvt_driver);
1268}
1269
1270module_param(debug, int, S_IRUGO | S_IWUSR);
1271MODULE_PARM_DESC(debug, "Enable debugging output");
1272
1273MODULE_DEVICE_TABLE(pnp, nvt_ids);
1274MODULE_DESCRIPTION("Nuvoton W83667HG-A & W83677HG-I CIR driver");
1275
1276MODULE_AUTHOR("Jarod Wilson <jarod@redhat.com>");
1277MODULE_LICENSE("GPL");
1278
1279module_init(nvt_init);
1280module_exit(nvt_exit);
kernel source for telekom puls (alcatel/mediatek)