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b5f1220d SN |
1 | /* |
2 | * Samsung S5P/EXYNOS4 SoC series MIPI-CSI receiver driver | |
3 | * | |
a1212162 | 4 | * Copyright (C) 2011 - 2012 Samsung Electronics Co., Ltd. |
29de2337 | 5 | * Sylwester Nawrocki <s.nawrocki@samsung.com> |
b5f1220d SN |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/clk.h> | |
13 | #include <linux/delay.h> | |
14 | #include <linux/device.h> | |
15 | #include <linux/errno.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/irq.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/memory.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/pm_runtime.h> | |
24 | #include <linux/regulator/consumer.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/spinlock.h> | |
27 | #include <linux/videodev2.h> | |
28 | #include <media/v4l2-subdev.h> | |
436d42c6 | 29 | #include <linux/platform_data/mipi-csis.h> |
b5f1220d SN |
30 | #include "mipi-csis.h" |
31 | ||
32 | static int debug; | |
33 | module_param(debug, int, 0644); | |
99c6902c | 34 | MODULE_PARM_DESC(debug, "Debug level (0-2)"); |
b5f1220d SN |
35 | |
36 | /* Register map definition */ | |
37 | ||
38 | /* CSIS global control */ | |
39 | #define S5PCSIS_CTRL 0x00 | |
40 | #define S5PCSIS_CTRL_DPDN_DEFAULT (0 << 31) | |
41 | #define S5PCSIS_CTRL_DPDN_SWAP (1 << 31) | |
42 | #define S5PCSIS_CTRL_ALIGN_32BIT (1 << 20) | |
43 | #define S5PCSIS_CTRL_UPDATE_SHADOW (1 << 16) | |
44 | #define S5PCSIS_CTRL_WCLK_EXTCLK (1 << 8) | |
45 | #define S5PCSIS_CTRL_RESET (1 << 4) | |
46 | #define S5PCSIS_CTRL_ENABLE (1 << 0) | |
47 | ||
48 | /* D-PHY control */ | |
49 | #define S5PCSIS_DPHYCTRL 0x04 | |
50 | #define S5PCSIS_DPHYCTRL_HSS_MASK (0x1f << 27) | |
51 | #define S5PCSIS_DPHYCTRL_ENABLE (0x1f << 0) | |
52 | ||
53 | #define S5PCSIS_CONFIG 0x08 | |
54 | #define S5PCSIS_CFG_FMT_YCBCR422_8BIT (0x1e << 2) | |
55 | #define S5PCSIS_CFG_FMT_RAW8 (0x2a << 2) | |
56 | #define S5PCSIS_CFG_FMT_RAW10 (0x2b << 2) | |
57 | #define S5PCSIS_CFG_FMT_RAW12 (0x2c << 2) | |
58 | /* User defined formats, x = 1...4 */ | |
59 | #define S5PCSIS_CFG_FMT_USER(x) ((0x30 + x - 1) << 2) | |
60 | #define S5PCSIS_CFG_FMT_MASK (0x3f << 2) | |
61 | #define S5PCSIS_CFG_NR_LANE_MASK 3 | |
62 | ||
99c6902c | 63 | /* Interrupt mask */ |
b5f1220d | 64 | #define S5PCSIS_INTMSK 0x10 |
99c6902c SN |
65 | #define S5PCSIS_INTMSK_EN_ALL 0xf000103f |
66 | #define S5PCSIS_INTMSK_EVEN_BEFORE (1 << 31) | |
67 | #define S5PCSIS_INTMSK_EVEN_AFTER (1 << 30) | |
68 | #define S5PCSIS_INTMSK_ODD_BEFORE (1 << 29) | |
69 | #define S5PCSIS_INTMSK_ODD_AFTER (1 << 28) | |
70 | #define S5PCSIS_INTMSK_ERR_SOT_HS (1 << 12) | |
71 | #define S5PCSIS_INTMSK_ERR_LOST_FS (1 << 5) | |
72 | #define S5PCSIS_INTMSK_ERR_LOST_FE (1 << 4) | |
73 | #define S5PCSIS_INTMSK_ERR_OVER (1 << 3) | |
74 | #define S5PCSIS_INTMSK_ERR_ECC (1 << 2) | |
75 | #define S5PCSIS_INTMSK_ERR_CRC (1 << 1) | |
76 | #define S5PCSIS_INTMSK_ERR_UNKNOWN (1 << 0) | |
77 | ||
78 | /* Interrupt source */ | |
b5f1220d | 79 | #define S5PCSIS_INTSRC 0x14 |
99c6902c SN |
80 | #define S5PCSIS_INTSRC_EVEN_BEFORE (1 << 31) |
81 | #define S5PCSIS_INTSRC_EVEN_AFTER (1 << 30) | |
82 | #define S5PCSIS_INTSRC_EVEN (0x3 << 30) | |
83 | #define S5PCSIS_INTSRC_ODD_BEFORE (1 << 29) | |
84 | #define S5PCSIS_INTSRC_ODD_AFTER (1 << 28) | |
85 | #define S5PCSIS_INTSRC_ODD (0x3 << 28) | |
86 | #define S5PCSIS_INTSRC_NON_IMAGE_DATA (0xff << 28) | |
87 | #define S5PCSIS_INTSRC_ERR_SOT_HS (0xf << 12) | |
88 | #define S5PCSIS_INTSRC_ERR_LOST_FS (1 << 5) | |
89 | #define S5PCSIS_INTSRC_ERR_LOST_FE (1 << 4) | |
90 | #define S5PCSIS_INTSRC_ERR_OVER (1 << 3) | |
91 | #define S5PCSIS_INTSRC_ERR_ECC (1 << 2) | |
92 | #define S5PCSIS_INTSRC_ERR_CRC (1 << 1) | |
93 | #define S5PCSIS_INTSRC_ERR_UNKNOWN (1 << 0) | |
94 | #define S5PCSIS_INTSRC_ERRORS 0xf03f | |
b5f1220d SN |
95 | |
96 | /* Pixel resolution */ | |
97 | #define S5PCSIS_RESOL 0x2c | |
98 | #define CSIS_MAX_PIX_WIDTH 0xffff | |
99 | #define CSIS_MAX_PIX_HEIGHT 0xffff | |
100 | ||
36fa8092 SN |
101 | /* Non-image packet data buffers */ |
102 | #define S5PCSIS_PKTDATA_ODD 0x2000 | |
103 | #define S5PCSIS_PKTDATA_EVEN 0x3000 | |
104 | #define S5PCSIS_PKTDATA_SIZE SZ_4K | |
105 | ||
b5f1220d SN |
106 | enum { |
107 | CSIS_CLK_MUX, | |
108 | CSIS_CLK_GATE, | |
109 | }; | |
110 | ||
111 | static char *csi_clock_name[] = { | |
112 | [CSIS_CLK_MUX] = "sclk_csis", | |
113 | [CSIS_CLK_GATE] = "csis", | |
114 | }; | |
115 | #define NUM_CSIS_CLOCKS ARRAY_SIZE(csi_clock_name) | |
116 | ||
438df3eb | 117 | static const char * const csis_supply_name[] = { |
29de2337 SN |
118 | "vddcore", /* CSIS Core (1.0V, 1.1V or 1.2V) suppply */ |
119 | "vddio", /* CSIS I/O and PLL (1.8V) supply */ | |
438df3eb SN |
120 | }; |
121 | #define CSIS_NUM_SUPPLIES ARRAY_SIZE(csis_supply_name) | |
122 | ||
b5f1220d SN |
123 | enum { |
124 | ST_POWERED = 1, | |
125 | ST_STREAMING = 2, | |
126 | ST_SUSPENDED = 4, | |
127 | }; | |
128 | ||
99c6902c SN |
129 | struct s5pcsis_event { |
130 | u32 mask; | |
131 | const char * const name; | |
132 | unsigned int counter; | |
133 | }; | |
134 | ||
135 | static const struct s5pcsis_event s5pcsis_events[] = { | |
136 | /* Errors */ | |
137 | { S5PCSIS_INTSRC_ERR_SOT_HS, "SOT Error" }, | |
138 | { S5PCSIS_INTSRC_ERR_LOST_FS, "Lost Frame Start Error" }, | |
139 | { S5PCSIS_INTSRC_ERR_LOST_FE, "Lost Frame End Error" }, | |
140 | { S5PCSIS_INTSRC_ERR_OVER, "FIFO Overflow Error" }, | |
141 | { S5PCSIS_INTSRC_ERR_ECC, "ECC Error" }, | |
142 | { S5PCSIS_INTSRC_ERR_CRC, "CRC Error" }, | |
143 | { S5PCSIS_INTSRC_ERR_UNKNOWN, "Unknown Error" }, | |
144 | /* Non-image data receive events */ | |
145 | { S5PCSIS_INTSRC_EVEN_BEFORE, "Non-image data before even frame" }, | |
146 | { S5PCSIS_INTSRC_EVEN_AFTER, "Non-image data after even frame" }, | |
147 | { S5PCSIS_INTSRC_ODD_BEFORE, "Non-image data before odd frame" }, | |
148 | { S5PCSIS_INTSRC_ODD_AFTER, "Non-image data after odd frame" }, | |
149 | }; | |
150 | #define S5PCSIS_NUM_EVENTS ARRAY_SIZE(s5pcsis_events) | |
151 | ||
36fa8092 SN |
152 | struct csis_pktbuf { |
153 | u32 *data; | |
154 | unsigned int len; | |
155 | }; | |
156 | ||
b5f1220d SN |
157 | /** |
158 | * struct csis_state - the driver's internal state data structure | |
159 | * @lock: mutex serializing the subdev and power management operations, | |
160 | * protecting @format and @flags members | |
161 | * @pads: CSIS pads array | |
162 | * @sd: v4l2_subdev associated with CSIS device instance | |
163 | * @pdev: CSIS platform device | |
b5f1220d | 164 | * @regs: mmaped I/O registers memory |
99c6902c | 165 | * @supplies: CSIS regulator supplies |
b5f1220d SN |
166 | * @clock: CSIS clocks |
167 | * @irq: requested s5p-mipi-csis irq number | |
168 | * @flags: the state variable for power and streaming control | |
169 | * @csis_fmt: current CSIS pixel format | |
170 | * @format: common media bus format for the source and sink pad | |
99c6902c | 171 | * @slock: spinlock protecting structure members below |
36fa8092 | 172 | * @pkt_buf: the frame embedded (non-image) data buffer |
99c6902c | 173 | * @events: MIPI-CSIS event (error) counters |
b5f1220d SN |
174 | */ |
175 | struct csis_state { | |
176 | struct mutex lock; | |
177 | struct media_pad pads[CSIS_PADS_NUM]; | |
178 | struct v4l2_subdev sd; | |
179 | struct platform_device *pdev; | |
b5f1220d | 180 | void __iomem *regs; |
438df3eb | 181 | struct regulator_bulk_data supplies[CSIS_NUM_SUPPLIES]; |
b5f1220d SN |
182 | struct clk *clock[NUM_CSIS_CLOCKS]; |
183 | int irq; | |
b5f1220d SN |
184 | u32 flags; |
185 | const struct csis_pix_format *csis_fmt; | |
186 | struct v4l2_mbus_framefmt format; | |
99c6902c SN |
187 | |
188 | struct spinlock slock; | |
36fa8092 | 189 | struct csis_pktbuf pkt_buf; |
99c6902c | 190 | struct s5pcsis_event events[S5PCSIS_NUM_EVENTS]; |
b5f1220d SN |
191 | }; |
192 | ||
193 | /** | |
194 | * struct csis_pix_format - CSIS pixel format description | |
195 | * @pix_width_alignment: horizontal pixel alignment, width will be | |
196 | * multiple of 2^pix_width_alignment | |
197 | * @code: corresponding media bus code | |
198 | * @fmt_reg: S5PCSIS_CONFIG register value | |
20676a4c | 199 | * @data_alignment: MIPI-CSI data alignment in bits |
b5f1220d SN |
200 | */ |
201 | struct csis_pix_format { | |
202 | unsigned int pix_width_alignment; | |
203 | enum v4l2_mbus_pixelcode code; | |
204 | u32 fmt_reg; | |
20676a4c | 205 | u8 data_alignment; |
b5f1220d SN |
206 | }; |
207 | ||
208 | static const struct csis_pix_format s5pcsis_formats[] = { | |
209 | { | |
210 | .code = V4L2_MBUS_FMT_VYUY8_2X8, | |
211 | .fmt_reg = S5PCSIS_CFG_FMT_YCBCR422_8BIT, | |
20676a4c | 212 | .data_alignment = 32, |
b5f1220d SN |
213 | }, { |
214 | .code = V4L2_MBUS_FMT_JPEG_1X8, | |
215 | .fmt_reg = S5PCSIS_CFG_FMT_USER(1), | |
20676a4c | 216 | .data_alignment = 32, |
14783d25 SN |
217 | }, { |
218 | .code = V4L2_MBUS_FMT_S5C_UYVY_JPEG_1X8, | |
219 | .fmt_reg = S5PCSIS_CFG_FMT_USER(1), | |
220 | .data_alignment = 32, | |
221 | } | |
b5f1220d SN |
222 | }; |
223 | ||
224 | #define s5pcsis_write(__csis, __r, __v) writel(__v, __csis->regs + __r) | |
225 | #define s5pcsis_read(__csis, __r) readl(__csis->regs + __r) | |
226 | ||
227 | static struct csis_state *sd_to_csis_state(struct v4l2_subdev *sdev) | |
228 | { | |
229 | return container_of(sdev, struct csis_state, sd); | |
230 | } | |
231 | ||
232 | static const struct csis_pix_format *find_csis_format( | |
233 | struct v4l2_mbus_framefmt *mf) | |
234 | { | |
235 | int i; | |
236 | ||
237 | for (i = 0; i < ARRAY_SIZE(s5pcsis_formats); i++) | |
238 | if (mf->code == s5pcsis_formats[i].code) | |
239 | return &s5pcsis_formats[i]; | |
240 | return NULL; | |
241 | } | |
242 | ||
243 | static void s5pcsis_enable_interrupts(struct csis_state *state, bool on) | |
244 | { | |
245 | u32 val = s5pcsis_read(state, S5PCSIS_INTMSK); | |
246 | ||
247 | val = on ? val | S5PCSIS_INTMSK_EN_ALL : | |
248 | val & ~S5PCSIS_INTMSK_EN_ALL; | |
249 | s5pcsis_write(state, S5PCSIS_INTMSK, val); | |
250 | } | |
251 | ||
252 | static void s5pcsis_reset(struct csis_state *state) | |
253 | { | |
254 | u32 val = s5pcsis_read(state, S5PCSIS_CTRL); | |
255 | ||
256 | s5pcsis_write(state, S5PCSIS_CTRL, val | S5PCSIS_CTRL_RESET); | |
257 | udelay(10); | |
258 | } | |
259 | ||
260 | static void s5pcsis_system_enable(struct csis_state *state, int on) | |
261 | { | |
262 | u32 val; | |
263 | ||
264 | val = s5pcsis_read(state, S5PCSIS_CTRL); | |
265 | if (on) | |
266 | val |= S5PCSIS_CTRL_ENABLE; | |
267 | else | |
268 | val &= ~S5PCSIS_CTRL_ENABLE; | |
269 | s5pcsis_write(state, S5PCSIS_CTRL, val); | |
270 | ||
271 | val = s5pcsis_read(state, S5PCSIS_DPHYCTRL); | |
272 | if (on) | |
273 | val |= S5PCSIS_DPHYCTRL_ENABLE; | |
274 | else | |
275 | val &= ~S5PCSIS_DPHYCTRL_ENABLE; | |
276 | s5pcsis_write(state, S5PCSIS_DPHYCTRL, val); | |
277 | } | |
278 | ||
279 | /* Called with the state.lock mutex held */ | |
280 | static void __s5pcsis_set_format(struct csis_state *state) | |
281 | { | |
282 | struct v4l2_mbus_framefmt *mf = &state->format; | |
283 | u32 val; | |
284 | ||
14783d25 | 285 | v4l2_dbg(1, debug, &state->sd, "fmt: %#x, %d x %d\n", |
b5f1220d SN |
286 | mf->code, mf->width, mf->height); |
287 | ||
288 | /* Color format */ | |
289 | val = s5pcsis_read(state, S5PCSIS_CONFIG); | |
290 | val = (val & ~S5PCSIS_CFG_FMT_MASK) | state->csis_fmt->fmt_reg; | |
291 | s5pcsis_write(state, S5PCSIS_CONFIG, val); | |
292 | ||
293 | /* Pixel resolution */ | |
294 | val = (mf->width << 16) | mf->height; | |
295 | s5pcsis_write(state, S5PCSIS_RESOL, val); | |
296 | } | |
297 | ||
298 | static void s5pcsis_set_hsync_settle(struct csis_state *state, int settle) | |
299 | { | |
300 | u32 val = s5pcsis_read(state, S5PCSIS_DPHYCTRL); | |
301 | ||
302 | val = (val & ~S5PCSIS_DPHYCTRL_HSS_MASK) | (settle << 27); | |
303 | s5pcsis_write(state, S5PCSIS_DPHYCTRL, val); | |
304 | } | |
305 | ||
306 | static void s5pcsis_set_params(struct csis_state *state) | |
307 | { | |
308 | struct s5p_platform_mipi_csis *pdata = state->pdev->dev.platform_data; | |
309 | u32 val; | |
310 | ||
311 | val = s5pcsis_read(state, S5PCSIS_CONFIG); | |
312 | val = (val & ~S5PCSIS_CFG_NR_LANE_MASK) | (pdata->lanes - 1); | |
313 | s5pcsis_write(state, S5PCSIS_CONFIG, val); | |
314 | ||
315 | __s5pcsis_set_format(state); | |
316 | s5pcsis_set_hsync_settle(state, pdata->hs_settle); | |
317 | ||
318 | val = s5pcsis_read(state, S5PCSIS_CTRL); | |
20676a4c | 319 | if (state->csis_fmt->data_alignment == 32) |
b5f1220d SN |
320 | val |= S5PCSIS_CTRL_ALIGN_32BIT; |
321 | else /* 24-bits */ | |
322 | val &= ~S5PCSIS_CTRL_ALIGN_32BIT; | |
323 | /* Not using external clock. */ | |
324 | val &= ~S5PCSIS_CTRL_WCLK_EXTCLK; | |
325 | s5pcsis_write(state, S5PCSIS_CTRL, val); | |
326 | ||
327 | /* Update the shadow register. */ | |
328 | val = s5pcsis_read(state, S5PCSIS_CTRL); | |
329 | s5pcsis_write(state, S5PCSIS_CTRL, val | S5PCSIS_CTRL_UPDATE_SHADOW); | |
330 | } | |
331 | ||
332 | static void s5pcsis_clk_put(struct csis_state *state) | |
333 | { | |
334 | int i; | |
335 | ||
bd7d8888 SN |
336 | for (i = 0; i < NUM_CSIS_CLOCKS; i++) { |
337 | if (IS_ERR_OR_NULL(state->clock[i])) | |
338 | continue; | |
339 | clk_unprepare(state->clock[i]); | |
340 | clk_put(state->clock[i]); | |
341 | state->clock[i] = NULL; | |
342 | } | |
b5f1220d SN |
343 | } |
344 | ||
345 | static int s5pcsis_clk_get(struct csis_state *state) | |
346 | { | |
347 | struct device *dev = &state->pdev->dev; | |
bd7d8888 | 348 | int i, ret; |
b5f1220d SN |
349 | |
350 | for (i = 0; i < NUM_CSIS_CLOCKS; i++) { | |
351 | state->clock[i] = clk_get(dev, csi_clock_name[i]); | |
bd7d8888 SN |
352 | if (IS_ERR(state->clock[i])) |
353 | goto err; | |
354 | ret = clk_prepare(state->clock[i]); | |
355 | if (ret < 0) { | |
356 | clk_put(state->clock[i]); | |
357 | state->clock[i] = NULL; | |
358 | goto err; | |
b5f1220d SN |
359 | } |
360 | } | |
361 | return 0; | |
bd7d8888 SN |
362 | err: |
363 | s5pcsis_clk_put(state); | |
364 | dev_err(dev, "failed to get clock: %s\n", csi_clock_name[i]); | |
365 | return -ENXIO; | |
b5f1220d SN |
366 | } |
367 | ||
b5f1220d SN |
368 | static void s5pcsis_start_stream(struct csis_state *state) |
369 | { | |
370 | s5pcsis_reset(state); | |
371 | s5pcsis_set_params(state); | |
372 | s5pcsis_system_enable(state, true); | |
373 | s5pcsis_enable_interrupts(state, true); | |
374 | } | |
375 | ||
376 | static void s5pcsis_stop_stream(struct csis_state *state) | |
377 | { | |
378 | s5pcsis_enable_interrupts(state, false); | |
379 | s5pcsis_system_enable(state, false); | |
380 | } | |
381 | ||
99c6902c SN |
382 | static void s5pcsis_clear_counters(struct csis_state *state) |
383 | { | |
384 | unsigned long flags; | |
385 | int i; | |
386 | ||
387 | spin_lock_irqsave(&state->slock, flags); | |
388 | for (i = 0; i < S5PCSIS_NUM_EVENTS; i++) | |
389 | state->events[i].counter = 0; | |
390 | spin_unlock_irqrestore(&state->slock, flags); | |
391 | } | |
392 | ||
393 | static void s5pcsis_log_counters(struct csis_state *state, bool non_errors) | |
394 | { | |
395 | int i = non_errors ? S5PCSIS_NUM_EVENTS : S5PCSIS_NUM_EVENTS - 4; | |
396 | unsigned long flags; | |
397 | ||
398 | spin_lock_irqsave(&state->slock, flags); | |
399 | ||
400 | for (i--; i >= 0; i--) | |
401 | if (state->events[i].counter >= 0) | |
402 | v4l2_info(&state->sd, "%s events: %d\n", | |
403 | state->events[i].name, | |
404 | state->events[i].counter); | |
405 | ||
406 | spin_unlock_irqrestore(&state->slock, flags); | |
407 | } | |
408 | ||
409 | /* | |
410 | * V4L2 subdev operations | |
411 | */ | |
412 | static int s5pcsis_s_power(struct v4l2_subdev *sd, int on) | |
413 | { | |
414 | struct csis_state *state = sd_to_csis_state(sd); | |
415 | struct device *dev = &state->pdev->dev; | |
416 | ||
417 | if (on) | |
418 | return pm_runtime_get_sync(dev); | |
419 | ||
420 | return pm_runtime_put_sync(dev); | |
421 | } | |
422 | ||
b5f1220d SN |
423 | static int s5pcsis_s_stream(struct v4l2_subdev *sd, int enable) |
424 | { | |
425 | struct csis_state *state = sd_to_csis_state(sd); | |
426 | int ret = 0; | |
427 | ||
428 | v4l2_dbg(1, debug, sd, "%s: %d, state: 0x%x\n", | |
429 | __func__, enable, state->flags); | |
430 | ||
431 | if (enable) { | |
99c6902c | 432 | s5pcsis_clear_counters(state); |
b5f1220d SN |
433 | ret = pm_runtime_get_sync(&state->pdev->dev); |
434 | if (ret && ret != 1) | |
435 | return ret; | |
436 | } | |
99c6902c | 437 | |
b5f1220d SN |
438 | mutex_lock(&state->lock); |
439 | if (enable) { | |
440 | if (state->flags & ST_SUSPENDED) { | |
441 | ret = -EBUSY; | |
442 | goto unlock; | |
443 | } | |
444 | s5pcsis_start_stream(state); | |
445 | state->flags |= ST_STREAMING; | |
446 | } else { | |
447 | s5pcsis_stop_stream(state); | |
448 | state->flags &= ~ST_STREAMING; | |
99c6902c SN |
449 | if (debug > 0) |
450 | s5pcsis_log_counters(state, true); | |
b5f1220d SN |
451 | } |
452 | unlock: | |
453 | mutex_unlock(&state->lock); | |
454 | if (!enable) | |
455 | pm_runtime_put(&state->pdev->dev); | |
456 | ||
457 | return ret == 1 ? 0 : ret; | |
458 | } | |
459 | ||
460 | static int s5pcsis_enum_mbus_code(struct v4l2_subdev *sd, | |
461 | struct v4l2_subdev_fh *fh, | |
462 | struct v4l2_subdev_mbus_code_enum *code) | |
463 | { | |
464 | if (code->index >= ARRAY_SIZE(s5pcsis_formats)) | |
465 | return -EINVAL; | |
466 | ||
467 | code->code = s5pcsis_formats[code->index].code; | |
468 | return 0; | |
469 | } | |
470 | ||
471 | static struct csis_pix_format const *s5pcsis_try_format( | |
472 | struct v4l2_mbus_framefmt *mf) | |
473 | { | |
474 | struct csis_pix_format const *csis_fmt; | |
475 | ||
476 | csis_fmt = find_csis_format(mf); | |
477 | if (csis_fmt == NULL) | |
478 | csis_fmt = &s5pcsis_formats[0]; | |
479 | ||
480 | mf->code = csis_fmt->code; | |
481 | v4l_bound_align_image(&mf->width, 1, CSIS_MAX_PIX_WIDTH, | |
482 | csis_fmt->pix_width_alignment, | |
483 | &mf->height, 1, CSIS_MAX_PIX_HEIGHT, 1, | |
484 | 0); | |
485 | return csis_fmt; | |
486 | } | |
487 | ||
488 | static struct v4l2_mbus_framefmt *__s5pcsis_get_format( | |
489 | struct csis_state *state, struct v4l2_subdev_fh *fh, | |
490 | u32 pad, enum v4l2_subdev_format_whence which) | |
491 | { | |
492 | if (which == V4L2_SUBDEV_FORMAT_TRY) | |
493 | return fh ? v4l2_subdev_get_try_format(fh, pad) : NULL; | |
494 | ||
495 | return &state->format; | |
496 | } | |
497 | ||
498 | static int s5pcsis_set_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh, | |
499 | struct v4l2_subdev_format *fmt) | |
500 | { | |
501 | struct csis_state *state = sd_to_csis_state(sd); | |
502 | struct csis_pix_format const *csis_fmt; | |
503 | struct v4l2_mbus_framefmt *mf; | |
504 | ||
505 | if (fmt->pad != CSIS_PAD_SOURCE && fmt->pad != CSIS_PAD_SINK) | |
506 | return -EINVAL; | |
507 | ||
508 | mf = __s5pcsis_get_format(state, fh, fmt->pad, fmt->which); | |
509 | ||
510 | if (fmt->pad == CSIS_PAD_SOURCE) { | |
511 | if (mf) { | |
512 | mutex_lock(&state->lock); | |
513 | fmt->format = *mf; | |
514 | mutex_unlock(&state->lock); | |
515 | } | |
516 | return 0; | |
517 | } | |
518 | csis_fmt = s5pcsis_try_format(&fmt->format); | |
519 | if (mf) { | |
520 | mutex_lock(&state->lock); | |
521 | *mf = fmt->format; | |
522 | if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) | |
523 | state->csis_fmt = csis_fmt; | |
524 | mutex_unlock(&state->lock); | |
525 | } | |
526 | return 0; | |
527 | } | |
528 | ||
529 | static int s5pcsis_get_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh, | |
530 | struct v4l2_subdev_format *fmt) | |
531 | { | |
532 | struct csis_state *state = sd_to_csis_state(sd); | |
533 | struct v4l2_mbus_framefmt *mf; | |
534 | ||
535 | if (fmt->pad != CSIS_PAD_SOURCE && fmt->pad != CSIS_PAD_SINK) | |
536 | return -EINVAL; | |
537 | ||
538 | mf = __s5pcsis_get_format(state, fh, fmt->pad, fmt->which); | |
539 | if (!mf) | |
540 | return -EINVAL; | |
541 | ||
542 | mutex_lock(&state->lock); | |
543 | fmt->format = *mf; | |
544 | mutex_unlock(&state->lock); | |
545 | return 0; | |
546 | } | |
547 | ||
36fa8092 SN |
548 | static int s5pcsis_s_rx_buffer(struct v4l2_subdev *sd, void *buf, |
549 | unsigned int *size) | |
550 | { | |
551 | struct csis_state *state = sd_to_csis_state(sd); | |
552 | unsigned long flags; | |
553 | ||
554 | *size = min_t(unsigned int, *size, S5PCSIS_PKTDATA_SIZE); | |
555 | ||
556 | spin_lock_irqsave(&state->slock, flags); | |
557 | state->pkt_buf.data = buf; | |
558 | state->pkt_buf.len = *size; | |
559 | spin_unlock_irqrestore(&state->slock, flags); | |
560 | ||
561 | return 0; | |
562 | } | |
563 | ||
99c6902c SN |
564 | static int s5pcsis_log_status(struct v4l2_subdev *sd) |
565 | { | |
566 | struct csis_state *state = sd_to_csis_state(sd); | |
567 | ||
568 | s5pcsis_log_counters(state, true); | |
569 | return 0; | |
570 | } | |
571 | ||
6cf1056f SN |
572 | static int s5pcsis_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) |
573 | { | |
574 | struct v4l2_mbus_framefmt *format = v4l2_subdev_get_try_format(fh, 0); | |
575 | ||
576 | format->colorspace = V4L2_COLORSPACE_JPEG; | |
577 | format->code = s5pcsis_formats[0].code; | |
578 | format->width = S5PCSIS_DEF_PIX_WIDTH; | |
579 | format->height = S5PCSIS_DEF_PIX_HEIGHT; | |
580 | format->field = V4L2_FIELD_NONE; | |
581 | ||
582 | return 0; | |
583 | } | |
584 | ||
585 | static const struct v4l2_subdev_internal_ops s5pcsis_sd_internal_ops = { | |
586 | .open = s5pcsis_open, | |
587 | }; | |
588 | ||
b5f1220d SN |
589 | static struct v4l2_subdev_core_ops s5pcsis_core_ops = { |
590 | .s_power = s5pcsis_s_power, | |
99c6902c | 591 | .log_status = s5pcsis_log_status, |
b5f1220d SN |
592 | }; |
593 | ||
594 | static struct v4l2_subdev_pad_ops s5pcsis_pad_ops = { | |
595 | .enum_mbus_code = s5pcsis_enum_mbus_code, | |
596 | .get_fmt = s5pcsis_get_fmt, | |
597 | .set_fmt = s5pcsis_set_fmt, | |
598 | }; | |
599 | ||
600 | static struct v4l2_subdev_video_ops s5pcsis_video_ops = { | |
36fa8092 | 601 | .s_rx_buffer = s5pcsis_s_rx_buffer, |
b5f1220d SN |
602 | .s_stream = s5pcsis_s_stream, |
603 | }; | |
604 | ||
605 | static struct v4l2_subdev_ops s5pcsis_subdev_ops = { | |
606 | .core = &s5pcsis_core_ops, | |
607 | .pad = &s5pcsis_pad_ops, | |
608 | .video = &s5pcsis_video_ops, | |
609 | }; | |
610 | ||
611 | static irqreturn_t s5pcsis_irq_handler(int irq, void *dev_id) | |
612 | { | |
613 | struct csis_state *state = dev_id; | |
36fa8092 | 614 | struct csis_pktbuf *pktbuf = &state->pkt_buf; |
99c6902c SN |
615 | unsigned long flags; |
616 | u32 status; | |
617 | ||
618 | status = s5pcsis_read(state, S5PCSIS_INTSRC); | |
99c6902c SN |
619 | spin_lock_irqsave(&state->slock, flags); |
620 | ||
36fa8092 SN |
621 | if ((status & S5PCSIS_INTSRC_NON_IMAGE_DATA) && pktbuf->data) { |
622 | u32 offset; | |
623 | ||
624 | if (status & S5PCSIS_INTSRC_EVEN) | |
625 | offset = S5PCSIS_PKTDATA_EVEN; | |
626 | else | |
627 | offset = S5PCSIS_PKTDATA_ODD; | |
628 | ||
629 | memcpy(pktbuf->data, state->regs + offset, pktbuf->len); | |
630 | pktbuf->data = NULL; | |
631 | rmb(); | |
632 | } | |
633 | ||
99c6902c SN |
634 | /* Update the event/error counters */ |
635 | if ((status & S5PCSIS_INTSRC_ERRORS) || debug) { | |
636 | int i; | |
637 | for (i = 0; i < S5PCSIS_NUM_EVENTS; i++) { | |
638 | if (!(status & state->events[i].mask)) | |
639 | continue; | |
640 | state->events[i].counter++; | |
641 | v4l2_dbg(2, debug, &state->sd, "%s: %d\n", | |
642 | state->events[i].name, | |
643 | state->events[i].counter); | |
644 | } | |
645 | v4l2_dbg(2, debug, &state->sd, "status: %08x\n", status); | |
646 | } | |
647 | spin_unlock_irqrestore(&state->slock, flags); | |
b5f1220d | 648 | |
99c6902c | 649 | s5pcsis_write(state, S5PCSIS_INTSRC, status); |
b5f1220d SN |
650 | return IRQ_HANDLED; |
651 | } | |
652 | ||
653 | static int __devinit s5pcsis_probe(struct platform_device *pdev) | |
654 | { | |
655 | struct s5p_platform_mipi_csis *pdata; | |
656 | struct resource *mem_res; | |
b5f1220d SN |
657 | struct csis_state *state; |
658 | int ret = -ENOMEM; | |
438df3eb | 659 | int i; |
b5f1220d | 660 | |
a1212162 | 661 | state = devm_kzalloc(&pdev->dev, sizeof(*state), GFP_KERNEL); |
b5f1220d SN |
662 | if (!state) |
663 | return -ENOMEM; | |
664 | ||
665 | mutex_init(&state->lock); | |
99c6902c SN |
666 | spin_lock_init(&state->slock); |
667 | ||
b5f1220d SN |
668 | state->pdev = pdev; |
669 | ||
670 | pdata = pdev->dev.platform_data; | |
671 | if (pdata == NULL || pdata->phy_enable == NULL) { | |
672 | dev_err(&pdev->dev, "Platform data not fully specified\n"); | |
a1212162 | 673 | return -EINVAL; |
b5f1220d SN |
674 | } |
675 | ||
676 | if ((pdev->id == 1 && pdata->lanes > CSIS1_MAX_LANES) || | |
677 | pdata->lanes > CSIS0_MAX_LANES) { | |
b5f1220d SN |
678 | dev_err(&pdev->dev, "Unsupported number of data lanes: %d\n", |
679 | pdata->lanes); | |
a1212162 | 680 | return -EINVAL; |
b5f1220d SN |
681 | } |
682 | ||
683 | mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
a1212162 SN |
684 | state->regs = devm_request_and_ioremap(&pdev->dev, mem_res); |
685 | if (state->regs == NULL) { | |
686 | dev_err(&pdev->dev, "Failed to request and remap io memory\n"); | |
687 | return -ENXIO; | |
b5f1220d | 688 | } |
b5f1220d SN |
689 | |
690 | state->irq = platform_get_irq(pdev, 0); | |
691 | if (state->irq < 0) { | |
b5f1220d | 692 | dev_err(&pdev->dev, "Failed to get irq\n"); |
a1212162 | 693 | return state->irq; |
b5f1220d SN |
694 | } |
695 | ||
438df3eb SN |
696 | for (i = 0; i < CSIS_NUM_SUPPLIES; i++) |
697 | state->supplies[i].supply = csis_supply_name[i]; | |
698 | ||
699 | ret = regulator_bulk_get(&pdev->dev, CSIS_NUM_SUPPLIES, | |
700 | state->supplies); | |
a1212162 SN |
701 | if (ret) |
702 | return ret; | |
703 | ||
704 | ret = s5pcsis_clk_get(state); | |
438df3eb SN |
705 | if (ret) |
706 | goto e_clkput; | |
b5f1220d | 707 | |
a1212162 SN |
708 | clk_enable(state->clock[CSIS_CLK_MUX]); |
709 | if (pdata->clk_rate) | |
710 | clk_set_rate(state->clock[CSIS_CLK_MUX], pdata->clk_rate); | |
711 | else | |
712 | dev_WARN(&pdev->dev, "No clock frequency specified!\n"); | |
713 | ||
714 | ret = devm_request_irq(&pdev->dev, state->irq, s5pcsis_irq_handler, | |
715 | 0, dev_name(&pdev->dev), state); | |
b5f1220d | 716 | if (ret) { |
a1212162 | 717 | dev_err(&pdev->dev, "Interrupt request failed\n"); |
b5f1220d SN |
718 | goto e_regput; |
719 | } | |
720 | ||
721 | v4l2_subdev_init(&state->sd, &s5pcsis_subdev_ops); | |
722 | state->sd.owner = THIS_MODULE; | |
723 | strlcpy(state->sd.name, dev_name(&pdev->dev), sizeof(state->sd.name)); | |
6cf1056f | 724 | state->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; |
b5f1220d SN |
725 | state->csis_fmt = &s5pcsis_formats[0]; |
726 | ||
6cf1056f SN |
727 | state->format.code = s5pcsis_formats[0].code; |
728 | state->format.width = S5PCSIS_DEF_PIX_WIDTH; | |
729 | state->format.height = S5PCSIS_DEF_PIX_HEIGHT; | |
730 | ||
b5f1220d SN |
731 | state->pads[CSIS_PAD_SINK].flags = MEDIA_PAD_FL_SINK; |
732 | state->pads[CSIS_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE; | |
733 | ret = media_entity_init(&state->sd.entity, | |
734 | CSIS_PADS_NUM, state->pads, 0); | |
735 | if (ret < 0) | |
a1212162 | 736 | goto e_clkput; |
b5f1220d SN |
737 | |
738 | /* This allows to retrieve the platform device id by the host driver */ | |
739 | v4l2_set_subdevdata(&state->sd, pdev); | |
740 | ||
741 | /* .. and a pointer to the subdev. */ | |
742 | platform_set_drvdata(pdev, &state->sd); | |
743 | ||
99c6902c SN |
744 | memcpy(state->events, s5pcsis_events, sizeof(state->events)); |
745 | ||
b5f1220d | 746 | pm_runtime_enable(&pdev->dev); |
b5f1220d SN |
747 | return 0; |
748 | ||
b5f1220d | 749 | e_regput: |
438df3eb | 750 | regulator_bulk_free(CSIS_NUM_SUPPLIES, state->supplies); |
b5f1220d SN |
751 | e_clkput: |
752 | clk_disable(state->clock[CSIS_CLK_MUX]); | |
753 | s5pcsis_clk_put(state); | |
b5f1220d SN |
754 | return ret; |
755 | } | |
756 | ||
d4d4e3c9 | 757 | static int s5pcsis_pm_suspend(struct device *dev, bool runtime) |
b5f1220d SN |
758 | { |
759 | struct s5p_platform_mipi_csis *pdata = dev->platform_data; | |
760 | struct platform_device *pdev = to_platform_device(dev); | |
761 | struct v4l2_subdev *sd = platform_get_drvdata(pdev); | |
762 | struct csis_state *state = sd_to_csis_state(sd); | |
c68956c1 | 763 | int ret = 0; |
b5f1220d SN |
764 | |
765 | v4l2_dbg(1, debug, sd, "%s: flags: 0x%x\n", | |
766 | __func__, state->flags); | |
767 | ||
768 | mutex_lock(&state->lock); | |
769 | if (state->flags & ST_POWERED) { | |
770 | s5pcsis_stop_stream(state); | |
771 | ret = pdata->phy_enable(state->pdev, false); | |
772 | if (ret) | |
773 | goto unlock; | |
438df3eb SN |
774 | ret = regulator_bulk_disable(CSIS_NUM_SUPPLIES, |
775 | state->supplies); | |
776 | if (ret) | |
777 | goto unlock; | |
b5f1220d SN |
778 | clk_disable(state->clock[CSIS_CLK_GATE]); |
779 | state->flags &= ~ST_POWERED; | |
d4d4e3c9 SN |
780 | if (!runtime) |
781 | state->flags |= ST_SUSPENDED; | |
b5f1220d | 782 | } |
b5f1220d SN |
783 | unlock: |
784 | mutex_unlock(&state->lock); | |
785 | return ret ? -EAGAIN : 0; | |
786 | } | |
787 | ||
d4d4e3c9 | 788 | static int s5pcsis_pm_resume(struct device *dev, bool runtime) |
b5f1220d SN |
789 | { |
790 | struct s5p_platform_mipi_csis *pdata = dev->platform_data; | |
791 | struct platform_device *pdev = to_platform_device(dev); | |
792 | struct v4l2_subdev *sd = platform_get_drvdata(pdev); | |
793 | struct csis_state *state = sd_to_csis_state(sd); | |
794 | int ret = 0; | |
795 | ||
796 | v4l2_dbg(1, debug, sd, "%s: flags: 0x%x\n", | |
797 | __func__, state->flags); | |
798 | ||
799 | mutex_lock(&state->lock); | |
d4d4e3c9 | 800 | if (!runtime && !(state->flags & ST_SUSPENDED)) |
b5f1220d SN |
801 | goto unlock; |
802 | ||
803 | if (!(state->flags & ST_POWERED)) { | |
438df3eb SN |
804 | ret = regulator_bulk_enable(CSIS_NUM_SUPPLIES, |
805 | state->supplies); | |
b5f1220d SN |
806 | if (ret) |
807 | goto unlock; | |
b5f1220d SN |
808 | ret = pdata->phy_enable(state->pdev, true); |
809 | if (!ret) { | |
810 | state->flags |= ST_POWERED; | |
438df3eb SN |
811 | } else { |
812 | regulator_bulk_disable(CSIS_NUM_SUPPLIES, | |
813 | state->supplies); | |
b5f1220d SN |
814 | goto unlock; |
815 | } | |
816 | clk_enable(state->clock[CSIS_CLK_GATE]); | |
817 | } | |
818 | if (state->flags & ST_STREAMING) | |
819 | s5pcsis_start_stream(state); | |
820 | ||
821 | state->flags &= ~ST_SUSPENDED; | |
822 | unlock: | |
823 | mutex_unlock(&state->lock); | |
824 | return ret ? -EAGAIN : 0; | |
825 | } | |
826 | ||
827 | #ifdef CONFIG_PM_SLEEP | |
d4d4e3c9 | 828 | static int s5pcsis_suspend(struct device *dev) |
b5f1220d | 829 | { |
d4d4e3c9 | 830 | return s5pcsis_pm_suspend(dev, false); |
b5f1220d SN |
831 | } |
832 | ||
d4d4e3c9 | 833 | static int s5pcsis_resume(struct device *dev) |
b5f1220d | 834 | { |
d4d4e3c9 SN |
835 | return s5pcsis_pm_resume(dev, false); |
836 | } | |
837 | #endif | |
b5f1220d | 838 | |
d4d4e3c9 SN |
839 | #ifdef CONFIG_PM_RUNTIME |
840 | static int s5pcsis_runtime_suspend(struct device *dev) | |
841 | { | |
842 | return s5pcsis_pm_suspend(dev, true); | |
843 | } | |
b5f1220d | 844 | |
d4d4e3c9 SN |
845 | static int s5pcsis_runtime_resume(struct device *dev) |
846 | { | |
847 | return s5pcsis_pm_resume(dev, true); | |
b5f1220d SN |
848 | } |
849 | #endif | |
850 | ||
851 | static int __devexit s5pcsis_remove(struct platform_device *pdev) | |
852 | { | |
853 | struct v4l2_subdev *sd = platform_get_drvdata(pdev); | |
854 | struct csis_state *state = sd_to_csis_state(sd); | |
b5f1220d SN |
855 | |
856 | pm_runtime_disable(&pdev->dev); | |
68a6bb54 | 857 | s5pcsis_pm_suspend(&pdev->dev, false); |
b5f1220d SN |
858 | clk_disable(state->clock[CSIS_CLK_MUX]); |
859 | pm_runtime_set_suspended(&pdev->dev); | |
b5f1220d | 860 | s5pcsis_clk_put(state); |
438df3eb | 861 | regulator_bulk_free(CSIS_NUM_SUPPLIES, state->supplies); |
b5f1220d SN |
862 | |
863 | media_entity_cleanup(&state->sd.entity); | |
b5f1220d SN |
864 | |
865 | return 0; | |
866 | } | |
867 | ||
868 | static const struct dev_pm_ops s5pcsis_pm_ops = { | |
d4d4e3c9 SN |
869 | SET_RUNTIME_PM_OPS(s5pcsis_runtime_suspend, s5pcsis_runtime_resume, |
870 | NULL) | |
871 | SET_SYSTEM_SLEEP_PM_OPS(s5pcsis_suspend, s5pcsis_resume) | |
b5f1220d SN |
872 | }; |
873 | ||
874 | static struct platform_driver s5pcsis_driver = { | |
875 | .probe = s5pcsis_probe, | |
876 | .remove = __devexit_p(s5pcsis_remove), | |
877 | .driver = { | |
878 | .name = CSIS_DRIVER_NAME, | |
879 | .owner = THIS_MODULE, | |
880 | .pm = &s5pcsis_pm_ops, | |
881 | }, | |
882 | }; | |
883 | ||
ecd9acbf | 884 | module_platform_driver(s5pcsis_driver); |
b5f1220d SN |
885 | |
886 | MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>"); | |
ecd9acbf | 887 | MODULE_DESCRIPTION("Samsung S5P/EXYNOS SoC MIPI-CSI2 receiver driver"); |
b5f1220d | 888 | MODULE_LICENSE("GPL"); |