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drivers: power: report battery voltage in AOSP compatible format
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / media / platform / marvell-ccic / mcam-core.h
CommitLineData
abfa3df3
JC		 1/*
2 * Marvell camera core structures.
3 *
4 * Copyright 2011 Jonathan Corbet corbet@lwn.net
5 */
b5210fd2
JC		 6#ifndef _MCAM_CORE_H
7#define _MCAM_CORE_H
8
9#include <linux/list.h>
10#include <media/v4l2-common.h>
593403c5 11#include <media/v4l2-ctrls.h>
b5210fd2
JC		 12#include <media/v4l2-dev.h>
13#include <media/videobuf2-core.h>
abfa3df3 14
7498469f
JC		 15/*
16 * Create our own symbols for the supported buffer modes, but, for now,
17 * base them entirely on which videobuf2 options have been selected.
18 */
f1c16adc 19#if IS_ENABLED(CONFIG_VIDEOBUF2_VMALLOC)
7498469f
JC		 20#define MCAM_MODE_VMALLOC 1
21#endif
22
f1c16adc 23#if IS_ENABLED(CONFIG_VIDEOBUF2_DMA_CONTIG)
7498469f
JC		 24#define MCAM_MODE_DMA_CONTIG 1
25#endif
26
f1c16adc 27#if IS_ENABLED(CONFIG_VIDEOBUF2_DMA_SG)
7498469f
JC		 28#define MCAM_MODE_DMA_SG 1
29#endif
30
31#if !defined(MCAM_MODE_VMALLOC) && !defined(MCAM_MODE_DMA_CONTIG) && \
32 !defined(MCAM_MODE_DMA_SG)
33#error One of the videobuf buffer modes must be selected in the config
34#endif
35
abfa3df3
JC		 36
37enum mcam_state {
38 S_NOTREADY, /* Not yet initialized */
39 S_IDLE, /* Just hanging around */
40 S_FLAKED, /* Some sort of problem */
a9b36e85
JC		 41 S_STREAMING, /* Streaming data */
42 S_BUFWAIT /* streaming requested but no buffers yet */
abfa3df3
JC		 43};
44#define MAX_DMA_BUFS 3
45
a9b36e85
JC		 46/*
47 * Different platforms work best with different buffer modes, so we
48 * let the platform pick.
49 */
50enum mcam_buffer_mode {
51 B_vmalloc = 0,
7498469f
JC		 52 B_DMA_contig = 1,
53 B_DMA_sg = 2
a9b36e85
JC		 54};
55
7498469f
JC		 56/*
57 * Is a given buffer mode supported by the current kernel configuration?
58 */
59static inline int mcam_buffer_mode_supported(enum mcam_buffer_mode mode)
60{
61 switch (mode) {
62#ifdef MCAM_MODE_VMALLOC
63 case B_vmalloc:
64#endif
65#ifdef MCAM_MODE_DMA_CONTIG
66 case B_DMA_contig:
67#endif
68#ifdef MCAM_MODE_DMA_SG
69 case B_DMA_sg:
70#endif
71 return 1;
72 default:
73 return 0;
74 }
75}
76
f698957a
LY		 77/*
78 * Basic frame states
79 */
80struct mcam_frame_state {
81 unsigned int frames;
82 unsigned int singles;
83 unsigned int delivered;
84};
7498469f 85
abfa3df3
JC		 86/*
87 * A description of one of our devices.
88 * Locking: controlled by s_mutex. Certain fields, however, require
89 * the dev_lock spinlock; they are marked as such by comments.
90 * dev_lock is also required for access to device registers.
91 */
92struct mcam_camera {
93 /*
94 * These fields should be set by the platform code prior to
95 * calling mcam_register().
96 */
595a93a4 97 struct i2c_adapter *i2c_adapter;
abfa3df3
JC		 98 unsigned char __iomem *regs;
99 spinlock_t dev_lock;
100 struct device *dev; /* For messages, dma alloc */
101 unsigned int chip_id;
2164b5af
JC		 102 short int clock_speed; /* Sensor clock speed, default 30 */
103 short int use_smbus; /* SMBUS or straight I2c? */
a9b36e85 104 enum mcam_buffer_mode buffer_mode;
abfa3df3
JC		 105 /*
106 * Callbacks from the core to the platform code.
107 */
108 void (*plat_power_up) (struct mcam_camera *cam);
109 void (*plat_power_down) (struct mcam_camera *cam);
110
111 /*
112 * Everything below here is private to the mcam core and
113 * should not be touched by the platform code.
114 */
115 struct v4l2_device v4l2_dev;
593403c5 116 struct v4l2_ctrl_handler ctrl_handler;
abfa3df3
JC		 117 enum mcam_state state;
118 unsigned long flags; /* Buffer status, mainly (dev_lock) */
119 int users; /* How many open FDs */
abfa3df3 120
f698957a 121 struct mcam_frame_state frame_state; /* Frame state counter */
abfa3df3
JC		 122 /*
123 * Subsystem structures.
124 */
125 struct video_device vdev;
126 struct v4l2_subdev *sensor;
127 unsigned short sensor_addr;
128
b5210fd2
JC		 129 /* Videobuf2 stuff */
130 struct vb2_queue vb_queue;
131 struct list_head buffers; /* Available frames */
132
abfa3df3
JC		 133 unsigned int nbufs; /* How many are alloc'd */
134 int next_buf; /* Next to consume (dev_lock) */
7498469f
JC		 135
136 /* DMA buffers - vmalloc mode */
137#ifdef MCAM_MODE_VMALLOC
abfa3df3
JC		 138 unsigned int dma_buf_size; /* allocated size */
139 void *dma_bufs[MAX_DMA_BUFS]; /* Internal buffer addresses */
140 dma_addr_t dma_handles[MAX_DMA_BUFS]; /* Buffer bus addresses */
7498469f
JC		 141 struct tasklet_struct s_tasklet;
142#endif
abfa3df3 143 unsigned int sequence; /* Frame sequence number */
b5210fd2 144 unsigned int buf_seq[MAX_DMA_BUFS]; /* Sequence for individual bufs */
abfa3df3 145
7498469f 146 /* DMA buffers - DMA modes */
a9b36e85
JC		 147 struct mcam_vb_buffer *vb_bufs[MAX_DMA_BUFS];
148 struct vb2_alloc_ctx *vb_alloc_ctx;
a9b36e85 149
7498469f
JC		 150 /* Mode-specific ops, set at open time */
151 void (*dma_setup)(struct mcam_camera *cam);
152 void (*frame_complete)(struct mcam_camera *cam, int frame);
abfa3df3
JC		 153
154 /* Current operating parameters */
155 u32 sensor_type; /* Currently ov7670 only */
156 struct v4l2_pix_format pix_format;
157 enum v4l2_mbus_pixelcode mbus_code;
158
159 /* Locks */
160 struct mutex s_mutex; /* Access to this structure */
abfa3df3
JC		 161};
162
163
164/*
165 * Register I/O functions. These are here because the platform code
166 * may legitimately need to mess with the register space.
167 */
168/*
169 * Device register I/O
170 */
171static inline void mcam_reg_write(struct mcam_camera *cam, unsigned int reg,
172 unsigned int val)
173{
174 iowrite32(val, cam->regs + reg);
175}
176
177static inline unsigned int mcam_reg_read(struct mcam_camera *cam,
178 unsigned int reg)
179{
180 return ioread32(cam->regs + reg);
181}
182
183
184static inline void mcam_reg_write_mask(struct mcam_camera *cam, unsigned int reg,
185 unsigned int val, unsigned int mask)
186{
187 unsigned int v = mcam_reg_read(cam, reg);
188
189 v = (v & ~mask) | (val & mask);
190 mcam_reg_write(cam, reg, v);
191}
192
193static inline void mcam_reg_clear_bit(struct mcam_camera *cam,
194 unsigned int reg, unsigned int val)
195{
196 mcam_reg_write_mask(cam, reg, 0, val);
197}
198
199static inline void mcam_reg_set_bit(struct mcam_camera *cam,
200 unsigned int reg, unsigned int val)
201{
202 mcam_reg_write_mask(cam, reg, val, val);
203}
204
205/*
206 * Functions for use by platform code.
207 */
208int mccic_register(struct mcam_camera *cam);
209int mccic_irq(struct mcam_camera *cam, unsigned int irqs);
210void mccic_shutdown(struct mcam_camera *cam);
211#ifdef CONFIG_PM
212void mccic_suspend(struct mcam_camera *cam);
213int mccic_resume(struct mcam_camera *cam);
214#endif
215
216/*
217 * Register definitions for the m88alp01 camera interface. Offsets in bytes
218 * as given in the spec.
219 */
220#define REG_Y0BAR 0x00
221#define REG_Y1BAR 0x04
222#define REG_Y2BAR 0x08
223/* ... */
224
225#define REG_IMGPITCH 0x24 /* Image pitch register */
226#define IMGP_YP_SHFT 2 /* Y pitch params */
227#define IMGP_YP_MASK 0x00003ffc /* Y pitch field */
228#define IMGP_UVP_SHFT 18 /* UV pitch (planar) */
229#define IMGP_UVP_MASK 0x3ffc0000
230#define REG_IRQSTATRAW 0x28 /* RAW IRQ Status */
231#define IRQ_EOF0 0x00000001 /* End of frame 0 */
232#define IRQ_EOF1 0x00000002 /* End of frame 1 */
233#define IRQ_EOF2 0x00000004 /* End of frame 2 */
234#define IRQ_SOF0 0x00000008 /* Start of frame 0 */
235#define IRQ_SOF1 0x00000010 /* Start of frame 1 */
236#define IRQ_SOF2 0x00000020 /* Start of frame 2 */
237#define IRQ_OVERFLOW 0x00000040 /* FIFO overflow */
238#define IRQ_TWSIW 0x00010000 /* TWSI (smbus) write */
239#define IRQ_TWSIR 0x00020000 /* TWSI read */
240#define IRQ_TWSIE 0x00040000 /* TWSI error */
241#define TWSIIRQS (IRQ_TWSIW|IRQ_TWSIR|IRQ_TWSIE)
242#define FRAMEIRQS (IRQ_EOF0|IRQ_EOF1|IRQ_EOF2|IRQ_SOF0|IRQ_SOF1|IRQ_SOF2)
243#define ALLIRQS (TWSIIRQS|FRAMEIRQS|IRQ_OVERFLOW)
244#define REG_IRQMASK 0x2c /* IRQ mask - same bits as IRQSTAT */
245#define REG_IRQSTAT 0x30 /* IRQ status / clear */
246
247#define REG_IMGSIZE 0x34 /* Image size */
248#define IMGSZ_V_MASK 0x1fff0000
249#define IMGSZ_V_SHIFT 16
250#define IMGSZ_H_MASK 0x00003fff
251#define REG_IMGOFFSET 0x38 /* IMage offset */
252
253#define REG_CTRL0 0x3c /* Control 0 */
254#define C0_ENABLE 0x00000001 /* Makes the whole thing go */
255
256/* Mask for all the format bits */
257#define C0_DF_MASK 0x00fffffc /* Bits 2-23 */
258
259/* RGB ordering */
260#define C0_RGB4_RGBX 0x00000000
261#define C0_RGB4_XRGB 0x00000004
262#define C0_RGB4_BGRX 0x00000008
263#define C0_RGB4_XBGR 0x0000000c
264#define C0_RGB5_RGGB 0x00000000
265#define C0_RGB5_GRBG 0x00000004
266#define C0_RGB5_GBRG 0x00000008
267#define C0_RGB5_BGGR 0x0000000c
268
269/* Spec has two fields for DIN and DOUT, but they must match, so
270 combine them here. */
271#define C0_DF_YUV 0x00000000 /* Data is YUV */
272#define C0_DF_RGB 0x000000a0 /* ... RGB */
273#define C0_DF_BAYER 0x00000140 /* ... Bayer */
274/* 8-8-8 must be missing from the below - ask */
275#define C0_RGBF_565 0x00000000
276#define C0_RGBF_444 0x00000800
277#define C0_RGB_BGR 0x00001000 /* Blue comes first */
278#define C0_YUV_PLANAR 0x00000000 /* YUV 422 planar format */
279#define C0_YUV_PACKED 0x00008000 /* YUV 422 packed */
280#define C0_YUV_420PL 0x0000a000 /* YUV 420 planar */
281/* Think that 420 packed must be 111 - ask */
282#define C0_YUVE_YUYV 0x00000000 /* Y1CbY0Cr */
283#define C0_YUVE_YVYU 0x00010000 /* Y1CrY0Cb */
284#define C0_YUVE_VYUY 0x00020000 /* CrY1CbY0 */
285#define C0_YUVE_UYVY 0x00030000 /* CbY1CrY0 */
286#define C0_YUVE_XYUV 0x00000000 /* 420: .YUV */
287#define C0_YUVE_XYVU 0x00010000 /* 420: .YVU */
288#define C0_YUVE_XUVY 0x00020000 /* 420: .UVY */
289#define C0_YUVE_XVUY 0x00030000 /* 420: .VUY */
290/* Bayer bits 18,19 if needed */
291#define C0_HPOL_LOW 0x01000000 /* HSYNC polarity active low */
292#define C0_VPOL_LOW 0x02000000 /* VSYNC polarity active low */
293#define C0_VCLK_LOW 0x04000000 /* VCLK on falling edge */
294#define C0_DOWNSCALE 0x08000000 /* Enable downscaler */
295#define C0_SIFM_MASK 0xc0000000 /* SIF mode bits */
296#define C0_SIF_HVSYNC 0x00000000 /* Use H/VSYNC */
297#define CO_SOF_NOSYNC 0x40000000 /* Use inband active signaling */
298
cbc4f3a2 299/* Bits below C1_444ALPHA are not present in Cafe */
abfa3df3 300#define REG_CTRL1 0x40 /* Control 1 */
cbc4f3a2
JC		 301#define C1_CLKGATE 0x00000001 /* Sensor clock gate */
302#define C1_DESC_ENA 0x00000100 /* DMA descriptor enable */
303#define C1_DESC_3WORD 0x00000200 /* Three-word descriptors used */
abfa3df3
JC		 304#define C1_444ALPHA 0x00f00000 /* Alpha field in RGB444 */
305#define C1_ALPHA_SHFT 20
306#define C1_DMAB32 0x00000000 /* 32-byte DMA burst */
307#define C1_DMAB16 0x02000000 /* 16-byte DMA burst */
308#define C1_DMAB64 0x04000000 /* 64-byte DMA burst */
309#define C1_DMAB_MASK 0x06000000
310#define C1_TWOBUFS 0x08000000 /* Use only two DMA buffers */
311#define C1_PWRDWN 0x10000000 /* Power down */
312
313#define REG_CLKCTRL 0x88 /* Clock control */
314#define CLK_DIV_MASK 0x0000ffff /* Upper bits RW "reserved" */
315
f8ff6a96 316/* This appears to be a Cafe-only register */
abfa3df3
JC		 317#define REG_UBAR 0xc4 /* Upper base address register */
318
cbc4f3a2
JC		 319/* Armada 610 DMA descriptor registers */
320#define REG_DMA_DESC_Y 0x200
321#define REG_DMA_DESC_U 0x204
322#define REG_DMA_DESC_V 0x208
323#define REG_DESC_LEN_Y 0x20c /* Lengths are in bytes */
324#define REG_DESC_LEN_U 0x210
325#define REG_DESC_LEN_V 0x214
326
abfa3df3
JC		 327/*
328 * Useful stuff that probably belongs somewhere global.
329 */
330#define VGA_WIDTH 640
331#define VGA_HEIGHT 480
b5210fd2
JC		 332
333#endif /* _MCAM_CORE_H */
kernel source for telekom puls (alcatel/mediatek)