Commit | Line | Data |
---|---|---|
abfa3df3 JC |
1 | /* |
2 | * The Marvell camera core. This device appears in a number of settings, | |
3 | * so it needs platform-specific support outside of the core. | |
4 | * | |
5 | * Copyright 2011 Jonathan Corbet corbet@lwn.net | |
6 | */ | |
7 | #include <linux/kernel.h> | |
8 | #include <linux/module.h> | |
9 | #include <linux/fs.h> | |
abfa3df3 JC |
10 | #include <linux/mm.h> |
11 | #include <linux/i2c.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/spinlock.h> | |
abfa3df3 | 14 | #include <linux/slab.h> |
abfa3df3 JC |
15 | #include <linux/device.h> |
16 | #include <linux/wait.h> | |
17 | #include <linux/list.h> | |
18 | #include <linux/dma-mapping.h> | |
19 | #include <linux/delay.h> | |
abfa3df3 | 20 | #include <linux/vmalloc.h> |
abfa3df3 | 21 | #include <linux/io.h> |
362d45b2 JC |
22 | #include <linux/videodev2.h> |
23 | #include <media/v4l2-device.h> | |
24 | #include <media/v4l2-ioctl.h> | |
593403c5 | 25 | #include <media/v4l2-ctrls.h> |
362d45b2 JC |
26 | #include <media/v4l2-chip-ident.h> |
27 | #include <media/ov7670.h> | |
28 | #include <media/videobuf2-vmalloc.h> | |
a9b36e85 | 29 | #include <media/videobuf2-dma-contig.h> |
cbc4f3a2 | 30 | #include <media/videobuf2-dma-sg.h> |
abfa3df3 JC |
31 | |
32 | #include "mcam-core.h" | |
33 | ||
7498469f | 34 | #ifdef MCAM_MODE_VMALLOC |
abfa3df3 JC |
35 | /* |
36 | * Internal DMA buffer management. Since the controller cannot do S/G I/O, | |
37 | * we must have physically contiguous buffers to bring frames into. | |
38 | * These parameters control how many buffers we use, whether we | |
39 | * allocate them at load time (better chance of success, but nails down | |
40 | * memory) or when somebody tries to use the camera (riskier), and, | |
41 | * for load-time allocation, how big they should be. | |
42 | * | |
43 | * The controller can cycle through three buffers. We could use | |
44 | * more by flipping pointers around, but it probably makes little | |
45 | * sense. | |
46 | */ | |
47 | ||
90ab5ee9 | 48 | static bool alloc_bufs_at_read; |
abfa3df3 JC |
49 | module_param(alloc_bufs_at_read, bool, 0444); |
50 | MODULE_PARM_DESC(alloc_bufs_at_read, | |
51 | "Non-zero value causes DMA buffers to be allocated when the " | |
52 | "video capture device is read, rather than at module load " | |
53 | "time. This saves memory, but decreases the chances of " | |
a9b36e85 JC |
54 | "successfully getting those buffers. This parameter is " |
55 | "only used in the vmalloc buffer mode"); | |
abfa3df3 JC |
56 | |
57 | static int n_dma_bufs = 3; | |
58 | module_param(n_dma_bufs, uint, 0644); | |
59 | MODULE_PARM_DESC(n_dma_bufs, | |
60 | "The number of DMA buffers to allocate. Can be either two " | |
61 | "(saves memory, makes timing tighter) or three."); | |
62 | ||
63 | static int dma_buf_size = VGA_WIDTH * VGA_HEIGHT * 2; /* Worst case */ | |
64 | module_param(dma_buf_size, uint, 0444); | |
65 | MODULE_PARM_DESC(dma_buf_size, | |
66 | "The size of the allocated DMA buffers. If actual operating " | |
67 | "parameters require larger buffers, an attempt to reallocate " | |
68 | "will be made."); | |
7498469f | 69 | #else /* MCAM_MODE_VMALLOC */ |
90ab5ee9 | 70 | static const bool alloc_bufs_at_read = 0; |
7498469f JC |
71 | static const int n_dma_bufs = 3; /* Used by S/G_PARM */ |
72 | #endif /* MCAM_MODE_VMALLOC */ | |
abfa3df3 | 73 | |
90ab5ee9 | 74 | static bool flip; |
abfa3df3 JC |
75 | module_param(flip, bool, 0444); |
76 | MODULE_PARM_DESC(flip, | |
77 | "If set, the sensor will be instructed to flip the image " | |
78 | "vertically."); | |
79 | ||
a9b36e85 JC |
80 | static int buffer_mode = -1; |
81 | module_param(buffer_mode, int, 0444); | |
82 | MODULE_PARM_DESC(buffer_mode, | |
83 | "Set the buffer mode to be used; default is to go with what " | |
84 | "the platform driver asks for. Set to 0 for vmalloc, 1 for " | |
85 | "DMA contiguous."); | |
86 | ||
abfa3df3 JC |
87 | /* |
88 | * Status flags. Always manipulated with bit operations. | |
89 | */ | |
90 | #define CF_BUF0_VALID 0 /* Buffers valid - first three */ | |
91 | #define CF_BUF1_VALID 1 | |
92 | #define CF_BUF2_VALID 2 | |
93 | #define CF_DMA_ACTIVE 3 /* A frame is incoming */ | |
94 | #define CF_CONFIG_NEEDED 4 /* Must configure hardware */ | |
a9b36e85 | 95 | #define CF_SINGLE_BUFFER 5 /* Running with a single buffer */ |
cbc4f3a2 | 96 | #define CF_SG_RESTART 6 /* SG restart needed */ |
abfa3df3 JC |
97 | |
98 | #define sensor_call(cam, o, f, args...) \ | |
99 | v4l2_subdev_call(cam->sensor, o, f, ##args) | |
100 | ||
101 | static struct mcam_format_struct { | |
102 | __u8 *desc; | |
103 | __u32 pixelformat; | |
104 | int bpp; /* Bytes per pixel */ | |
105 | enum v4l2_mbus_pixelcode mbus_code; | |
106 | } mcam_formats[] = { | |
107 | { | |
108 | .desc = "YUYV 4:2:2", | |
109 | .pixelformat = V4L2_PIX_FMT_YUYV, | |
110 | .mbus_code = V4L2_MBUS_FMT_YUYV8_2X8, | |
111 | .bpp = 2, | |
112 | }, | |
113 | { | |
114 | .desc = "RGB 444", | |
115 | .pixelformat = V4L2_PIX_FMT_RGB444, | |
116 | .mbus_code = V4L2_MBUS_FMT_RGB444_2X8_PADHI_LE, | |
117 | .bpp = 2, | |
118 | }, | |
119 | { | |
120 | .desc = "RGB 565", | |
121 | .pixelformat = V4L2_PIX_FMT_RGB565, | |
122 | .mbus_code = V4L2_MBUS_FMT_RGB565_2X8_LE, | |
123 | .bpp = 2, | |
124 | }, | |
125 | { | |
126 | .desc = "Raw RGB Bayer", | |
127 | .pixelformat = V4L2_PIX_FMT_SBGGR8, | |
128 | .mbus_code = V4L2_MBUS_FMT_SBGGR8_1X8, | |
129 | .bpp = 1 | |
130 | }, | |
131 | }; | |
132 | #define N_MCAM_FMTS ARRAY_SIZE(mcam_formats) | |
133 | ||
134 | static struct mcam_format_struct *mcam_find_format(u32 pixelformat) | |
135 | { | |
136 | unsigned i; | |
137 | ||
138 | for (i = 0; i < N_MCAM_FMTS; i++) | |
139 | if (mcam_formats[i].pixelformat == pixelformat) | |
140 | return mcam_formats + i; | |
141 | /* Not found? Then return the first format. */ | |
142 | return mcam_formats; | |
143 | } | |
144 | ||
145 | /* | |
d43dae75 | 146 | * The default format we use until somebody says otherwise. |
abfa3df3 | 147 | */ |
d43dae75 JC |
148 | static const struct v4l2_pix_format mcam_def_pix_format = { |
149 | .width = VGA_WIDTH, | |
150 | .height = VGA_HEIGHT, | |
151 | .pixelformat = V4L2_PIX_FMT_YUYV, | |
152 | .field = V4L2_FIELD_NONE, | |
153 | .bytesperline = VGA_WIDTH*2, | |
154 | .sizeimage = VGA_WIDTH*VGA_HEIGHT*2, | |
155 | }; | |
abfa3df3 | 156 | |
d43dae75 JC |
157 | static const enum v4l2_mbus_pixelcode mcam_def_mbus_code = |
158 | V4L2_MBUS_FMT_YUYV8_2X8; | |
abfa3df3 | 159 | |
abfa3df3 | 160 | |
cbc4f3a2 JC |
161 | /* |
162 | * The two-word DMA descriptor format used by the Armada 610 and like. There | |
163 | * Is a three-word format as well (set C1_DESC_3WORD) where the third | |
164 | * word is a pointer to the next descriptor, but we don't use it. Two-word | |
165 | * descriptors have to be contiguous in memory. | |
166 | */ | |
167 | struct mcam_dma_desc { | |
168 | u32 dma_addr; | |
169 | u32 segment_len; | |
170 | }; | |
171 | ||
b5210fd2 JC |
172 | /* |
173 | * Our buffer type for working with videobuf2. Note that the vb2 | |
174 | * developers have decreed that struct vb2_buffer must be at the | |
175 | * beginning of this structure. | |
176 | */ | |
177 | struct mcam_vb_buffer { | |
178 | struct vb2_buffer vb_buf; | |
179 | struct list_head queue; | |
cbc4f3a2 JC |
180 | struct mcam_dma_desc *dma_desc; /* Descriptor virtual address */ |
181 | dma_addr_t dma_desc_pa; /* Descriptor physical address */ | |
182 | int dma_desc_nent; /* Number of mapped descriptors */ | |
b5210fd2 JC |
183 | }; |
184 | ||
185 | static inline struct mcam_vb_buffer *vb_to_mvb(struct vb2_buffer *vb) | |
186 | { | |
187 | return container_of(vb, struct mcam_vb_buffer, vb_buf); | |
188 | } | |
189 | ||
d43dae75 JC |
190 | /* |
191 | * Hand a completed buffer back to user space. | |
192 | */ | |
193 | static void mcam_buffer_done(struct mcam_camera *cam, int frame, | |
194 | struct vb2_buffer *vbuf) | |
195 | { | |
196 | vbuf->v4l2_buf.bytesused = cam->pix_format.sizeimage; | |
197 | vbuf->v4l2_buf.sequence = cam->buf_seq[frame]; | |
198 | vb2_set_plane_payload(vbuf, 0, cam->pix_format.sizeimage); | |
199 | vb2_buffer_done(vbuf, VB2_BUF_STATE_DONE); | |
200 | } | |
201 | ||
202 | ||
abfa3df3 JC |
203 | |
204 | /* | |
67a8dbbc | 205 | * Debugging and related. |
abfa3df3 JC |
206 | */ |
207 | #define cam_err(cam, fmt, arg...) \ | |
208 | dev_err((cam)->dev, fmt, ##arg); | |
209 | #define cam_warn(cam, fmt, arg...) \ | |
210 | dev_warn((cam)->dev, fmt, ##arg); | |
211 | #define cam_dbg(cam, fmt, arg...) \ | |
212 | dev_dbg((cam)->dev, fmt, ##arg); | |
213 | ||
214 | ||
d43dae75 JC |
215 | /* |
216 | * Flag manipulation helpers | |
217 | */ | |
218 | static void mcam_reset_buffers(struct mcam_camera *cam) | |
219 | { | |
220 | int i; | |
221 | ||
222 | cam->next_buf = -1; | |
223 | for (i = 0; i < cam->nbufs; i++) | |
224 | clear_bit(i, &cam->flags); | |
225 | } | |
226 | ||
227 | static inline int mcam_needs_config(struct mcam_camera *cam) | |
228 | { | |
229 | return test_bit(CF_CONFIG_NEEDED, &cam->flags); | |
230 | } | |
231 | ||
232 | static void mcam_set_config_needed(struct mcam_camera *cam, int needed) | |
233 | { | |
234 | if (needed) | |
235 | set_bit(CF_CONFIG_NEEDED, &cam->flags); | |
236 | else | |
237 | clear_bit(CF_CONFIG_NEEDED, &cam->flags); | |
238 | } | |
abfa3df3 JC |
239 | |
240 | /* ------------------------------------------------------------------- */ | |
241 | /* | |
d43dae75 JC |
242 | * Make the controller start grabbing images. Everything must |
243 | * be set up before doing this. | |
abfa3df3 | 244 | */ |
d43dae75 JC |
245 | static void mcam_ctlr_start(struct mcam_camera *cam) |
246 | { | |
247 | /* set_bit performs a read, so no other barrier should be | |
248 | needed here */ | |
249 | mcam_reg_set_bit(cam, REG_CTRL0, C0_ENABLE); | |
250 | } | |
251 | ||
252 | static void mcam_ctlr_stop(struct mcam_camera *cam) | |
253 | { | |
254 | mcam_reg_clear_bit(cam, REG_CTRL0, C0_ENABLE); | |
255 | } | |
256 | ||
257 | /* ------------------------------------------------------------------- */ | |
7498469f JC |
258 | |
259 | #ifdef MCAM_MODE_VMALLOC | |
d43dae75 JC |
260 | /* |
261 | * Code specific to the vmalloc buffer mode. | |
262 | */ | |
263 | ||
264 | /* | |
265 | * Allocate in-kernel DMA buffers for vmalloc mode. | |
266 | */ | |
267 | static int mcam_alloc_dma_bufs(struct mcam_camera *cam, int loadtime) | |
268 | { | |
269 | int i; | |
270 | ||
271 | mcam_set_config_needed(cam, 1); | |
272 | if (loadtime) | |
273 | cam->dma_buf_size = dma_buf_size; | |
274 | else | |
275 | cam->dma_buf_size = cam->pix_format.sizeimage; | |
276 | if (n_dma_bufs > 3) | |
277 | n_dma_bufs = 3; | |
278 | ||
279 | cam->nbufs = 0; | |
280 | for (i = 0; i < n_dma_bufs; i++) { | |
281 | cam->dma_bufs[i] = dma_alloc_coherent(cam->dev, | |
282 | cam->dma_buf_size, cam->dma_handles + i, | |
283 | GFP_KERNEL); | |
284 | if (cam->dma_bufs[i] == NULL) { | |
285 | cam_warn(cam, "Failed to allocate DMA buffer\n"); | |
286 | break; | |
287 | } | |
288 | (cam->nbufs)++; | |
289 | } | |
290 | ||
291 | switch (cam->nbufs) { | |
292 | case 1: | |
293 | dma_free_coherent(cam->dev, cam->dma_buf_size, | |
294 | cam->dma_bufs[0], cam->dma_handles[0]); | |
295 | cam->nbufs = 0; | |
296 | case 0: | |
297 | cam_err(cam, "Insufficient DMA buffers, cannot operate\n"); | |
298 | return -ENOMEM; | |
299 | ||
300 | case 2: | |
301 | if (n_dma_bufs > 2) | |
302 | cam_warn(cam, "Will limp along with only 2 buffers\n"); | |
303 | break; | |
304 | } | |
305 | return 0; | |
306 | } | |
307 | ||
308 | static void mcam_free_dma_bufs(struct mcam_camera *cam) | |
309 | { | |
310 | int i; | |
311 | ||
312 | for (i = 0; i < cam->nbufs; i++) { | |
313 | dma_free_coherent(cam->dev, cam->dma_buf_size, | |
314 | cam->dma_bufs[i], cam->dma_handles[i]); | |
315 | cam->dma_bufs[i] = NULL; | |
316 | } | |
317 | cam->nbufs = 0; | |
318 | } | |
319 | ||
abfa3df3 JC |
320 | |
321 | /* | |
a9b36e85 | 322 | * Set up DMA buffers when operating in vmalloc mode |
abfa3df3 | 323 | */ |
a9b36e85 | 324 | static void mcam_ctlr_dma_vmalloc(struct mcam_camera *cam) |
abfa3df3 JC |
325 | { |
326 | /* | |
327 | * Store the first two Y buffers (we aren't supporting | |
328 | * planar formats for now, so no UV bufs). Then either | |
329 | * set the third if it exists, or tell the controller | |
330 | * to just use two. | |
331 | */ | |
332 | mcam_reg_write(cam, REG_Y0BAR, cam->dma_handles[0]); | |
333 | mcam_reg_write(cam, REG_Y1BAR, cam->dma_handles[1]); | |
334 | if (cam->nbufs > 2) { | |
335 | mcam_reg_write(cam, REG_Y2BAR, cam->dma_handles[2]); | |
336 | mcam_reg_clear_bit(cam, REG_CTRL1, C1_TWOBUFS); | |
337 | } else | |
338 | mcam_reg_set_bit(cam, REG_CTRL1, C1_TWOBUFS); | |
67a8dbbc JC |
339 | if (cam->chip_id == V4L2_IDENT_CAFE) |
340 | mcam_reg_write(cam, REG_UBAR, 0); /* 32 bits only */ | |
abfa3df3 JC |
341 | } |
342 | ||
d43dae75 JC |
343 | /* |
344 | * Copy data out to user space in the vmalloc case | |
345 | */ | |
346 | static void mcam_frame_tasklet(unsigned long data) | |
347 | { | |
348 | struct mcam_camera *cam = (struct mcam_camera *) data; | |
349 | int i; | |
350 | unsigned long flags; | |
351 | struct mcam_vb_buffer *buf; | |
352 | ||
353 | spin_lock_irqsave(&cam->dev_lock, flags); | |
354 | for (i = 0; i < cam->nbufs; i++) { | |
355 | int bufno = cam->next_buf; | |
356 | ||
357 | if (cam->state != S_STREAMING || bufno < 0) | |
358 | break; /* I/O got stopped */ | |
359 | if (++(cam->next_buf) >= cam->nbufs) | |
360 | cam->next_buf = 0; | |
361 | if (!test_bit(bufno, &cam->flags)) | |
362 | continue; | |
363 | if (list_empty(&cam->buffers)) { | |
f698957a | 364 | cam->frame_state.singles++; |
d43dae75 JC |
365 | break; /* Leave it valid, hope for better later */ |
366 | } | |
f698957a | 367 | cam->frame_state.delivered++; |
d43dae75 JC |
368 | clear_bit(bufno, &cam->flags); |
369 | buf = list_first_entry(&cam->buffers, struct mcam_vb_buffer, | |
370 | queue); | |
371 | list_del_init(&buf->queue); | |
372 | /* | |
373 | * Drop the lock during the big copy. This *should* be safe... | |
374 | */ | |
375 | spin_unlock_irqrestore(&cam->dev_lock, flags); | |
376 | memcpy(vb2_plane_vaddr(&buf->vb_buf, 0), cam->dma_bufs[bufno], | |
377 | cam->pix_format.sizeimage); | |
378 | mcam_buffer_done(cam, bufno, &buf->vb_buf); | |
379 | spin_lock_irqsave(&cam->dev_lock, flags); | |
380 | } | |
381 | spin_unlock_irqrestore(&cam->dev_lock, flags); | |
382 | } | |
383 | ||
384 | ||
7498469f JC |
385 | /* |
386 | * Make sure our allocated buffers are up to the task. | |
387 | */ | |
388 | static int mcam_check_dma_buffers(struct mcam_camera *cam) | |
389 | { | |
390 | if (cam->nbufs > 0 && cam->dma_buf_size < cam->pix_format.sizeimage) | |
391 | mcam_free_dma_bufs(cam); | |
392 | if (cam->nbufs == 0) | |
393 | return mcam_alloc_dma_bufs(cam, 0); | |
394 | return 0; | |
395 | } | |
396 | ||
397 | static void mcam_vmalloc_done(struct mcam_camera *cam, int frame) | |
398 | { | |
399 | tasklet_schedule(&cam->s_tasklet); | |
400 | } | |
401 | ||
402 | #else /* MCAM_MODE_VMALLOC */ | |
403 | ||
404 | static inline int mcam_alloc_dma_bufs(struct mcam_camera *cam, int loadtime) | |
405 | { | |
406 | return 0; | |
407 | } | |
408 | ||
409 | static inline void mcam_free_dma_bufs(struct mcam_camera *cam) | |
410 | { | |
411 | return; | |
412 | } | |
413 | ||
414 | static inline int mcam_check_dma_buffers(struct mcam_camera *cam) | |
415 | { | |
416 | return 0; | |
417 | } | |
418 | ||
419 | ||
420 | ||
421 | #endif /* MCAM_MODE_VMALLOC */ | |
422 | ||
423 | ||
424 | #ifdef MCAM_MODE_DMA_CONTIG | |
d43dae75 JC |
425 | /* ---------------------------------------------------------------------- */ |
426 | /* | |
427 | * DMA-contiguous code. | |
428 | */ | |
a9b36e85 JC |
429 | /* |
430 | * Set up a contiguous buffer for the given frame. Here also is where | |
431 | * the underrun strategy is set: if there is no buffer available, reuse | |
432 | * the buffer from the other BAR and set the CF_SINGLE_BUFFER flag to | |
433 | * keep the interrupt handler from giving that buffer back to user | |
434 | * space. In this way, we always have a buffer to DMA to and don't | |
435 | * have to try to play games stopping and restarting the controller. | |
436 | */ | |
437 | static void mcam_set_contig_buffer(struct mcam_camera *cam, int frame) | |
438 | { | |
439 | struct mcam_vb_buffer *buf; | |
440 | /* | |
441 | * If there are no available buffers, go into single mode | |
442 | */ | |
443 | if (list_empty(&cam->buffers)) { | |
444 | buf = cam->vb_bufs[frame ^ 0x1]; | |
445 | cam->vb_bufs[frame] = buf; | |
446 | mcam_reg_write(cam, frame == 0 ? REG_Y0BAR : REG_Y1BAR, | |
ba7fcb0c | 447 | vb2_dma_contig_plane_dma_addr(&buf->vb_buf, 0)); |
a9b36e85 | 448 | set_bit(CF_SINGLE_BUFFER, &cam->flags); |
f698957a | 449 | cam->frame_state.singles++; |
a9b36e85 JC |
450 | return; |
451 | } | |
452 | /* | |
453 | * OK, we have a buffer we can use. | |
454 | */ | |
455 | buf = list_first_entry(&cam->buffers, struct mcam_vb_buffer, queue); | |
456 | list_del_init(&buf->queue); | |
457 | mcam_reg_write(cam, frame == 0 ? REG_Y0BAR : REG_Y1BAR, | |
ba7fcb0c | 458 | vb2_dma_contig_plane_dma_addr(&buf->vb_buf, 0)); |
a9b36e85 JC |
459 | cam->vb_bufs[frame] = buf; |
460 | clear_bit(CF_SINGLE_BUFFER, &cam->flags); | |
461 | } | |
462 | ||
cbc4f3a2 JC |
463 | /* |
464 | * Initial B_DMA_contig setup. | |
465 | */ | |
a9b36e85 JC |
466 | static void mcam_ctlr_dma_contig(struct mcam_camera *cam) |
467 | { | |
468 | mcam_reg_set_bit(cam, REG_CTRL1, C1_TWOBUFS); | |
469 | cam->nbufs = 2; | |
470 | mcam_set_contig_buffer(cam, 0); | |
471 | mcam_set_contig_buffer(cam, 1); | |
472 | } | |
473 | ||
d43dae75 JC |
474 | /* |
475 | * Frame completion handling. | |
476 | */ | |
477 | static void mcam_dma_contig_done(struct mcam_camera *cam, int frame) | |
478 | { | |
479 | struct mcam_vb_buffer *buf = cam->vb_bufs[frame]; | |
480 | ||
481 | if (!test_bit(CF_SINGLE_BUFFER, &cam->flags)) { | |
f698957a | 482 | cam->frame_state.delivered++; |
d43dae75 JC |
483 | mcam_buffer_done(cam, frame, &buf->vb_buf); |
484 | } | |
485 | mcam_set_contig_buffer(cam, frame); | |
486 | } | |
487 | ||
7498469f | 488 | #endif /* MCAM_MODE_DMA_CONTIG */ |
d43dae75 | 489 | |
7498469f | 490 | #ifdef MCAM_MODE_DMA_SG |
d43dae75 JC |
491 | /* ---------------------------------------------------------------------- */ |
492 | /* | |
493 | * Scatter/gather-specific code. | |
494 | */ | |
a9b36e85 | 495 | |
cbc4f3a2 JC |
496 | /* |
497 | * Set up the next buffer for S/G I/O; caller should be sure that | |
498 | * the controller is stopped and a buffer is available. | |
499 | */ | |
500 | static void mcam_sg_next_buffer(struct mcam_camera *cam) | |
a9b36e85 | 501 | { |
cbc4f3a2 JC |
502 | struct mcam_vb_buffer *buf; |
503 | ||
504 | buf = list_first_entry(&cam->buffers, struct mcam_vb_buffer, queue); | |
505 | list_del_init(&buf->queue); | |
121bbe25 JC |
506 | /* |
507 | * Very Bad Not Good Things happen if you don't clear | |
508 | * C1_DESC_ENA before making any descriptor changes. | |
509 | */ | |
510 | mcam_reg_clear_bit(cam, REG_CTRL1, C1_DESC_ENA); | |
cbc4f3a2 JC |
511 | mcam_reg_write(cam, REG_DMA_DESC_Y, buf->dma_desc_pa); |
512 | mcam_reg_write(cam, REG_DESC_LEN_Y, | |
513 | buf->dma_desc_nent*sizeof(struct mcam_dma_desc)); | |
514 | mcam_reg_write(cam, REG_DESC_LEN_U, 0); | |
515 | mcam_reg_write(cam, REG_DESC_LEN_V, 0); | |
121bbe25 | 516 | mcam_reg_set_bit(cam, REG_CTRL1, C1_DESC_ENA); |
cbc4f3a2 | 517 | cam->vb_bufs[0] = buf; |
a9b36e85 JC |
518 | } |
519 | ||
cbc4f3a2 JC |
520 | /* |
521 | * Initial B_DMA_sg setup | |
522 | */ | |
523 | static void mcam_ctlr_dma_sg(struct mcam_camera *cam) | |
524 | { | |
bb0a896e JC |
525 | /* |
526 | * The list-empty condition can hit us at resume time | |
527 | * if the buffer list was empty when the system was suspended. | |
528 | */ | |
529 | if (list_empty(&cam->buffers)) { | |
530 | set_bit(CF_SG_RESTART, &cam->flags); | |
531 | return; | |
532 | } | |
533 | ||
cbc4f3a2 JC |
534 | mcam_reg_clear_bit(cam, REG_CTRL1, C1_DESC_3WORD); |
535 | mcam_sg_next_buffer(cam); | |
cbc4f3a2 JC |
536 | cam->nbufs = 3; |
537 | } | |
538 | ||
d43dae75 | 539 | |
cbc4f3a2 | 540 | /* |
d43dae75 JC |
541 | * Frame completion with S/G is trickier. We can't muck with |
542 | * a descriptor chain on the fly, since the controller buffers it | |
543 | * internally. So we have to actually stop and restart; Marvell | |
544 | * says this is the way to do it. | |
545 | * | |
546 | * Of course, stopping is easier said than done; experience shows | |
547 | * that the controller can start a frame *after* C0_ENABLE has been | |
548 | * cleared. So when running in S/G mode, the controller is "stopped" | |
549 | * on receipt of the start-of-frame interrupt. That means we can | |
550 | * safely change the DMA descriptor array here and restart things | |
551 | * (assuming there's another buffer waiting to go). | |
552 | */ | |
553 | static void mcam_dma_sg_done(struct mcam_camera *cam, int frame) | |
554 | { | |
555 | struct mcam_vb_buffer *buf = cam->vb_bufs[0]; | |
556 | ||
49df19eb JC |
557 | /* |
558 | * If we're no longer supposed to be streaming, don't do anything. | |
559 | */ | |
560 | if (cam->state != S_STREAMING) | |
561 | return; | |
d43dae75 JC |
562 | /* |
563 | * If we have another buffer available, put it in and | |
564 | * restart the engine. | |
565 | */ | |
566 | if (!list_empty(&cam->buffers)) { | |
567 | mcam_sg_next_buffer(cam); | |
d43dae75 JC |
568 | mcam_ctlr_start(cam); |
569 | /* | |
570 | * Otherwise set CF_SG_RESTART and the controller will | |
571 | * be restarted once another buffer shows up. | |
572 | */ | |
573 | } else { | |
574 | set_bit(CF_SG_RESTART, &cam->flags); | |
f698957a | 575 | cam->frame_state.singles++; |
bb0a896e | 576 | cam->vb_bufs[0] = NULL; |
d43dae75 JC |
577 | } |
578 | /* | |
579 | * Now we can give the completed frame back to user space. | |
580 | */ | |
f698957a | 581 | cam->frame_state.delivered++; |
d43dae75 JC |
582 | mcam_buffer_done(cam, frame, &buf->vb_buf); |
583 | } | |
584 | ||
585 | ||
586 | /* | |
587 | * Scatter/gather mode requires stopping the controller between | |
588 | * frames so we can put in a new DMA descriptor array. If no new | |
589 | * buffer exists at frame completion, the controller is left stopped; | |
590 | * this function is charged with gettig things going again. | |
591 | */ | |
592 | static void mcam_sg_restart(struct mcam_camera *cam) | |
593 | { | |
594 | mcam_ctlr_dma_sg(cam); | |
595 | mcam_ctlr_start(cam); | |
596 | clear_bit(CF_SG_RESTART, &cam->flags); | |
597 | } | |
598 | ||
7498469f JC |
599 | #else /* MCAM_MODE_DMA_SG */ |
600 | ||
601 | static inline void mcam_sg_restart(struct mcam_camera *cam) | |
602 | { | |
603 | return; | |
604 | } | |
605 | ||
606 | #endif /* MCAM_MODE_DMA_SG */ | |
d43dae75 JC |
607 | |
608 | /* ---------------------------------------------------------------------- */ | |
609 | /* | |
610 | * Buffer-mode-independent controller code. | |
611 | */ | |
612 | ||
613 | /* | |
614 | * Image format setup | |
cbc4f3a2 | 615 | */ |
abfa3df3 JC |
616 | static void mcam_ctlr_image(struct mcam_camera *cam) |
617 | { | |
618 | int imgsz; | |
619 | struct v4l2_pix_format *fmt = &cam->pix_format; | |
620 | ||
621 | imgsz = ((fmt->height << IMGSZ_V_SHIFT) & IMGSZ_V_MASK) | | |
622 | (fmt->bytesperline & IMGSZ_H_MASK); | |
623 | mcam_reg_write(cam, REG_IMGSIZE, imgsz); | |
624 | mcam_reg_write(cam, REG_IMGOFFSET, 0); | |
625 | /* YPITCH just drops the last two bits */ | |
626 | mcam_reg_write_mask(cam, REG_IMGPITCH, fmt->bytesperline, | |
627 | IMGP_YP_MASK); | |
628 | /* | |
629 | * Tell the controller about the image format we are using. | |
630 | */ | |
631 | switch (cam->pix_format.pixelformat) { | |
632 | case V4L2_PIX_FMT_YUYV: | |
633 | mcam_reg_write_mask(cam, REG_CTRL0, | |
634 | C0_DF_YUV|C0_YUV_PACKED|C0_YUVE_YUYV, | |
635 | C0_DF_MASK); | |
636 | break; | |
637 | ||
638 | case V4L2_PIX_FMT_RGB444: | |
639 | mcam_reg_write_mask(cam, REG_CTRL0, | |
640 | C0_DF_RGB|C0_RGBF_444|C0_RGB4_XRGB, | |
641 | C0_DF_MASK); | |
642 | /* Alpha value? */ | |
643 | break; | |
644 | ||
645 | case V4L2_PIX_FMT_RGB565: | |
646 | mcam_reg_write_mask(cam, REG_CTRL0, | |
647 | C0_DF_RGB|C0_RGBF_565|C0_RGB5_BGGR, | |
648 | C0_DF_MASK); | |
649 | break; | |
650 | ||
651 | default: | |
652 | cam_err(cam, "Unknown format %x\n", cam->pix_format.pixelformat); | |
653 | break; | |
654 | } | |
655 | /* | |
656 | * Make sure it knows we want to use hsync/vsync. | |
657 | */ | |
658 | mcam_reg_write_mask(cam, REG_CTRL0, C0_SIF_HVSYNC, | |
659 | C0_SIFM_MASK); | |
660 | } | |
661 | ||
662 | ||
663 | /* | |
664 | * Configure the controller for operation; caller holds the | |
665 | * device mutex. | |
666 | */ | |
667 | static int mcam_ctlr_configure(struct mcam_camera *cam) | |
668 | { | |
669 | unsigned long flags; | |
670 | ||
671 | spin_lock_irqsave(&cam->dev_lock, flags); | |
bb0a896e | 672 | clear_bit(CF_SG_RESTART, &cam->flags); |
7498469f | 673 | cam->dma_setup(cam); |
abfa3df3 JC |
674 | mcam_ctlr_image(cam); |
675 | mcam_set_config_needed(cam, 0); | |
676 | spin_unlock_irqrestore(&cam->dev_lock, flags); | |
677 | return 0; | |
678 | } | |
679 | ||
680 | static void mcam_ctlr_irq_enable(struct mcam_camera *cam) | |
681 | { | |
682 | /* | |
683 | * Clear any pending interrupts, since we do not | |
684 | * expect to have I/O active prior to enabling. | |
685 | */ | |
686 | mcam_reg_write(cam, REG_IRQSTAT, FRAMEIRQS); | |
687 | mcam_reg_set_bit(cam, REG_IRQMASK, FRAMEIRQS); | |
688 | } | |
689 | ||
690 | static void mcam_ctlr_irq_disable(struct mcam_camera *cam) | |
691 | { | |
692 | mcam_reg_clear_bit(cam, REG_IRQMASK, FRAMEIRQS); | |
693 | } | |
694 | ||
abfa3df3 | 695 | |
cbc4f3a2 | 696 | |
abfa3df3 JC |
697 | static void mcam_ctlr_init(struct mcam_camera *cam) |
698 | { | |
699 | unsigned long flags; | |
700 | ||
701 | spin_lock_irqsave(&cam->dev_lock, flags); | |
702 | /* | |
703 | * Make sure it's not powered down. | |
704 | */ | |
705 | mcam_reg_clear_bit(cam, REG_CTRL1, C1_PWRDWN); | |
706 | /* | |
707 | * Turn off the enable bit. It sure should be off anyway, | |
708 | * but it's good to be sure. | |
709 | */ | |
710 | mcam_reg_clear_bit(cam, REG_CTRL0, C0_ENABLE); | |
711 | /* | |
712 | * Clock the sensor appropriately. Controller clock should | |
713 | * be 48MHz, sensor "typical" value is half that. | |
714 | */ | |
715 | mcam_reg_write_mask(cam, REG_CLKCTRL, 2, CLK_DIV_MASK); | |
716 | spin_unlock_irqrestore(&cam->dev_lock, flags); | |
717 | } | |
718 | ||
719 | ||
720 | /* | |
721 | * Stop the controller, and don't return until we're really sure that no | |
722 | * further DMA is going on. | |
723 | */ | |
724 | static void mcam_ctlr_stop_dma(struct mcam_camera *cam) | |
725 | { | |
726 | unsigned long flags; | |
727 | ||
728 | /* | |
729 | * Theory: stop the camera controller (whether it is operating | |
730 | * or not). Delay briefly just in case we race with the SOF | |
731 | * interrupt, then wait until no DMA is active. | |
732 | */ | |
733 | spin_lock_irqsave(&cam->dev_lock, flags); | |
cbc4f3a2 | 734 | clear_bit(CF_SG_RESTART, &cam->flags); |
abfa3df3 | 735 | mcam_ctlr_stop(cam); |
cbc4f3a2 | 736 | cam->state = S_IDLE; |
abfa3df3 | 737 | spin_unlock_irqrestore(&cam->dev_lock, flags); |
482d35c4 JC |
738 | /* |
739 | * This is a brutally long sleep, but experience shows that | |
740 | * it can take the controller a while to get the message that | |
741 | * it needs to stop grabbing frames. In particular, we can | |
742 | * sometimes (on mmp) get a frame at the end WITHOUT the | |
743 | * start-of-frame indication. | |
744 | */ | |
745 | msleep(150); | |
abfa3df3 JC |
746 | if (test_bit(CF_DMA_ACTIVE, &cam->flags)) |
747 | cam_err(cam, "Timeout waiting for DMA to end\n"); | |
748 | /* This would be bad news - what now? */ | |
749 | spin_lock_irqsave(&cam->dev_lock, flags); | |
abfa3df3 JC |
750 | mcam_ctlr_irq_disable(cam); |
751 | spin_unlock_irqrestore(&cam->dev_lock, flags); | |
752 | } | |
753 | ||
754 | /* | |
755 | * Power up and down. | |
756 | */ | |
757 | static void mcam_ctlr_power_up(struct mcam_camera *cam) | |
758 | { | |
759 | unsigned long flags; | |
760 | ||
761 | spin_lock_irqsave(&cam->dev_lock, flags); | |
abfa3df3 | 762 | cam->plat_power_up(cam); |
67a8dbbc | 763 | mcam_reg_clear_bit(cam, REG_CTRL1, C1_PWRDWN); |
abfa3df3 JC |
764 | spin_unlock_irqrestore(&cam->dev_lock, flags); |
765 | msleep(5); /* Just to be sure */ | |
766 | } | |
767 | ||
768 | static void mcam_ctlr_power_down(struct mcam_camera *cam) | |
769 | { | |
770 | unsigned long flags; | |
771 | ||
772 | spin_lock_irqsave(&cam->dev_lock, flags); | |
67a8dbbc JC |
773 | /* |
774 | * School of hard knocks department: be sure we do any register | |
775 | * twiddling on the controller *before* calling the platform | |
776 | * power down routine. | |
777 | */ | |
abfa3df3 | 778 | mcam_reg_set_bit(cam, REG_CTRL1, C1_PWRDWN); |
67a8dbbc | 779 | cam->plat_power_down(cam); |
abfa3df3 JC |
780 | spin_unlock_irqrestore(&cam->dev_lock, flags); |
781 | } | |
782 | ||
783 | /* -------------------------------------------------------------------- */ | |
784 | /* | |
785 | * Communications with the sensor. | |
786 | */ | |
787 | ||
788 | static int __mcam_cam_reset(struct mcam_camera *cam) | |
789 | { | |
790 | return sensor_call(cam, core, reset, 0); | |
791 | } | |
792 | ||
793 | /* | |
794 | * We have found the sensor on the i2c. Let's try to have a | |
795 | * conversation. | |
796 | */ | |
797 | static int mcam_cam_init(struct mcam_camera *cam) | |
798 | { | |
799 | struct v4l2_dbg_chip_ident chip; | |
800 | int ret; | |
801 | ||
802 | mutex_lock(&cam->s_mutex); | |
803 | if (cam->state != S_NOTREADY) | |
804 | cam_warn(cam, "Cam init with device in funky state %d", | |
805 | cam->state); | |
806 | ret = __mcam_cam_reset(cam); | |
807 | if (ret) | |
808 | goto out; | |
809 | chip.ident = V4L2_IDENT_NONE; | |
810 | chip.match.type = V4L2_CHIP_MATCH_I2C_ADDR; | |
811 | chip.match.addr = cam->sensor_addr; | |
812 | ret = sensor_call(cam, core, g_chip_ident, &chip); | |
813 | if (ret) | |
814 | goto out; | |
815 | cam->sensor_type = chip.ident; | |
816 | if (cam->sensor_type != V4L2_IDENT_OV7670) { | |
817 | cam_err(cam, "Unsupported sensor type 0x%x", cam->sensor_type); | |
818 | ret = -EINVAL; | |
819 | goto out; | |
820 | } | |
821 | /* Get/set parameters? */ | |
d43dae75 JC |
822 | ret = 0; |
823 | cam->state = S_IDLE; | |
824 | out: | |
825 | mcam_ctlr_power_down(cam); | |
826 | mutex_unlock(&cam->s_mutex); | |
827 | return ret; | |
abfa3df3 JC |
828 | } |
829 | ||
d43dae75 JC |
830 | /* |
831 | * Configure the sensor to match the parameters we have. Caller should | |
832 | * hold s_mutex | |
833 | */ | |
834 | static int mcam_cam_set_flip(struct mcam_camera *cam) | |
abfa3df3 | 835 | { |
d43dae75 | 836 | struct v4l2_control ctrl; |
abfa3df3 | 837 | |
d43dae75 JC |
838 | memset(&ctrl, 0, sizeof(ctrl)); |
839 | ctrl.id = V4L2_CID_VFLIP; | |
840 | ctrl.value = flip; | |
841 | return sensor_call(cam, core, s_ctrl, &ctrl); | |
abfa3df3 JC |
842 | } |
843 | ||
844 | ||
d43dae75 JC |
845 | static int mcam_cam_configure(struct mcam_camera *cam) |
846 | { | |
847 | struct v4l2_mbus_framefmt mbus_fmt; | |
848 | int ret; | |
abfa3df3 | 849 | |
d43dae75 JC |
850 | v4l2_fill_mbus_format(&mbus_fmt, &cam->pix_format, cam->mbus_code); |
851 | ret = sensor_call(cam, core, init, 0); | |
852 | if (ret == 0) | |
853 | ret = sensor_call(cam, video, s_mbus_fmt, &mbus_fmt); | |
854 | /* | |
855 | * OV7670 does weird things if flip is set *before* format... | |
856 | */ | |
857 | ret += mcam_cam_set_flip(cam); | |
858 | return ret; | |
859 | } | |
abfa3df3 JC |
860 | |
861 | /* | |
862 | * Get everything ready, and start grabbing frames. | |
863 | */ | |
a9b36e85 | 864 | static int mcam_read_setup(struct mcam_camera *cam) |
abfa3df3 JC |
865 | { |
866 | int ret; | |
867 | unsigned long flags; | |
868 | ||
869 | /* | |
870 | * Configuration. If we still don't have DMA buffers, | |
871 | * make one last, desperate attempt. | |
872 | */ | |
a9b36e85 JC |
873 | if (cam->buffer_mode == B_vmalloc && cam->nbufs == 0 && |
874 | mcam_alloc_dma_bufs(cam, 0)) | |
875 | return -ENOMEM; | |
abfa3df3 JC |
876 | |
877 | if (mcam_needs_config(cam)) { | |
878 | mcam_cam_configure(cam); | |
879 | ret = mcam_ctlr_configure(cam); | |
880 | if (ret) | |
881 | return ret; | |
882 | } | |
883 | ||
884 | /* | |
885 | * Turn it loose. | |
886 | */ | |
887 | spin_lock_irqsave(&cam->dev_lock, flags); | |
482d35c4 | 888 | clear_bit(CF_DMA_ACTIVE, &cam->flags); |
abfa3df3 JC |
889 | mcam_reset_buffers(cam); |
890 | mcam_ctlr_irq_enable(cam); | |
a9b36e85 | 891 | cam->state = S_STREAMING; |
bb0a896e JC |
892 | if (!test_bit(CF_SG_RESTART, &cam->flags)) |
893 | mcam_ctlr_start(cam); | |
abfa3df3 JC |
894 | spin_unlock_irqrestore(&cam->dev_lock, flags); |
895 | return 0; | |
896 | } | |
897 | ||
b5210fd2 JC |
898 | /* ----------------------------------------------------------------------- */ |
899 | /* | |
900 | * Videobuf2 interface code. | |
901 | */ | |
abfa3df3 | 902 | |
fc714e70 GL |
903 | static int mcam_vb_queue_setup(struct vb2_queue *vq, |
904 | const struct v4l2_format *fmt, unsigned int *nbufs, | |
035aa147 | 905 | unsigned int *num_planes, unsigned int sizes[], |
b5210fd2 | 906 | void *alloc_ctxs[]) |
abfa3df3 | 907 | { |
b5210fd2 | 908 | struct mcam_camera *cam = vb2_get_drv_priv(vq); |
cbc4f3a2 | 909 | int minbufs = (cam->buffer_mode == B_DMA_contig) ? 3 : 2; |
b5210fd2 JC |
910 | |
911 | sizes[0] = cam->pix_format.sizeimage; | |
912 | *num_planes = 1; /* Someday we have to support planar formats... */ | |
cbc4f3a2 JC |
913 | if (*nbufs < minbufs) |
914 | *nbufs = minbufs; | |
a9b36e85 JC |
915 | if (cam->buffer_mode == B_DMA_contig) |
916 | alloc_ctxs[0] = cam->vb_alloc_ctx; | |
b5210fd2 JC |
917 | return 0; |
918 | } | |
919 | ||
cbc4f3a2 | 920 | |
b5210fd2 JC |
921 | static void mcam_vb_buf_queue(struct vb2_buffer *vb) |
922 | { | |
923 | struct mcam_vb_buffer *mvb = vb_to_mvb(vb); | |
924 | struct mcam_camera *cam = vb2_get_drv_priv(vb->vb2_queue); | |
925 | unsigned long flags; | |
a9b36e85 | 926 | int start; |
b5210fd2 JC |
927 | |
928 | spin_lock_irqsave(&cam->dev_lock, flags); | |
a9b36e85 JC |
929 | start = (cam->state == S_BUFWAIT) && !list_empty(&cam->buffers); |
930 | list_add(&mvb->queue, &cam->buffers); | |
49df19eb | 931 | if (cam->state == S_STREAMING && test_bit(CF_SG_RESTART, &cam->flags)) |
cbc4f3a2 | 932 | mcam_sg_restart(cam); |
b5210fd2 | 933 | spin_unlock_irqrestore(&cam->dev_lock, flags); |
a9b36e85 JC |
934 | if (start) |
935 | mcam_read_setup(cam); | |
b5210fd2 JC |
936 | } |
937 | ||
cbc4f3a2 | 938 | |
b5210fd2 JC |
939 | /* |
940 | * vb2 uses these to release the mutex when waiting in dqbuf. I'm | |
941 | * not actually sure we need to do this (I'm not sure that vb2_dqbuf() needs | |
942 | * to be called with the mutex held), but better safe than sorry. | |
943 | */ | |
944 | static void mcam_vb_wait_prepare(struct vb2_queue *vq) | |
945 | { | |
946 | struct mcam_camera *cam = vb2_get_drv_priv(vq); | |
947 | ||
948 | mutex_unlock(&cam->s_mutex); | |
949 | } | |
950 | ||
951 | static void mcam_vb_wait_finish(struct vb2_queue *vq) | |
952 | { | |
953 | struct mcam_camera *cam = vb2_get_drv_priv(vq); | |
abfa3df3 | 954 | |
abfa3df3 | 955 | mutex_lock(&cam->s_mutex); |
b5210fd2 | 956 | } |
abfa3df3 | 957 | |
b5210fd2 JC |
958 | /* |
959 | * These need to be called with the mutex held from vb2 | |
960 | */ | |
bd323e28 | 961 | static int mcam_vb_start_streaming(struct vb2_queue *vq, unsigned int count) |
b5210fd2 JC |
962 | { |
963 | struct mcam_camera *cam = vb2_get_drv_priv(vq); | |
abfa3df3 | 964 | |
bd323e28 MS |
965 | if (cam->state != S_IDLE) { |
966 | INIT_LIST_HEAD(&cam->buffers); | |
a9b36e85 | 967 | return -EINVAL; |
bd323e28 | 968 | } |
a9b36e85 JC |
969 | cam->sequence = 0; |
970 | /* | |
971 | * Videobuf2 sneakily hoards all the buffers and won't | |
972 | * give them to us until *after* streaming starts. But | |
973 | * we can't actually start streaming until we have a | |
974 | * destination. So go into a wait state and hope they | |
975 | * give us buffers soon. | |
976 | */ | |
977 | if (cam->buffer_mode != B_vmalloc && list_empty(&cam->buffers)) { | |
978 | cam->state = S_BUFWAIT; | |
979 | return 0; | |
abfa3df3 | 980 | } |
a9b36e85 | 981 | return mcam_read_setup(cam); |
b5210fd2 JC |
982 | } |
983 | ||
984 | static int mcam_vb_stop_streaming(struct vb2_queue *vq) | |
985 | { | |
986 | struct mcam_camera *cam = vb2_get_drv_priv(vq); | |
987 | unsigned long flags; | |
988 | ||
a9b36e85 JC |
989 | if (cam->state == S_BUFWAIT) { |
990 | /* They never gave us buffers */ | |
991 | cam->state = S_IDLE; | |
992 | return 0; | |
993 | } | |
b5210fd2 JC |
994 | if (cam->state != S_STREAMING) |
995 | return -EINVAL; | |
996 | mcam_ctlr_stop_dma(cam); | |
abfa3df3 | 997 | /* |
b5210fd2 JC |
998 | * VB2 reclaims the buffers, so we need to forget |
999 | * about them. | |
abfa3df3 | 1000 | */ |
b5210fd2 JC |
1001 | spin_lock_irqsave(&cam->dev_lock, flags); |
1002 | INIT_LIST_HEAD(&cam->buffers); | |
1003 | spin_unlock_irqrestore(&cam->dev_lock, flags); | |
1004 | return 0; | |
abfa3df3 JC |
1005 | } |
1006 | ||
1007 | ||
b5210fd2 JC |
1008 | static const struct vb2_ops mcam_vb2_ops = { |
1009 | .queue_setup = mcam_vb_queue_setup, | |
b5210fd2 JC |
1010 | .buf_queue = mcam_vb_buf_queue, |
1011 | .start_streaming = mcam_vb_start_streaming, | |
1012 | .stop_streaming = mcam_vb_stop_streaming, | |
1013 | .wait_prepare = mcam_vb_wait_prepare, | |
1014 | .wait_finish = mcam_vb_wait_finish, | |
1015 | }; | |
abfa3df3 | 1016 | |
7498469f JC |
1017 | |
1018 | #ifdef MCAM_MODE_DMA_SG | |
cbc4f3a2 | 1019 | /* |
d43dae75 JC |
1020 | * Scatter/gather mode uses all of the above functions plus a |
1021 | * few extras to deal with DMA mapping. | |
cbc4f3a2 | 1022 | */ |
d43dae75 JC |
1023 | static int mcam_vb_sg_buf_init(struct vb2_buffer *vb) |
1024 | { | |
1025 | struct mcam_vb_buffer *mvb = vb_to_mvb(vb); | |
1026 | struct mcam_camera *cam = vb2_get_drv_priv(vb->vb2_queue); | |
1027 | int ndesc = cam->pix_format.sizeimage/PAGE_SIZE + 1; | |
1028 | ||
1029 | mvb->dma_desc = dma_alloc_coherent(cam->dev, | |
1030 | ndesc * sizeof(struct mcam_dma_desc), | |
1031 | &mvb->dma_desc_pa, GFP_KERNEL); | |
1032 | if (mvb->dma_desc == NULL) { | |
1033 | cam_err(cam, "Unable to get DMA descriptor array\n"); | |
1034 | return -ENOMEM; | |
1035 | } | |
1036 | return 0; | |
1037 | } | |
1038 | ||
1039 | static int mcam_vb_sg_buf_prepare(struct vb2_buffer *vb) | |
1040 | { | |
1041 | struct mcam_vb_buffer *mvb = vb_to_mvb(vb); | |
1042 | struct mcam_camera *cam = vb2_get_drv_priv(vb->vb2_queue); | |
1043 | struct vb2_dma_sg_desc *sgd = vb2_dma_sg_plane_desc(vb, 0); | |
1044 | struct mcam_dma_desc *desc = mvb->dma_desc; | |
1045 | struct scatterlist *sg; | |
1046 | int i; | |
1047 | ||
1048 | mvb->dma_desc_nent = dma_map_sg(cam->dev, sgd->sglist, sgd->num_pages, | |
1049 | DMA_FROM_DEVICE); | |
1050 | if (mvb->dma_desc_nent <= 0) | |
1051 | return -EIO; /* Not sure what's right here */ | |
1052 | for_each_sg(sgd->sglist, sg, mvb->dma_desc_nent, i) { | |
1053 | desc->dma_addr = sg_dma_address(sg); | |
1054 | desc->segment_len = sg_dma_len(sg); | |
1055 | desc++; | |
1056 | } | |
1057 | return 0; | |
1058 | } | |
1059 | ||
1060 | static int mcam_vb_sg_buf_finish(struct vb2_buffer *vb) | |
1061 | { | |
1062 | struct mcam_camera *cam = vb2_get_drv_priv(vb->vb2_queue); | |
1063 | struct vb2_dma_sg_desc *sgd = vb2_dma_sg_plane_desc(vb, 0); | |
1064 | ||
1065 | dma_unmap_sg(cam->dev, sgd->sglist, sgd->num_pages, DMA_FROM_DEVICE); | |
1066 | return 0; | |
1067 | } | |
1068 | ||
1069 | static void mcam_vb_sg_buf_cleanup(struct vb2_buffer *vb) | |
1070 | { | |
1071 | struct mcam_camera *cam = vb2_get_drv_priv(vb->vb2_queue); | |
1072 | struct mcam_vb_buffer *mvb = vb_to_mvb(vb); | |
1073 | int ndesc = cam->pix_format.sizeimage/PAGE_SIZE + 1; | |
1074 | ||
1075 | dma_free_coherent(cam->dev, ndesc * sizeof(struct mcam_dma_desc), | |
1076 | mvb->dma_desc, mvb->dma_desc_pa); | |
1077 | } | |
1078 | ||
1079 | ||
cbc4f3a2 JC |
1080 | static const struct vb2_ops mcam_vb2_sg_ops = { |
1081 | .queue_setup = mcam_vb_queue_setup, | |
1082 | .buf_init = mcam_vb_sg_buf_init, | |
1083 | .buf_prepare = mcam_vb_sg_buf_prepare, | |
1084 | .buf_queue = mcam_vb_buf_queue, | |
1085 | .buf_finish = mcam_vb_sg_buf_finish, | |
1086 | .buf_cleanup = mcam_vb_sg_buf_cleanup, | |
1087 | .start_streaming = mcam_vb_start_streaming, | |
1088 | .stop_streaming = mcam_vb_stop_streaming, | |
1089 | .wait_prepare = mcam_vb_wait_prepare, | |
1090 | .wait_finish = mcam_vb_wait_finish, | |
1091 | }; | |
1092 | ||
7498469f JC |
1093 | #endif /* MCAM_MODE_DMA_SG */ |
1094 | ||
b5210fd2 JC |
1095 | static int mcam_setup_vb2(struct mcam_camera *cam) |
1096 | { | |
1097 | struct vb2_queue *vq = &cam->vb_queue; | |
abfa3df3 | 1098 | |
b5210fd2 JC |
1099 | memset(vq, 0, sizeof(*vq)); |
1100 | vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; | |
b5210fd2 | 1101 | vq->drv_priv = cam; |
cbc4f3a2 JC |
1102 | INIT_LIST_HEAD(&cam->buffers); |
1103 | switch (cam->buffer_mode) { | |
1104 | case B_DMA_contig: | |
7498469f | 1105 | #ifdef MCAM_MODE_DMA_CONTIG |
cbc4f3a2 | 1106 | vq->ops = &mcam_vb2_ops; |
a9b36e85 JC |
1107 | vq->mem_ops = &vb2_dma_contig_memops; |
1108 | cam->vb_alloc_ctx = vb2_dma_contig_init_ctx(cam->dev); | |
cbc4f3a2 | 1109 | vq->io_modes = VB2_MMAP | VB2_USERPTR; |
7498469f JC |
1110 | cam->dma_setup = mcam_ctlr_dma_contig; |
1111 | cam->frame_complete = mcam_dma_contig_done; | |
1112 | #endif | |
cbc4f3a2 JC |
1113 | break; |
1114 | case B_DMA_sg: | |
7498469f | 1115 | #ifdef MCAM_MODE_DMA_SG |
cbc4f3a2 JC |
1116 | vq->ops = &mcam_vb2_sg_ops; |
1117 | vq->mem_ops = &vb2_dma_sg_memops; | |
1118 | vq->io_modes = VB2_MMAP | VB2_USERPTR; | |
7498469f JC |
1119 | cam->dma_setup = mcam_ctlr_dma_sg; |
1120 | cam->frame_complete = mcam_dma_sg_done; | |
1121 | #endif | |
cbc4f3a2 JC |
1122 | break; |
1123 | case B_vmalloc: | |
7498469f JC |
1124 | #ifdef MCAM_MODE_VMALLOC |
1125 | tasklet_init(&cam->s_tasklet, mcam_frame_tasklet, | |
1126 | (unsigned long) cam); | |
cbc4f3a2 | 1127 | vq->ops = &mcam_vb2_ops; |
a9b36e85 | 1128 | vq->mem_ops = &vb2_vmalloc_memops; |
cbc4f3a2 JC |
1129 | vq->buf_struct_size = sizeof(struct mcam_vb_buffer); |
1130 | vq->io_modes = VB2_MMAP; | |
7498469f JC |
1131 | cam->dma_setup = mcam_ctlr_dma_vmalloc; |
1132 | cam->frame_complete = mcam_vmalloc_done; | |
1133 | #endif | |
cbc4f3a2 JC |
1134 | break; |
1135 | } | |
b5210fd2 JC |
1136 | return vb2_queue_init(vq); |
1137 | } | |
1138 | ||
1139 | static void mcam_cleanup_vb2(struct mcam_camera *cam) | |
1140 | { | |
1141 | vb2_queue_release(&cam->vb_queue); | |
7498469f | 1142 | #ifdef MCAM_MODE_DMA_CONTIG |
a9b36e85 JC |
1143 | if (cam->buffer_mode == B_DMA_contig) |
1144 | vb2_dma_contig_cleanup_ctx(cam->vb_alloc_ctx); | |
7498469f | 1145 | #endif |
b5210fd2 JC |
1146 | } |
1147 | ||
abfa3df3 | 1148 | |
d43dae75 | 1149 | /* ---------------------------------------------------------------------- */ |
abfa3df3 | 1150 | /* |
d43dae75 | 1151 | * The long list of V4L2 ioctl() operations. |
abfa3df3 JC |
1152 | */ |
1153 | ||
abfa3df3 JC |
1154 | static int mcam_vidioc_streamon(struct file *filp, void *priv, |
1155 | enum v4l2_buf_type type) | |
1156 | { | |
1157 | struct mcam_camera *cam = filp->private_data; | |
b5210fd2 | 1158 | int ret; |
abfa3df3 | 1159 | |
abfa3df3 | 1160 | mutex_lock(&cam->s_mutex); |
b5210fd2 | 1161 | ret = vb2_streamon(&cam->vb_queue, type); |
abfa3df3 | 1162 | mutex_unlock(&cam->s_mutex); |
abfa3df3 JC |
1163 | return ret; |
1164 | } | |
1165 | ||
1166 | ||
1167 | static int mcam_vidioc_streamoff(struct file *filp, void *priv, | |
1168 | enum v4l2_buf_type type) | |
1169 | { | |
1170 | struct mcam_camera *cam = filp->private_data; | |
b5210fd2 | 1171 | int ret; |
abfa3df3 | 1172 | |
abfa3df3 | 1173 | mutex_lock(&cam->s_mutex); |
b5210fd2 | 1174 | ret = vb2_streamoff(&cam->vb_queue, type); |
abfa3df3 | 1175 | mutex_unlock(&cam->s_mutex); |
abfa3df3 JC |
1176 | return ret; |
1177 | } | |
1178 | ||
1179 | ||
abfa3df3 JC |
1180 | static int mcam_vidioc_reqbufs(struct file *filp, void *priv, |
1181 | struct v4l2_requestbuffers *req) | |
1182 | { | |
1183 | struct mcam_camera *cam = filp->private_data; | |
b5210fd2 | 1184 | int ret; |
abfa3df3 | 1185 | |
abfa3df3 | 1186 | mutex_lock(&cam->s_mutex); |
b5210fd2 | 1187 | ret = vb2_reqbufs(&cam->vb_queue, req); |
abfa3df3 JC |
1188 | mutex_unlock(&cam->s_mutex); |
1189 | return ret; | |
1190 | } | |
1191 | ||
1192 | ||
1193 | static int mcam_vidioc_querybuf(struct file *filp, void *priv, | |
1194 | struct v4l2_buffer *buf) | |
1195 | { | |
1196 | struct mcam_camera *cam = filp->private_data; | |
b5210fd2 | 1197 | int ret; |
abfa3df3 JC |
1198 | |
1199 | mutex_lock(&cam->s_mutex); | |
d43dae75 | 1200 | ret = vb2_querybuf(&cam->vb_queue, buf); |
abfa3df3 | 1201 | mutex_unlock(&cam->s_mutex); |
d43dae75 | 1202 | return ret; |
abfa3df3 JC |
1203 | } |
1204 | ||
d43dae75 JC |
1205 | static int mcam_vidioc_qbuf(struct file *filp, void *priv, |
1206 | struct v4l2_buffer *buf) | |
1207 | { | |
1208 | struct mcam_camera *cam = filp->private_data; | |
1209 | int ret; | |
abfa3df3 | 1210 | |
d43dae75 JC |
1211 | mutex_lock(&cam->s_mutex); |
1212 | ret = vb2_qbuf(&cam->vb_queue, buf); | |
1213 | mutex_unlock(&cam->s_mutex); | |
1214 | return ret; | |
1215 | } | |
abfa3df3 | 1216 | |
d43dae75 JC |
1217 | static int mcam_vidioc_dqbuf(struct file *filp, void *priv, |
1218 | struct v4l2_buffer *buf) | |
abfa3df3 JC |
1219 | { |
1220 | struct mcam_camera *cam = filp->private_data; | |
b5210fd2 | 1221 | int ret; |
abfa3df3 | 1222 | |
b5210fd2 | 1223 | mutex_lock(&cam->s_mutex); |
d43dae75 | 1224 | ret = vb2_dqbuf(&cam->vb_queue, buf, filp->f_flags & O_NONBLOCK); |
b5210fd2 JC |
1225 | mutex_unlock(&cam->s_mutex); |
1226 | return ret; | |
abfa3df3 JC |
1227 | } |
1228 | ||
abfa3df3 JC |
1229 | static int mcam_vidioc_querycap(struct file *file, void *priv, |
1230 | struct v4l2_capability *cap) | |
1231 | { | |
1232 | strcpy(cap->driver, "marvell_ccic"); | |
1233 | strcpy(cap->card, "marvell_ccic"); | |
1234 | cap->version = 1; | |
1235 | cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | | |
1236 | V4L2_CAP_READWRITE | V4L2_CAP_STREAMING; | |
1237 | return 0; | |
1238 | } | |
1239 | ||
1240 | ||
abfa3df3 JC |
1241 | static int mcam_vidioc_enum_fmt_vid_cap(struct file *filp, |
1242 | void *priv, struct v4l2_fmtdesc *fmt) | |
1243 | { | |
1244 | if (fmt->index >= N_MCAM_FMTS) | |
1245 | return -EINVAL; | |
1246 | strlcpy(fmt->description, mcam_formats[fmt->index].desc, | |
1247 | sizeof(fmt->description)); | |
1248 | fmt->pixelformat = mcam_formats[fmt->index].pixelformat; | |
1249 | return 0; | |
1250 | } | |
1251 | ||
1252 | static int mcam_vidioc_try_fmt_vid_cap(struct file *filp, void *priv, | |
1253 | struct v4l2_format *fmt) | |
1254 | { | |
1255 | struct mcam_camera *cam = priv; | |
1256 | struct mcam_format_struct *f; | |
1257 | struct v4l2_pix_format *pix = &fmt->fmt.pix; | |
1258 | struct v4l2_mbus_framefmt mbus_fmt; | |
1259 | int ret; | |
1260 | ||
1261 | f = mcam_find_format(pix->pixelformat); | |
1262 | pix->pixelformat = f->pixelformat; | |
1263 | v4l2_fill_mbus_format(&mbus_fmt, pix, f->mbus_code); | |
1264 | mutex_lock(&cam->s_mutex); | |
1265 | ret = sensor_call(cam, video, try_mbus_fmt, &mbus_fmt); | |
1266 | mutex_unlock(&cam->s_mutex); | |
1267 | v4l2_fill_pix_format(pix, &mbus_fmt); | |
1268 | pix->bytesperline = pix->width * f->bpp; | |
1269 | pix->sizeimage = pix->height * pix->bytesperline; | |
1270 | return ret; | |
1271 | } | |
1272 | ||
1273 | static int mcam_vidioc_s_fmt_vid_cap(struct file *filp, void *priv, | |
1274 | struct v4l2_format *fmt) | |
1275 | { | |
1276 | struct mcam_camera *cam = priv; | |
1277 | struct mcam_format_struct *f; | |
1278 | int ret; | |
1279 | ||
1280 | /* | |
1281 | * Can't do anything if the device is not idle | |
1282 | * Also can't if there are streaming buffers in place. | |
1283 | */ | |
b5210fd2 | 1284 | if (cam->state != S_IDLE || cam->vb_queue.num_buffers > 0) |
abfa3df3 JC |
1285 | return -EBUSY; |
1286 | ||
1287 | f = mcam_find_format(fmt->fmt.pix.pixelformat); | |
1288 | ||
1289 | /* | |
1290 | * See if the formatting works in principle. | |
1291 | */ | |
1292 | ret = mcam_vidioc_try_fmt_vid_cap(filp, priv, fmt); | |
1293 | if (ret) | |
1294 | return ret; | |
1295 | /* | |
1296 | * Now we start to change things for real, so let's do it | |
1297 | * under lock. | |
1298 | */ | |
1299 | mutex_lock(&cam->s_mutex); | |
1300 | cam->pix_format = fmt->fmt.pix; | |
1301 | cam->mbus_code = f->mbus_code; | |
1302 | ||
1303 | /* | |
1304 | * Make sure we have appropriate DMA buffers. | |
1305 | */ | |
a9b36e85 | 1306 | if (cam->buffer_mode == B_vmalloc) { |
7498469f JC |
1307 | ret = mcam_check_dma_buffers(cam); |
1308 | if (ret) | |
1309 | goto out; | |
abfa3df3 | 1310 | } |
a9b36e85 | 1311 | mcam_set_config_needed(cam, 1); |
abfa3df3 JC |
1312 | out: |
1313 | mutex_unlock(&cam->s_mutex); | |
1314 | return ret; | |
1315 | } | |
1316 | ||
1317 | /* | |
1318 | * Return our stored notion of how the camera is/should be configured. | |
1319 | * The V4l2 spec wants us to be smarter, and actually get this from | |
1320 | * the camera (and not mess with it at open time). Someday. | |
1321 | */ | |
1322 | static int mcam_vidioc_g_fmt_vid_cap(struct file *filp, void *priv, | |
1323 | struct v4l2_format *f) | |
1324 | { | |
1325 | struct mcam_camera *cam = priv; | |
1326 | ||
1327 | f->fmt.pix = cam->pix_format; | |
1328 | return 0; | |
1329 | } | |
1330 | ||
1331 | /* | |
1332 | * We only have one input - the sensor - so minimize the nonsense here. | |
1333 | */ | |
1334 | static int mcam_vidioc_enum_input(struct file *filp, void *priv, | |
1335 | struct v4l2_input *input) | |
1336 | { | |
1337 | if (input->index != 0) | |
1338 | return -EINVAL; | |
1339 | ||
1340 | input->type = V4L2_INPUT_TYPE_CAMERA; | |
1341 | input->std = V4L2_STD_ALL; /* Not sure what should go here */ | |
1342 | strcpy(input->name, "Camera"); | |
1343 | return 0; | |
1344 | } | |
1345 | ||
1346 | static int mcam_vidioc_g_input(struct file *filp, void *priv, unsigned int *i) | |
1347 | { | |
1348 | *i = 0; | |
1349 | return 0; | |
1350 | } | |
1351 | ||
1352 | static int mcam_vidioc_s_input(struct file *filp, void *priv, unsigned int i) | |
1353 | { | |
1354 | if (i != 0) | |
1355 | return -EINVAL; | |
1356 | return 0; | |
1357 | } | |
1358 | ||
1359 | /* from vivi.c */ | |
314527ac | 1360 | static int mcam_vidioc_s_std(struct file *filp, void *priv, v4l2_std_id a) |
abfa3df3 JC |
1361 | { |
1362 | return 0; | |
1363 | } | |
1364 | ||
1365 | /* | |
1366 | * G/S_PARM. Most of this is done by the sensor, but we are | |
1367 | * the level which controls the number of read buffers. | |
1368 | */ | |
1369 | static int mcam_vidioc_g_parm(struct file *filp, void *priv, | |
1370 | struct v4l2_streamparm *parms) | |
1371 | { | |
1372 | struct mcam_camera *cam = priv; | |
1373 | int ret; | |
1374 | ||
1375 | mutex_lock(&cam->s_mutex); | |
1376 | ret = sensor_call(cam, video, g_parm, parms); | |
1377 | mutex_unlock(&cam->s_mutex); | |
1378 | parms->parm.capture.readbuffers = n_dma_bufs; | |
1379 | return ret; | |
1380 | } | |
1381 | ||
1382 | static int mcam_vidioc_s_parm(struct file *filp, void *priv, | |
1383 | struct v4l2_streamparm *parms) | |
1384 | { | |
1385 | struct mcam_camera *cam = priv; | |
1386 | int ret; | |
1387 | ||
1388 | mutex_lock(&cam->s_mutex); | |
1389 | ret = sensor_call(cam, video, s_parm, parms); | |
1390 | mutex_unlock(&cam->s_mutex); | |
1391 | parms->parm.capture.readbuffers = n_dma_bufs; | |
1392 | return ret; | |
1393 | } | |
1394 | ||
1395 | static int mcam_vidioc_g_chip_ident(struct file *file, void *priv, | |
1396 | struct v4l2_dbg_chip_ident *chip) | |
1397 | { | |
1398 | struct mcam_camera *cam = priv; | |
1399 | ||
1400 | chip->ident = V4L2_IDENT_NONE; | |
1401 | chip->revision = 0; | |
1402 | if (v4l2_chip_match_host(&chip->match)) { | |
1403 | chip->ident = cam->chip_id; | |
1404 | return 0; | |
1405 | } | |
1406 | return sensor_call(cam, core, g_chip_ident, chip); | |
1407 | } | |
1408 | ||
1409 | static int mcam_vidioc_enum_framesizes(struct file *filp, void *priv, | |
1410 | struct v4l2_frmsizeenum *sizes) | |
1411 | { | |
1412 | struct mcam_camera *cam = priv; | |
1413 | int ret; | |
1414 | ||
1415 | mutex_lock(&cam->s_mutex); | |
1416 | ret = sensor_call(cam, video, enum_framesizes, sizes); | |
1417 | mutex_unlock(&cam->s_mutex); | |
1418 | return ret; | |
1419 | } | |
1420 | ||
1421 | static int mcam_vidioc_enum_frameintervals(struct file *filp, void *priv, | |
1422 | struct v4l2_frmivalenum *interval) | |
1423 | { | |
1424 | struct mcam_camera *cam = priv; | |
1425 | int ret; | |
1426 | ||
1427 | mutex_lock(&cam->s_mutex); | |
1428 | ret = sensor_call(cam, video, enum_frameintervals, interval); | |
1429 | mutex_unlock(&cam->s_mutex); | |
1430 | return ret; | |
1431 | } | |
1432 | ||
1433 | #ifdef CONFIG_VIDEO_ADV_DEBUG | |
1434 | static int mcam_vidioc_g_register(struct file *file, void *priv, | |
1435 | struct v4l2_dbg_register *reg) | |
1436 | { | |
1437 | struct mcam_camera *cam = priv; | |
1438 | ||
1439 | if (v4l2_chip_match_host(®->match)) { | |
1440 | reg->val = mcam_reg_read(cam, reg->reg); | |
1441 | reg->size = 4; | |
1442 | return 0; | |
1443 | } | |
1444 | return sensor_call(cam, core, g_register, reg); | |
1445 | } | |
1446 | ||
1447 | static int mcam_vidioc_s_register(struct file *file, void *priv, | |
977ba3b1 | 1448 | const struct v4l2_dbg_register *reg) |
abfa3df3 JC |
1449 | { |
1450 | struct mcam_camera *cam = priv; | |
1451 | ||
1452 | if (v4l2_chip_match_host(®->match)) { | |
1453 | mcam_reg_write(cam, reg->reg, reg->val); | |
1454 | return 0; | |
1455 | } | |
1456 | return sensor_call(cam, core, s_register, reg); | |
1457 | } | |
1458 | #endif | |
1459 | ||
abfa3df3 JC |
1460 | static const struct v4l2_ioctl_ops mcam_v4l_ioctl_ops = { |
1461 | .vidioc_querycap = mcam_vidioc_querycap, | |
1462 | .vidioc_enum_fmt_vid_cap = mcam_vidioc_enum_fmt_vid_cap, | |
1463 | .vidioc_try_fmt_vid_cap = mcam_vidioc_try_fmt_vid_cap, | |
1464 | .vidioc_s_fmt_vid_cap = mcam_vidioc_s_fmt_vid_cap, | |
1465 | .vidioc_g_fmt_vid_cap = mcam_vidioc_g_fmt_vid_cap, | |
1466 | .vidioc_enum_input = mcam_vidioc_enum_input, | |
1467 | .vidioc_g_input = mcam_vidioc_g_input, | |
1468 | .vidioc_s_input = mcam_vidioc_s_input, | |
1469 | .vidioc_s_std = mcam_vidioc_s_std, | |
1470 | .vidioc_reqbufs = mcam_vidioc_reqbufs, | |
1471 | .vidioc_querybuf = mcam_vidioc_querybuf, | |
1472 | .vidioc_qbuf = mcam_vidioc_qbuf, | |
1473 | .vidioc_dqbuf = mcam_vidioc_dqbuf, | |
1474 | .vidioc_streamon = mcam_vidioc_streamon, | |
1475 | .vidioc_streamoff = mcam_vidioc_streamoff, | |
abfa3df3 JC |
1476 | .vidioc_g_parm = mcam_vidioc_g_parm, |
1477 | .vidioc_s_parm = mcam_vidioc_s_parm, | |
1478 | .vidioc_enum_framesizes = mcam_vidioc_enum_framesizes, | |
1479 | .vidioc_enum_frameintervals = mcam_vidioc_enum_frameintervals, | |
1480 | .vidioc_g_chip_ident = mcam_vidioc_g_chip_ident, | |
1481 | #ifdef CONFIG_VIDEO_ADV_DEBUG | |
1482 | .vidioc_g_register = mcam_vidioc_g_register, | |
1483 | .vidioc_s_register = mcam_vidioc_s_register, | |
1484 | #endif | |
1485 | }; | |
1486 | ||
abfa3df3 JC |
1487 | /* ---------------------------------------------------------------------- */ |
1488 | /* | |
d43dae75 | 1489 | * Our various file operations. |
abfa3df3 | 1490 | */ |
d43dae75 JC |
1491 | static int mcam_v4l_open(struct file *filp) |
1492 | { | |
1493 | struct mcam_camera *cam = video_drvdata(filp); | |
1494 | int ret = 0; | |
abfa3df3 | 1495 | |
d43dae75 | 1496 | filp->private_data = cam; |
abfa3df3 | 1497 | |
f698957a LY |
1498 | cam->frame_state.frames = 0; |
1499 | cam->frame_state.singles = 0; | |
1500 | cam->frame_state.delivered = 0; | |
d43dae75 JC |
1501 | mutex_lock(&cam->s_mutex); |
1502 | if (cam->users == 0) { | |
1503 | ret = mcam_setup_vb2(cam); | |
1504 | if (ret) | |
1505 | goto out; | |
1506 | mcam_ctlr_power_up(cam); | |
1507 | __mcam_cam_reset(cam); | |
1508 | mcam_set_config_needed(cam, 1); | |
1509 | } | |
1510 | (cam->users)++; | |
1511 | out: | |
1512 | mutex_unlock(&cam->s_mutex); | |
1513 | return ret; | |
a9b36e85 | 1514 | } |
abfa3df3 | 1515 | |
abfa3df3 | 1516 | |
d43dae75 JC |
1517 | static int mcam_v4l_release(struct file *filp) |
1518 | { | |
1519 | struct mcam_camera *cam = filp->private_data; | |
b5210fd2 | 1520 | |
f698957a LY |
1521 | cam_dbg(cam, "Release, %d frames, %d singles, %d delivered\n", |
1522 | cam->frame_state.frames, cam->frame_state.singles, | |
1523 | cam->frame_state.delivered); | |
d43dae75 JC |
1524 | mutex_lock(&cam->s_mutex); |
1525 | (cam->users)--; | |
d43dae75 | 1526 | if (cam->users == 0) { |
0770d07f | 1527 | mcam_ctlr_stop_dma(cam); |
d43dae75 JC |
1528 | mcam_cleanup_vb2(cam); |
1529 | mcam_ctlr_power_down(cam); | |
1530 | if (cam->buffer_mode == B_vmalloc && alloc_bufs_at_read) | |
1531 | mcam_free_dma_bufs(cam); | |
1532 | } | |
1533 | mutex_unlock(&cam->s_mutex); | |
1534 | return 0; | |
abfa3df3 JC |
1535 | } |
1536 | ||
d43dae75 JC |
1537 | static ssize_t mcam_v4l_read(struct file *filp, |
1538 | char __user *buffer, size_t len, loff_t *pos) | |
a9b36e85 | 1539 | { |
d43dae75 JC |
1540 | struct mcam_camera *cam = filp->private_data; |
1541 | int ret; | |
a9b36e85 | 1542 | |
d43dae75 JC |
1543 | mutex_lock(&cam->s_mutex); |
1544 | ret = vb2_read(&cam->vb_queue, buffer, len, pos, | |
1545 | filp->f_flags & O_NONBLOCK); | |
1546 | mutex_unlock(&cam->s_mutex); | |
1547 | return ret; | |
a9b36e85 | 1548 | } |
abfa3df3 | 1549 | |
d43dae75 JC |
1550 | |
1551 | ||
1552 | static unsigned int mcam_v4l_poll(struct file *filp, | |
1553 | struct poll_table_struct *pt) | |
cbc4f3a2 | 1554 | { |
d43dae75 JC |
1555 | struct mcam_camera *cam = filp->private_data; |
1556 | int ret; | |
cbc4f3a2 | 1557 | |
d43dae75 JC |
1558 | mutex_lock(&cam->s_mutex); |
1559 | ret = vb2_poll(&cam->vb_queue, filp, pt); | |
1560 | mutex_unlock(&cam->s_mutex); | |
1561 | return ret; | |
1562 | } | |
1563 | ||
1564 | ||
1565 | static int mcam_v4l_mmap(struct file *filp, struct vm_area_struct *vma) | |
1566 | { | |
1567 | struct mcam_camera *cam = filp->private_data; | |
1568 | int ret; | |
1569 | ||
1570 | mutex_lock(&cam->s_mutex); | |
1571 | ret = vb2_mmap(&cam->vb_queue, vma); | |
1572 | mutex_unlock(&cam->s_mutex); | |
1573 | return ret; | |
cbc4f3a2 JC |
1574 | } |
1575 | ||
1576 | ||
abfa3df3 | 1577 | |
d43dae75 JC |
1578 | static const struct v4l2_file_operations mcam_v4l_fops = { |
1579 | .owner = THIS_MODULE, | |
1580 | .open = mcam_v4l_open, | |
1581 | .release = mcam_v4l_release, | |
1582 | .read = mcam_v4l_read, | |
1583 | .poll = mcam_v4l_poll, | |
1584 | .mmap = mcam_v4l_mmap, | |
1585 | .unlocked_ioctl = video_ioctl2, | |
1586 | }; | |
1587 | ||
1588 | ||
1589 | /* | |
1590 | * This template device holds all of those v4l2 methods; we | |
1591 | * clone it for specific real devices. | |
1592 | */ | |
1593 | static struct video_device mcam_v4l_template = { | |
1594 | .name = "mcam", | |
1595 | .tvnorms = V4L2_STD_NTSC_M, | |
1596 | .current_norm = V4L2_STD_NTSC_M, /* make mplayer happy */ | |
1597 | ||
1598 | .fops = &mcam_v4l_fops, | |
1599 | .ioctl_ops = &mcam_v4l_ioctl_ops, | |
1600 | .release = video_device_release_empty, | |
1601 | }; | |
1602 | ||
1603 | /* ---------------------------------------------------------------------- */ | |
1604 | /* | |
1605 | * Interrupt handler stuff | |
1606 | */ | |
abfa3df3 JC |
1607 | static void mcam_frame_complete(struct mcam_camera *cam, int frame) |
1608 | { | |
1609 | /* | |
1610 | * Basic frame housekeeping. | |
1611 | */ | |
abfa3df3 JC |
1612 | set_bit(frame, &cam->flags); |
1613 | clear_bit(CF_DMA_ACTIVE, &cam->flags); | |
a9b36e85 | 1614 | cam->next_buf = frame; |
abfa3df3 | 1615 | cam->buf_seq[frame] = ++(cam->sequence); |
f698957a | 1616 | cam->frame_state.frames++; |
abfa3df3 | 1617 | /* |
cbc4f3a2 | 1618 | * "This should never happen" |
abfa3df3 | 1619 | */ |
cbc4f3a2 JC |
1620 | if (cam->state != S_STREAMING) |
1621 | return; | |
1622 | /* | |
1623 | * Process the frame and set up the next one. | |
1624 | */ | |
7498469f | 1625 | cam->frame_complete(cam, frame); |
abfa3df3 JC |
1626 | } |
1627 | ||
1628 | ||
d43dae75 JC |
1629 | /* |
1630 | * The interrupt handler; this needs to be called from the | |
1631 | * platform irq handler with the lock held. | |
1632 | */ | |
abfa3df3 JC |
1633 | int mccic_irq(struct mcam_camera *cam, unsigned int irqs) |
1634 | { | |
1635 | unsigned int frame, handled = 0; | |
1636 | ||
1637 | mcam_reg_write(cam, REG_IRQSTAT, FRAMEIRQS); /* Clear'em all */ | |
1638 | /* | |
1639 | * Handle any frame completions. There really should | |
1640 | * not be more than one of these, or we have fallen | |
1641 | * far behind. | |
cbc4f3a2 JC |
1642 | * |
1643 | * When running in S/G mode, the frame number lacks any | |
1644 | * real meaning - there's only one descriptor array - but | |
1645 | * the controller still picks a different one to signal | |
1646 | * each time. | |
abfa3df3 JC |
1647 | */ |
1648 | for (frame = 0; frame < cam->nbufs; frame++) | |
1649 | if (irqs & (IRQ_EOF0 << frame)) { | |
1650 | mcam_frame_complete(cam, frame); | |
1651 | handled = 1; | |
f2354dd1 JC |
1652 | if (cam->buffer_mode == B_DMA_sg) |
1653 | break; | |
abfa3df3 JC |
1654 | } |
1655 | /* | |
1656 | * If a frame starts, note that we have DMA active. This | |
1657 | * code assumes that we won't get multiple frame interrupts | |
1658 | * at once; may want to rethink that. | |
1659 | */ | |
1660 | if (irqs & (IRQ_SOF0 | IRQ_SOF1 | IRQ_SOF2)) { | |
1661 | set_bit(CF_DMA_ACTIVE, &cam->flags); | |
1662 | handled = 1; | |
cbc4f3a2 JC |
1663 | if (cam->buffer_mode == B_DMA_sg) |
1664 | mcam_ctlr_stop(cam); | |
abfa3df3 JC |
1665 | } |
1666 | return handled; | |
1667 | } | |
1668 | ||
d43dae75 | 1669 | /* ---------------------------------------------------------------------- */ |
abfa3df3 JC |
1670 | /* |
1671 | * Registration and such. | |
1672 | */ | |
abfa3df3 | 1673 | static struct ov7670_config sensor_cfg = { |
abfa3df3 JC |
1674 | /* |
1675 | * Exclude QCIF mode, because it only captures a tiny portion | |
1676 | * of the sensor FOV | |
1677 | */ | |
1678 | .min_width = 320, | |
1679 | .min_height = 240, | |
1680 | }; | |
1681 | ||
1682 | ||
1683 | int mccic_register(struct mcam_camera *cam) | |
1684 | { | |
1685 | struct i2c_board_info ov7670_info = { | |
1686 | .type = "ov7670", | |
1c68f889 | 1687 | .addr = 0x42 >> 1, |
abfa3df3 JC |
1688 | .platform_data = &sensor_cfg, |
1689 | }; | |
1690 | int ret; | |
1691 | ||
7498469f JC |
1692 | /* |
1693 | * Validate the requested buffer mode. | |
1694 | */ | |
1695 | if (buffer_mode >= 0) | |
1696 | cam->buffer_mode = buffer_mode; | |
1697 | if (cam->buffer_mode == B_DMA_sg && | |
1698 | cam->chip_id == V4L2_IDENT_CAFE) { | |
1699 | printk(KERN_ERR "marvell-cam: Cafe can't do S/G I/O, " | |
1700 | "attempting vmalloc mode instead\n"); | |
1701 | cam->buffer_mode = B_vmalloc; | |
1702 | } | |
1703 | if (!mcam_buffer_mode_supported(cam->buffer_mode)) { | |
1704 | printk(KERN_ERR "marvell-cam: buffer mode %d unsupported\n", | |
1705 | cam->buffer_mode); | |
1706 | return -EINVAL; | |
1707 | } | |
abfa3df3 JC |
1708 | /* |
1709 | * Register with V4L | |
1710 | */ | |
1711 | ret = v4l2_device_register(cam->dev, &cam->v4l2_dev); | |
1712 | if (ret) | |
1713 | return ret; | |
1714 | ||
1715 | mutex_init(&cam->s_mutex); | |
1716 | cam->state = S_NOTREADY; | |
1717 | mcam_set_config_needed(cam, 1); | |
abfa3df3 JC |
1718 | cam->pix_format = mcam_def_pix_format; |
1719 | cam->mbus_code = mcam_def_mbus_code; | |
b5210fd2 | 1720 | INIT_LIST_HEAD(&cam->buffers); |
abfa3df3 JC |
1721 | mcam_ctlr_init(cam); |
1722 | ||
abfa3df3 JC |
1723 | /* |
1724 | * Try to find the sensor. | |
1725 | */ | |
2164b5af JC |
1726 | sensor_cfg.clock_speed = cam->clock_speed; |
1727 | sensor_cfg.use_smbus = cam->use_smbus; | |
abfa3df3 JC |
1728 | cam->sensor_addr = ov7670_info.addr; |
1729 | cam->sensor = v4l2_i2c_new_subdev_board(&cam->v4l2_dev, | |
595a93a4 | 1730 | cam->i2c_adapter, &ov7670_info, NULL); |
abfa3df3 JC |
1731 | if (cam->sensor == NULL) { |
1732 | ret = -ENODEV; | |
1733 | goto out_unregister; | |
1734 | } | |
1735 | ||
1736 | ret = mcam_cam_init(cam); | |
1737 | if (ret) | |
1738 | goto out_unregister; | |
1739 | /* | |
1740 | * Get the v4l2 setup done. | |
1741 | */ | |
593403c5 JM |
1742 | ret = v4l2_ctrl_handler_init(&cam->ctrl_handler, 10); |
1743 | if (ret) | |
1744 | goto out_unregister; | |
1745 | cam->v4l2_dev.ctrl_handler = &cam->ctrl_handler; | |
1746 | ||
abfa3df3 JC |
1747 | mutex_lock(&cam->s_mutex); |
1748 | cam->vdev = mcam_v4l_template; | |
1749 | cam->vdev.debug = 0; | |
1750 | cam->vdev.v4l2_dev = &cam->v4l2_dev; | |
593403c5 | 1751 | video_set_drvdata(&cam->vdev, cam); |
abfa3df3 JC |
1752 | ret = video_register_device(&cam->vdev, VFL_TYPE_GRABBER, -1); |
1753 | if (ret) | |
1754 | goto out; | |
abfa3df3 JC |
1755 | |
1756 | /* | |
1757 | * If so requested, try to get our DMA buffers now. | |
1758 | */ | |
a9b36e85 | 1759 | if (cam->buffer_mode == B_vmalloc && !alloc_bufs_at_read) { |
abfa3df3 JC |
1760 | if (mcam_alloc_dma_bufs(cam, 1)) |
1761 | cam_warn(cam, "Unable to alloc DMA buffers at load" | |
1762 | " will try again later."); | |
1763 | } | |
1764 | ||
1765 | out: | |
593403c5 | 1766 | v4l2_ctrl_handler_free(&cam->ctrl_handler); |
abfa3df3 JC |
1767 | mutex_unlock(&cam->s_mutex); |
1768 | return ret; | |
1769 | out_unregister: | |
1770 | v4l2_device_unregister(&cam->v4l2_dev); | |
1771 | return ret; | |
1772 | } | |
1773 | ||
1774 | ||
1775 | void mccic_shutdown(struct mcam_camera *cam) | |
1776 | { | |
67a8dbbc JC |
1777 | /* |
1778 | * If we have no users (and we really, really should have no | |
1779 | * users) the device will already be powered down. Trying to | |
1780 | * take it down again will wedge the machine, which is frowned | |
1781 | * upon. | |
1782 | */ | |
1783 | if (cam->users > 0) { | |
abfa3df3 | 1784 | cam_warn(cam, "Removing a device with users!\n"); |
67a8dbbc JC |
1785 | mcam_ctlr_power_down(cam); |
1786 | } | |
b5210fd2 | 1787 | vb2_queue_release(&cam->vb_queue); |
a9b36e85 JC |
1788 | if (cam->buffer_mode == B_vmalloc) |
1789 | mcam_free_dma_bufs(cam); | |
abfa3df3 | 1790 | video_unregister_device(&cam->vdev); |
593403c5 | 1791 | v4l2_ctrl_handler_free(&cam->ctrl_handler); |
abfa3df3 JC |
1792 | v4l2_device_unregister(&cam->v4l2_dev); |
1793 | } | |
1794 | ||
1795 | /* | |
1796 | * Power management | |
1797 | */ | |
1798 | #ifdef CONFIG_PM | |
1799 | ||
1800 | void mccic_suspend(struct mcam_camera *cam) | |
1801 | { | |
bb0a896e JC |
1802 | mutex_lock(&cam->s_mutex); |
1803 | if (cam->users > 0) { | |
1804 | enum mcam_state cstate = cam->state; | |
abfa3df3 | 1805 | |
bb0a896e JC |
1806 | mcam_ctlr_stop_dma(cam); |
1807 | mcam_ctlr_power_down(cam); | |
1808 | cam->state = cstate; | |
1809 | } | |
1810 | mutex_unlock(&cam->s_mutex); | |
abfa3df3 JC |
1811 | } |
1812 | ||
1813 | int mccic_resume(struct mcam_camera *cam) | |
1814 | { | |
1815 | int ret = 0; | |
1816 | ||
1817 | mutex_lock(&cam->s_mutex); | |
1818 | if (cam->users > 0) { | |
1819 | mcam_ctlr_power_up(cam); | |
1820 | __mcam_cam_reset(cam); | |
1821 | } else { | |
1822 | mcam_ctlr_power_down(cam); | |
1823 | } | |
1824 | mutex_unlock(&cam->s_mutex); | |
1825 | ||
1826 | set_bit(CF_CONFIG_NEEDED, &cam->flags); | |
bb0a896e JC |
1827 | if (cam->state == S_STREAMING) { |
1828 | /* | |
1829 | * If there was a buffer in the DMA engine at suspend | |
1830 | * time, put it back on the queue or we'll forget about it. | |
1831 | */ | |
1832 | if (cam->buffer_mode == B_DMA_sg && cam->vb_bufs[0]) | |
1833 | list_add(&cam->vb_bufs[0]->queue, &cam->buffers); | |
a9b36e85 | 1834 | ret = mcam_read_setup(cam); |
bb0a896e | 1835 | } |
abfa3df3 JC |
1836 | return ret; |
1837 | } | |
1838 | #endif /* CONFIG_PM */ |