Commit | Line | Data |
---|---|---|
d8b14f8a MA |
1 | /* |
2 | Mantis PCI bridge driver | |
3 | ||
8825a097 | 4 | Copyright (C) Manu Abraham (abraham.manu@gmail.com) |
d8b14f8a MA |
5 | |
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2 of the License, or | |
9 | (at your option) any later version. | |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
18 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
19 | */ | |
20 | ||
b3b96144 MA |
21 | #include <linux/kernel.h> |
22 | #include <linux/signal.h> | |
23 | #include <linux/sched.h> | |
24 | ||
b3b96144 MA |
25 | #include <linux/interrupt.h> |
26 | ||
27 | #include "dmxdev.h" | |
28 | #include "dvbdev.h" | |
29 | #include "dvb_demux.h" | |
30 | #include "dvb_frontend.h" | |
31 | #include "dvb_net.h" | |
32 | ||
d8b14f8a | 33 | #include "mantis_common.h" |
b3b96144 | 34 | |
d8b14f8a MA |
35 | #include "mantis_hif.h" |
36 | #include "mantis_link.h" /* temporary due to physical layer stuff */ | |
37 | ||
b3b96144 MA |
38 | #include "mantis_reg.h" |
39 | ||
d8b14f8a MA |
40 | |
41 | static int mantis_hif_sbuf_opdone_wait(struct mantis_ca *ca) | |
42 | { | |
43 | struct mantis_pci *mantis = ca->ca_priv; | |
44 | int rc = 0; | |
45 | ||
ac8f04d2 MA |
46 | if (wait_event_timeout(ca->hif_opdone_wq, |
47 | ca->hif_event & MANTIS_SBUF_OPDONE, | |
48 | msecs_to_jiffies(500)) == -ERESTARTSYS) { | |
d8b14f8a | 49 | |
b3b96144 | 50 | dprintk(MANTIS_ERROR, 1, "Adapter(%d) Slot(0): Smart buffer operation timeout !", mantis->num); |
d8b14f8a MA |
51 | rc = -EREMOTEIO; |
52 | } | |
b3b96144 | 53 | dprintk(MANTIS_DEBUG, 1, "Smart Buffer Operation complete"); |
d8b14f8a | 54 | ca->hif_event &= ~MANTIS_SBUF_OPDONE; |
d8b14f8a MA |
55 | return rc; |
56 | } | |
57 | ||
e0e099a7 MA |
58 | static int mantis_hif_write_wait(struct mantis_ca *ca) |
59 | { | |
60 | struct mantis_pci *mantis = ca->ca_priv; | |
61 | u32 opdone = 0, timeout = 0; | |
62 | int rc = 0; | |
63 | ||
64 | if (wait_event_timeout(ca->hif_write_wq, | |
65 | mantis->gpif_status & MANTIS_GPIF_WRACK, | |
66 | msecs_to_jiffies(500)) == -ERESTARTSYS) { | |
67 | ||
b3b96144 | 68 | dprintk(MANTIS_ERROR, 1, "Adapter(%d) Slot(0): Write ACK timed out !", mantis->num); |
e0e099a7 MA |
69 | rc = -EREMOTEIO; |
70 | } | |
b3b96144 | 71 | dprintk(MANTIS_DEBUG, 1, "Write Acknowledged"); |
e0e099a7 MA |
72 | mantis->gpif_status &= ~MANTIS_GPIF_WRACK; |
73 | while (!opdone) { | |
74 | opdone = (mmread(MANTIS_GPIF_STATUS) & MANTIS_SBUF_OPDONE); | |
75 | udelay(500); | |
76 | timeout++; | |
77 | if (timeout > 100) { | |
b3b96144 | 78 | dprintk(MANTIS_ERROR, 1, "Adater(%d) Slot(0): Write operation timed out!", mantis->num); |
e0e099a7 MA |
79 | rc = -ETIMEDOUT; |
80 | break; | |
81 | } | |
82 | } | |
b3b96144 | 83 | dprintk(MANTIS_DEBUG, 1, "HIF Write success"); |
e0e099a7 MA |
84 | return rc; |
85 | } | |
86 | ||
b2d8f5ea | 87 | |
d8b14f8a MA |
88 | int mantis_hif_read_mem(struct mantis_ca *ca, u32 addr) |
89 | { | |
90 | struct mantis_pci *mantis = ca->ca_priv; | |
91 | u32 hif_addr = 0, data, count = 4; | |
92 | ||
b3b96144 | 93 | dprintk(MANTIS_DEBUG, 1, "Adapter(%d) Slot(0): Request HIF Mem Read", mantis->num); |
f684336b | 94 | mutex_lock(&ca->ca_lock); |
d8b14f8a MA |
95 | hif_addr &= ~MANTIS_GPIF_PCMCIAREG; |
96 | hif_addr &= ~MANTIS_GPIF_PCMCIAIOM; | |
b29f6ac2 | 97 | hif_addr |= MANTIS_HIF_STATUS; |
d8b14f8a MA |
98 | hif_addr |= addr; |
99 | ||
b29f6ac2 | 100 | mmwrite(hif_addr, MANTIS_GPIF_BRADDR); |
d8b14f8a | 101 | mmwrite(count, MANTIS_GPIF_BRBYTES); |
d8b14f8a | 102 | udelay(20); |
b29f6ac2 | 103 | mmwrite(hif_addr | MANTIS_GPIF_HIFRDWRN, MANTIS_GPIF_ADDR); |
d8b14f8a | 104 | |
d8b14f8a | 105 | if (mantis_hif_sbuf_opdone_wait(ca) != 0) { |
b3b96144 | 106 | dprintk(MANTIS_ERROR, 1, "Adapter(%d) Slot(0): GPIF Smart Buffer operation failed", mantis->num); |
f684336b | 107 | mutex_unlock(&ca->ca_lock); |
d8b14f8a MA |
108 | return -EREMOTEIO; |
109 | } | |
a0c59063 | 110 | data = mmread(MANTIS_GPIF_DIN); |
f684336b | 111 | mutex_unlock(&ca->ca_lock); |
b3b96144 | 112 | dprintk(MANTIS_DEBUG, 1, "Mem Read: 0x%02x", data); |
d8b14f8a MA |
113 | return (data >> 24) & 0xff; |
114 | } | |
115 | ||
116 | int mantis_hif_write_mem(struct mantis_ca *ca, u32 addr, u8 data) | |
117 | { | |
118 | struct mantis_slot *slot = ca->slot; | |
119 | struct mantis_pci *mantis = ca->ca_priv; | |
120 | u32 hif_addr = 0; | |
121 | ||
b3b96144 | 122 | dprintk(MANTIS_DEBUG, 1, "Adapter(%d) Slot(0): Request HIF Mem Write", mantis->num); |
f684336b | 123 | mutex_lock(&ca->ca_lock); |
d8b14f8a MA |
124 | hif_addr &= ~MANTIS_GPIF_HIFRDWRN; |
125 | hif_addr &= ~MANTIS_GPIF_PCMCIAREG; | |
126 | hif_addr &= ~MANTIS_GPIF_PCMCIAIOM; | |
b29f6ac2 MA |
127 | hif_addr |= MANTIS_HIF_STATUS; |
128 | hif_addr |= addr; | |
d8b14f8a MA |
129 | |
130 | mmwrite(slot->slave_cfg, MANTIS_GPIF_CFGSLA); /* Slot0 alone for now */ | |
b29f6ac2 | 131 | mmwrite(hif_addr, MANTIS_GPIF_ADDR); |
a0c59063 | 132 | mmwrite(data, MANTIS_GPIF_DOUT); |
d8b14f8a | 133 | |
e0e099a7 | 134 | if (mantis_hif_write_wait(ca) != 0) { |
b3b96144 | 135 | dprintk(MANTIS_ERROR, 1, "Adapter(%d) Slot(0): HIF Smart Buffer operation failed", mantis->num); |
f684336b | 136 | mutex_unlock(&ca->ca_lock); |
d8b14f8a MA |
137 | return -EREMOTEIO; |
138 | } | |
b3b96144 | 139 | dprintk(MANTIS_DEBUG, 1, "Mem Write: (0x%02x to 0x%02x)", data, addr); |
f684336b | 140 | mutex_unlock(&ca->ca_lock); |
8b9c385f | 141 | |
d8b14f8a MA |
142 | return 0; |
143 | } | |
144 | ||
6053240f | 145 | int mantis_hif_read_iom(struct mantis_ca *ca, u32 addr) |
c9a750c9 MA |
146 | { |
147 | struct mantis_pci *mantis = ca->ca_priv; | |
6053240f | 148 | u32 data, hif_addr = 0; |
c9a750c9 | 149 | |
b3b96144 | 150 | dprintk(MANTIS_DEBUG, 1, "Adapter(%d) Slot(0): Request HIF I/O Read", mantis->num); |
f684336b | 151 | mutex_lock(&ca->ca_lock); |
c9a750c9 | 152 | hif_addr &= ~MANTIS_GPIF_PCMCIAREG; |
c9a750c9 | 153 | hif_addr |= MANTIS_GPIF_PCMCIAIOM; |
b29f6ac2 | 154 | hif_addr |= MANTIS_HIF_STATUS; |
c9a750c9 MA |
155 | hif_addr |= addr; |
156 | ||
b29f6ac2 | 157 | mmwrite(hif_addr, MANTIS_GPIF_BRADDR); |
c63e5073 | 158 | mmwrite(1, MANTIS_GPIF_BRBYTES); |
c63e5073 | 159 | udelay(20); |
b29f6ac2 | 160 | mmwrite(hif_addr | MANTIS_GPIF_HIFRDWRN, MANTIS_GPIF_ADDR); |
c9a750c9 MA |
161 | |
162 | if (mantis_hif_sbuf_opdone_wait(ca) != 0) { | |
b3b96144 | 163 | dprintk(MANTIS_ERROR, 1, "Adapter(%d) Slot(0): HIF Smart Buffer operation failed", mantis->num); |
f684336b | 164 | mutex_unlock(&ca->ca_lock); |
c9a750c9 MA |
165 | return -EREMOTEIO; |
166 | } | |
a0c59063 | 167 | data = mmread(MANTIS_GPIF_DIN); |
b3b96144 | 168 | dprintk(MANTIS_DEBUG, 1, "I/O Read: 0x%02x", data); |
8e0d58ec | 169 | udelay(50); |
f684336b | 170 | mutex_unlock(&ca->ca_lock); |
c9a750c9 | 171 | |
9c867955 | 172 | return (u8) data; |
c9a750c9 MA |
173 | } |
174 | ||
6053240f | 175 | int mantis_hif_write_iom(struct mantis_ca *ca, u32 addr, u8 data) |
c9a750c9 MA |
176 | { |
177 | struct mantis_pci *mantis = ca->ca_priv; | |
178 | u32 hif_addr = 0; | |
179 | ||
b3b96144 | 180 | dprintk(MANTIS_DEBUG, 1, "Adapter(%d) Slot(0): Request HIF I/O Write", mantis->num); |
f684336b | 181 | mutex_lock(&ca->ca_lock); |
c9a750c9 MA |
182 | hif_addr &= ~MANTIS_GPIF_PCMCIAREG; |
183 | hif_addr &= ~MANTIS_GPIF_HIFRDWRN; | |
184 | hif_addr |= MANTIS_GPIF_PCMCIAIOM; | |
b29f6ac2 | 185 | hif_addr |= MANTIS_HIF_STATUS; |
c9a750c9 MA |
186 | hif_addr |= addr; |
187 | ||
b29f6ac2 | 188 | mmwrite(hif_addr, MANTIS_GPIF_ADDR); |
a0c59063 | 189 | mmwrite(data, MANTIS_GPIF_DOUT); |
c9a750c9 | 190 | |
e0e099a7 | 191 | if (mantis_hif_write_wait(ca) != 0) { |
b3b96144 | 192 | dprintk(MANTIS_ERROR, 1, "Adapter(%d) Slot(0): HIF Smart Buffer operation failed", mantis->num); |
f684336b | 193 | mutex_unlock(&ca->ca_lock); |
c9a750c9 MA |
194 | return -EREMOTEIO; |
195 | } | |
b3b96144 | 196 | dprintk(MANTIS_DEBUG, 1, "I/O Write: (0x%02x to 0x%02x)", data, addr); |
f684336b | 197 | mutex_unlock(&ca->ca_lock); |
8e0d58ec | 198 | udelay(50); |
c9a750c9 MA |
199 | |
200 | return 0; | |
201 | } | |
202 | ||
d8b14f8a MA |
203 | int mantis_hif_init(struct mantis_ca *ca) |
204 | { | |
ac23f4c8 | 205 | struct mantis_slot *slot = ca->slot; |
d8b14f8a MA |
206 | struct mantis_pci *mantis = ca->ca_priv; |
207 | u32 irqcfg; | |
208 | ||
ac23f4c8 | 209 | slot[0].slave_cfg = 0x70773028; |
b3b96144 | 210 | dprintk(MANTIS_ERROR, 1, "Adapter(%d) Initializing Mantis Host Interface", mantis->num); |
d8b14f8a | 211 | |
f684336b | 212 | mutex_lock(&ca->ca_lock); |
c90d345f MA |
213 | irqcfg = mmread(MANTIS_GPIF_IRQCFG); |
214 | irqcfg = MANTIS_MASK_BRRDY | | |
215 | MANTIS_MASK_WRACK | | |
216 | MANTIS_MASK_EXTIRQ | | |
217 | MANTIS_MASK_WSTO | | |
218 | MANTIS_MASK_OTHERR | | |
219 | MANTIS_MASK_OVFLW; | |
220 | ||
d8b14f8a | 221 | mmwrite(irqcfg, MANTIS_GPIF_IRQCFG); |
f684336b | 222 | mutex_unlock(&ca->ca_lock); |
d8b14f8a MA |
223 | |
224 | return 0; | |
225 | } | |
226 | ||
227 | void mantis_hif_exit(struct mantis_ca *ca) | |
228 | { | |
229 | struct mantis_pci *mantis = ca->ca_priv; | |
230 | u32 irqcfg; | |
231 | ||
b3b96144 | 232 | dprintk(MANTIS_ERROR, 1, "Adapter(%d) Exiting Mantis Host Interface", mantis->num); |
f684336b | 233 | mutex_lock(&ca->ca_lock); |
d8b14f8a MA |
234 | irqcfg = mmread(MANTIS_GPIF_IRQCFG); |
235 | irqcfg &= ~MANTIS_MASK_BRRDY; | |
236 | mmwrite(irqcfg, MANTIS_GPIF_IRQCFG); | |
f684336b | 237 | mutex_unlock(&ca->ca_lock); |
d8b14f8a | 238 | } |