[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / media / dvb / frontends / mt352.c

/*
 *  Driver for Zarlink DVB-T MT352 demodulator
 *
 *  Written by Holger Waechtler <holger@qanu.de>
 *	 and Daniel Mack <daniel@qanu.de>
 *
 *  AVerMedia AVerTV DVB-T 771 support by
 *       Wolfram Joost <dbox2@frokaschwei.de>
 *
 *  Support for Samsung TDTC9251DH01C(M) tuner
 *  Copyright (C) 2004 Antonio Mancuso <antonio.mancuso@digitaltelevision.it>
 *                     Amauri  Celani  <acelani@essegi.net>
 *
 *  DVICO FusionHDTV DVB-T1 and DVICO FusionHDTV DVB-T Lite support by
 *       Christopher Pascoe <c.pascoe@itee.uq.edu.au>
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.=
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/string.h>
#include <linux/slab.h>

#include "dvb_frontend.h"
#include "mt352_priv.h"
#include "mt352.h"

struct mt352_state {
	struct i2c_adapter* i2c;
	struct dvb_frontend frontend;
	struct dvb_frontend_ops ops;

	/* configuration settings */
	struct mt352_config config;
};

static int debug;
#define dprintk(args...) \
	do { \
		if (debug) printk(KERN_DEBUG "mt352: " args); \
	} while (0)

static int mt352_single_write(struct dvb_frontend *fe, u8 reg, u8 val)
{
	struct mt352_state* state = fe->demodulator_priv;
	u8 buf[2] = { reg, val };
	struct i2c_msg msg = { .addr = state->config.demod_address, .flags = 0,
			       .buf = buf, .len = 2 };
	int err = i2c_transfer(state->i2c, &msg, 1);
	if (err != 1) {
		printk("mt352_write() to reg %x failed (err = %d)!\n", reg, err);
		return err;
	}
	return 0;
}

int mt352_write(struct dvb_frontend* fe, u8* ibuf, int ilen)
{
	int err,i;
	for (i=0; i < ilen-1; i++)
		if ((err = mt352_single_write(fe,ibuf[0]+i,ibuf[i+1])))
			return err;

	return 0;
}

static int mt352_read_register(struct mt352_state* state, u8 reg)
{
	int ret;
	u8 b0 [] = { reg };
	u8 b1 [] = { 0 };
	struct i2c_msg msg [] = { { .addr = state->config.demod_address,
				    .flags = 0,
				    .buf = b0, .len = 1 },
				  { .addr = state->config.demod_address,
				    .flags = I2C_M_RD,
				    .buf = b1, .len = 1 } };

	ret = i2c_transfer(state->i2c, msg, 2);

	if (ret != 2) {
		printk("%s: readreg error (reg=%d, ret==%i)\n",
		       __FUNCTION__, reg, ret);
		return ret;
	}

	return b1[0];
}

static int mt352_sleep(struct dvb_frontend* fe)
{
	static u8 mt352_softdown[] = { CLOCK_CTL, 0x20, 0x08 };

	mt352_write(fe, mt352_softdown, sizeof(mt352_softdown));
	return 0;
}

static void mt352_calc_nominal_rate(struct mt352_state* state,
				    enum fe_bandwidth bandwidth,
				    unsigned char *buf)
{
	u32 adc_clock = 20480; /* 20.340 MHz */
	u32 bw,value;

	switch (bandwidth) {
	case BANDWIDTH_6_MHZ:
		bw = 6;
		break;
	case BANDWIDTH_7_MHZ:
		bw = 7;
		break;
	case BANDWIDTH_8_MHZ:
	default:
		bw = 8;
		break;
	}
	if (state->config.adc_clock)
		adc_clock = state->config.adc_clock;

	value = 64 * bw * (1<<16) / (7 * 8);
	value = value * 1000 / adc_clock;
	dprintk("%s: bw %d, adc_clock %d => 0x%x\n",
		__FUNCTION__, bw, adc_clock, value);
	buf[0] = msb(value);
	buf[1] = lsb(value);
}

static void mt352_calc_input_freq(struct mt352_state* state,
				  unsigned char *buf)
{
	int adc_clock = 20480; /* 20.480000 MHz */
	int if2       = 36167; /* 36.166667 MHz */
	int ife,value;

	if (state->config.adc_clock)
		adc_clock = state->config.adc_clock;
	if (state->config.if2)
		if2 = state->config.if2;

	ife = (2*adc_clock - if2);
	value = -16374 * ife / adc_clock;
	dprintk("%s: if2 %d, ife %d, adc_clock %d => %d / 0x%x\n",
		__FUNCTION__, if2, ife, adc_clock, value, value & 0x3fff);
	buf[0] = msb(value);
	buf[1] = lsb(value);
}

static int mt352_set_parameters(struct dvb_frontend* fe,
				struct dvb_frontend_parameters *param)
{
	struct mt352_state* state = fe->demodulator_priv;
	unsigned char buf[13];
	static unsigned char tuner_go[] = { 0x5d, 0x01 };
	static unsigned char fsm_go[]   = { 0x5e, 0x01 };
	unsigned int tps = 0;
	struct dvb_ofdm_parameters *op = &param->u.ofdm;

	switch (op->code_rate_HP) {
		case FEC_2_3:
			tps |= (1 << 7);
			break;
		case FEC_3_4:
			tps |= (2 << 7);
			break;
		case FEC_5_6:
			tps |= (3 << 7);
			break;
		case FEC_7_8:
			tps |= (4 << 7);
			break;
		case FEC_1_2:
		case FEC_AUTO:
			break;
		default:
			return -EINVAL;
	}

	switch (op->code_rate_LP) {
		case FEC_2_3:
			tps |= (1 << 4);
			break;
		case FEC_3_4:
			tps |= (2 << 4);
			break;
		case FEC_5_6:
			tps |= (3 << 4);
			break;
		case FEC_7_8:
			tps |= (4 << 4);
			break;
		case FEC_1_2:
		case FEC_AUTO:
			break;
		case FEC_NONE:
			if (op->hierarchy_information == HIERARCHY_AUTO ||
			    op->hierarchy_information == HIERARCHY_NONE)
				break;
		default:
			return -EINVAL;
	}

	switch (op->constellation) {
		case QPSK:
			break;
		case QAM_AUTO:
		case QAM_16:
			tps |= (1 << 13);
			break;
		case QAM_64:
			tps |= (2 << 13);
			break;
		default:
			return -EINVAL;
	}

	switch (op->transmission_mode) {
		case TRANSMISSION_MODE_2K:
		case TRANSMISSION_MODE_AUTO:
			break;
		case TRANSMISSION_MODE_8K:
			tps |= (1 << 0);
			break;
		default:
			return -EINVAL;
	}

	switch (op->guard_interval) {
		case GUARD_INTERVAL_1_32:
		case GUARD_INTERVAL_AUTO:
			break;
		case GUARD_INTERVAL_1_16:
			tps |= (1 << 2);
			break;
		case GUARD_INTERVAL_1_8:
			tps |= (2 << 2);
			break;
		case GUARD_INTERVAL_1_4:
			tps |= (3 << 2);
			break;
		default:
			return -EINVAL;
	}

	switch (op->hierarchy_information) {
		case HIERARCHY_AUTO:
		case HIERARCHY_NONE:
			break;
		case HIERARCHY_1:
			tps |= (1 << 10);
			break;
		case HIERARCHY_2:
			tps |= (2 << 10);
			break;
		case HIERARCHY_4:
			tps |= (3 << 10);
			break;
		default:
			return -EINVAL;
	}


	buf[0] = TPS_GIVEN_1; /* TPS_GIVEN_1 and following registers */

	buf[1] = msb(tps);      /* TPS_GIVEN_(1|0) */
	buf[2] = lsb(tps);

	buf[3] = 0x50;  // old
//	buf[3] = 0xf4;  // pinnacle

	mt352_calc_nominal_rate(state, op->bandwidth, buf+4);
	mt352_calc_input_freq(state, buf+6);
	state->config.pll_set(fe, param, buf+8);

	mt352_write(fe, buf, sizeof(buf));
	if (state->config.no_tuner) {
		/* start decoding */
		mt352_write(fe, fsm_go, 2);
	} else {
		/* start tuning */
		mt352_write(fe, tuner_go, 2);
	}
	return 0;
}

static int mt352_get_parameters(struct dvb_frontend* fe,
				struct dvb_frontend_parameters *param)
{
	struct mt352_state* state = fe->demodulator_priv;
	u16 tps;
	u16 div;
	u8 trl;
	struct dvb_ofdm_parameters *op = &param->u.ofdm;
	static const u8 tps_fec_to_api[8] =
	{
		FEC_1_2,
		FEC_2_3,
		FEC_3_4,
		FEC_5_6,
		FEC_7_8,
		FEC_AUTO,
		FEC_AUTO,
		FEC_AUTO
	};

	if ( (mt352_read_register(state,0x00) & 0xC0) != 0xC0 )
		return -EINVAL;

	/* Use TPS_RECEIVED-registers, not the TPS_CURRENT-registers because
	 * the mt352 sometimes works with the wrong parameters
	 */
	tps = (mt352_read_register(state, TPS_RECEIVED_1) << 8) | mt352_read_register(state, TPS_RECEIVED_0);
	div = (mt352_read_register(state, CHAN_START_1) << 8) | mt352_read_register(state, CHAN_START_0);
	trl = mt352_read_register(state, TRL_NOMINAL_RATE_1);

	op->code_rate_HP = tps_fec_to_api[(tps >> 7) & 7];
	op->code_rate_LP = tps_fec_to_api[(tps >> 4) & 7];

	switch ( (tps >> 13) & 3)
	{
		case 0:
			op->constellation = QPSK;
			break;
		case 1:
			op->constellation = QAM_16;
			break;
		case 2:
			op->constellation = QAM_64;
			break;
		default:
			op->constellation = QAM_AUTO;
			break;
	}

	op->transmission_mode = (tps & 0x01) ? TRANSMISSION_MODE_8K : TRANSMISSION_MODE_2K;

	switch ( (tps >> 2) & 3)
	{
		case 0:
			op->guard_interval = GUARD_INTERVAL_1_32;
			break;
		case 1:
			op->guard_interval = GUARD_INTERVAL_1_16;
			break;
		case 2:
			op->guard_interval = GUARD_INTERVAL_1_8;
			break;
		case 3:
			op->guard_interval = GUARD_INTERVAL_1_4;
			break;
		default:
			op->guard_interval = GUARD_INTERVAL_AUTO;
			break;
	}

	switch ( (tps >> 10) & 7)
	{
		case 0:
			op->hierarchy_information = HIERARCHY_NONE;
			break;
		case 1:
			op->hierarchy_information = HIERARCHY_1;
			break;
		case 2:
			op->hierarchy_information = HIERARCHY_2;
			break;
		case 3:
			op->hierarchy_information = HIERARCHY_4;
			break;
		default:
			op->hierarchy_information = HIERARCHY_AUTO;
			break;
	}

	param->frequency = ( 500 * (div - IF_FREQUENCYx6) ) / 3 * 1000;

	if (trl == 0x72)
		op->bandwidth = BANDWIDTH_8_MHZ;
	else if (trl == 0x64)
		op->bandwidth = BANDWIDTH_7_MHZ;
	else
		op->bandwidth = BANDWIDTH_6_MHZ;


	if (mt352_read_register(state, STATUS_2) & 0x02)
		param->inversion = INVERSION_OFF;
	else
		param->inversion = INVERSION_ON;

	return 0;
}

static int mt352_read_status(struct dvb_frontend* fe, fe_status_t* status)
{
	struct mt352_state* state = fe->demodulator_priv;
	int s0, s1, s3;

	/* FIXME:
	 *
	 * The MT352 design manual from Zarlink states (page 46-47):
	 *
	 * Notes about the TUNER_GO register:
	 *
	 * If the Read_Tuner_Byte (bit-1) is activated, then the tuner status
	 * byte is copied from the tuner to the STATUS_3 register and
	 * completion of the read operation is indicated by bit-5 of the
	 * INTERRUPT_3 register.
	 */

	if ((s0 = mt352_read_register(state, STATUS_0)) < 0)
		return -EREMOTEIO;
	if ((s1 = mt352_read_register(state, STATUS_1)) < 0)
		return -EREMOTEIO;
	if ((s3 = mt352_read_register(state, STATUS_3)) < 0)
		return -EREMOTEIO;

	*status = 0;
	if (s0 & (1 << 4))
		*status |= FE_HAS_CARRIER;
	if (s0 & (1 << 1))
		*status |= FE_HAS_VITERBI;
	if (s0 & (1 << 5))
		*status |= FE_HAS_LOCK;
	if (s1 & (1 << 1))
		*status |= FE_HAS_SYNC;
	if (s3 & (1 << 6))
		*status |= FE_HAS_SIGNAL;

	if ((*status & (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC)) !=
		      (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC))
		*status &= ~FE_HAS_LOCK;

	return 0;
}

static int mt352_read_ber(struct dvb_frontend* fe, u32* ber)
{
	struct mt352_state* state = fe->demodulator_priv;

	*ber = (mt352_read_register (state, RS_ERR_CNT_2) << 16) |
	       (mt352_read_register (state, RS_ERR_CNT_1) << 8) |
	       (mt352_read_register (state, RS_ERR_CNT_0));

	return 0;
}

static int mt352_read_signal_strength(struct dvb_frontend* fe, u16* strength)
{
	struct mt352_state* state = fe->demodulator_priv;

	/* align the 12 bit AGC gain with the most significant bits */
	u16 signal = ((mt352_read_register(state, AGC_GAIN_1) & 0x0f) << 12) |
		(mt352_read_register(state, AGC_GAIN_0) << 4);

	/* inverse of gain is signal strength */
	*strength = ~signal;
	return 0;
}

static int mt352_read_snr(struct dvb_frontend* fe, u16* snr)
{
	struct mt352_state* state = fe->demodulator_priv;

	u8 _snr = mt352_read_register (state, SNR);
	*snr = (_snr << 8) | _snr;

	return 0;
}

static int mt352_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
{
	struct mt352_state* state = fe->demodulator_priv;

	*ucblocks = (mt352_read_register (state,  RS_UBC_1) << 8) |
		    (mt352_read_register (state,  RS_UBC_0));

	return 0;
}

static int mt352_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fe_tune_settings)
{
	fe_tune_settings->min_delay_ms = 800;
	fe_tune_settings->step_size = 0;
	fe_tune_settings->max_drift = 0;

	return 0;
}

static int mt352_init(struct dvb_frontend* fe)
{
	struct mt352_state* state = fe->demodulator_priv;

	static u8 mt352_reset_attach [] = { RESET, 0xC0 };

	dprintk("%s: hello\n",__FUNCTION__);

	if ((mt352_read_register(state, CLOCK_CTL) & 0x10) == 0 ||
	    (mt352_read_register(state, CONFIG) & 0x20) == 0) {

		/* Do a "hard" reset */
		mt352_write(fe, mt352_reset_attach, sizeof(mt352_reset_attach));
		return state->config.demod_init(fe);
	}

	return 0;
}

static void mt352_release(struct dvb_frontend* fe)
{
	struct mt352_state* state = fe->demodulator_priv;
	kfree(state);
}

static struct dvb_frontend_ops mt352_ops;

struct dvb_frontend* mt352_attach(const struct mt352_config* config,
				  struct i2c_adapter* i2c)
{
	struct mt352_state* state = NULL;

	/* allocate memory for the internal state */
	state = kzalloc(sizeof(struct mt352_state), GFP_KERNEL);
	if (state == NULL) goto error;

	/* setup the state */
	state->i2c = i2c;
	memcpy(&state->config,config,sizeof(struct mt352_config));
	memcpy(&state->ops, &mt352_ops, sizeof(struct dvb_frontend_ops));

	/* check if the demod is there */
	if (mt352_read_register(state, CHIP_ID) != ID_MT352) goto error;

	/* create dvb_frontend */
	state->frontend.ops = &state->ops;
	state->frontend.demodulator_priv = state;
	return &state->frontend;

error:
	kfree(state);
	return NULL;
}

static struct dvb_frontend_ops mt352_ops = {

	.info = {
		.name			= "Zarlink MT352 DVB-T",
		.type			= FE_OFDM,
		.frequency_min		= 174000000,
		.frequency_max		= 862000000,
		.frequency_stepsize	= 166667,
		.frequency_tolerance	= 0,
		.caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
			FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
			FE_CAN_FEC_AUTO |
			FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
			FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
			FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER |
			FE_CAN_MUTE_TS
	},

	.release = mt352_release,

	.init = mt352_init,
	.sleep = mt352_sleep,

	.set_frontend = mt352_set_parameters,
	.get_frontend = mt352_get_parameters,
	.get_tune_settings = mt352_get_tune_settings,

	.read_status = mt352_read_status,
	.read_ber = mt352_read_ber,
	.read_signal_strength = mt352_read_signal_strength,
	.read_snr = mt352_read_snr,
	.read_ucblocks = mt352_read_ucblocks,
};

module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");

MODULE_DESCRIPTION("Zarlink MT352 DVB-T Demodulator driver");
MODULE_AUTHOR("Holger Waechtler, Daniel Mack, Antonio Mancuso");
MODULE_LICENSE("GPL");

EXPORT_SYMBOL(mt352_attach);
EXPORT_SYMBOL(mt352_write);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Driver for Zarlink DVB-T MT352 demodulator
	3	*
	4	* Written by Holger Waechtler <holger@qanu.de>
	5	* and Daniel Mack <daniel@qanu.de>
	6	*
	7	* AVerMedia AVerTV DVB-T 771 support by
	8	* Wolfram Joost <dbox2@frokaschwei.de>
	9	*
	10	* Support for Samsung TDTC9251DH01C(M) tuner
	11	* Copyright (C) 2004 Antonio Mancuso <antonio.mancuso@digitaltelevision.it>
	12	* Amauri Celani <acelani@essegi.net>
	13	*
	14	* DVICO FusionHDTV DVB-T1 and DVICO FusionHDTV DVB-T Lite support by
	15	* Christopher Pascoe <c.pascoe@itee.uq.edu.au>
	16	*
	17	* This program is free software; you can redistribute it and/or modify
	18	* it under the terms of the GNU General Public License as published by
	19	* the Free Software Foundation; either version 2 of the License, or
	20	* (at your option) any later version.
	21	*
	22	* This program is distributed in the hope that it will be useful,
	23	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	24	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	25	*
	26	* GNU General Public License for more details.
	27	*
	28	* You should have received a copy of the GNU General Public License
	29	* along with this program; if not, write to the Free Software
	30	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.=
	31	*/
	32
	33	#include <linux/kernel.h>
	34	#include <linux/module.h>
	35	#include <linux/moduleparam.h>
	36	#include <linux/init.h>
	37	#include <linux/delay.h>
4e57b681 TS	38	#include <linux/string.h>
4e57b681 TS	39	#include <linux/slab.h>
1da177e4 LT	40
	41	#include "dvb_frontend.h"
	42	#include "mt352_priv.h"
	43	#include "mt352.h"
	44
	45	struct mt352_state {
	46	struct i2c_adapter* i2c;
	47	struct dvb_frontend frontend;
	48	struct dvb_frontend_ops ops;
	49
	50	/* configuration settings */
77b3bd0c	51	struct mt352_config config;
1da177e4 LT	52	};
	53
	54	static int debug;
	55	#define dprintk(args...) \
	56	do { \
	57	if (debug) printk(KERN_DEBUG "mt352: " args); \
	58	} while (0)
	59
	60	static int mt352_single_write(struct dvb_frontend *fe, u8 reg, u8 val)
	61	{
	62	struct mt352_state* state = fe->demodulator_priv;
	63	u8 buf[2] = { reg, val };
77b3bd0c	64	struct i2c_msg msg = { .addr = state->config.demod_address, .flags = 0,
1da177e4 LT	65	.buf = buf, .len = 2 };
	66	int err = i2c_transfer(state->i2c, &msg, 1);
	67	if (err != 1) {
	68	printk("mt352_write() to reg %x failed (err = %d)!\n", reg, err);
	69	return err;
	70	}
	71	return 0;
	72	}
	73
	74	int mt352_write(struct dvb_frontend* fe, u8* ibuf, int ilen)
	75	{
	76	int err,i;
	77	for (i=0; i < ilen-1; i++)
	78	if ((err = mt352_single_write(fe,ibuf[0]+i,ibuf[i+1])))
	79	return err;
	80
	81	return 0;
	82	}
	83
	84	static int mt352_read_register(struct mt352_state* state, u8 reg)
	85	{
	86	int ret;
	87	u8 b0 [] = { reg };
	88	u8 b1 [] = { 0 };
77b3bd0c	89	struct i2c_msg msg [] = { { .addr = state->config.demod_address,
1da177e4 LT	90	.flags = 0,
1da177e4 LT	91	.buf = b0, .len = 1 },
77b3bd0c	92	{ .addr = state->config.demod_address,
1da177e4 LT	93	.flags = I2C_M_RD,
	94	.buf = b1, .len = 1 } };
	95
	96	ret = i2c_transfer(state->i2c, msg, 2);
	97
	98	if (ret != 2) {
	99	printk("%s: readreg error (reg=%d, ret==%i)\n",
	100	__FUNCTION__, reg, ret);
	101	return ret;
	102	}
	103
	104	return b1[0];
	105	}
	106
1da177e4 LT	107	static int mt352_sleep(struct dvb_frontend* fe)
	108	{
	109	static u8 mt352_softdown[] = { CLOCK_CTL, 0x20, 0x08 };
	110
	111	mt352_write(fe, mt352_softdown, sizeof(mt352_softdown));
	112	return 0;
	113	}
	114
	115	static void mt352_calc_nominal_rate(struct mt352_state* state,
	116	enum fe_bandwidth bandwidth,
	117	unsigned char *buf)
	118	{
	119	u32 adc_clock = 20480; /* 20.340 MHz */
	120	u32 bw,value;
	121
	122	switch (bandwidth) {
	123	case BANDWIDTH_6_MHZ:
	124	bw = 6;
	125	break;
	126	case BANDWIDTH_7_MHZ:
	127	bw = 7;
	128	break;
	129	case BANDWIDTH_8_MHZ:
	130	default:
	131	bw = 8;
	132	break;
	133	}
77b3bd0c JS	134	if (state->config.adc_clock)
77b3bd0c JS	135	adc_clock = state->config.adc_clock;
1da177e4 LT	136
	137	value = 64 * bw * (1<<16) / (7 * 8);
	138	value = value * 1000 / adc_clock;
	139	dprintk("%s: bw %d, adc_clock %d => 0x%x\n",
	140	__FUNCTION__, bw, adc_clock, value);
	141	buf[0] = msb(value);
	142	buf[1] = lsb(value);
	143	}
	144
	145	static void mt352_calc_input_freq(struct mt352_state* state,
	146	unsigned char *buf)
	147	{
	148	int adc_clock = 20480; /* 20.480000 MHz */
	149	int if2 = 36167; /* 36.166667 MHz */
	150	int ife,value;
	151
77b3bd0c JS	152	if (state->config.adc_clock)
	153	adc_clock = state->config.adc_clock;
	154	if (state->config.if2)
	155	if2 = state->config.if2;
1da177e4 LT	156
	157	ife = (2*adc_clock - if2);
	158	value = -16374 * ife / adc_clock;
	159	dprintk("%s: if2 %d, ife %d, adc_clock %d => %d / 0x%x\n",
	160	__FUNCTION__, if2, ife, adc_clock, value, value & 0x3fff);
	161	buf[0] = msb(value);
	162	buf[1] = lsb(value);
	163	}
	164
	165	static int mt352_set_parameters(struct dvb_frontend* fe,
	166	struct dvb_frontend_parameters *param)
	167	{
	168	struct mt352_state* state = fe->demodulator_priv;
	169	unsigned char buf[13];
	170	static unsigned char tuner_go[] = { 0x5d, 0x01 };
	171	static unsigned char fsm_go[] = { 0x5e, 0x01 };
	172	unsigned int tps = 0;
	173	struct dvb_ofdm_parameters *op = &param->u.ofdm;
	174
	175	switch (op->code_rate_HP) {
	176	case FEC_2_3:
	177	tps \|= (1 << 7);
	178	break;
	179	case FEC_3_4:
	180	tps \|= (2 << 7);
	181	break;
	182	case FEC_5_6:
	183	tps \|= (3 << 7);
	184	break;
	185	case FEC_7_8:
	186	tps \|= (4 << 7);
	187	break;
	188	case FEC_1_2:
	189	case FEC_AUTO:
	190	break;
	191	default:
	192	return -EINVAL;
	193	}
	194
	195	switch (op->code_rate_LP) {
	196	case FEC_2_3:
	197	tps \|= (1 << 4);
	198	break;
	199	case FEC_3_4:
	200	tps \|= (2 << 4);
	201	break;
	202	case FEC_5_6:
	203	tps \|= (3 << 4);
	204	break;
	205	case FEC_7_8:
	206	tps \|= (4 << 4);
	207	break;
	208	case FEC_1_2:
	209	case FEC_AUTO:
	210	break;
	211	case FEC_NONE:
	212	if (op->hierarchy_information == HIERARCHY_AUTO \|\|
	213	op->hierarchy_information == HIERARCHY_NONE)
	214	break;
	215	default:
	216	return -EINVAL;
	217	}
	218
	219	switch (op->constellation) {
220	case QPSK:
221	break;
222	case QAM_AUTO:
223	case QAM_16:
224	tps \|= (1 << 13);
225	break;
226	case QAM_64:
227	tps \|= (2 << 13);
228	break;
229	default:
230	return -EINVAL;
231	}
232
233	switch (op->transmission_mode) {
234	case TRANSMISSION_MODE_2K:
235	case TRANSMISSION_MODE_AUTO:
236	break;
237	case TRANSMISSION_MODE_8K:
238	tps \|= (1 << 0);
239	break;
240	default:
241	return -EINVAL;
242	}
243
244	switch (op->guard_interval) {
245	case GUARD_INTERVAL_1_32:
246	case GUARD_INTERVAL_AUTO:
247	break;
248	case GUARD_INTERVAL_1_16:
249	tps \|= (1 << 2);
250	break;
251	case GUARD_INTERVAL_1_8:
252	tps \|= (2 << 2);
253	break;
254	case GUARD_INTERVAL_1_4:
255	tps \|= (3 << 2);
256	break;
257	default:
258	return -EINVAL;
259	}
260
261	switch (op->hierarchy_information) {
262	case HIERARCHY_AUTO:
263	case HIERARCHY_NONE:
264	break;
265	case HIERARCHY_1:
266	tps \|= (1 << 10);
267	break;
268	case HIERARCHY_2:
269	tps \|= (2 << 10);
270	break;
271	case HIERARCHY_4:
272	tps \|= (3 << 10);
273	break;
274	default:
275	return -EINVAL;
276	}
277
278
279	buf[0] = TPS_GIVEN_1; /* TPS_GIVEN_1 and following registers */
280
281	buf[1] = msb(tps); /* TPS_GIVEN_(1\|0) */
282	buf[2] = lsb(tps);
283
284	buf[3] = 0x50; // old
285	// buf[3] = 0xf4; // pinnacle
286
287	mt352_calc_nominal_rate(state, op->bandwidth, buf+4);
288	mt352_calc_input_freq(state, buf+6);
77b3bd0c	289	state->config.pll_set(fe, param, buf+8);
1da177e4 LT	290
1da177e4 LT	291	mt352_write(fe, buf, sizeof(buf));
77b3bd0c	292	if (state->config.no_tuner) {
1da177e4 LT	293	/* start decoding */
	294	mt352_write(fe, fsm_go, 2);
	295	} else {
	296	/* start tuning */
	297	mt352_write(fe, tuner_go, 2);
	298	}
	299	return 0;
	300	}
	301
	302	static int mt352_get_parameters(struct dvb_frontend* fe,
	303	struct dvb_frontend_parameters *param)
	304	{
	305	struct mt352_state* state = fe->demodulator_priv;
	306	u16 tps;
	307	u16 div;
	308	u8 trl;
	309	struct dvb_ofdm_parameters *op = &param->u.ofdm;
	310	static const u8 tps_fec_to_api[8] =
	311	{
	312	FEC_1_2,
	313	FEC_2_3,
	314	FEC_3_4,
	315	FEC_5_6,
	316	FEC_7_8,
	317	FEC_AUTO,
	318	FEC_AUTO,
	319	FEC_AUTO
	320	};
	321
	322	if ( (mt352_read_register(state,0x00) & 0xC0) != 0xC0 )
	323	return -EINVAL;
	324
	325	/* Use TPS_RECEIVED-registers, not the TPS_CURRENT-registers because
	326	* the mt352 sometimes works with the wrong parameters
	327	*/
	328	tps = (mt352_read_register(state, TPS_RECEIVED_1) << 8) \| mt352_read_register(state, TPS_RECEIVED_0);
	329	div = (mt352_read_register(state, CHAN_START_1) << 8) \| mt352_read_register(state, CHAN_START_0);
	330	trl = mt352_read_register(state, TRL_NOMINAL_RATE_1);
	331
	332	op->code_rate_HP = tps_fec_to_api[(tps >> 7) & 7];
	333	op->code_rate_LP = tps_fec_to_api[(tps >> 4) & 7];
	334
	335	switch ( (tps >> 13) & 3)
	336	{
	337	case 0:
	338	op->constellation = QPSK;
	339	break;
	340	case 1:
	341	op->constellation = QAM_16;
	342	break;
	343	case 2:
	344	op->constellation = QAM_64;
	345	break;
	346	default:
	347	op->constellation = QAM_AUTO;
	348	break;
	349	}
	350
	351	op->transmission_mode = (tps & 0x01) ? TRANSMISSION_MODE_8K : TRANSMISSION_MODE_2K;
	352
	353	switch ( (tps >> 2) & 3)
	354	{
	355	case 0:
	356	op->guard_interval = GUARD_INTERVAL_1_32;
357	break;
358	case 1:
359	op->guard_interval = GUARD_INTERVAL_1_16;
360	break;
361	case 2:
362	op->guard_interval = GUARD_INTERVAL_1_8;
363	break;
364	case 3:
365	op->guard_interval = GUARD_INTERVAL_1_4;
366	break;
367	default:
368	op->guard_interval = GUARD_INTERVAL_AUTO;
369	break;
370	}
371
372	switch ( (tps >> 10) & 7)
373	{
374	case 0:
375	op->hierarchy_information = HIERARCHY_NONE;
376	break;
377	case 1:
378	op->hierarchy_information = HIERARCHY_1;
379	break;
380	case 2:
381	op->hierarchy_information = HIERARCHY_2;
382	break;
383	case 3:
384	op->hierarchy_information = HIERARCHY_4;
385	break;
386	default:
387	op->hierarchy_information = HIERARCHY_AUTO;
388	break;
389	}
390
391	param->frequency = ( 500 * (div - IF_FREQUENCYx6) ) / 3 * 1000;
392
393	if (trl == 0x72)
394	op->bandwidth = BANDWIDTH_8_MHZ;
395	else if (trl == 0x64)
396	op->bandwidth = BANDWIDTH_7_MHZ;
397	else
398	op->bandwidth = BANDWIDTH_6_MHZ;
399
400
401	if (mt352_read_register(state, STATUS_2) & 0x02)
402	param->inversion = INVERSION_OFF;
403	else
404	param->inversion = INVERSION_ON;
405
406	return 0;
407	}
408
409	static int mt352_read_status(struct dvb_frontend* fe, fe_status_t* status)
410	{
411	struct mt352_state* state = fe->demodulator_priv;
412	int s0, s1, s3;
413
414	/* FIXME:
415	*
416	* The MT352 design manual from Zarlink states (page 46-47):
417	*
418	* Notes about the TUNER_GO register:
419	*
420	* If the Read_Tuner_Byte (bit-1) is activated, then the tuner status
421	* byte is copied from the tuner to the STATUS_3 register and
422	* completion of the read operation is indicated by bit-5 of the
423	* INTERRUPT_3 register.
424	*/
425
426	if ((s0 = mt352_read_register(state, STATUS_0)) < 0)
427	return -EREMOTEIO;
428	if ((s1 = mt352_read_register(state, STATUS_1)) < 0)
429	return -EREMOTEIO;
430	if ((s3 = mt352_read_register(state, STATUS_3)) < 0)
431	return -EREMOTEIO;
432
433	*status = 0;
434	if (s0 & (1 << 4))
435	*status \|= FE_HAS_CARRIER;
436	if (s0 & (1 << 1))
437	*status \|= FE_HAS_VITERBI;
438	if (s0 & (1 << 5))
439	*status \|= FE_HAS_LOCK;
440	if (s1 & (1 << 1))
441	*status \|= FE_HAS_SYNC;
442	if (s3 & (1 << 6))
443	*status \|= FE_HAS_SIGNAL;
444
445	if ((*status & (FE_HAS_CARRIER \| FE_HAS_VITERBI \| FE_HAS_SYNC)) !=
446	(FE_HAS_CARRIER \| FE_HAS_VITERBI \| FE_HAS_SYNC))
447	*status &= ~FE_HAS_LOCK;
448
449	return 0;
450	}
451
452	static int mt352_read_ber(struct dvb_frontend* fe, u32* ber)
453	{
454	struct mt352_state* state = fe->demodulator_priv;
455
456	*ber = (mt352_read_register (state, RS_ERR_CNT_2) << 16) \|
457	(mt352_read_register (state, RS_ERR_CNT_1) << 8) \|
458	(mt352_read_register (state, RS_ERR_CNT_0));
459
460	return 0;
461	}
462
463	static int mt352_read_signal_strength(struct dvb_frontend* fe, u16* strength)
464	{
465	struct mt352_state* state = fe->demodulator_priv;
466
4ff4ac1b BS	467	/* align the 12 bit AGC gain with the most significant bits */
	468	u16 signal = ((mt352_read_register(state, AGC_GAIN_1) & 0x0f) << 12) \|
	469	(mt352_read_register(state, AGC_GAIN_0) << 4);
1da177e4	470
4ff4ac1b	471	/* inverse of gain is signal strength */
1da177e4 LT	472	*strength = ~signal;
	473	return 0;
	474	}
	475
	476	static int mt352_read_snr(struct dvb_frontend* fe, u16* snr)
	477	{
	478	struct mt352_state* state = fe->demodulator_priv;
	479
	480	u8 _snr = mt352_read_register (state, SNR);
	481	*snr = (_snr << 8) \| _snr;
	482
	483	return 0;
	484	}
	485
	486	static int mt352_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
	487	{
	488	struct mt352_state* state = fe->demodulator_priv;
	489
	490	*ucblocks = (mt352_read_register (state, RS_UBC_1) << 8) \|
	491	(mt352_read_register (state, RS_UBC_0));
	492
	493	return 0;
	494	}
	495
	496	static int mt352_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fe_tune_settings)
	497	{
	498	fe_tune_settings->min_delay_ms = 800;
	499	fe_tune_settings->step_size = 0;
	500	fe_tune_settings->max_drift = 0;
	501
	502	return 0;
	503	}
	504
	505	static int mt352_init(struct dvb_frontend* fe)
	506	{
	507	struct mt352_state* state = fe->demodulator_priv;
	508
	509	static u8 mt352_reset_attach [] = { RESET, 0xC0 };
	510
	511	dprintk("%s: hello\n",__FUNCTION__);
	512
	513	if ((mt352_read_register(state, CLOCK_CTL) & 0x10) == 0 \|\|
	514	(mt352_read_register(state, CONFIG) & 0x20) == 0) {
	515
	516	/* Do a "hard" reset */
	517	mt352_write(fe, mt352_reset_attach, sizeof(mt352_reset_attach));
77b3bd0c	518	return state->config.demod_init(fe);
1da177e4 LT	519	}
	520
	521	return 0;
	522	}
	523
	524	static void mt352_release(struct dvb_frontend* fe)
	525	{
	526	struct mt352_state* state = fe->demodulator_priv;
	527	kfree(state);
	528	}
	529
	530	static struct dvb_frontend_ops mt352_ops;
	531
	532	struct dvb_frontend* mt352_attach(const struct mt352_config* config,
	533	struct i2c_adapter* i2c)
	534	{
	535	struct mt352_state* state = NULL;
	536
	537	/* allocate memory for the internal state */
7408187d	538	state = kzalloc(sizeof(struct mt352_state), GFP_KERNEL);
1da177e4	539	if (state == NULL) goto error;
1da177e4 LT	540
1da177e4 LT	541	/* setup the state */
1da177e4	542	state->i2c = i2c;
77b3bd0c	543	memcpy(&state->config,config,sizeof(struct mt352_config));
1da177e4 LT	544	memcpy(&state->ops, &mt352_ops, sizeof(struct dvb_frontend_ops));
	545
	546	/* check if the demod is there */
	547	if (mt352_read_register(state, CHIP_ID) != ID_MT352) goto error;
	548
	549	/* create dvb_frontend */
	550	state->frontend.ops = &state->ops;
	551	state->frontend.demodulator_priv = state;
	552	return &state->frontend;
	553
	554	error:
	555	kfree(state);
	556	return NULL;
	557	}
	558
	559	static struct dvb_frontend_ops mt352_ops = {
	560
	561	.info = {
	562	.name = "Zarlink MT352 DVB-T",
	563	.type = FE_OFDM,
	564	.frequency_min = 174000000,
	565	.frequency_max = 862000000,
	566	.frequency_stepsize = 166667,
	567	.frequency_tolerance = 0,
	568	.caps = FE_CAN_FEC_1_2 \| FE_CAN_FEC_2_3 \|
	569	FE_CAN_FEC_3_4 \| FE_CAN_FEC_5_6 \| FE_CAN_FEC_7_8 \|
	570	FE_CAN_FEC_AUTO \|
	571	FE_CAN_QPSK \| FE_CAN_QAM_16 \| FE_CAN_QAM_64 \| FE_CAN_QAM_AUTO \|
	572	FE_CAN_TRANSMISSION_MODE_AUTO \| FE_CAN_GUARD_INTERVAL_AUTO \|
	573	FE_CAN_HIERARCHY_AUTO \| FE_CAN_RECOVER \|
	574	FE_CAN_MUTE_TS
	575	},
	576
	577	.release = mt352_release,
	578
	579	.init = mt352_init,
	580	.sleep = mt352_sleep,
	581
	582	.set_frontend = mt352_set_parameters,
	583	.get_frontend = mt352_get_parameters,
	584	.get_tune_settings = mt352_get_tune_settings,
	585
	586	.read_status = mt352_read_status,
	587	.read_ber = mt352_read_ber,
	588	.read_signal_strength = mt352_read_signal_strength,
	589	.read_snr = mt352_read_snr,
	590	.read_ucblocks = mt352_read_ucblocks,
	591	};
	592
	593	module_param(debug, int, 0644);
	594	MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
	595
	596	MODULE_DESCRIPTION("Zarlink MT352 DVB-T Demodulator driver");
	597	MODULE_AUTHOR("Holger Waechtler, Daniel Mack, Antonio Mancuso");
	598	MODULE_LICENSE("GPL");
	599
	600	EXPORT_SYMBOL(mt352_attach);
	601	EXPORT_SYMBOL(mt352_write);