Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | Driver for Zarlink VP310/MT312 Satellite Channel Decoder | |
3 | ||
4 | Copyright (C) 2003 Andreas Oberritter <obi@linuxtv.org> | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2 of the License, or | |
9 | (at your option) any later version. | |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ||
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
20 | ||
21 | References: | |
22 | http://products.zarlink.com/product_profiles/MT312.htm | |
23 | http://products.zarlink.com/product_profiles/SL1935.htm | |
24 | */ | |
25 | ||
26 | #include <linux/delay.h> | |
27 | #include <linux/errno.h> | |
28 | #include <linux/init.h> | |
29 | #include <linux/kernel.h> | |
30 | #include <linux/module.h> | |
31 | #include <linux/moduleparam.h> | |
32 | ||
33 | #include "dvb_frontend.h" | |
34 | #include "mt312_priv.h" | |
35 | #include "mt312.h" | |
36 | ||
37 | ||
38 | struct mt312_state { | |
39 | struct i2c_adapter* i2c; | |
40 | struct dvb_frontend_ops ops; | |
41 | /* configuration settings */ | |
42 | const struct mt312_config* config; | |
43 | struct dvb_frontend frontend; | |
44 | ||
45 | u8 id; | |
46 | u8 frequency; | |
47 | }; | |
48 | ||
49 | static int debug; | |
50 | #define dprintk(args...) \ | |
51 | do { \ | |
52 | if (debug) printk(KERN_DEBUG "mt312: " args); \ | |
53 | } while (0) | |
54 | ||
55 | #define MT312_SYS_CLK 90000000UL /* 90 MHz */ | |
56 | #define MT312_LPOWER_SYS_CLK 60000000UL /* 60 MHz */ | |
57 | #define MT312_PLL_CLK 10000000UL /* 10 MHz */ | |
58 | ||
59 | static int mt312_read(struct mt312_state* state, const enum mt312_reg_addr reg, | |
60 | void *buf, const size_t count) | |
61 | { | |
62 | int ret; | |
63 | struct i2c_msg msg[2]; | |
64 | u8 regbuf[1] = { reg }; | |
65 | ||
66 | msg[0].addr = state->config->demod_address; | |
67 | msg[0].flags = 0; | |
68 | msg[0].buf = regbuf; | |
69 | msg[0].len = 1; | |
70 | msg[1].addr = state->config->demod_address; | |
71 | msg[1].flags = I2C_M_RD; | |
72 | msg[1].buf = buf; | |
73 | msg[1].len = count; | |
74 | ||
75 | ret = i2c_transfer(state->i2c, msg, 2); | |
76 | ||
77 | if (ret != 2) { | |
78 | printk(KERN_ERR "%s: ret == %d\n", __FUNCTION__, ret); | |
79 | return -EREMOTEIO; | |
80 | } | |
81 | ||
82 | if(debug) { | |
83 | int i; | |
84 | dprintk("R(%d):", reg & 0x7f); | |
85 | for (i = 0; i < count; i++) | |
86 | printk(" %02x", ((const u8 *) buf)[i]); | |
87 | printk("\n"); | |
88 | } | |
89 | ||
90 | return 0; | |
91 | } | |
92 | ||
93 | static int mt312_write(struct mt312_state* state, const enum mt312_reg_addr reg, | |
94 | const void *src, const size_t count) | |
95 | { | |
96 | int ret; | |
97 | u8 buf[count + 1]; | |
98 | struct i2c_msg msg; | |
99 | ||
100 | if(debug) { | |
101 | int i; | |
102 | dprintk("W(%d):", reg & 0x7f); | |
103 | for (i = 0; i < count; i++) | |
104 | printk(" %02x", ((const u8 *) src)[i]); | |
105 | printk("\n"); | |
106 | } | |
107 | ||
108 | buf[0] = reg; | |
109 | memcpy(&buf[1], src, count); | |
110 | ||
111 | msg.addr = state->config->demod_address; | |
112 | msg.flags = 0; | |
113 | msg.buf = buf; | |
114 | msg.len = count + 1; | |
115 | ||
116 | ret = i2c_transfer(state->i2c, &msg, 1); | |
117 | ||
118 | if (ret != 1) { | |
119 | dprintk("%s: ret == %d\n", __FUNCTION__, ret); | |
120 | return -EREMOTEIO; | |
121 | } | |
122 | ||
123 | return 0; | |
124 | } | |
125 | ||
126 | static inline int mt312_readreg(struct mt312_state* state, | |
127 | const enum mt312_reg_addr reg, u8 *val) | |
128 | { | |
129 | return mt312_read(state, reg, val, 1); | |
130 | } | |
131 | ||
132 | static inline int mt312_writereg(struct mt312_state* state, | |
133 | const enum mt312_reg_addr reg, const u8 val) | |
134 | { | |
135 | return mt312_write(state, reg, &val, 1); | |
136 | } | |
137 | ||
138 | static inline u32 mt312_div(u32 a, u32 b) | |
139 | { | |
140 | return (a + (b / 2)) / b; | |
141 | } | |
142 | ||
143 | static int mt312_reset(struct mt312_state* state, const u8 full) | |
144 | { | |
145 | return mt312_writereg(state, RESET, full ? 0x80 : 0x40); | |
146 | } | |
147 | ||
148 | static int mt312_get_inversion(struct mt312_state* state, | |
149 | fe_spectral_inversion_t *i) | |
150 | { | |
151 | int ret; | |
152 | u8 vit_mode; | |
153 | ||
154 | if ((ret = mt312_readreg(state, VIT_MODE, &vit_mode)) < 0) | |
155 | return ret; | |
156 | ||
157 | if (vit_mode & 0x80) /* auto inversion was used */ | |
158 | *i = (vit_mode & 0x40) ? INVERSION_ON : INVERSION_OFF; | |
159 | ||
160 | return 0; | |
161 | } | |
162 | ||
163 | static int mt312_get_symbol_rate(struct mt312_state* state, u32 *sr) | |
164 | { | |
165 | int ret; | |
166 | u8 sym_rate_h; | |
167 | u8 dec_ratio; | |
168 | u16 sym_rat_op; | |
169 | u16 monitor; | |
170 | u8 buf[2]; | |
171 | ||
172 | if ((ret = mt312_readreg(state, SYM_RATE_H, &sym_rate_h)) < 0) | |
173 | return ret; | |
174 | ||
175 | if (sym_rate_h & 0x80) { /* symbol rate search was used */ | |
176 | if ((ret = mt312_writereg(state, MON_CTRL, 0x03)) < 0) | |
177 | return ret; | |
178 | ||
179 | if ((ret = mt312_read(state, MONITOR_H, buf, sizeof(buf))) < 0) | |
180 | return ret; | |
181 | ||
182 | monitor = (buf[0] << 8) | buf[1]; | |
183 | ||
184 | dprintk(KERN_DEBUG "sr(auto) = %u\n", | |
185 | mt312_div(monitor * 15625, 4)); | |
186 | } else { | |
187 | if ((ret = mt312_writereg(state, MON_CTRL, 0x05)) < 0) | |
188 | return ret; | |
189 | ||
190 | if ((ret = mt312_read(state, MONITOR_H, buf, sizeof(buf))) < 0) | |
191 | return ret; | |
192 | ||
193 | dec_ratio = ((buf[0] >> 5) & 0x07) * 32; | |
194 | ||
195 | if ((ret = mt312_read(state, SYM_RAT_OP_H, buf, sizeof(buf))) < 0) | |
196 | return ret; | |
197 | ||
198 | sym_rat_op = (buf[0] << 8) | buf[1]; | |
199 | ||
200 | dprintk(KERN_DEBUG "sym_rat_op=%d dec_ratio=%d\n", | |
201 | sym_rat_op, dec_ratio); | |
202 | dprintk(KERN_DEBUG "*sr(manual) = %lu\n", | |
203 | (((MT312_PLL_CLK * 8192) / (sym_rat_op + 8192)) * | |
204 | 2) - dec_ratio); | |
205 | } | |
206 | ||
207 | return 0; | |
208 | } | |
209 | ||
210 | static int mt312_get_code_rate(struct mt312_state* state, fe_code_rate_t *cr) | |
211 | { | |
212 | const fe_code_rate_t fec_tab[8] = | |
213 | { FEC_1_2, FEC_2_3, FEC_3_4, FEC_5_6, FEC_6_7, FEC_7_8, | |
214 | FEC_AUTO, FEC_AUTO }; | |
215 | ||
216 | int ret; | |
217 | u8 fec_status; | |
218 | ||
219 | if ((ret = mt312_readreg(state, FEC_STATUS, &fec_status)) < 0) | |
220 | return ret; | |
221 | ||
222 | *cr = fec_tab[(fec_status >> 4) & 0x07]; | |
223 | ||
224 | return 0; | |
225 | } | |
226 | ||
227 | static int mt312_initfe(struct dvb_frontend* fe) | |
228 | { | |
b8742700 | 229 | struct mt312_state *state = fe->demodulator_priv; |
1da177e4 LT |
230 | int ret; |
231 | u8 buf[2]; | |
232 | ||
233 | /* wake up */ | |
234 | if ((ret = mt312_writereg(state, CONFIG, (state->frequency == 60 ? 0x88 : 0x8c))) < 0) | |
235 | return ret; | |
236 | ||
237 | /* wait at least 150 usec */ | |
238 | udelay(150); | |
239 | ||
240 | /* full reset */ | |
241 | if ((ret = mt312_reset(state, 1)) < 0) | |
242 | return ret; | |
243 | ||
244 | // Per datasheet, write correct values. 09/28/03 ACCJr. | |
245 | // If we don't do this, we won't get FE_HAS_VITERBI in the VP310. | |
246 | { | |
247 | u8 buf_def[8]={0x14, 0x12, 0x03, 0x02, 0x01, 0x00, 0x00, 0x00}; | |
248 | ||
249 | if ((ret = mt312_write(state, VIT_SETUP, buf_def, sizeof(buf_def))) < 0) | |
250 | return ret; | |
251 | } | |
252 | ||
253 | /* SYS_CLK */ | |
254 | buf[0] = mt312_div((state->frequency == 60 ? MT312_LPOWER_SYS_CLK : MT312_SYS_CLK) * 2, 1000000); | |
255 | ||
256 | /* DISEQC_RATIO */ | |
257 | buf[1] = mt312_div(MT312_PLL_CLK, 15000 * 4); | |
258 | ||
259 | if ((ret = mt312_write(state, SYS_CLK, buf, sizeof(buf))) < 0) | |
260 | return ret; | |
261 | ||
262 | if ((ret = mt312_writereg(state, SNR_THS_HIGH, 0x32)) < 0) | |
263 | return ret; | |
264 | ||
265 | if ((ret = mt312_writereg(state, OP_CTRL, 0x53)) < 0) | |
266 | return ret; | |
267 | ||
268 | /* TS_SW_LIM */ | |
269 | buf[0] = 0x8c; | |
270 | buf[1] = 0x98; | |
271 | ||
272 | if ((ret = mt312_write(state, TS_SW_LIM_L, buf, sizeof(buf))) < 0) | |
273 | return ret; | |
274 | ||
275 | if ((ret = mt312_writereg(state, CS_SW_LIM, 0x69)) < 0) | |
276 | return ret; | |
277 | ||
278 | if (state->config->pll_init) { | |
279 | mt312_writereg(state, GPP_CTRL, 0x40); | |
280 | state->config->pll_init(fe); | |
281 | mt312_writereg(state, GPP_CTRL, 0x00); | |
282 | } | |
283 | ||
284 | return 0; | |
285 | } | |
286 | ||
287 | static int mt312_send_master_cmd(struct dvb_frontend* fe, | |
288 | struct dvb_diseqc_master_cmd *c) | |
289 | { | |
b8742700 | 290 | struct mt312_state *state = fe->demodulator_priv; |
1da177e4 LT |
291 | int ret; |
292 | u8 diseqc_mode; | |
293 | ||
294 | if ((c->msg_len == 0) || (c->msg_len > sizeof(c->msg))) | |
295 | return -EINVAL; | |
296 | ||
297 | if ((ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode)) < 0) | |
298 | return ret; | |
299 | ||
300 | if ((ret = | |
301 | mt312_write(state, (0x80 | DISEQC_INSTR), c->msg, c->msg_len)) < 0) | |
302 | return ret; | |
303 | ||
304 | if ((ret = | |
305 | mt312_writereg(state, DISEQC_MODE, | |
306 | (diseqc_mode & 0x40) | ((c->msg_len - 1) << 3) | |
307 | | 0x04)) < 0) | |
308 | return ret; | |
309 | ||
310 | /* set DISEQC_MODE[2:0] to zero if a return message is expected */ | |
311 | if (c->msg[0] & 0x02) | |
312 | if ((ret = | |
313 | mt312_writereg(state, DISEQC_MODE, (diseqc_mode & 0x40))) < 0) | |
314 | return ret; | |
315 | ||
316 | return 0; | |
317 | } | |
318 | ||
319 | static int mt312_send_burst(struct dvb_frontend* fe, const fe_sec_mini_cmd_t c) | |
320 | { | |
b8742700 | 321 | struct mt312_state *state = fe->demodulator_priv; |
1da177e4 LT |
322 | const u8 mini_tab[2] = { 0x02, 0x03 }; |
323 | ||
324 | int ret; | |
325 | u8 diseqc_mode; | |
326 | ||
327 | if (c > SEC_MINI_B) | |
328 | return -EINVAL; | |
329 | ||
330 | if ((ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode)) < 0) | |
331 | return ret; | |
332 | ||
333 | if ((ret = | |
334 | mt312_writereg(state, DISEQC_MODE, | |
335 | (diseqc_mode & 0x40) | mini_tab[c])) < 0) | |
336 | return ret; | |
337 | ||
338 | return 0; | |
339 | } | |
340 | ||
341 | static int mt312_set_tone(struct dvb_frontend* fe, const fe_sec_tone_mode_t t) | |
342 | { | |
b8742700 | 343 | struct mt312_state *state = fe->demodulator_priv; |
1da177e4 LT |
344 | const u8 tone_tab[2] = { 0x01, 0x00 }; |
345 | ||
346 | int ret; | |
347 | u8 diseqc_mode; | |
348 | ||
349 | if (t > SEC_TONE_OFF) | |
350 | return -EINVAL; | |
351 | ||
352 | if ((ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode)) < 0) | |
353 | return ret; | |
354 | ||
355 | if ((ret = | |
356 | mt312_writereg(state, DISEQC_MODE, | |
357 | (diseqc_mode & 0x40) | tone_tab[t])) < 0) | |
358 | return ret; | |
359 | ||
360 | return 0; | |
361 | } | |
362 | ||
363 | static int mt312_set_voltage(struct dvb_frontend* fe, const fe_sec_voltage_t v) | |
364 | { | |
b8742700 | 365 | struct mt312_state *state = fe->demodulator_priv; |
1da177e4 LT |
366 | const u8 volt_tab[3] = { 0x00, 0x40, 0x00 }; |
367 | ||
368 | if (v > SEC_VOLTAGE_OFF) | |
369 | return -EINVAL; | |
370 | ||
371 | return mt312_writereg(state, DISEQC_MODE, volt_tab[v]); | |
372 | } | |
373 | ||
374 | static int mt312_read_status(struct dvb_frontend* fe, fe_status_t *s) | |
375 | { | |
b8742700 | 376 | struct mt312_state *state = fe->demodulator_priv; |
1da177e4 LT |
377 | int ret; |
378 | u8 status[3]; | |
379 | ||
380 | *s = 0; | |
381 | ||
382 | if ((ret = mt312_read(state, QPSK_STAT_H, status, sizeof(status))) < 0) | |
383 | return ret; | |
384 | ||
385 | dprintk(KERN_DEBUG "QPSK_STAT_H: 0x%02x, QPSK_STAT_L: 0x%02x, FEC_STATUS: 0x%02x\n", status[0], status[1], status[2]); | |
386 | ||
387 | if (status[0] & 0xc0) | |
388 | *s |= FE_HAS_SIGNAL; /* signal noise ratio */ | |
389 | if (status[0] & 0x04) | |
390 | *s |= FE_HAS_CARRIER; /* qpsk carrier lock */ | |
391 | if (status[2] & 0x02) | |
392 | *s |= FE_HAS_VITERBI; /* viterbi lock */ | |
393 | if (status[2] & 0x04) | |
394 | *s |= FE_HAS_SYNC; /* byte align lock */ | |
395 | if (status[0] & 0x01) | |
396 | *s |= FE_HAS_LOCK; /* qpsk lock */ | |
397 | ||
398 | return 0; | |
399 | } | |
400 | ||
401 | static int mt312_read_ber(struct dvb_frontend* fe, u32 *ber) | |
402 | { | |
b8742700 | 403 | struct mt312_state *state = fe->demodulator_priv; |
1da177e4 LT |
404 | int ret; |
405 | u8 buf[3]; | |
406 | ||
407 | if ((ret = mt312_read(state, RS_BERCNT_H, buf, 3)) < 0) | |
408 | return ret; | |
409 | ||
410 | *ber = ((buf[0] << 16) | (buf[1] << 8) | buf[2]) * 64; | |
411 | ||
412 | return 0; | |
413 | } | |
414 | ||
415 | static int mt312_read_signal_strength(struct dvb_frontend* fe, u16 *signal_strength) | |
416 | { | |
b8742700 | 417 | struct mt312_state *state = fe->demodulator_priv; |
1da177e4 LT |
418 | int ret; |
419 | u8 buf[3]; | |
420 | u16 agc; | |
421 | s16 err_db; | |
422 | ||
423 | if ((ret = mt312_read(state, AGC_H, buf, sizeof(buf))) < 0) | |
424 | return ret; | |
425 | ||
426 | agc = (buf[0] << 6) | (buf[1] >> 2); | |
427 | err_db = (s16) (((buf[1] & 0x03) << 14) | buf[2] << 6) >> 6; | |
428 | ||
429 | *signal_strength = agc; | |
430 | ||
431 | dprintk(KERN_DEBUG "agc=%08x err_db=%hd\n", agc, err_db); | |
432 | ||
433 | return 0; | |
434 | } | |
435 | ||
436 | static int mt312_read_snr(struct dvb_frontend* fe, u16 *snr) | |
437 | { | |
b8742700 | 438 | struct mt312_state *state = fe->demodulator_priv; |
1da177e4 LT |
439 | int ret; |
440 | u8 buf[2]; | |
441 | ||
442 | if ((ret = mt312_read(state, M_SNR_H, &buf, sizeof(buf))) < 0) | |
443 | return ret; | |
444 | ||
445 | *snr = 0xFFFF - ((((buf[0] & 0x7f) << 8) | buf[1]) << 1); | |
446 | ||
447 | return 0; | |
448 | } | |
449 | ||
450 | static int mt312_read_ucblocks(struct dvb_frontend* fe, u32 *ubc) | |
451 | { | |
b8742700 | 452 | struct mt312_state *state = fe->demodulator_priv; |
1da177e4 LT |
453 | int ret; |
454 | u8 buf[2]; | |
455 | ||
456 | if ((ret = mt312_read(state, RS_UBC_H, &buf, sizeof(buf))) < 0) | |
457 | return ret; | |
458 | ||
459 | *ubc = (buf[0] << 8) | buf[1]; | |
460 | ||
461 | return 0; | |
462 | } | |
463 | ||
464 | static int mt312_set_frontend(struct dvb_frontend* fe, | |
465 | struct dvb_frontend_parameters *p) | |
466 | { | |
b8742700 | 467 | struct mt312_state *state = fe->demodulator_priv; |
1da177e4 LT |
468 | int ret; |
469 | u8 buf[5], config_val; | |
470 | u16 sr; | |
471 | ||
472 | const u8 fec_tab[10] = | |
473 | { 0x00, 0x01, 0x02, 0x04, 0x3f, 0x08, 0x10, 0x20, 0x3f, 0x3f }; | |
474 | const u8 inv_tab[3] = { 0x00, 0x40, 0x80 }; | |
475 | ||
476 | dprintk("%s: Freq %d\n", __FUNCTION__, p->frequency); | |
477 | ||
478 | if ((p->frequency < fe->ops->info.frequency_min) | |
479 | || (p->frequency > fe->ops->info.frequency_max)) | |
480 | return -EINVAL; | |
481 | ||
482 | if ((p->inversion < INVERSION_OFF) | |
483 | || (p->inversion > INVERSION_ON)) | |
484 | return -EINVAL; | |
485 | ||
486 | if ((p->u.qpsk.symbol_rate < fe->ops->info.symbol_rate_min) | |
487 | || (p->u.qpsk.symbol_rate > fe->ops->info.symbol_rate_max)) | |
488 | return -EINVAL; | |
489 | ||
490 | if ((p->u.qpsk.fec_inner < FEC_NONE) | |
491 | || (p->u.qpsk.fec_inner > FEC_AUTO)) | |
492 | return -EINVAL; | |
493 | ||
494 | if ((p->u.qpsk.fec_inner == FEC_4_5) | |
495 | || (p->u.qpsk.fec_inner == FEC_8_9)) | |
496 | return -EINVAL; | |
497 | ||
498 | switch (state->id) { | |
499 | case ID_VP310: | |
500 | // For now we will do this only for the VP310. | |
501 | // It should be better for the mt312 as well, but tunning will be slower. ACCJr 09/29/03 | |
502 | if ((ret = mt312_readreg(state, CONFIG, &config_val) < 0)) | |
503 | return ret; | |
504 | if (p->u.qpsk.symbol_rate >= 30000000) //Note that 30MS/s should use 90MHz | |
505 | { | |
506 | if ((config_val & 0x0c) == 0x08) { //We are running 60MHz | |
507 | state->frequency = 90; | |
508 | if ((ret = mt312_initfe(fe)) < 0) | |
509 | return ret; | |
510 | } | |
511 | } | |
512 | else | |
513 | { | |
514 | if ((config_val & 0x0c) == 0x0C) { //We are running 90MHz | |
515 | state->frequency = 60; | |
516 | if ((ret = mt312_initfe(fe)) < 0) | |
517 | return ret; | |
518 | } | |
519 | } | |
520 | break; | |
521 | ||
522 | case ID_MT312: | |
523 | break; | |
524 | ||
525 | default: | |
526 | return -EINVAL; | |
527 | } | |
528 | ||
529 | mt312_writereg(state, GPP_CTRL, 0x40); | |
530 | state->config->pll_set(fe, p); | |
531 | mt312_writereg(state, GPP_CTRL, 0x00); | |
532 | ||
533 | /* sr = (u16)(sr * 256.0 / 1000000.0) */ | |
534 | sr = mt312_div(p->u.qpsk.symbol_rate * 4, 15625); | |
535 | ||
536 | /* SYM_RATE */ | |
537 | buf[0] = (sr >> 8) & 0x3f; | |
538 | buf[1] = (sr >> 0) & 0xff; | |
539 | ||
540 | /* VIT_MODE */ | |
541 | buf[2] = inv_tab[p->inversion] | fec_tab[p->u.qpsk.fec_inner]; | |
542 | ||
543 | /* QPSK_CTRL */ | |
544 | buf[3] = 0x40; /* swap I and Q before QPSK demodulation */ | |
545 | ||
546 | if (p->u.qpsk.symbol_rate < 10000000) | |
547 | buf[3] |= 0x04; /* use afc mode */ | |
548 | ||
549 | /* GO */ | |
550 | buf[4] = 0x01; | |
551 | ||
552 | if ((ret = mt312_write(state, SYM_RATE_H, buf, sizeof(buf))) < 0) | |
553 | return ret; | |
554 | ||
555 | mt312_reset(state, 0); | |
556 | ||
557 | return 0; | |
558 | } | |
559 | ||
560 | static int mt312_get_frontend(struct dvb_frontend* fe, | |
561 | struct dvb_frontend_parameters *p) | |
562 | { | |
b8742700 | 563 | struct mt312_state *state = fe->demodulator_priv; |
1da177e4 LT |
564 | int ret; |
565 | ||
566 | if ((ret = mt312_get_inversion(state, &p->inversion)) < 0) | |
567 | return ret; | |
568 | ||
569 | if ((ret = mt312_get_symbol_rate(state, &p->u.qpsk.symbol_rate)) < 0) | |
570 | return ret; | |
571 | ||
572 | if ((ret = mt312_get_code_rate(state, &p->u.qpsk.fec_inner)) < 0) | |
573 | return ret; | |
574 | ||
575 | return 0; | |
576 | } | |
577 | ||
578 | static int mt312_sleep(struct dvb_frontend* fe) | |
579 | { | |
b8742700 | 580 | struct mt312_state *state = fe->demodulator_priv; |
1da177e4 LT |
581 | int ret; |
582 | u8 config; | |
583 | ||
584 | /* reset all registers to defaults */ | |
585 | if ((ret = mt312_reset(state, 1)) < 0) | |
586 | return ret; | |
587 | ||
588 | if ((ret = mt312_readreg(state, CONFIG, &config)) < 0) | |
589 | return ret; | |
590 | ||
591 | /* enter standby */ | |
592 | if ((ret = mt312_writereg(state, CONFIG, config & 0x7f)) < 0) | |
593 | return ret; | |
594 | ||
595 | return 0; | |
596 | } | |
597 | ||
598 | static int mt312_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings) | |
599 | { | |
600 | fesettings->min_delay_ms = 50; | |
601 | fesettings->step_size = 0; | |
602 | fesettings->max_drift = 0; | |
603 | return 0; | |
604 | } | |
605 | ||
606 | static void mt312_release(struct dvb_frontend* fe) | |
607 | { | |
b8742700 | 608 | struct mt312_state* state = fe->demodulator_priv; |
1da177e4 LT |
609 | kfree(state); |
610 | } | |
611 | ||
612 | static struct dvb_frontend_ops vp310_mt312_ops; | |
613 | ||
614 | struct dvb_frontend* vp310_attach(const struct mt312_config* config, | |
615 | struct i2c_adapter* i2c) | |
616 | { | |
617 | struct mt312_state* state = NULL; | |
618 | ||
619 | /* allocate memory for the internal state */ | |
b8742700 | 620 | state = kmalloc(sizeof(struct mt312_state), GFP_KERNEL); |
1da177e4 LT |
621 | if (state == NULL) |
622 | goto error; | |
623 | ||
624 | /* setup the state */ | |
625 | state->config = config; | |
626 | state->i2c = i2c; | |
627 | memcpy(&state->ops, &vp310_mt312_ops, sizeof(struct dvb_frontend_ops)); | |
628 | strcpy(state->ops.info.name, "Zarlink VP310 DVB-S"); | |
629 | ||
630 | /* check if the demod is there */ | |
631 | if (mt312_readreg(state, ID, &state->id) < 0) | |
632 | goto error; | |
633 | if (state->id != ID_VP310) { | |
634 | goto error; | |
635 | } | |
636 | ||
637 | /* create dvb_frontend */ | |
638 | state->frequency = 90; | |
639 | state->frontend.ops = &state->ops; | |
640 | state->frontend.demodulator_priv = state; | |
641 | return &state->frontend; | |
642 | ||
643 | error: | |
644 | kfree(state); | |
645 | return NULL; | |
646 | } | |
647 | ||
648 | struct dvb_frontend* mt312_attach(const struct mt312_config* config, | |
649 | struct i2c_adapter* i2c) | |
650 | { | |
651 | struct mt312_state* state = NULL; | |
652 | ||
653 | /* allocate memory for the internal state */ | |
b8742700 | 654 | state = kmalloc(sizeof(struct mt312_state), GFP_KERNEL); |
1da177e4 LT |
655 | if (state == NULL) |
656 | goto error; | |
657 | ||
658 | /* setup the state */ | |
659 | state->config = config; | |
660 | state->i2c = i2c; | |
661 | memcpy(&state->ops, &vp310_mt312_ops, sizeof(struct dvb_frontend_ops)); | |
662 | strcpy(state->ops.info.name, "Zarlink MT312 DVB-S"); | |
663 | ||
664 | /* check if the demod is there */ | |
665 | if (mt312_readreg(state, ID, &state->id) < 0) | |
666 | goto error; | |
667 | if (state->id != ID_MT312) { | |
668 | goto error; | |
669 | } | |
670 | ||
671 | /* create dvb_frontend */ | |
672 | state->frequency = 60; | |
673 | state->frontend.ops = &state->ops; | |
674 | state->frontend.demodulator_priv = state; | |
675 | return &state->frontend; | |
676 | ||
677 | error: | |
678 | if (state) | |
679 | kfree(state); | |
680 | return NULL; | |
681 | } | |
682 | ||
683 | static struct dvb_frontend_ops vp310_mt312_ops = { | |
684 | ||
685 | .info = { | |
686 | .name = "Zarlink ???? DVB-S", | |
687 | .type = FE_QPSK, | |
688 | .frequency_min = 950000, | |
689 | .frequency_max = 2150000, | |
690 | .frequency_stepsize = (MT312_PLL_CLK / 1000) / 128, | |
691 | .symbol_rate_min = MT312_SYS_CLK / 128, | |
692 | .symbol_rate_max = MT312_SYS_CLK / 2, | |
693 | .caps = | |
694 | FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | | |
695 | FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | | |
696 | FE_CAN_FEC_AUTO | FE_CAN_QPSK | FE_CAN_MUTE_TS | | |
697 | FE_CAN_RECOVER | |
698 | }, | |
699 | ||
700 | .release = mt312_release, | |
701 | ||
702 | .init = mt312_initfe, | |
703 | .sleep = mt312_sleep, | |
704 | ||
705 | .set_frontend = mt312_set_frontend, | |
706 | .get_frontend = mt312_get_frontend, | |
707 | .get_tune_settings = mt312_get_tune_settings, | |
708 | ||
709 | .read_status = mt312_read_status, | |
710 | .read_ber = mt312_read_ber, | |
711 | .read_signal_strength = mt312_read_signal_strength, | |
712 | .read_snr = mt312_read_snr, | |
713 | .read_ucblocks = mt312_read_ucblocks, | |
714 | ||
715 | .diseqc_send_master_cmd = mt312_send_master_cmd, | |
716 | .diseqc_send_burst = mt312_send_burst, | |
717 | .set_tone = mt312_set_tone, | |
718 | .set_voltage = mt312_set_voltage, | |
719 | }; | |
720 | ||
721 | module_param(debug, int, 0644); | |
722 | MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); | |
723 | ||
724 | MODULE_DESCRIPTION("Zarlink VP310/MT312 DVB-S Demodulator driver"); | |
725 | MODULE_AUTHOR("Andreas Oberritter <obi@linuxtv.org>"); | |
726 | MODULE_LICENSE("GPL"); | |
727 | ||
728 | EXPORT_SYMBOL(mt312_attach); | |
729 | EXPORT_SYMBOL(vp310_attach); |