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126f1e61 RM |
1 | /* |
2 | * drxd_firm.h | |
3 | * | |
4 | * Copyright (C) 2006-2007 Micronas | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * version 2 only, as published by the Free Software Foundation. | |
9 | * | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA | |
20 | * 02110-1301, USA | |
21 | * Or, point your browser to http://www.gnu.org/copyleft/gpl.html | |
22 | */ | |
23 | ||
24 | #ifndef _DRXD_FIRM_H_ | |
25 | #define _DRXD_FIRM_H_ | |
26 | ||
27 | #include "drxd_map_firm.h" | |
28 | ||
29 | typedef unsigned char u8_t; | |
30 | typedef unsigned short u16_t; | |
31 | typedef unsigned long u32_t; | |
32 | ||
33 | #define VERSION_MAJOR 1 | |
34 | #define VERSION_MINOR 4 | |
35 | #define VERSION_PATCH 23 | |
36 | ||
37 | #define HI_TR_FUNC_ADDR HI_IF_RAM_USR_BEGIN__A | |
38 | ||
39 | #define DRXD_MAX_RETRIES (1000) | |
40 | #define HI_I2C_DELAY 84 | |
41 | #define HI_I2C_BRIDGE_DELAY 750 | |
42 | ||
6cacdd46 | 43 | #define EQ_TD_TPS_PWR_UNKNOWN 0x00C0 /* Unknown configurations */ |
126f1e61 RM |
44 | #define EQ_TD_TPS_PWR_QPSK 0x016a |
45 | #define EQ_TD_TPS_PWR_QAM16_ALPHAN 0x0195 | |
46 | #define EQ_TD_TPS_PWR_QAM16_ALPHA1 0x0195 | |
47 | #define EQ_TD_TPS_PWR_QAM16_ALPHA2 0x011E | |
48 | #define EQ_TD_TPS_PWR_QAM16_ALPHA4 0x01CE | |
49 | #define EQ_TD_TPS_PWR_QAM64_ALPHAN 0x019F | |
50 | #define EQ_TD_TPS_PWR_QAM64_ALPHA1 0x019F | |
51 | #define EQ_TD_TPS_PWR_QAM64_ALPHA2 0x00F8 | |
52 | #define EQ_TD_TPS_PWR_QAM64_ALPHA4 0x014D | |
53 | ||
54 | #define DRXD_DEF_AG_PWD_CONSUMER 0x000E | |
55 | #define DRXD_DEF_AG_PWD_PRO 0x0000 | |
56 | #define DRXD_DEF_AG_AGC_SIO 0x0000 | |
57 | ||
58 | #define DRXD_FE_CTRL_MAX 1023 | |
59 | ||
60 | #define DRXD_OSCDEV_DO_SCAN (16) | |
61 | ||
62 | #define DRXD_OSCDEV_DONT_SCAN (0) | |
63 | ||
64 | #define DRXD_OSCDEV_STEP (275) | |
65 | ||
66 | #define DRXD_SCAN_TIMEOUT (650) | |
67 | ||
126f1e61 RM |
68 | #define DRXD_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L) |
69 | #define DRXD_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L) | |
70 | #define DRXD_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L) | |
71 | ||
72 | #define IRLEN_COARSE_8K (10) | |
73 | #define IRLEN_FINE_8K (10) | |
74 | #define IRLEN_COARSE_2K (7) | |
75 | #define IRLEN_FINE_2K (9) | |
76 | #define DIFF_INVALID (511) | |
77 | #define DIFF_TARGET (4) | |
78 | #define DIFF_MARGIN (1) | |
79 | ||
126f1e61 RM |
80 | extern u8_t DRXD_InitAtomicRead[]; |
81 | extern u8_t DRXD_HiI2cPatch_1[]; | |
82 | extern u8_t DRXD_HiI2cPatch_3[]; | |
83 | ||
84 | extern u8_t DRXD_InitSC[]; | |
85 | ||
86 | extern u8_t DRXD_ResetCEFR[]; | |
87 | extern u8_t DRXD_InitFEA2_1[]; | |
88 | extern u8_t DRXD_InitFEA2_2[]; | |
89 | extern u8_t DRXD_InitCPA2[]; | |
90 | extern u8_t DRXD_InitCEA2[]; | |
91 | extern u8_t DRXD_InitEQA2[]; | |
92 | extern u8_t DRXD_InitECA2[]; | |
93 | extern u8_t DRXD_ResetECA2[]; | |
94 | extern u8_t DRXD_ResetECRAM[]; | |
95 | ||
6cacdd46 | 96 | extern u8_t DRXD_A2_microcode[]; |
126f1e61 RM |
97 | extern u32_t DRXD_A2_microcode_length; |
98 | ||
99 | extern u8_t DRXD_InitFEB1_1[]; | |
100 | extern u8_t DRXD_InitFEB1_2[]; | |
101 | extern u8_t DRXD_InitCPB1[]; | |
102 | extern u8_t DRXD_InitCEB1[]; | |
103 | extern u8_t DRXD_InitEQB1[]; | |
104 | extern u8_t DRXD_InitECB1[]; | |
105 | ||
106 | extern u8_t DRXD_InitDiversityFront[]; | |
107 | extern u8_t DRXD_InitDiversityEnd[]; | |
108 | extern u8_t DRXD_DisableDiversity[]; | |
109 | extern u8_t DRXD_StartDiversityFront[]; | |
110 | extern u8_t DRXD_StartDiversityEnd[]; | |
111 | ||
112 | extern u8_t DRXD_DiversityDelay8MHZ[]; | |
113 | extern u8_t DRXD_DiversityDelay6MHZ[]; | |
114 | ||
6cacdd46 | 115 | extern u8_t DRXD_B1_microcode[]; |
126f1e61 RM |
116 | extern u32_t DRXD_B1_microcode_length; |
117 | ||
118 | #endif |