Commit | Line | Data |
---|---|---|
a611d0ca IL |
1 | /* |
2 | * dm1105.c - driver for DVB cards based on SDMC DM1105 PCI chip | |
3 | * | |
4 | * Copyright (C) 2008 Igor M. Liplianin <liplianin@me.by> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
19 | * | |
20 | */ | |
21 | ||
a611d0ca | 22 | #include <linux/i2c.h> |
0017505d | 23 | #include <linux/i2c-algo-bit.h> |
a611d0ca IL |
24 | #include <linux/init.h> |
25 | #include <linux/kernel.h> | |
26 | #include <linux/module.h> | |
27 | #include <linux/proc_fs.h> | |
28 | #include <linux/pci.h> | |
29 | #include <linux/dma-mapping.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
6bda9644 | 31 | #include <media/rc-core.h> |
a611d0ca IL |
32 | |
33 | #include "demux.h" | |
34 | #include "dmxdev.h" | |
35 | #include "dvb_demux.h" | |
36 | #include "dvb_frontend.h" | |
37 | #include "dvb_net.h" | |
38 | #include "dvbdev.h" | |
39 | #include "dvb-pll.h" | |
40 | ||
41 | #include "stv0299.h" | |
e4aab64c IL |
42 | #include "stv0288.h" |
43 | #include "stb6000.h" | |
04ad28c9 | 44 | #include "si21xx.h" |
35d9c427 | 45 | #include "cx24116.h" |
a611d0ca | 46 | #include "z0194a.h" |
b4a0e816 | 47 | #include "ds3000.h" |
a611d0ca | 48 | |
727e625c MCC |
49 | #define MODULE_NAME "dm1105" |
50 | ||
d8300df9 IL |
51 | #define UNSET (-1U) |
52 | ||
0017505d IL |
53 | #define DM1105_BOARD_NOAUTO UNSET |
54 | #define DM1105_BOARD_UNKNOWN 0 | |
55 | #define DM1105_BOARD_DVBWORLD_2002 1 | |
56 | #define DM1105_BOARD_DVBWORLD_2004 2 | |
57 | #define DM1105_BOARD_AXESS_DM05 3 | |
58 | #define DM1105_BOARD_UNBRANDED_I2C_ON_GPIO 4 | |
d8300df9 | 59 | |
a611d0ca IL |
60 | /* ----------------------------------------------- */ |
61 | /* | |
62 | * PCI ID's | |
63 | */ | |
64 | #ifndef PCI_VENDOR_ID_TRIGEM | |
65 | #define PCI_VENDOR_ID_TRIGEM 0x109f | |
66 | #endif | |
519a4bdc IL |
67 | #ifndef PCI_VENDOR_ID_AXESS |
68 | #define PCI_VENDOR_ID_AXESS 0x195d | |
69 | #endif | |
a611d0ca IL |
70 | #ifndef PCI_DEVICE_ID_DM1105 |
71 | #define PCI_DEVICE_ID_DM1105 0x036f | |
72 | #endif | |
73 | #ifndef PCI_DEVICE_ID_DW2002 | |
74 | #define PCI_DEVICE_ID_DW2002 0x2002 | |
75 | #endif | |
76 | #ifndef PCI_DEVICE_ID_DW2004 | |
77 | #define PCI_DEVICE_ID_DW2004 0x2004 | |
78 | #endif | |
519a4bdc IL |
79 | #ifndef PCI_DEVICE_ID_DM05 |
80 | #define PCI_DEVICE_ID_DM05 0x1105 | |
81 | #endif | |
a611d0ca IL |
82 | /* ----------------------------------------------- */ |
83 | /* sdmc dm1105 registers */ | |
84 | ||
85 | /* TS Control */ | |
86 | #define DM1105_TSCTR 0x00 | |
87 | #define DM1105_DTALENTH 0x04 | |
88 | ||
89 | /* GPIO Interface */ | |
90 | #define DM1105_GPIOVAL 0x08 | |
91 | #define DM1105_GPIOCTR 0x0c | |
92 | ||
93 | /* PID serial number */ | |
94 | #define DM1105_PIDN 0x10 | |
95 | ||
96 | /* Odd-even secret key select */ | |
97 | #define DM1105_CWSEL 0x14 | |
98 | ||
99 | /* Host Command Interface */ | |
100 | #define DM1105_HOST_CTR 0x18 | |
101 | #define DM1105_HOST_AD 0x1c | |
102 | ||
103 | /* PCI Interface */ | |
104 | #define DM1105_CR 0x30 | |
105 | #define DM1105_RST 0x34 | |
106 | #define DM1105_STADR 0x38 | |
107 | #define DM1105_RLEN 0x3c | |
108 | #define DM1105_WRP 0x40 | |
109 | #define DM1105_INTCNT 0x44 | |
110 | #define DM1105_INTMAK 0x48 | |
111 | #define DM1105_INTSTS 0x4c | |
112 | ||
113 | /* CW Value */ | |
114 | #define DM1105_ODD 0x50 | |
115 | #define DM1105_EVEN 0x58 | |
116 | ||
117 | /* PID Value */ | |
118 | #define DM1105_PID 0x60 | |
119 | ||
120 | /* IR Control */ | |
121 | #define DM1105_IRCTR 0x64 | |
122 | #define DM1105_IRMODE 0x68 | |
123 | #define DM1105_SYSTEMCODE 0x6c | |
124 | #define DM1105_IRCODE 0x70 | |
125 | ||
126 | /* Unknown Values */ | |
127 | #define DM1105_ENCRYPT 0x74 | |
128 | #define DM1105_VER 0x7c | |
129 | ||
130 | /* I2C Interface */ | |
131 | #define DM1105_I2CCTR 0x80 | |
132 | #define DM1105_I2CSTS 0x81 | |
133 | #define DM1105_I2CDAT 0x82 | |
134 | #define DM1105_I2C_RA 0x83 | |
135 | /* ----------------------------------------------- */ | |
136 | /* Interrupt Mask Bits */ | |
137 | ||
138 | #define INTMAK_TSIRQM 0x01 | |
139 | #define INTMAK_HIRQM 0x04 | |
140 | #define INTMAK_IRM 0x08 | |
141 | #define INTMAK_ALLMASK (INTMAK_TSIRQM | \ | |
142 | INTMAK_HIRQM | \ | |
143 | INTMAK_IRM) | |
144 | #define INTMAK_NONEMASK 0x00 | |
145 | ||
146 | /* Interrupt Status Bits */ | |
147 | #define INTSTS_TSIRQ 0x01 | |
148 | #define INTSTS_HIRQ 0x04 | |
149 | #define INTSTS_IR 0x08 | |
150 | ||
151 | /* IR Control Bits */ | |
152 | #define DM1105_IR_EN 0x01 | |
153 | #define DM1105_SYS_CHK 0x02 | |
154 | #define DM1105_REP_FLG 0x08 | |
155 | ||
156 | /* EEPROM addr */ | |
157 | #define IIC_24C01_addr 0xa0 | |
158 | /* Max board count */ | |
159 | #define DM1105_MAX 0x04 | |
160 | ||
161 | #define DRIVER_NAME "dm1105" | |
0017505d | 162 | #define DM1105_I2C_GPIO_NAME "dm1105-gpio" |
a611d0ca IL |
163 | |
164 | #define DM1105_DMA_PACKETS 47 | |
165 | #define DM1105_DMA_PACKET_LENGTH (128*4) | |
166 | #define DM1105_DMA_BYTES (128 * 4 * DM1105_DMA_PACKETS) | |
167 | ||
0017505d IL |
168 | /* */ |
169 | #define GPIO08 (1 << 8) | |
170 | #define GPIO13 (1 << 13) | |
171 | #define GPIO14 (1 << 14) | |
172 | #define GPIO15 (1 << 15) | |
173 | #define GPIO16 (1 << 16) | |
174 | #define GPIO17 (1 << 17) | |
175 | #define GPIO_ALL 0x03ffff | |
176 | ||
a611d0ca | 177 | /* GPIO's for LNB power control */ |
0017505d IL |
178 | #define DM1105_LNB_MASK (GPIO_ALL & ~(GPIO14 | GPIO13)) |
179 | #define DM1105_LNB_OFF GPIO17 | |
180 | #define DM1105_LNB_13V (GPIO16 | GPIO08) | |
181 | #define DM1105_LNB_18V GPIO08 | |
a611d0ca | 182 | |
519a4bdc | 183 | /* GPIO's for LNB power control for Axess DM05 */ |
0017505d IL |
184 | #define DM05_LNB_MASK (GPIO_ALL & ~(GPIO14 | GPIO13)) |
185 | #define DM05_LNB_OFF GPIO17/* actually 13v */ | |
186 | #define DM05_LNB_13V GPIO17 | |
187 | #define DM05_LNB_18V (GPIO17 | GPIO16) | |
188 | ||
189 | /* GPIO's for LNB power control for unbranded with I2C on GPIO */ | |
190 | #define UNBR_LNB_MASK (GPIO17 | GPIO16) | |
191 | #define UNBR_LNB_OFF 0 | |
192 | #define UNBR_LNB_13V GPIO17 | |
193 | #define UNBR_LNB_18V (GPIO17 | GPIO16) | |
519a4bdc | 194 | |
d8300df9 IL |
195 | static unsigned int card[] = {[0 ... 3] = UNSET }; |
196 | module_param_array(card, int, NULL, 0444); | |
197 | MODULE_PARM_DESC(card, "card type"); | |
198 | ||
a611d0ca IL |
199 | static int ir_debug; |
200 | module_param(ir_debug, int, 0644); | |
201 | MODULE_PARM_DESC(ir_debug, "enable debugging information for IR decoding"); | |
202 | ||
d8300df9 IL |
203 | static unsigned int dm1105_devcount; |
204 | ||
a611d0ca IL |
205 | DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); |
206 | ||
d8300df9 | 207 | struct dm1105_board { |
0017505d IL |
208 | char *name; |
209 | struct { | |
210 | u32 mask, off, v13, v18; | |
211 | } lnb; | |
212 | u32 gpio_scl, gpio_sda; | |
d8300df9 IL |
213 | }; |
214 | ||
215 | struct dm1105_subid { | |
216 | u16 subvendor; | |
217 | u16 subdevice; | |
218 | u32 card; | |
219 | }; | |
220 | ||
221 | static const struct dm1105_board dm1105_boards[] = { | |
222 | [DM1105_BOARD_UNKNOWN] = { | |
223 | .name = "UNKNOWN/GENERIC", | |
0017505d IL |
224 | .lnb = { |
225 | .mask = DM1105_LNB_MASK, | |
226 | .off = DM1105_LNB_OFF, | |
227 | .v13 = DM1105_LNB_13V, | |
228 | .v18 = DM1105_LNB_18V, | |
229 | }, | |
d8300df9 IL |
230 | }, |
231 | [DM1105_BOARD_DVBWORLD_2002] = { | |
232 | .name = "DVBWorld PCI 2002", | |
0017505d IL |
233 | .lnb = { |
234 | .mask = DM1105_LNB_MASK, | |
235 | .off = DM1105_LNB_OFF, | |
236 | .v13 = DM1105_LNB_13V, | |
237 | .v18 = DM1105_LNB_18V, | |
238 | }, | |
d8300df9 IL |
239 | }, |
240 | [DM1105_BOARD_DVBWORLD_2004] = { | |
241 | .name = "DVBWorld PCI 2004", | |
0017505d IL |
242 | .lnb = { |
243 | .mask = DM1105_LNB_MASK, | |
244 | .off = DM1105_LNB_OFF, | |
245 | .v13 = DM1105_LNB_13V, | |
246 | .v18 = DM1105_LNB_18V, | |
247 | }, | |
d8300df9 IL |
248 | }, |
249 | [DM1105_BOARD_AXESS_DM05] = { | |
250 | .name = "Axess/EasyTv DM05", | |
0017505d IL |
251 | .lnb = { |
252 | .mask = DM05_LNB_MASK, | |
253 | .off = DM05_LNB_OFF, | |
254 | .v13 = DM05_LNB_13V, | |
255 | .v18 = DM05_LNB_18V, | |
256 | }, | |
257 | }, | |
258 | [DM1105_BOARD_UNBRANDED_I2C_ON_GPIO] = { | |
259 | .name = "Unbranded DM1105 with i2c on GPIOs", | |
260 | .lnb = { | |
261 | .mask = UNBR_LNB_MASK, | |
262 | .off = UNBR_LNB_OFF, | |
263 | .v13 = UNBR_LNB_13V, | |
264 | .v18 = UNBR_LNB_18V, | |
265 | }, | |
266 | .gpio_scl = GPIO14, | |
267 | .gpio_sda = GPIO13, | |
d8300df9 IL |
268 | }, |
269 | }; | |
270 | ||
271 | static const struct dm1105_subid dm1105_subids[] = { | |
272 | { | |
273 | .subvendor = 0x0000, | |
274 | .subdevice = 0x2002, | |
275 | .card = DM1105_BOARD_DVBWORLD_2002, | |
276 | }, { | |
277 | .subvendor = 0x0001, | |
278 | .subdevice = 0x2002, | |
279 | .card = DM1105_BOARD_DVBWORLD_2002, | |
280 | }, { | |
281 | .subvendor = 0x0000, | |
282 | .subdevice = 0x2004, | |
283 | .card = DM1105_BOARD_DVBWORLD_2004, | |
284 | }, { | |
285 | .subvendor = 0x0001, | |
286 | .subdevice = 0x2004, | |
287 | .card = DM1105_BOARD_DVBWORLD_2004, | |
288 | }, { | |
289 | .subvendor = 0x195d, | |
290 | .subdevice = 0x1105, | |
291 | .card = DM1105_BOARD_AXESS_DM05, | |
292 | }, | |
293 | }; | |
294 | ||
295 | static void dm1105_card_list(struct pci_dev *pci) | |
296 | { | |
297 | int i; | |
298 | ||
299 | if (0 == pci->subsystem_vendor && | |
300 | 0 == pci->subsystem_device) { | |
301 | printk(KERN_ERR | |
302 | "dm1105: Your board has no valid PCI Subsystem ID\n" | |
303 | "dm1105: and thus can't be autodetected\n" | |
304 | "dm1105: Please pass card=<n> insmod option to\n" | |
305 | "dm1105: workaround that. Redirect complaints to\n" | |
306 | "dm1105: the vendor of the TV card. Best regards,\n" | |
307 | "dm1105: -- tux\n"); | |
308 | } else { | |
309 | printk(KERN_ERR | |
310 | "dm1105: Your board isn't known (yet) to the driver.\n" | |
311 | "dm1105: You can try to pick one of the existing\n" | |
312 | "dm1105: card configs via card=<n> insmod option.\n" | |
313 | "dm1105: Updating to the latest version might help\n" | |
314 | "dm1105: as well.\n"); | |
315 | } | |
316 | printk(KERN_ERR "Here is a list of valid choices for the card=<n> " | |
317 | "insmod option:\n"); | |
318 | for (i = 0; i < ARRAY_SIZE(dm1105_boards); i++) | |
319 | printk(KERN_ERR "dm1105: card=%d -> %s\n", | |
320 | i, dm1105_boards[i].name); | |
321 | } | |
322 | ||
a611d0ca IL |
323 | /* infrared remote control */ |
324 | struct infrared { | |
d8b4b582 | 325 | struct rc_dev *dev; |
a611d0ca | 326 | char input_phys[32]; |
b72857dd | 327 | struct work_struct work; |
a611d0ca IL |
328 | u32 ir_command; |
329 | }; | |
330 | ||
34d2f9bf | 331 | struct dm1105_dev { |
a611d0ca IL |
332 | /* pci */ |
333 | struct pci_dev *pdev; | |
334 | u8 __iomem *io_mem; | |
335 | ||
336 | /* ir */ | |
337 | struct infrared ir; | |
338 | ||
339 | /* dvb */ | |
340 | struct dmx_frontend hw_frontend; | |
341 | struct dmx_frontend mem_frontend; | |
342 | struct dmxdev dmxdev; | |
343 | struct dvb_adapter dvb_adapter; | |
344 | struct dvb_demux demux; | |
345 | struct dvb_frontend *fe; | |
346 | struct dvb_net dvbnet; | |
347 | unsigned int full_ts_users; | |
d8300df9 IL |
348 | unsigned int boardnr; |
349 | int nr; | |
a611d0ca IL |
350 | |
351 | /* i2c */ | |
352 | struct i2c_adapter i2c_adap; | |
0017505d IL |
353 | struct i2c_adapter i2c_bb_adap; |
354 | struct i2c_algo_bit_data i2c_bit; | |
a611d0ca | 355 | |
d1498ffc IL |
356 | /* irq */ |
357 | struct work_struct work; | |
519a4bdc IL |
358 | struct workqueue_struct *wq; |
359 | char wqn[16]; | |
d1498ffc | 360 | |
a611d0ca IL |
361 | /* dma */ |
362 | dma_addr_t dma_addr; | |
363 | unsigned char *ts_buf; | |
364 | u32 wrp; | |
d1498ffc | 365 | u32 nextwrp; |
a611d0ca IL |
366 | u32 buffer_size; |
367 | unsigned int PacketErrorCount; | |
368 | unsigned int dmarst; | |
369 | spinlock_t lock; | |
a611d0ca IL |
370 | }; |
371 | ||
34d2f9bf | 372 | #define dm_io_mem(reg) ((unsigned long)(&dev->io_mem[reg])) |
a611d0ca | 373 | |
5eb3291f IL |
374 | #define dm_readb(reg) inb(dm_io_mem(reg)) |
375 | #define dm_writeb(reg, value) outb((value), (dm_io_mem(reg))) | |
376 | ||
377 | #define dm_readw(reg) inw(dm_io_mem(reg)) | |
378 | #define dm_writew(reg, value) outw((value), (dm_io_mem(reg))) | |
379 | ||
380 | #define dm_readl(reg) inl(dm_io_mem(reg)) | |
381 | #define dm_writel(reg, value) outl((value), (dm_io_mem(reg))) | |
382 | ||
383 | #define dm_andorl(reg, mask, value) \ | |
384 | outl((inl(dm_io_mem(reg)) & ~(mask)) |\ | |
385 | ((value) & (mask)), (dm_io_mem(reg))) | |
386 | ||
387 | #define dm_setl(reg, bit) dm_andorl((reg), (bit), (bit)) | |
388 | #define dm_clearl(reg, bit) dm_andorl((reg), (bit), 0) | |
389 | ||
0017505d IL |
390 | /* The chip has 18 GPIOs. In HOST mode GPIO's used as 15 bit address lines, |
391 | so we can use only 3 GPIO's from GPIO15 to GPIO17. | |
392 | Here I don't check whether HOST is enebled as it is not implemented yet. | |
393 | */ | |
394 | static void dm1105_gpio_set(struct dm1105_dev *dev, u32 mask) | |
395 | { | |
396 | if (mask & 0xfffc0000) | |
397 | printk(KERN_ERR "%s: Only 18 GPIO's are allowed\n", __func__); | |
398 | ||
399 | if (mask & 0x0003ffff) | |
400 | dm_setl(DM1105_GPIOVAL, mask & 0x0003ffff); | |
401 | ||
402 | } | |
403 | ||
404 | static void dm1105_gpio_clear(struct dm1105_dev *dev, u32 mask) | |
405 | { | |
406 | if (mask & 0xfffc0000) | |
407 | printk(KERN_ERR "%s: Only 18 GPIO's are allowed\n", __func__); | |
408 | ||
409 | if (mask & 0x0003ffff) | |
410 | dm_clearl(DM1105_GPIOVAL, mask & 0x0003ffff); | |
411 | ||
412 | } | |
413 | ||
414 | static void dm1105_gpio_andor(struct dm1105_dev *dev, u32 mask, u32 val) | |
415 | { | |
416 | if (mask & 0xfffc0000) | |
417 | printk(KERN_ERR "%s: Only 18 GPIO's are allowed\n", __func__); | |
418 | ||
419 | if (mask & 0x0003ffff) | |
420 | dm_andorl(DM1105_GPIOVAL, mask & 0x0003ffff, val); | |
421 | ||
422 | } | |
423 | ||
424 | static u32 dm1105_gpio_get(struct dm1105_dev *dev, u32 mask) | |
425 | { | |
426 | if (mask & 0xfffc0000) | |
427 | printk(KERN_ERR "%s: Only 18 GPIO's are allowed\n", __func__); | |
428 | ||
429 | if (mask & 0x0003ffff) | |
430 | return dm_readl(DM1105_GPIOVAL) & mask & 0x0003ffff; | |
431 | ||
432 | return 0; | |
433 | } | |
434 | ||
435 | static void dm1105_gpio_enable(struct dm1105_dev *dev, u32 mask, int asoutput) | |
436 | { | |
437 | if (mask & 0xfffc0000) | |
438 | printk(KERN_ERR "%s: Only 18 GPIO's are allowed\n", __func__); | |
439 | ||
440 | if ((mask & 0x0003ffff) && asoutput) | |
441 | dm_clearl(DM1105_GPIOCTR, mask & 0x0003ffff); | |
442 | else if ((mask & 0x0003ffff) && !asoutput) | |
443 | dm_setl(DM1105_GPIOCTR, mask & 0x0003ffff); | |
444 | ||
445 | } | |
446 | ||
447 | static void dm1105_setline(struct dm1105_dev *dev, u32 line, int state) | |
448 | { | |
449 | if (state) | |
450 | dm1105_gpio_enable(dev, line, 0); | |
451 | else { | |
452 | dm1105_gpio_enable(dev, line, 1); | |
453 | dm1105_gpio_clear(dev, line); | |
454 | } | |
455 | } | |
456 | ||
457 | static void dm1105_setsda(void *data, int state) | |
458 | { | |
459 | struct dm1105_dev *dev = data; | |
460 | ||
461 | dm1105_setline(dev, dm1105_boards[dev->boardnr].gpio_sda, state); | |
462 | } | |
463 | ||
464 | static void dm1105_setscl(void *data, int state) | |
465 | { | |
466 | struct dm1105_dev *dev = data; | |
467 | ||
468 | dm1105_setline(dev, dm1105_boards[dev->boardnr].gpio_scl, state); | |
469 | } | |
470 | ||
471 | static int dm1105_getsda(void *data) | |
472 | { | |
473 | struct dm1105_dev *dev = data; | |
474 | ||
475 | return dm1105_gpio_get(dev, dm1105_boards[dev->boardnr].gpio_sda) | |
476 | ? 1 : 0; | |
477 | } | |
478 | ||
479 | static int dm1105_getscl(void *data) | |
480 | { | |
481 | struct dm1105_dev *dev = data; | |
482 | ||
483 | return dm1105_gpio_get(dev, dm1105_boards[dev->boardnr].gpio_scl) | |
484 | ? 1 : 0; | |
485 | } | |
486 | ||
a611d0ca IL |
487 | static int dm1105_i2c_xfer(struct i2c_adapter *i2c_adap, |
488 | struct i2c_msg *msgs, int num) | |
489 | { | |
34d2f9bf | 490 | struct dm1105_dev *dev ; |
a611d0ca IL |
491 | |
492 | int addr, rc, i, j, k, len, byte, data; | |
493 | u8 status; | |
494 | ||
34d2f9bf | 495 | dev = i2c_adap->algo_data; |
a611d0ca | 496 | for (i = 0; i < num; i++) { |
5eb3291f | 497 | dm_writeb(DM1105_I2CCTR, 0x00); |
a611d0ca IL |
498 | if (msgs[i].flags & I2C_M_RD) { |
499 | /* read bytes */ | |
500 | addr = msgs[i].addr << 1; | |
501 | addr |= 1; | |
5eb3291f | 502 | dm_writeb(DM1105_I2CDAT, addr); |
a611d0ca | 503 | for (byte = 0; byte < msgs[i].len; byte++) |
5eb3291f | 504 | dm_writeb(DM1105_I2CDAT + byte + 1, 0); |
a611d0ca | 505 | |
5eb3291f | 506 | dm_writeb(DM1105_I2CCTR, 0x81 + msgs[i].len); |
a611d0ca IL |
507 | for (j = 0; j < 55; j++) { |
508 | mdelay(10); | |
5eb3291f | 509 | status = dm_readb(DM1105_I2CSTS); |
a611d0ca IL |
510 | if ((status & 0xc0) == 0x40) |
511 | break; | |
512 | } | |
513 | if (j >= 55) | |
514 | return -1; | |
515 | ||
516 | for (byte = 0; byte < msgs[i].len; byte++) { | |
5eb3291f | 517 | rc = dm_readb(DM1105_I2CDAT + byte + 1); |
a611d0ca IL |
518 | if (rc < 0) |
519 | goto err; | |
520 | msgs[i].buf[byte] = rc; | |
521 | } | |
ed7c847a IL |
522 | } else if ((msgs[i].buf[0] == 0xf7) && (msgs[i].addr == 0x55)) { |
523 | /* prepaired for cx24116 firmware */ | |
524 | /* Write in small blocks */ | |
525 | len = msgs[i].len - 1; | |
526 | k = 1; | |
527 | do { | |
5eb3291f IL |
528 | dm_writeb(DM1105_I2CDAT, msgs[i].addr << 1); |
529 | dm_writeb(DM1105_I2CDAT + 1, 0xf7); | |
ed7c847a IL |
530 | for (byte = 0; byte < (len > 48 ? 48 : len); byte++) { |
531 | data = msgs[i].buf[k + byte]; | |
5eb3291f | 532 | dm_writeb(DM1105_I2CDAT + byte + 2, data); |
a611d0ca | 533 | } |
5eb3291f | 534 | dm_writeb(DM1105_I2CCTR, 0x82 + (len > 48 ? 48 : len)); |
a611d0ca IL |
535 | for (j = 0; j < 25; j++) { |
536 | mdelay(10); | |
5eb3291f | 537 | status = dm_readb(DM1105_I2CSTS); |
a611d0ca IL |
538 | if ((status & 0xc0) == 0x40) |
539 | break; | |
540 | } | |
541 | ||
542 | if (j >= 25) | |
543 | return -1; | |
ed7c847a IL |
544 | |
545 | k += 48; | |
546 | len -= 48; | |
547 | } while (len > 0); | |
548 | } else { | |
549 | /* write bytes */ | |
5eb3291f | 550 | dm_writeb(DM1105_I2CDAT, msgs[i].addr << 1); |
ed7c847a IL |
551 | for (byte = 0; byte < msgs[i].len; byte++) { |
552 | data = msgs[i].buf[byte]; | |
5eb3291f | 553 | dm_writeb(DM1105_I2CDAT + byte + 1, data); |
ed7c847a | 554 | } |
5eb3291f | 555 | dm_writeb(DM1105_I2CCTR, 0x81 + msgs[i].len); |
ed7c847a IL |
556 | for (j = 0; j < 25; j++) { |
557 | mdelay(10); | |
5eb3291f | 558 | status = dm_readb(DM1105_I2CSTS); |
ed7c847a IL |
559 | if ((status & 0xc0) == 0x40) |
560 | break; | |
a611d0ca | 561 | } |
ed7c847a IL |
562 | |
563 | if (j >= 25) | |
564 | return -1; | |
a611d0ca IL |
565 | } |
566 | } | |
567 | return num; | |
568 | err: | |
569 | return rc; | |
570 | } | |
571 | ||
572 | static u32 functionality(struct i2c_adapter *adap) | |
573 | { | |
574 | return I2C_FUNC_I2C; | |
575 | } | |
576 | ||
577 | static struct i2c_algorithm dm1105_algo = { | |
578 | .master_xfer = dm1105_i2c_xfer, | |
579 | .functionality = functionality, | |
580 | }; | |
581 | ||
34d2f9bf | 582 | static inline struct dm1105_dev *feed_to_dm1105_dev(struct dvb_demux_feed *feed) |
a611d0ca | 583 | { |
34d2f9bf | 584 | return container_of(feed->demux, struct dm1105_dev, demux); |
a611d0ca IL |
585 | } |
586 | ||
34d2f9bf | 587 | static inline struct dm1105_dev *frontend_to_dm1105_dev(struct dvb_frontend *fe) |
a611d0ca | 588 | { |
34d2f9bf | 589 | return container_of(fe->dvb, struct dm1105_dev, dvb_adapter); |
a611d0ca IL |
590 | } |
591 | ||
34d2f9bf | 592 | static int dm1105_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage) |
a611d0ca | 593 | { |
34d2f9bf | 594 | struct dm1105_dev *dev = frontend_to_dm1105_dev(fe); |
a611d0ca | 595 | |
0017505d | 596 | dm1105_gpio_enable(dev, dm1105_boards[dev->boardnr].lnb.mask, 1); |
519a4bdc | 597 | if (voltage == SEC_VOLTAGE_18) |
0017505d IL |
598 | dm1105_gpio_andor(dev, |
599 | dm1105_boards[dev->boardnr].lnb.mask, | |
600 | dm1105_boards[dev->boardnr].lnb.v18); | |
d8300df9 | 601 | else if (voltage == SEC_VOLTAGE_13) |
0017505d IL |
602 | dm1105_gpio_andor(dev, |
603 | dm1105_boards[dev->boardnr].lnb.mask, | |
604 | dm1105_boards[dev->boardnr].lnb.v13); | |
d8300df9 | 605 | else |
0017505d IL |
606 | dm1105_gpio_andor(dev, |
607 | dm1105_boards[dev->boardnr].lnb.mask, | |
608 | dm1105_boards[dev->boardnr].lnb.off); | |
a611d0ca IL |
609 | |
610 | return 0; | |
611 | } | |
612 | ||
34d2f9bf | 613 | static void dm1105_set_dma_addr(struct dm1105_dev *dev) |
a611d0ca | 614 | { |
5eb3291f | 615 | dm_writel(DM1105_STADR, cpu_to_le32(dev->dma_addr)); |
a611d0ca IL |
616 | } |
617 | ||
34d2f9bf | 618 | static int __devinit dm1105_dma_map(struct dm1105_dev *dev) |
a611d0ca | 619 | { |
34d2f9bf IL |
620 | dev->ts_buf = pci_alloc_consistent(dev->pdev, |
621 | 6 * DM1105_DMA_BYTES, | |
622 | &dev->dma_addr); | |
a611d0ca | 623 | |
34d2f9bf | 624 | return !dev->ts_buf; |
a611d0ca IL |
625 | } |
626 | ||
34d2f9bf | 627 | static void dm1105_dma_unmap(struct dm1105_dev *dev) |
a611d0ca | 628 | { |
34d2f9bf IL |
629 | pci_free_consistent(dev->pdev, |
630 | 6 * DM1105_DMA_BYTES, | |
631 | dev->ts_buf, | |
632 | dev->dma_addr); | |
a611d0ca IL |
633 | } |
634 | ||
34d2f9bf | 635 | static void dm1105_enable_irqs(struct dm1105_dev *dev) |
a611d0ca | 636 | { |
5eb3291f IL |
637 | dm_writeb(DM1105_INTMAK, INTMAK_ALLMASK); |
638 | dm_writeb(DM1105_CR, 1); | |
a611d0ca IL |
639 | } |
640 | ||
34d2f9bf | 641 | static void dm1105_disable_irqs(struct dm1105_dev *dev) |
a611d0ca | 642 | { |
5eb3291f IL |
643 | dm_writeb(DM1105_INTMAK, INTMAK_IRM); |
644 | dm_writeb(DM1105_CR, 0); | |
a611d0ca IL |
645 | } |
646 | ||
34d2f9bf | 647 | static int dm1105_start_feed(struct dvb_demux_feed *f) |
a611d0ca | 648 | { |
34d2f9bf | 649 | struct dm1105_dev *dev = feed_to_dm1105_dev(f); |
a611d0ca | 650 | |
34d2f9bf IL |
651 | if (dev->full_ts_users++ == 0) |
652 | dm1105_enable_irqs(dev); | |
a611d0ca IL |
653 | |
654 | return 0; | |
655 | } | |
656 | ||
34d2f9bf | 657 | static int dm1105_stop_feed(struct dvb_demux_feed *f) |
a611d0ca | 658 | { |
34d2f9bf | 659 | struct dm1105_dev *dev = feed_to_dm1105_dev(f); |
a611d0ca | 660 | |
34d2f9bf IL |
661 | if (--dev->full_ts_users == 0) |
662 | dm1105_disable_irqs(dev); | |
a611d0ca IL |
663 | |
664 | return 0; | |
665 | } | |
666 | ||
b72857dd IL |
667 | /* ir work handler */ |
668 | static void dm1105_emit_key(struct work_struct *work) | |
a611d0ca | 669 | { |
b72857dd | 670 | struct infrared *ir = container_of(work, struct infrared, work); |
a611d0ca IL |
671 | u32 ircom = ir->ir_command; |
672 | u8 data; | |
a611d0ca | 673 | |
d1498ffc IL |
674 | if (ir_debug) |
675 | printk(KERN_INFO "%s: received byte 0x%04x\n", __func__, ircom); | |
676 | ||
a611d0ca IL |
677 | data = (ircom >> 8) & 0x7f; |
678 | ||
ca86674b | 679 | rc_keydown(ir->dev, data, 0); |
a611d0ca IL |
680 | } |
681 | ||
d1498ffc IL |
682 | /* work handler */ |
683 | static void dm1105_dmx_buffer(struct work_struct *work) | |
684 | { | |
34d2f9bf | 685 | struct dm1105_dev *dev = container_of(work, struct dm1105_dev, work); |
d1498ffc | 686 | unsigned int nbpackets; |
34d2f9bf IL |
687 | u32 oldwrp = dev->wrp; |
688 | u32 nextwrp = dev->nextwrp; | |
d1498ffc | 689 | |
34d2f9bf IL |
690 | if (!((dev->ts_buf[oldwrp] == 0x47) && |
691 | (dev->ts_buf[oldwrp + 188] == 0x47) && | |
692 | (dev->ts_buf[oldwrp + 188 * 2] == 0x47))) { | |
693 | dev->PacketErrorCount++; | |
d1498ffc | 694 | /* bad packet found */ |
34d2f9bf IL |
695 | if ((dev->PacketErrorCount >= 2) && |
696 | (dev->dmarst == 0)) { | |
5eb3291f | 697 | dm_writeb(DM1105_RST, 1); |
34d2f9bf IL |
698 | dev->wrp = 0; |
699 | dev->PacketErrorCount = 0; | |
700 | dev->dmarst = 0; | |
d1498ffc IL |
701 | return; |
702 | } | |
703 | } | |
704 | ||
705 | if (nextwrp < oldwrp) { | |
34d2f9bf IL |
706 | memcpy(dev->ts_buf + dev->buffer_size, dev->ts_buf, nextwrp); |
707 | nbpackets = ((dev->buffer_size - oldwrp) + nextwrp) / 188; | |
d1498ffc IL |
708 | } else |
709 | nbpackets = (nextwrp - oldwrp) / 188; | |
710 | ||
34d2f9bf IL |
711 | dev->wrp = nextwrp; |
712 | dvb_dmx_swfilter_packets(&dev->demux, &dev->ts_buf[oldwrp], nbpackets); | |
d1498ffc IL |
713 | } |
714 | ||
34d2f9bf | 715 | static irqreturn_t dm1105_irq(int irq, void *dev_id) |
a611d0ca | 716 | { |
34d2f9bf | 717 | struct dm1105_dev *dev = dev_id; |
a611d0ca IL |
718 | |
719 | /* Read-Write INSTS Ack's Interrupt for DM1105 chip 16.03.2008 */ | |
5eb3291f IL |
720 | unsigned int intsts = dm_readb(DM1105_INTSTS); |
721 | dm_writeb(DM1105_INTSTS, intsts); | |
a611d0ca IL |
722 | |
723 | switch (intsts) { | |
724 | case INTSTS_TSIRQ: | |
725 | case (INTSTS_TSIRQ | INTSTS_IR): | |
5eb3291f | 726 | dev->nextwrp = dm_readl(DM1105_WRP) - dm_readl(DM1105_STADR); |
34d2f9bf | 727 | queue_work(dev->wq, &dev->work); |
a611d0ca IL |
728 | break; |
729 | case INTSTS_IR: | |
5eb3291f | 730 | dev->ir.ir_command = dm_readl(DM1105_IRCODE); |
34d2f9bf | 731 | schedule_work(&dev->ir.work); |
a611d0ca IL |
732 | break; |
733 | } | |
a611d0ca | 734 | |
d1498ffc | 735 | return IRQ_HANDLED; |
a611d0ca IL |
736 | } |
737 | ||
34d2f9bf | 738 | int __devinit dm1105_ir_init(struct dm1105_dev *dm1105) |
a611d0ca | 739 | { |
d8b4b582 | 740 | struct rc_dev *dev; |
b72857dd | 741 | int err = -ENOMEM; |
a611d0ca | 742 | |
d8b4b582 DH |
743 | dev = rc_allocate_device(); |
744 | if (!dev) | |
a611d0ca IL |
745 | return -ENOMEM; |
746 | ||
a611d0ca IL |
747 | snprintf(dm1105->ir.input_phys, sizeof(dm1105->ir.input_phys), |
748 | "pci-%s/ir0", pci_name(dm1105->pdev)); | |
749 | ||
d8b4b582 DH |
750 | dev->driver_name = MODULE_NAME; |
751 | dev->map_name = RC_MAP_DM1105_NEC; | |
752 | dev->driver_type = RC_DRIVER_SCANCODE; | |
753 | dev->input_name = "DVB on-card IR receiver"; | |
754 | dev->input_phys = dm1105->ir.input_phys; | |
755 | dev->input_id.bustype = BUS_PCI; | |
756 | dev->input_id.version = 1; | |
a611d0ca | 757 | if (dm1105->pdev->subsystem_vendor) { |
d8b4b582 DH |
758 | dev->input_id.vendor = dm1105->pdev->subsystem_vendor; |
759 | dev->input_id.product = dm1105->pdev->subsystem_device; | |
a611d0ca | 760 | } else { |
d8b4b582 DH |
761 | dev->input_id.vendor = dm1105->pdev->vendor; |
762 | dev->input_id.product = dm1105->pdev->device; | |
a611d0ca | 763 | } |
d8b4b582 | 764 | dev->dev.parent = &dm1105->pdev->dev; |
b72857dd IL |
765 | |
766 | INIT_WORK(&dm1105->ir.work, dm1105_emit_key); | |
767 | ||
d8b4b582 | 768 | err = rc_register_device(dev); |
15100d89 | 769 | if (err < 0) { |
d8b4b582 | 770 | rc_free_device(dev); |
15100d89 DH |
771 | return err; |
772 | } | |
a611d0ca | 773 | |
d8b4b582 | 774 | dm1105->ir.dev = dev; |
15100d89 | 775 | return 0; |
a611d0ca IL |
776 | } |
777 | ||
34d2f9bf | 778 | void __devexit dm1105_ir_exit(struct dm1105_dev *dm1105) |
a611d0ca | 779 | { |
d8b4b582 | 780 | rc_unregister_device(dm1105->ir.dev); |
a611d0ca IL |
781 | } |
782 | ||
34d2f9bf | 783 | static int __devinit dm1105_hw_init(struct dm1105_dev *dev) |
a611d0ca | 784 | { |
34d2f9bf | 785 | dm1105_disable_irqs(dev); |
a611d0ca | 786 | |
5eb3291f | 787 | dm_writeb(DM1105_HOST_CTR, 0); |
a611d0ca IL |
788 | |
789 | /*DATALEN 188,*/ | |
5eb3291f | 790 | dm_writeb(DM1105_DTALENTH, 188); |
a611d0ca | 791 | /*TS_STRT TS_VALP MSBFIRST TS_MODE ALPAS TSPES*/ |
5eb3291f | 792 | dm_writew(DM1105_TSCTR, 0xc10a); |
a611d0ca IL |
793 | |
794 | /* map DMA and set address */ | |
34d2f9bf IL |
795 | dm1105_dma_map(dev); |
796 | dm1105_set_dma_addr(dev); | |
a611d0ca | 797 | /* big buffer */ |
5eb3291f IL |
798 | dm_writel(DM1105_RLEN, 5 * DM1105_DMA_BYTES); |
799 | dm_writeb(DM1105_INTCNT, 47); | |
a611d0ca IL |
800 | |
801 | /* IR NEC mode enable */ | |
5eb3291f IL |
802 | dm_writeb(DM1105_IRCTR, (DM1105_IR_EN | DM1105_SYS_CHK)); |
803 | dm_writeb(DM1105_IRMODE, 0); | |
804 | dm_writew(DM1105_SYSTEMCODE, 0); | |
a611d0ca IL |
805 | |
806 | return 0; | |
807 | } | |
808 | ||
34d2f9bf | 809 | static void dm1105_hw_exit(struct dm1105_dev *dev) |
a611d0ca | 810 | { |
34d2f9bf | 811 | dm1105_disable_irqs(dev); |
a611d0ca IL |
812 | |
813 | /* IR disable */ | |
5eb3291f IL |
814 | dm_writeb(DM1105_IRCTR, 0); |
815 | dm_writeb(DM1105_INTMAK, INTMAK_NONEMASK); | |
a611d0ca | 816 | |
34d2f9bf | 817 | dm1105_dma_unmap(dev); |
a611d0ca | 818 | } |
e4aab64c | 819 | |
d4305c68 IL |
820 | static struct stv0299_config sharp_z0194a_config = { |
821 | .demod_address = 0x68, | |
822 | .inittab = sharp_z0194a_inittab, | |
823 | .mclk = 88000000UL, | |
824 | .invert = 1, | |
825 | .skip_reinit = 0, | |
826 | .lock_output = STV0299_LOCKOUTPUT_1, | |
827 | .volt13_op0_op1 = STV0299_VOLT13_OP1, | |
828 | .min_delay_ms = 100, | |
829 | .set_symbol_rate = sharp_z0194a_set_symbol_rate, | |
830 | }; | |
831 | ||
a611d0ca IL |
832 | static struct stv0288_config earda_config = { |
833 | .demod_address = 0x68, | |
834 | .min_delay_ms = 100, | |
835 | }; | |
836 | ||
837 | static struct si21xx_config serit_config = { | |
838 | .demod_address = 0x68, | |
839 | .min_delay_ms = 100, | |
840 | ||
841 | }; | |
842 | ||
843 | static struct cx24116_config serit_sp2633_config = { | |
844 | .demod_address = 0x55, | |
845 | }; | |
a611d0ca | 846 | |
b4a0e816 IL |
847 | static struct ds3000_config dvbworld_ds3000_config = { |
848 | .demod_address = 0x68, | |
849 | }; | |
850 | ||
34d2f9bf | 851 | static int __devinit frontend_init(struct dm1105_dev *dev) |
a611d0ca IL |
852 | { |
853 | int ret; | |
854 | ||
34d2f9bf | 855 | switch (dev->boardnr) { |
0017505d IL |
856 | case DM1105_BOARD_UNBRANDED_I2C_ON_GPIO: |
857 | dm1105_gpio_enable(dev, GPIO15, 1); | |
858 | dm1105_gpio_clear(dev, GPIO15); | |
859 | msleep(100); | |
860 | dm1105_gpio_set(dev, GPIO15); | |
861 | msleep(200); | |
862 | dev->fe = dvb_attach( | |
863 | stv0299_attach, &sharp_z0194a_config, | |
864 | &dev->i2c_bb_adap); | |
865 | if (dev->fe) { | |
866 | dev->fe->ops.set_voltage = dm1105_set_voltage; | |
867 | dvb_attach(dvb_pll_attach, dev->fe, 0x60, | |
868 | &dev->i2c_bb_adap, DVB_PLL_OPERA1); | |
869 | break; | |
870 | } | |
871 | ||
872 | dev->fe = dvb_attach( | |
873 | stv0288_attach, &earda_config, | |
874 | &dev->i2c_bb_adap); | |
875 | if (dev->fe) { | |
876 | dev->fe->ops.set_voltage = dm1105_set_voltage; | |
877 | dvb_attach(stb6000_attach, dev->fe, 0x61, | |
878 | &dev->i2c_bb_adap); | |
879 | break; | |
880 | } | |
881 | ||
882 | dev->fe = dvb_attach( | |
883 | si21xx_attach, &serit_config, | |
884 | &dev->i2c_bb_adap); | |
885 | if (dev->fe) | |
886 | dev->fe->ops.set_voltage = dm1105_set_voltage; | |
887 | break; | |
d8300df9 | 888 | case DM1105_BOARD_DVBWORLD_2004: |
34d2f9bf | 889 | dev->fe = dvb_attach( |
519a4bdc | 890 | cx24116_attach, &serit_sp2633_config, |
34d2f9bf IL |
891 | &dev->i2c_adap); |
892 | if (dev->fe) { | |
893 | dev->fe->ops.set_voltage = dm1105_set_voltage; | |
b4a0e816 IL |
894 | break; |
895 | } | |
896 | ||
34d2f9bf | 897 | dev->fe = dvb_attach( |
b4a0e816 | 898 | ds3000_attach, &dvbworld_ds3000_config, |
34d2f9bf IL |
899 | &dev->i2c_adap); |
900 | if (dev->fe) | |
901 | dev->fe->ops.set_voltage = dm1105_set_voltage; | |
a611d0ca | 902 | |
519a4bdc | 903 | break; |
d8300df9 IL |
904 | case DM1105_BOARD_DVBWORLD_2002: |
905 | case DM1105_BOARD_AXESS_DM05: | |
519a4bdc | 906 | default: |
34d2f9bf | 907 | dev->fe = dvb_attach( |
519a4bdc | 908 | stv0299_attach, &sharp_z0194a_config, |
34d2f9bf IL |
909 | &dev->i2c_adap); |
910 | if (dev->fe) { | |
911 | dev->fe->ops.set_voltage = dm1105_set_voltage; | |
912 | dvb_attach(dvb_pll_attach, dev->fe, 0x60, | |
913 | &dev->i2c_adap, DVB_PLL_OPERA1); | |
519a4bdc | 914 | break; |
a611d0ca | 915 | } |
e4aab64c | 916 | |
34d2f9bf | 917 | dev->fe = dvb_attach( |
519a4bdc | 918 | stv0288_attach, &earda_config, |
34d2f9bf IL |
919 | &dev->i2c_adap); |
920 | if (dev->fe) { | |
921 | dev->fe->ops.set_voltage = dm1105_set_voltage; | |
922 | dvb_attach(stb6000_attach, dev->fe, 0x61, | |
923 | &dev->i2c_adap); | |
519a4bdc | 924 | break; |
a611d0ca | 925 | } |
e4aab64c | 926 | |
34d2f9bf | 927 | dev->fe = dvb_attach( |
519a4bdc | 928 | si21xx_attach, &serit_config, |
34d2f9bf IL |
929 | &dev->i2c_adap); |
930 | if (dev->fe) | |
931 | dev->fe->ops.set_voltage = dm1105_set_voltage; | |
519a4bdc | 932 | |
a611d0ca IL |
933 | } |
934 | ||
34d2f9bf IL |
935 | if (!dev->fe) { |
936 | dev_err(&dev->pdev->dev, "could not attach frontend\n"); | |
a611d0ca IL |
937 | return -ENODEV; |
938 | } | |
939 | ||
34d2f9bf | 940 | ret = dvb_register_frontend(&dev->dvb_adapter, dev->fe); |
a611d0ca | 941 | if (ret < 0) { |
34d2f9bf IL |
942 | if (dev->fe->ops.release) |
943 | dev->fe->ops.release(dev->fe); | |
944 | dev->fe = NULL; | |
a611d0ca IL |
945 | return ret; |
946 | } | |
947 | ||
948 | return 0; | |
949 | } | |
950 | ||
34d2f9bf | 951 | static void __devinit dm1105_read_mac(struct dm1105_dev *dev, u8 *mac) |
a611d0ca IL |
952 | { |
953 | static u8 command[1] = { 0x28 }; | |
954 | ||
955 | struct i2c_msg msg[] = { | |
519a4bdc IL |
956 | { |
957 | .addr = IIC_24C01_addr >> 1, | |
958 | .flags = 0, | |
959 | .buf = command, | |
960 | .len = 1 | |
961 | }, { | |
962 | .addr = IIC_24C01_addr >> 1, | |
963 | .flags = I2C_M_RD, | |
964 | .buf = mac, | |
965 | .len = 6 | |
966 | }, | |
a611d0ca IL |
967 | }; |
968 | ||
34d2f9bf IL |
969 | dm1105_i2c_xfer(&dev->i2c_adap, msg , 2); |
970 | dev_info(&dev->pdev->dev, "MAC %pM\n", mac); | |
a611d0ca IL |
971 | } |
972 | ||
973 | static int __devinit dm1105_probe(struct pci_dev *pdev, | |
974 | const struct pci_device_id *ent) | |
975 | { | |
34d2f9bf | 976 | struct dm1105_dev *dev; |
a611d0ca IL |
977 | struct dvb_adapter *dvb_adapter; |
978 | struct dvb_demux *dvbdemux; | |
979 | struct dmx_demux *dmx; | |
980 | int ret = -ENOMEM; | |
d8300df9 | 981 | int i; |
a611d0ca | 982 | |
34d2f9bf IL |
983 | dev = kzalloc(sizeof(struct dm1105_dev), GFP_KERNEL); |
984 | if (!dev) | |
d1498ffc | 985 | return -ENOMEM; |
a611d0ca | 986 | |
d8300df9 | 987 | /* board config */ |
34d2f9bf IL |
988 | dev->nr = dm1105_devcount; |
989 | dev->boardnr = UNSET; | |
990 | if (card[dev->nr] < ARRAY_SIZE(dm1105_boards)) | |
991 | dev->boardnr = card[dev->nr]; | |
992 | for (i = 0; UNSET == dev->boardnr && | |
d8300df9 IL |
993 | i < ARRAY_SIZE(dm1105_subids); i++) |
994 | if (pdev->subsystem_vendor == | |
995 | dm1105_subids[i].subvendor && | |
996 | pdev->subsystem_device == | |
997 | dm1105_subids[i].subdevice) | |
34d2f9bf | 998 | dev->boardnr = dm1105_subids[i].card; |
d8300df9 | 999 | |
34d2f9bf IL |
1000 | if (UNSET == dev->boardnr) { |
1001 | dev->boardnr = DM1105_BOARD_UNKNOWN; | |
d8300df9 IL |
1002 | dm1105_card_list(pdev); |
1003 | } | |
1004 | ||
1005 | dm1105_devcount++; | |
34d2f9bf IL |
1006 | dev->pdev = pdev; |
1007 | dev->buffer_size = 5 * DM1105_DMA_BYTES; | |
1008 | dev->PacketErrorCount = 0; | |
1009 | dev->dmarst = 0; | |
a611d0ca IL |
1010 | |
1011 | ret = pci_enable_device(pdev); | |
1012 | if (ret < 0) | |
1013 | goto err_kfree; | |
1014 | ||
284901a9 | 1015 | ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
a611d0ca IL |
1016 | if (ret < 0) |
1017 | goto err_pci_disable_device; | |
1018 | ||
1019 | pci_set_master(pdev); | |
1020 | ||
1021 | ret = pci_request_regions(pdev, DRIVER_NAME); | |
1022 | if (ret < 0) | |
1023 | goto err_pci_disable_device; | |
1024 | ||
34d2f9bf IL |
1025 | dev->io_mem = pci_iomap(pdev, 0, pci_resource_len(pdev, 0)); |
1026 | if (!dev->io_mem) { | |
a611d0ca IL |
1027 | ret = -EIO; |
1028 | goto err_pci_release_regions; | |
1029 | } | |
1030 | ||
34d2f9bf IL |
1031 | spin_lock_init(&dev->lock); |
1032 | pci_set_drvdata(pdev, dev); | |
a611d0ca | 1033 | |
34d2f9bf | 1034 | ret = dm1105_hw_init(dev); |
a611d0ca | 1035 | if (ret < 0) |
d1498ffc | 1036 | goto err_pci_iounmap; |
a611d0ca IL |
1037 | |
1038 | /* i2c */ | |
34d2f9bf IL |
1039 | i2c_set_adapdata(&dev->i2c_adap, dev); |
1040 | strcpy(dev->i2c_adap.name, DRIVER_NAME); | |
1041 | dev->i2c_adap.owner = THIS_MODULE; | |
34d2f9bf IL |
1042 | dev->i2c_adap.dev.parent = &pdev->dev; |
1043 | dev->i2c_adap.algo = &dm1105_algo; | |
1044 | dev->i2c_adap.algo_data = dev; | |
1045 | ret = i2c_add_adapter(&dev->i2c_adap); | |
a611d0ca IL |
1046 | |
1047 | if (ret < 0) | |
34d2f9bf | 1048 | goto err_dm1105_hw_exit; |
a611d0ca | 1049 | |
0017505d IL |
1050 | i2c_set_adapdata(&dev->i2c_bb_adap, dev); |
1051 | strcpy(dev->i2c_bb_adap.name, DM1105_I2C_GPIO_NAME); | |
1052 | dev->i2c_bb_adap.owner = THIS_MODULE; | |
1053 | dev->i2c_bb_adap.dev.parent = &pdev->dev; | |
1054 | dev->i2c_bb_adap.algo_data = &dev->i2c_bit; | |
1055 | dev->i2c_bit.data = dev; | |
1056 | dev->i2c_bit.setsda = dm1105_setsda; | |
1057 | dev->i2c_bit.setscl = dm1105_setscl; | |
1058 | dev->i2c_bit.getsda = dm1105_getsda; | |
1059 | dev->i2c_bit.getscl = dm1105_getscl; | |
1060 | dev->i2c_bit.udelay = 10; | |
1061 | dev->i2c_bit.timeout = 10; | |
1062 | ||
1063 | /* Raise SCL and SDA */ | |
1064 | dm1105_setsda(dev, 1); | |
1065 | dm1105_setscl(dev, 1); | |
1066 | ||
1067 | ret = i2c_bit_add_bus(&dev->i2c_bb_adap); | |
1068 | if (ret < 0) | |
1069 | goto err_i2c_del_adapter; | |
1070 | ||
a611d0ca | 1071 | /* dvb */ |
34d2f9bf | 1072 | ret = dvb_register_adapter(&dev->dvb_adapter, DRIVER_NAME, |
a611d0ca IL |
1073 | THIS_MODULE, &pdev->dev, adapter_nr); |
1074 | if (ret < 0) | |
0017505d | 1075 | goto err_i2c_del_adapters; |
a611d0ca | 1076 | |
34d2f9bf | 1077 | dvb_adapter = &dev->dvb_adapter; |
a611d0ca | 1078 | |
34d2f9bf | 1079 | dm1105_read_mac(dev, dvb_adapter->proposed_mac); |
a611d0ca | 1080 | |
34d2f9bf | 1081 | dvbdemux = &dev->demux; |
a611d0ca IL |
1082 | dvbdemux->filternum = 256; |
1083 | dvbdemux->feednum = 256; | |
34d2f9bf IL |
1084 | dvbdemux->start_feed = dm1105_start_feed; |
1085 | dvbdemux->stop_feed = dm1105_stop_feed; | |
a611d0ca IL |
1086 | dvbdemux->dmx.capabilities = (DMX_TS_FILTERING | |
1087 | DMX_SECTION_FILTERING | DMX_MEMORY_BASED_FILTERING); | |
1088 | ret = dvb_dmx_init(dvbdemux); | |
1089 | if (ret < 0) | |
1090 | goto err_dvb_unregister_adapter; | |
1091 | ||
1092 | dmx = &dvbdemux->dmx; | |
34d2f9bf IL |
1093 | dev->dmxdev.filternum = 256; |
1094 | dev->dmxdev.demux = dmx; | |
1095 | dev->dmxdev.capabilities = 0; | |
a611d0ca | 1096 | |
34d2f9bf | 1097 | ret = dvb_dmxdev_init(&dev->dmxdev, dvb_adapter); |
a611d0ca IL |
1098 | if (ret < 0) |
1099 | goto err_dvb_dmx_release; | |
1100 | ||
34d2f9bf | 1101 | dev->hw_frontend.source = DMX_FRONTEND_0; |
a611d0ca | 1102 | |
34d2f9bf | 1103 | ret = dmx->add_frontend(dmx, &dev->hw_frontend); |
a611d0ca IL |
1104 | if (ret < 0) |
1105 | goto err_dvb_dmxdev_release; | |
1106 | ||
34d2f9bf | 1107 | dev->mem_frontend.source = DMX_MEMORY_FE; |
a611d0ca | 1108 | |
34d2f9bf | 1109 | ret = dmx->add_frontend(dmx, &dev->mem_frontend); |
a611d0ca IL |
1110 | if (ret < 0) |
1111 | goto err_remove_hw_frontend; | |
1112 | ||
34d2f9bf | 1113 | ret = dmx->connect_frontend(dmx, &dev->hw_frontend); |
a611d0ca IL |
1114 | if (ret < 0) |
1115 | goto err_remove_mem_frontend; | |
1116 | ||
34d2f9bf | 1117 | ret = frontend_init(dev); |
a611d0ca IL |
1118 | if (ret < 0) |
1119 | goto err_disconnect_frontend; | |
1120 | ||
34d2f9bf IL |
1121 | dvb_net_init(dvb_adapter, &dev->dvbnet, dmx); |
1122 | dm1105_ir_init(dev); | |
d1498ffc | 1123 | |
34d2f9bf IL |
1124 | INIT_WORK(&dev->work, dm1105_dmx_buffer); |
1125 | sprintf(dev->wqn, "%s/%d", dvb_adapter->name, dvb_adapter->num); | |
1126 | dev->wq = create_singlethread_workqueue(dev->wqn); | |
1127 | if (!dev->wq) | |
519a4bdc | 1128 | goto err_dvb_net; |
d1498ffc | 1129 | |
34d2f9bf IL |
1130 | ret = request_irq(pdev->irq, dm1105_irq, IRQF_SHARED, |
1131 | DRIVER_NAME, dev); | |
d1498ffc | 1132 | if (ret < 0) |
519a4bdc | 1133 | goto err_workqueue; |
d1498ffc IL |
1134 | |
1135 | return 0; | |
a611d0ca | 1136 | |
519a4bdc | 1137 | err_workqueue: |
34d2f9bf | 1138 | destroy_workqueue(dev->wq); |
519a4bdc | 1139 | err_dvb_net: |
34d2f9bf | 1140 | dvb_net_release(&dev->dvbnet); |
a611d0ca IL |
1141 | err_disconnect_frontend: |
1142 | dmx->disconnect_frontend(dmx); | |
1143 | err_remove_mem_frontend: | |
34d2f9bf | 1144 | dmx->remove_frontend(dmx, &dev->mem_frontend); |
a611d0ca | 1145 | err_remove_hw_frontend: |
34d2f9bf | 1146 | dmx->remove_frontend(dmx, &dev->hw_frontend); |
a611d0ca | 1147 | err_dvb_dmxdev_release: |
34d2f9bf | 1148 | dvb_dmxdev_release(&dev->dmxdev); |
a611d0ca IL |
1149 | err_dvb_dmx_release: |
1150 | dvb_dmx_release(dvbdemux); | |
1151 | err_dvb_unregister_adapter: | |
1152 | dvb_unregister_adapter(dvb_adapter); | |
0017505d IL |
1153 | err_i2c_del_adapters: |
1154 | i2c_del_adapter(&dev->i2c_bb_adap); | |
a611d0ca | 1155 | err_i2c_del_adapter: |
34d2f9bf IL |
1156 | i2c_del_adapter(&dev->i2c_adap); |
1157 | err_dm1105_hw_exit: | |
1158 | dm1105_hw_exit(dev); | |
a611d0ca | 1159 | err_pci_iounmap: |
34d2f9bf | 1160 | pci_iounmap(pdev, dev->io_mem); |
a611d0ca IL |
1161 | err_pci_release_regions: |
1162 | pci_release_regions(pdev); | |
1163 | err_pci_disable_device: | |
1164 | pci_disable_device(pdev); | |
1165 | err_kfree: | |
1166 | pci_set_drvdata(pdev, NULL); | |
34d2f9bf | 1167 | kfree(dev); |
d1498ffc | 1168 | return ret; |
a611d0ca IL |
1169 | } |
1170 | ||
1171 | static void __devexit dm1105_remove(struct pci_dev *pdev) | |
1172 | { | |
34d2f9bf IL |
1173 | struct dm1105_dev *dev = pci_get_drvdata(pdev); |
1174 | struct dvb_adapter *dvb_adapter = &dev->dvb_adapter; | |
1175 | struct dvb_demux *dvbdemux = &dev->demux; | |
a611d0ca IL |
1176 | struct dmx_demux *dmx = &dvbdemux->dmx; |
1177 | ||
34d2f9bf | 1178 | dm1105_ir_exit(dev); |
a611d0ca | 1179 | dmx->close(dmx); |
34d2f9bf IL |
1180 | dvb_net_release(&dev->dvbnet); |
1181 | if (dev->fe) | |
1182 | dvb_unregister_frontend(dev->fe); | |
a611d0ca IL |
1183 | |
1184 | dmx->disconnect_frontend(dmx); | |
34d2f9bf IL |
1185 | dmx->remove_frontend(dmx, &dev->mem_frontend); |
1186 | dmx->remove_frontend(dmx, &dev->hw_frontend); | |
1187 | dvb_dmxdev_release(&dev->dmxdev); | |
a611d0ca IL |
1188 | dvb_dmx_release(dvbdemux); |
1189 | dvb_unregister_adapter(dvb_adapter); | |
34d2f9bf IL |
1190 | if (&dev->i2c_adap) |
1191 | i2c_del_adapter(&dev->i2c_adap); | |
a611d0ca | 1192 | |
34d2f9bf | 1193 | dm1105_hw_exit(dev); |
a611d0ca | 1194 | synchronize_irq(pdev->irq); |
34d2f9bf IL |
1195 | free_irq(pdev->irq, dev); |
1196 | pci_iounmap(pdev, dev->io_mem); | |
a611d0ca IL |
1197 | pci_release_regions(pdev); |
1198 | pci_disable_device(pdev); | |
1199 | pci_set_drvdata(pdev, NULL); | |
d8300df9 | 1200 | dm1105_devcount--; |
34d2f9bf | 1201 | kfree(dev); |
a611d0ca IL |
1202 | } |
1203 | ||
1204 | static struct pci_device_id dm1105_id_table[] __devinitdata = { | |
1205 | { | |
1206 | .vendor = PCI_VENDOR_ID_TRIGEM, | |
1207 | .device = PCI_DEVICE_ID_DM1105, | |
1208 | .subvendor = PCI_ANY_ID, | |
d8300df9 | 1209 | .subdevice = PCI_ANY_ID, |
519a4bdc IL |
1210 | }, { |
1211 | .vendor = PCI_VENDOR_ID_AXESS, | |
1212 | .device = PCI_DEVICE_ID_DM05, | |
d8300df9 IL |
1213 | .subvendor = PCI_ANY_ID, |
1214 | .subdevice = PCI_ANY_ID, | |
a611d0ca IL |
1215 | }, { |
1216 | /* empty */ | |
1217 | }, | |
1218 | }; | |
1219 | ||
1220 | MODULE_DEVICE_TABLE(pci, dm1105_id_table); | |
1221 | ||
1222 | static struct pci_driver dm1105_driver = { | |
1223 | .name = DRIVER_NAME, | |
1224 | .id_table = dm1105_id_table, | |
1225 | .probe = dm1105_probe, | |
1226 | .remove = __devexit_p(dm1105_remove), | |
1227 | }; | |
1228 | ||
1229 | static int __init dm1105_init(void) | |
1230 | { | |
1231 | return pci_register_driver(&dm1105_driver); | |
1232 | } | |
1233 | ||
1234 | static void __exit dm1105_exit(void) | |
1235 | { | |
1236 | pci_unregister_driver(&dm1105_driver); | |
1237 | } | |
1238 | ||
1239 | module_init(dm1105_init); | |
1240 | module_exit(dm1105_exit); | |
1241 | ||
1242 | MODULE_AUTHOR("Igor M. Liplianin <liplianin@me.by>"); | |
1243 | MODULE_DESCRIPTION("SDMC DM1105 DVB driver"); | |
1244 | MODULE_LICENSE("GPL"); |