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Merge branch 'topic/hda' into for-linus
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / media / IR / nuvoton-cir.c
CommitLineData
6d2f5c27
JW		 1/*
2 * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR
3 *
4 * Copyright (C) 2010 Jarod Wilson <jarod@redhat.com>
5 * Copyright (C) 2009 Nuvoton PS Team
6 *
7 * Special thanks to Nuvoton for providing hardware, spec sheets and
8 * sample code upon which portions of this driver are based. Indirect
9 * thanks also to Maxim Levitsky, whose ene_ir driver this driver is
10 * modeled after.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
25 * USA
26 */
27
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/pnp.h>
31#include <linux/io.h>
32#include <linux/interrupt.h>
33#include <linux/sched.h>
34#include <linux/slab.h>
35#include <linux/input.h>
36#include <media/ir-core.h>
37#include <linux/pci_ids.h>
38
39#include "nuvoton-cir.h"
40
41static char *chip_id = "w836x7hg";
42
43/* write val to config reg */
44static inline void nvt_cr_write(struct nvt_dev *nvt, u8 val, u8 reg)
45{
46 outb(reg, nvt->cr_efir);
47 outb(val, nvt->cr_efdr);
48}
49
50/* read val from config reg */
51static inline u8 nvt_cr_read(struct nvt_dev *nvt, u8 reg)
52{
53 outb(reg, nvt->cr_efir);
54 return inb(nvt->cr_efdr);
55}
56
57/* update config register bit without changing other bits */
58static inline void nvt_set_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
59{
60 u8 tmp = nvt_cr_read(nvt, reg) | val;
61 nvt_cr_write(nvt, tmp, reg);
62}
63
64/* clear config register bit without changing other bits */
65static inline void nvt_clear_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
66{
67 u8 tmp = nvt_cr_read(nvt, reg) & ~val;
68 nvt_cr_write(nvt, tmp, reg);
69}
70
71/* enter extended function mode */
72static inline void nvt_efm_enable(struct nvt_dev *nvt)
73{
74 /* Enabling Extended Function Mode explicitly requires writing 2x */
75 outb(EFER_EFM_ENABLE, nvt->cr_efir);
76 outb(EFER_EFM_ENABLE, nvt->cr_efir);
77}
78
79/* exit extended function mode */
80static inline void nvt_efm_disable(struct nvt_dev *nvt)
81{
82 outb(EFER_EFM_DISABLE, nvt->cr_efir);
83}
84
85/*
86 * When you want to address a specific logical device, write its logical
87 * device number to CR_LOGICAL_DEV_SEL, then enable/disable by writing
88 * 0x1/0x0 respectively to CR_LOGICAL_DEV_EN.
89 */
90static inline void nvt_select_logical_dev(struct nvt_dev *nvt, u8 ldev)
91{
92 outb(CR_LOGICAL_DEV_SEL, nvt->cr_efir);
93 outb(ldev, nvt->cr_efdr);
94}
95
96/* write val to cir config register */
97static inline void nvt_cir_reg_write(struct nvt_dev *nvt, u8 val, u8 offset)
98{
99 outb(val, nvt->cir_addr + offset);
100}
101
102/* read val from cir config register */
103static u8 nvt_cir_reg_read(struct nvt_dev *nvt, u8 offset)
104{
105 u8 val;
106
107 val = inb(nvt->cir_addr + offset);
108
109 return val;
110}
111
112/* write val to cir wake register */
113static inline void nvt_cir_wake_reg_write(struct nvt_dev *nvt,
114 u8 val, u8 offset)
115{
116 outb(val, nvt->cir_wake_addr + offset);
117}
118
119/* read val from cir wake config register */
120static u8 nvt_cir_wake_reg_read(struct nvt_dev *nvt, u8 offset)
121{
122 u8 val;
123
124 val = inb(nvt->cir_wake_addr + offset);
125
126 return val;
127}
128
4e6e29ad
JW		 129#define pr_reg(text, ...) \
130 printk(KERN_INFO KBUILD_MODNAME ": " text, ## __VA_ARGS__)
131
6d2f5c27
JW		 132/* dump current cir register contents */
133static void cir_dump_regs(struct nvt_dev *nvt)
134{
135 nvt_efm_enable(nvt);
136 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
137
4e6e29ad
JW		 138 pr_reg("%s: Dump CIR logical device registers:\n", NVT_DRIVER_NAME);
139 pr_reg(" * CR CIR ACTIVE : 0x%x\n",
6d2f5c27 140 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
4e6e29ad 141 pr_reg(" * CR CIR BASE ADDR: 0x%x\n",
6d2f5c27
JW		 142 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
143 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
4e6e29ad 144 pr_reg(" * CR CIR IRQ NUM: 0x%x\n",
6d2f5c27
JW		 145 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
146
147 nvt_efm_disable(nvt);
148
4e6e29ad
JW		 149 pr_reg("%s: Dump CIR registers:\n", NVT_DRIVER_NAME);
150 pr_reg(" * IRCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRCON));
151 pr_reg(" * IRSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRSTS));
152 pr_reg(" * IREN: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IREN));
153 pr_reg(" * RXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_RXFCONT));
154 pr_reg(" * CP: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CP));
155 pr_reg(" * CC: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CC));
156 pr_reg(" * SLCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCH));
157 pr_reg(" * SLCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCL));
158 pr_reg(" * FIFOCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FIFOCON));
159 pr_reg(" * IRFIFOSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFIFOSTS));
160 pr_reg(" * SRXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SRXFIFO));
161 pr_reg(" * TXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_TXFCONT));
162 pr_reg(" * STXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_STXFIFO));
163 pr_reg(" * FCCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCH));
164 pr_reg(" * FCCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCL));
165 pr_reg(" * IRFSM: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFSM));
6d2f5c27
JW		 166}
167
168/* dump current cir wake register contents */
169static void cir_wake_dump_regs(struct nvt_dev *nvt)
170{
171 u8 i, fifo_len;
172
173 nvt_efm_enable(nvt);
174 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
175
4e6e29ad 176 pr_reg("%s: Dump CIR WAKE logical device registers:\n",
6d2f5c27 177 NVT_DRIVER_NAME);
4e6e29ad 178 pr_reg(" * CR CIR WAKE ACTIVE : 0x%x\n",
6d2f5c27 179 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
4e6e29ad 180 pr_reg(" * CR CIR WAKE BASE ADDR: 0x%x\n",
6d2f5c27 181 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
4e6e29ad
JW		 182 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
183 pr_reg(" * CR CIR WAKE IRQ NUM: 0x%x\n",
6d2f5c27
JW		 184 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
185
186 nvt_efm_disable(nvt);
187
4e6e29ad
JW		 188 pr_reg("%s: Dump CIR WAKE registers\n", NVT_DRIVER_NAME);
189 pr_reg(" * IRCON: 0x%x\n",
6d2f5c27 190 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON));
4e6e29ad 191 pr_reg(" * IRSTS: 0x%x\n",
6d2f5c27 192 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS));
4e6e29ad 193 pr_reg(" * IREN: 0x%x\n",
6d2f5c27 194 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN));
4e6e29ad 195 pr_reg(" * FIFO CMP DEEP: 0x%x\n",
6d2f5c27 196 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_DEEP));
4e6e29ad 197 pr_reg(" * FIFO CMP TOL: 0x%x\n",
6d2f5c27 198 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_TOL));
4e6e29ad 199 pr_reg(" * FIFO COUNT: 0x%x\n",
6d2f5c27 200 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT));
4e6e29ad 201 pr_reg(" * SLCH: 0x%x\n",
6d2f5c27 202 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCH));
4e6e29ad 203 pr_reg(" * SLCL: 0x%x\n",
6d2f5c27 204 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCL));
4e6e29ad 205 pr_reg(" * FIFOCON: 0x%x\n",
6d2f5c27 206 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON));
4e6e29ad 207 pr_reg(" * SRXFSTS: 0x%x\n",
6d2f5c27 208 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SRXFSTS));
4e6e29ad 209 pr_reg(" * SAMPLE RX FIFO: 0x%x\n",
6d2f5c27 210 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SAMPLE_RX_FIFO));
4e6e29ad 211 pr_reg(" * WR FIFO DATA: 0x%x\n",
6d2f5c27 212 nvt_cir_wake_reg_read(nvt, CIR_WAKE_WR_FIFO_DATA));
4e6e29ad 213 pr_reg(" * RD FIFO ONLY: 0x%x\n",
6d2f5c27 214 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
4e6e29ad 215 pr_reg(" * RD FIFO ONLY IDX: 0x%x\n",
6d2f5c27 216 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX));
4e6e29ad 217 pr_reg(" * FIFO IGNORE: 0x%x\n",
6d2f5c27 218 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_IGNORE));
4e6e29ad 219 pr_reg(" * IRFSM: 0x%x\n",
6d2f5c27
JW		 220 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRFSM));
221
222 fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT);
4e6e29ad
JW		 223 pr_reg("%s: Dump CIR WAKE FIFO (len %d)\n", NVT_DRIVER_NAME, fifo_len);
224 pr_reg("* Contents = ");
6d2f5c27 225 for (i = 0; i < fifo_len; i++)
4e6e29ad 226 printk(KERN_CONT "%02x ",
6d2f5c27 227 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
4e6e29ad 228 printk(KERN_CONT "\n");
6d2f5c27
JW		 229}
230
231/* detect hardware features */
232static int nvt_hw_detect(struct nvt_dev *nvt)
233{
234 unsigned long flags;
235 u8 chip_major, chip_minor;
236 int ret = 0;
237
238 nvt_efm_enable(nvt);
239
240 /* Check if we're wired for the alternate EFER setup */
241 chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
242 if (chip_major == 0xff) {
243 nvt->cr_efir = CR_EFIR2;
244 nvt->cr_efdr = CR_EFDR2;
245 nvt_efm_enable(nvt);
246 chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
247 }
248
249 chip_minor = nvt_cr_read(nvt, CR_CHIP_ID_LO);
250 nvt_dbg("%s: chip id: 0x%02x 0x%02x", chip_id, chip_major, chip_minor);
251
252 if (chip_major != CHIP_ID_HIGH &&
253 (chip_minor != CHIP_ID_LOW || chip_minor != CHIP_ID_LOW2))
254 ret = -ENODEV;
255
256 nvt_efm_disable(nvt);
257
258 spin_lock_irqsave(&nvt->nvt_lock, flags);
259 nvt->chip_major = chip_major;
260 nvt->chip_minor = chip_minor;
261 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
262
263 return ret;
264}
265
266static void nvt_cir_ldev_init(struct nvt_dev *nvt)
267{
268 u8 val;
269
270 /* output pin selection (Pin95=CIRRX, Pin96=CIRTX1, WB enabled */
271 val = nvt_cr_read(nvt, CR_OUTPUT_PIN_SEL);
272 val &= OUTPUT_PIN_SEL_MASK;
273 val |= (OUTPUT_ENABLE_CIR | OUTPUT_ENABLE_CIRWB);
274 nvt_cr_write(nvt, val, CR_OUTPUT_PIN_SEL);
275
276 /* Select CIR logical device and enable */
277 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
278 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
279
280 nvt_cr_write(nvt, nvt->cir_addr >> 8, CR_CIR_BASE_ADDR_HI);
281 nvt_cr_write(nvt, nvt->cir_addr & 0xff, CR_CIR_BASE_ADDR_LO);
282
283 nvt_cr_write(nvt, nvt->cir_irq, CR_CIR_IRQ_RSRC);
284
285 nvt_dbg("CIR initialized, base io port address: 0x%lx, irq: %d",
286 nvt->cir_addr, nvt->cir_irq);
287}
288
289static void nvt_cir_wake_ldev_init(struct nvt_dev *nvt)
290{
291 /* Select ACPI logical device, enable it and CIR Wake */
292 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
293 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
294
295 /* Enable CIR Wake via PSOUT# (Pin60) */
296 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
297
298 /* enable cir interrupt of mouse/keyboard IRQ event */
299 nvt_set_reg_bit(nvt, CIR_INTR_MOUSE_IRQ_BIT, CR_ACPI_IRQ_EVENTS);
300
301 /* enable pme interrupt of cir wakeup event */
302 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
303
304 /* Select CIR Wake logical device and enable */
305 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
306 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
307
308 nvt_cr_write(nvt, nvt->cir_wake_addr >> 8, CR_CIR_BASE_ADDR_HI);
309 nvt_cr_write(nvt, nvt->cir_wake_addr & 0xff, CR_CIR_BASE_ADDR_LO);
310
311 nvt_cr_write(nvt, nvt->cir_wake_irq, CR_CIR_IRQ_RSRC);
312
313 nvt_dbg("CIR Wake initialized, base io port address: 0x%lx, irq: %d",
314 nvt->cir_wake_addr, nvt->cir_wake_irq);
315}
316
317/* clear out the hardware's cir rx fifo */
318static void nvt_clear_cir_fifo(struct nvt_dev *nvt)
319{
320 u8 val;
321
322 val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
323 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON);
324}
325
326/* clear out the hardware's cir wake rx fifo */
327static void nvt_clear_cir_wake_fifo(struct nvt_dev *nvt)
328{
329 u8 val;
330
331 val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON);
332 nvt_cir_wake_reg_write(nvt, val | CIR_WAKE_FIFOCON_RXFIFOCLR,
333 CIR_WAKE_FIFOCON);
334}
335
336/* clear out the hardware's cir tx fifo */
337static void nvt_clear_tx_fifo(struct nvt_dev *nvt)
338{
339 u8 val;
340
341 val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
342 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_TXFIFOCLR, CIR_FIFOCON);
343}
344
fbdc781c
JW		 345/* enable RX Trigger Level Reach and Packet End interrupts */
346static void nvt_set_cir_iren(struct nvt_dev *nvt)
347{
348 u8 iren;
349
350 iren = CIR_IREN_RTR | CIR_IREN_PE;
351 nvt_cir_reg_write(nvt, iren, CIR_IREN);
352}
353
6d2f5c27
JW		 354static void nvt_cir_regs_init(struct nvt_dev *nvt)
355{
356 /* set sample limit count (PE interrupt raised when reached) */
357 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_SLCH);
358 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_SLCL);
359
360 /* set fifo irq trigger levels */
361 nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV |
362 CIR_FIFOCON_RX_TRIGGER_LEV, CIR_FIFOCON);
363
364 /*
365 * Enable TX and RX, specify carrier on = low, off = high, and set
366 * sample period (currently 50us)
367 */
4e6e29ad
JW		 368 nvt_cir_reg_write(nvt,
369 CIR_IRCON_TXEN | CIR_IRCON_RXEN |
370 CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL,
371 CIR_IRCON);
6d2f5c27
JW		 372
373 /* clear hardware rx and tx fifos */
374 nvt_clear_cir_fifo(nvt);
375 nvt_clear_tx_fifo(nvt);
376
377 /* clear any and all stray interrupts */
378 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
379
fbdc781c
JW		 380 /* and finally, enable interrupts */
381 nvt_set_cir_iren(nvt);
6d2f5c27
JW		 382}
383
384static void nvt_cir_wake_regs_init(struct nvt_dev *nvt)
385{
386 /* set number of bytes needed for wake key comparison (default 67) */
387 nvt_cir_wake_reg_write(nvt, CIR_WAKE_FIFO_LEN, CIR_WAKE_FIFO_CMP_DEEP);
388
389 /* set tolerance/variance allowed per byte during wake compare */
390 nvt_cir_wake_reg_write(nvt, CIR_WAKE_CMP_TOLERANCE,
391 CIR_WAKE_FIFO_CMP_TOL);
392
393 /* set sample limit count (PE interrupt raised when reached) */
394 nvt_cir_wake_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_WAKE_SLCH);
395 nvt_cir_wake_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_WAKE_SLCL);
396
397 /* set cir wake fifo rx trigger level (currently 67) */
398 nvt_cir_wake_reg_write(nvt, CIR_WAKE_FIFOCON_RX_TRIGGER_LEV,
399 CIR_WAKE_FIFOCON);
400
401 /*
402 * Enable TX and RX, specific carrier on = low, off = high, and set
403 * sample period (currently 50us)
404 */
405 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN |
406 CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
407 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL,
408 CIR_WAKE_IRCON);
409
410 /* clear cir wake rx fifo */
411 nvt_clear_cir_wake_fifo(nvt);
412
413 /* clear any and all stray interrupts */
414 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
415}
416
417static void nvt_enable_wake(struct nvt_dev *nvt)
418{
419 nvt_efm_enable(nvt);
420
421 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
422 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
423 nvt_set_reg_bit(nvt, CIR_INTR_MOUSE_IRQ_BIT, CR_ACPI_IRQ_EVENTS);
424 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
425
426 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
427 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
428
429 nvt_efm_disable(nvt);
430
431 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN |
432 CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
4e6e29ad
JW		 433 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL,
434 CIR_WAKE_IRCON);
6d2f5c27
JW		 435 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
436 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN);
437}
438
439/* rx carrier detect only works in learning mode, must be called w/nvt_lock */
440static u32 nvt_rx_carrier_detect(struct nvt_dev *nvt)
441{
442 u32 count, carrier, duration = 0;
443 int i;
444
445 count = nvt_cir_reg_read(nvt, CIR_FCCL) |
446 nvt_cir_reg_read(nvt, CIR_FCCH) << 8;
447
448 for (i = 0; i < nvt->pkts; i++) {
449 if (nvt->buf[i] & BUF_PULSE_BIT)
450 duration += nvt->buf[i] & BUF_LEN_MASK;
451 }
452
453 duration *= SAMPLE_PERIOD;
454
455 if (!count || !duration) {
456 nvt_pr(KERN_NOTICE, "Unable to determine carrier! (c:%u, d:%u)",
457 count, duration);
458 return 0;
459 }
460
461 carrier = (count * 1000000) / duration;
462
463 if ((carrier > MAX_CARRIER) || (carrier < MIN_CARRIER))
464 nvt_dbg("WTF? Carrier frequency out of range!");
465
466 nvt_dbg("Carrier frequency: %u (count %u, duration %u)",
467 carrier, count, duration);
468
469 return carrier;
470}
471
472/*
473 * set carrier frequency
474 *
475 * set carrier on 2 registers: CP & CC
476 * always set CP as 0x81
477 * set CC by SPEC, CC = 3MHz/carrier - 1
478 */
479static int nvt_set_tx_carrier(void *data, u32 carrier)
480{
481 struct nvt_dev *nvt = data;
482 u16 val;
483
484 nvt_cir_reg_write(nvt, 1, CIR_CP);
485 val = 3000000 / (carrier) - 1;
486 nvt_cir_reg_write(nvt, val & 0xff, CIR_CC);
487
488 nvt_dbg("cp: 0x%x cc: 0x%x\n",
489 nvt_cir_reg_read(nvt, CIR_CP), nvt_cir_reg_read(nvt, CIR_CC));
490
491 return 0;
492}
493
494/*
495 * nvt_tx_ir
496 *
497 * 1) clean TX fifo first (handled by AP)
498 * 2) copy data from user space
499 * 3) disable RX interrupts, enable TX interrupts: TTR & TFU
500 * 4) send 9 packets to TX FIFO to open TTR
501 * in interrupt_handler:
502 * 5) send all data out
503 * go back to write():
504 * 6) disable TX interrupts, re-enable RX interupts
505 *
506 * The key problem of this function is user space data may larger than
507 * driver's data buf length. So nvt_tx_ir() will only copy TX_BUF_LEN data to
508 * buf, and keep current copied data buf num in cur_buf_num. But driver's buf
509 * number may larger than TXFCONT (0xff). So in interrupt_handler, it has to
510 * set TXFCONT as 0xff, until buf_count less than 0xff.
511 */
512static int nvt_tx_ir(void *priv, int *txbuf, u32 n)
513{
514 struct nvt_dev *nvt = priv;
515 unsigned long flags;
516 size_t cur_count;
517 unsigned int i;
518 u8 iren;
519 int ret;
520
521 spin_lock_irqsave(&nvt->tx.lock, flags);
522
523 if (n >= TX_BUF_LEN) {
524 nvt->tx.buf_count = cur_count = TX_BUF_LEN;
525 ret = TX_BUF_LEN;
526 } else {
527 nvt->tx.buf_count = cur_count = n;
528 ret = n;
529 }
530
531 memcpy(nvt->tx.buf, txbuf, nvt->tx.buf_count);
532
533 nvt->tx.cur_buf_num = 0;
534
535 /* save currently enabled interrupts */
536 iren = nvt_cir_reg_read(nvt, CIR_IREN);
537
538 /* now disable all interrupts, save TFU & TTR */
539 nvt_cir_reg_write(nvt, CIR_IREN_TFU | CIR_IREN_TTR, CIR_IREN);
540
541 nvt->tx.tx_state = ST_TX_REPLY;
542
543 nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV_8 |
544 CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON);
545
546 /* trigger TTR interrupt by writing out ones, (yes, it's ugly) */
547 for (i = 0; i < 9; i++)
548 nvt_cir_reg_write(nvt, 0x01, CIR_STXFIFO);
549
550 spin_unlock_irqrestore(&nvt->tx.lock, flags);
551
552 wait_event(nvt->tx.queue, nvt->tx.tx_state == ST_TX_REQUEST);
553
554 spin_lock_irqsave(&nvt->tx.lock, flags);
555 nvt->tx.tx_state = ST_TX_NONE;
556 spin_unlock_irqrestore(&nvt->tx.lock, flags);
557
558 /* restore enabled interrupts to prior state */
559 nvt_cir_reg_write(nvt, iren, CIR_IREN);
560
561 return ret;
562}
563
564/* dump contents of the last rx buffer we got from the hw rx fifo */
565static void nvt_dump_rx_buf(struct nvt_dev *nvt)
566{
567 int i;
568
4e6e29ad 569 printk(KERN_DEBUG "%s (len %d): ", __func__, nvt->pkts);
6d2f5c27 570 for (i = 0; (i < nvt->pkts) && (i < RX_BUF_LEN); i++)
4e6e29ad
JW		 571 printk(KERN_CONT "0x%02x ", nvt->buf[i]);
572 printk(KERN_CONT "\n");
6d2f5c27
JW		 573}
574
575/*
576 * Process raw data in rx driver buffer, store it in raw IR event kfifo,
577 * trigger decode when appropriate.
578 *
579 * We get IR data samples one byte at a time. If the msb is set, its a pulse,
580 * otherwise its a space. The lower 7 bits are the count of SAMPLE_PERIOD
581 * (default 50us) intervals for that pulse/space. A discrete signal is
582 * followed by a series of 0x7f packets, then either 0x7<something> or 0x80
583 * to signal more IR coming (repeats) or end of IR, respectively. We store
584 * sample data in the raw event kfifo until we see 0x7<something> (except f)
585 * or 0x80, at which time, we trigger a decode operation.
586 */
587static void nvt_process_rx_ir_data(struct nvt_dev *nvt)
588{
4651918a 589 DEFINE_IR_RAW_EVENT(rawir);
6d2f5c27
JW		 590 unsigned int count;
591 u32 carrier;
592 u8 sample;
593 int i;
594
595 nvt_dbg_verbose("%s firing", __func__);
596
597 if (debug)
598 nvt_dump_rx_buf(nvt);
599
600 if (nvt->carrier_detect_enabled)
601 carrier = nvt_rx_carrier_detect(nvt);
602
603 count = nvt->pkts;
604 nvt_dbg_verbose("Processing buffer of len %d", count);
605
b7582815
JW		 606 init_ir_raw_event(&rawir);
607
6d2f5c27
JW		 608 for (i = 0; i < count; i++) {
609 nvt->pkts--;
610 sample = nvt->buf[i];
611
612 rawir.pulse = ((sample & BUF_PULSE_BIT) != 0);
613 rawir.duration = (sample & BUF_LEN_MASK)
614 * SAMPLE_PERIOD * 1000;
615
616 if ((sample & BUF_LEN_MASK) == BUF_LEN_MASK) {
617 if (nvt->rawir.pulse == rawir.pulse)
618 nvt->rawir.duration += rawir.duration;
619 else {
620 nvt->rawir.duration = rawir.duration;
621 nvt->rawir.pulse = rawir.pulse;
622 }
623 continue;
624 }
625
626 rawir.duration += nvt->rawir.duration;
4651918a
ML		 627
628 init_ir_raw_event(&nvt->rawir);
6d2f5c27
JW		 629 nvt->rawir.duration = 0;
630 nvt->rawir.pulse = rawir.pulse;
631
632 if (sample == BUF_PULSE_BIT)
633 rawir.pulse = false;
634
635 if (rawir.duration) {
636 nvt_dbg("Storing %s with duration %d",
637 rawir.pulse ? "pulse" : "space",
638 rawir.duration);
639
640 ir_raw_event_store(nvt->rdev, &rawir);
641 }
642
643 /*
644 * BUF_PULSE_BIT indicates end of IR data, BUF_REPEAT_BYTE
645 * indicates end of IR signal, but new data incoming. In both
646 * cases, it means we're ready to call ir_raw_event_handle
647 */
b7582815
JW		 648 if ((sample == BUF_PULSE_BIT) && nvt->pkts) {
649 nvt_dbg("Calling ir_raw_event_handle (signal end)\n");
6d2f5c27 650 ir_raw_event_handle(nvt->rdev);
b7582815 651 }
6d2f5c27
JW		 652 }
653
b7582815
JW		 654 nvt_dbg("Calling ir_raw_event_handle (buffer empty)\n");
655 ir_raw_event_handle(nvt->rdev);
656
6d2f5c27
JW		 657 if (nvt->pkts) {
658 nvt_dbg("Odd, pkts should be 0 now... (its %u)", nvt->pkts);
659 nvt->pkts = 0;
660 }
661
662 nvt_dbg_verbose("%s done", __func__);
663}
664
fbdc781c
JW		 665static void nvt_handle_rx_fifo_overrun(struct nvt_dev *nvt)
666{
667 nvt_pr(KERN_WARNING, "RX FIFO overrun detected, flushing data!");
668
669 nvt->pkts = 0;
670 nvt_clear_cir_fifo(nvt);
671 ir_raw_event_reset(nvt->rdev);
672}
673
6d2f5c27
JW		 674/* copy data from hardware rx fifo into driver buffer */
675static void nvt_get_rx_ir_data(struct nvt_dev *nvt)
676{
677 unsigned long flags;
678 u8 fifocount, val;
679 unsigned int b_idx;
fbdc781c 680 bool overrun = false;
6d2f5c27
JW		 681 int i;
682
683 /* Get count of how many bytes to read from RX FIFO */
684 fifocount = nvt_cir_reg_read(nvt, CIR_RXFCONT);
685 /* if we get 0xff, probably means the logical dev is disabled */
686 if (fifocount == 0xff)
687 return;
fbdc781c 688 /* watch out for a fifo overrun condition */
6d2f5c27 689 else if (fifocount > RX_BUF_LEN) {
fbdc781c
JW		 690 overrun = true;
691 fifocount = RX_BUF_LEN;
6d2f5c27
JW		 692 }
693
694 nvt_dbg("attempting to fetch %u bytes from hw rx fifo", fifocount);
695
696 spin_lock_irqsave(&nvt->nvt_lock, flags);
697
698 b_idx = nvt->pkts;
699
700 /* This should never happen, but lets check anyway... */
701 if (b_idx + fifocount > RX_BUF_LEN) {
702 nvt_process_rx_ir_data(nvt);
703 b_idx = 0;
704 }
705
706 /* Read fifocount bytes from CIR Sample RX FIFO register */
707 for (i = 0; i < fifocount; i++) {
708 val = nvt_cir_reg_read(nvt, CIR_SRXFIFO);
709 nvt->buf[b_idx + i] = val;
710 }
711
712 nvt->pkts += fifocount;
713 nvt_dbg("%s: pkts now %d", __func__, nvt->pkts);
714
715 nvt_process_rx_ir_data(nvt);
716
fbdc781c
JW		 717 if (overrun)
718 nvt_handle_rx_fifo_overrun(nvt);
719
6d2f5c27
JW		 720 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
721}
722
723static void nvt_cir_log_irqs(u8 status, u8 iren)
724{
725 nvt_pr(KERN_INFO, "IRQ 0x%02x (IREN 0x%02x) :%s%s%s%s%s%s%s%s%s",
726 status, iren,
727 status & CIR_IRSTS_RDR ? " RDR" : "",
728 status & CIR_IRSTS_RTR ? " RTR" : "",
729 status & CIR_IRSTS_PE ? " PE" : "",
730 status & CIR_IRSTS_RFO ? " RFO" : "",
731 status & CIR_IRSTS_TE ? " TE" : "",
732 status & CIR_IRSTS_TTR ? " TTR" : "",
733 status & CIR_IRSTS_TFU ? " TFU" : "",
734 status & CIR_IRSTS_GH ? " GH" : "",
735 status & ~(CIR_IRSTS_RDR | CIR_IRSTS_RTR | CIR_IRSTS_PE |
736 CIR_IRSTS_RFO | CIR_IRSTS_TE | CIR_IRSTS_TTR |
737 CIR_IRSTS_TFU | CIR_IRSTS_GH) ? " ?" : "");
738}
739
740static bool nvt_cir_tx_inactive(struct nvt_dev *nvt)
741{
742 unsigned long flags;
743 bool tx_inactive;
744 u8 tx_state;
745
746 spin_lock_irqsave(&nvt->tx.lock, flags);
747 tx_state = nvt->tx.tx_state;
748 spin_unlock_irqrestore(&nvt->tx.lock, flags);
749
750 tx_inactive = (tx_state == ST_TX_NONE);
751
752 return tx_inactive;
753}
754
755/* interrupt service routine for incoming and outgoing CIR data */
756static irqreturn_t nvt_cir_isr(int irq, void *data)
757{
758 struct nvt_dev *nvt = data;
759 u8 status, iren, cur_state;
760 unsigned long flags;
761
762 nvt_dbg_verbose("%s firing", __func__);
763
764 nvt_efm_enable(nvt);
765 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
766 nvt_efm_disable(nvt);
767
768 /*
769 * Get IR Status register contents. Write 1 to ack/clear
770 *
771 * bit: reg name - description
772 * 7: CIR_IRSTS_RDR - RX Data Ready
773 * 6: CIR_IRSTS_RTR - RX FIFO Trigger Level Reach
774 * 5: CIR_IRSTS_PE - Packet End
775 * 4: CIR_IRSTS_RFO - RX FIFO Overrun (RDR will also be set)
776 * 3: CIR_IRSTS_TE - TX FIFO Empty
777 * 2: CIR_IRSTS_TTR - TX FIFO Trigger Level Reach
778 * 1: CIR_IRSTS_TFU - TX FIFO Underrun
779 * 0: CIR_IRSTS_GH - Min Length Detected
780 */
781 status = nvt_cir_reg_read(nvt, CIR_IRSTS);
782 if (!status) {
783 nvt_dbg_verbose("%s exiting, IRSTS 0x0", __func__);
784 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
785 return IRQ_RETVAL(IRQ_NONE);
786 }
787
788 /* ack/clear all irq flags we've got */
789 nvt_cir_reg_write(nvt, status, CIR_IRSTS);
790 nvt_cir_reg_write(nvt, 0, CIR_IRSTS);
791
792 /* Interrupt may be shared with CIR Wake, bail if CIR not enabled */
793 iren = nvt_cir_reg_read(nvt, CIR_IREN);
794 if (!iren) {
795 nvt_dbg_verbose("%s exiting, CIR not enabled", __func__);
796 return IRQ_RETVAL(IRQ_NONE);
797 }
798
799 if (debug)
800 nvt_cir_log_irqs(status, iren);
801
802 if (status & CIR_IRSTS_RTR) {
803 /* FIXME: add code for study/learn mode */
804 /* We only do rx if not tx'ing */
805 if (nvt_cir_tx_inactive(nvt))
806 nvt_get_rx_ir_data(nvt);
807 }
808
809 if (status & CIR_IRSTS_PE) {
810 if (nvt_cir_tx_inactive(nvt))
811 nvt_get_rx_ir_data(nvt);
812
813 spin_lock_irqsave(&nvt->nvt_lock, flags);
814
815 cur_state = nvt->study_state;
816
817 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
818
819 if (cur_state == ST_STUDY_NONE)
820 nvt_clear_cir_fifo(nvt);
821 }
822
823 if (status & CIR_IRSTS_TE)
824 nvt_clear_tx_fifo(nvt);
825
826 if (status & CIR_IRSTS_TTR) {
827 unsigned int pos, count;
828 u8 tmp;
829
830 spin_lock_irqsave(&nvt->tx.lock, flags);
831
832 pos = nvt->tx.cur_buf_num;
833 count = nvt->tx.buf_count;
834
835 /* Write data into the hardware tx fifo while pos < count */
836 if (pos < count) {
837 nvt_cir_reg_write(nvt, nvt->tx.buf[pos], CIR_STXFIFO);
838 nvt->tx.cur_buf_num++;
839 /* Disable TX FIFO Trigger Level Reach (TTR) interrupt */
840 } else {
841 tmp = nvt_cir_reg_read(nvt, CIR_IREN);
842 nvt_cir_reg_write(nvt, tmp & ~CIR_IREN_TTR, CIR_IREN);
843 }
844
845 spin_unlock_irqrestore(&nvt->tx.lock, flags);
846
847 }
848
849 if (status & CIR_IRSTS_TFU) {
850 spin_lock_irqsave(&nvt->tx.lock, flags);
851 if (nvt->tx.tx_state == ST_TX_REPLY) {
852 nvt->tx.tx_state = ST_TX_REQUEST;
853 wake_up(&nvt->tx.queue);
854 }
855 spin_unlock_irqrestore(&nvt->tx.lock, flags);
856 }
857
858 nvt_dbg_verbose("%s done", __func__);
859 return IRQ_RETVAL(IRQ_HANDLED);
860}
861
862/* Interrupt service routine for CIR Wake */
863static irqreturn_t nvt_cir_wake_isr(int irq, void *data)
864{
865 u8 status, iren, val;
866 struct nvt_dev *nvt = data;
867 unsigned long flags;
868
869 nvt_dbg_wake("%s firing", __func__);
870
871 status = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS);
872 if (!status)
873 return IRQ_RETVAL(IRQ_NONE);
874
875 if (status & CIR_WAKE_IRSTS_IR_PENDING)
876 nvt_clear_cir_wake_fifo(nvt);
877
878 nvt_cir_wake_reg_write(nvt, status, CIR_WAKE_IRSTS);
879 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IRSTS);
880
881 /* Interrupt may be shared with CIR, bail if Wake not enabled */
882 iren = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN);
883 if (!iren) {
884 nvt_dbg_wake("%s exiting, wake not enabled", __func__);
885 return IRQ_RETVAL(IRQ_HANDLED);
886 }
887
888 if ((status & CIR_WAKE_IRSTS_PE) &&
889 (nvt->wake_state == ST_WAKE_START)) {
890 while (nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX)) {
891 val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY);
892 nvt_dbg("setting wake up key: 0x%x", val);
893 }
894
895 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN);
896 spin_lock_irqsave(&nvt->nvt_lock, flags);
897 nvt->wake_state = ST_WAKE_FINISH;
898 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
899 }
900
901 nvt_dbg_wake("%s done", __func__);
902 return IRQ_RETVAL(IRQ_HANDLED);
903}
904
905static void nvt_enable_cir(struct nvt_dev *nvt)
906{
907 /* set function enable flags */
908 nvt_cir_reg_write(nvt, CIR_IRCON_TXEN | CIR_IRCON_RXEN |
909 CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL,
910 CIR_IRCON);
911
912 nvt_efm_enable(nvt);
913
914 /* enable the CIR logical device */
915 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
916 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
917
918 nvt_efm_disable(nvt);
919
920 /* clear all pending interrupts */
921 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
922
923 /* enable interrupts */
fbdc781c 924 nvt_set_cir_iren(nvt);
6d2f5c27
JW		 925}
926
927static void nvt_disable_cir(struct nvt_dev *nvt)
928{
929 /* disable CIR interrupts */
930 nvt_cir_reg_write(nvt, 0, CIR_IREN);
931
932 /* clear any and all pending interrupts */
933 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
934
935 /* clear all function enable flags */
936 nvt_cir_reg_write(nvt, 0, CIR_IRCON);
937
938 /* clear hardware rx and tx fifos */
939 nvt_clear_cir_fifo(nvt);
940 nvt_clear_tx_fifo(nvt);
941
942 nvt_efm_enable(nvt);
943
944 /* disable the CIR logical device */
945 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
946 nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN);
947
948 nvt_efm_disable(nvt);
949}
950
951static int nvt_open(void *data)
952{
953 struct nvt_dev *nvt = (struct nvt_dev *)data;
954 unsigned long flags;
955
956 spin_lock_irqsave(&nvt->nvt_lock, flags);
957 nvt->in_use = true;
958 nvt_enable_cir(nvt);
959 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
960
961 return 0;
962}
963
964static void nvt_close(void *data)
965{
966 struct nvt_dev *nvt = (struct nvt_dev *)data;
967 unsigned long flags;
968
969 spin_lock_irqsave(&nvt->nvt_lock, flags);
970 nvt->in_use = false;
971 nvt_disable_cir(nvt);
972 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
973}
974
975/* Allocate memory, probe hardware, and initialize everything */
976static int nvt_probe(struct pnp_dev *pdev, const struct pnp_device_id *dev_id)
977{
978 struct nvt_dev *nvt = NULL;
979 struct input_dev *rdev = NULL;
980 struct ir_dev_props *props = NULL;
981 int ret = -ENOMEM;
982
983 nvt = kzalloc(sizeof(struct nvt_dev), GFP_KERNEL);
984 if (!nvt)
985 return ret;
986
987 props = kzalloc(sizeof(struct ir_dev_props), GFP_KERNEL);
988 if (!props)
989 goto failure;
990
991 /* input device for IR remote (and tx) */
992 rdev = input_allocate_device();
993 if (!rdev)
994 goto failure;
995
996 ret = -ENODEV;
997 /* validate pnp resources */
998 if (!pnp_port_valid(pdev, 0) ||
999 pnp_port_len(pdev, 0) < CIR_IOREG_LENGTH) {
1000 dev_err(&pdev->dev, "IR PNP Port not valid!\n");
1001 goto failure;
1002 }
1003
1004 if (!pnp_irq_valid(pdev, 0)) {
1005 dev_err(&pdev->dev, "PNP IRQ not valid!\n");
1006 goto failure;
1007 }
1008
1009 if (!pnp_port_valid(pdev, 1) ||
1010 pnp_port_len(pdev, 1) < CIR_IOREG_LENGTH) {
1011 dev_err(&pdev->dev, "Wake PNP Port not valid!\n");
1012 goto failure;
1013 }
1014
1015 nvt->cir_addr = pnp_port_start(pdev, 0);
1016 nvt->cir_irq = pnp_irq(pdev, 0);
1017
1018 nvt->cir_wake_addr = pnp_port_start(pdev, 1);
1019 /* irq is always shared between cir and cir wake */
1020 nvt->cir_wake_irq = nvt->cir_irq;
1021
1022 nvt->cr_efir = CR_EFIR;
1023 nvt->cr_efdr = CR_EFDR;
1024
1025 spin_lock_init(&nvt->nvt_lock);
1026 spin_lock_init(&nvt->tx.lock);
4651918a 1027 init_ir_raw_event(&nvt->rawir);
6d2f5c27
JW		 1028
1029 ret = -EBUSY;
1030 /* now claim resources */
1031 if (!request_region(nvt->cir_addr,
1032 CIR_IOREG_LENGTH, NVT_DRIVER_NAME))
1033 goto failure;
1034
1035 if (request_irq(nvt->cir_irq, nvt_cir_isr, IRQF_SHARED,
1036 NVT_DRIVER_NAME, (void *)nvt))
1037 goto failure;
1038
1039 if (!request_region(nvt->cir_wake_addr,
1040 CIR_IOREG_LENGTH, NVT_DRIVER_NAME))
1041 goto failure;
1042
1043 if (request_irq(nvt->cir_wake_irq, nvt_cir_wake_isr, IRQF_SHARED,
1044 NVT_DRIVER_NAME, (void *)nvt))
1045 goto failure;
1046
1047 pnp_set_drvdata(pdev, nvt);
1048 nvt->pdev = pdev;
1049
1050 init_waitqueue_head(&nvt->tx.queue);
1051
1052 ret = nvt_hw_detect(nvt);
1053 if (ret)
1054 goto failure;
1055
1056 /* Initialize CIR & CIR Wake Logical Devices */
1057 nvt_efm_enable(nvt);
1058 nvt_cir_ldev_init(nvt);
1059 nvt_cir_wake_ldev_init(nvt);
1060 nvt_efm_disable(nvt);
1061
1062 /* Initialize CIR & CIR Wake Config Registers */
1063 nvt_cir_regs_init(nvt);
1064 nvt_cir_wake_regs_init(nvt);
1065
1066 /* Set up ir-core props */
1067 props->priv = nvt;
1068 props->driver_type = RC_DRIVER_IR_RAW;
1069 props->allowed_protos = IR_TYPE_ALL;
1070 props->open = nvt_open;
1071 props->close = nvt_close;
1072#if 0
1073 props->min_timeout = XYZ;
1074 props->max_timeout = XYZ;
1075 props->timeout = XYZ;
1076 /* rx resolution is hardwired to 50us atm, 1, 25, 100 also possible */
1077 props->rx_resolution = XYZ;
1078
1079 /* tx bits */
1080 props->tx_resolution = XYZ;
1081#endif
1082 props->tx_ir = nvt_tx_ir;
1083 props->s_tx_carrier = nvt_set_tx_carrier;
1084
1085 rdev->name = "Nuvoton w836x7hg Infrared Remote Transceiver";
1086 rdev->id.bustype = BUS_HOST;
1087 rdev->id.vendor = PCI_VENDOR_ID_WINBOND2;
1088 rdev->id.product = nvt->chip_major;
1089 rdev->id.version = nvt->chip_minor;
1090
1091 nvt->props = props;
1092 nvt->rdev = rdev;
1093
1094 device_set_wakeup_capable(&pdev->dev, 1);
1095 device_set_wakeup_enable(&pdev->dev, 1);
1096
1097 ret = ir_input_register(rdev, RC_MAP_RC6_MCE, props, NVT_DRIVER_NAME);
1098 if (ret)
1099 goto failure;
1100
1101 nvt_pr(KERN_NOTICE, "driver has been successfully loaded\n");
1102 if (debug) {
1103 cir_dump_regs(nvt);
1104 cir_wake_dump_regs(nvt);
1105 }
1106
1107 return 0;
1108
1109failure:
1110 if (nvt->cir_irq)
1111 free_irq(nvt->cir_irq, nvt);
1112 if (nvt->cir_addr)
1113 release_region(nvt->cir_addr, CIR_IOREG_LENGTH);
1114
1115 if (nvt->cir_wake_irq)
1116 free_irq(nvt->cir_wake_irq, nvt);
1117 if (nvt->cir_wake_addr)
1118 release_region(nvt->cir_wake_addr, CIR_IOREG_LENGTH);
1119
1120 input_free_device(rdev);
1121 kfree(props);
1122 kfree(nvt);
1123
1124 return ret;
1125}
1126
1127static void __devexit nvt_remove(struct pnp_dev *pdev)
1128{
1129 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1130 unsigned long flags;
1131
1132 spin_lock_irqsave(&nvt->nvt_lock, flags);
1133 /* disable CIR */
1134 nvt_cir_reg_write(nvt, 0, CIR_IREN);
1135 nvt_disable_cir(nvt);
1136 /* enable CIR Wake (for IR power-on) */
1137 nvt_enable_wake(nvt);
1138 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1139
1140 /* free resources */
1141 free_irq(nvt->cir_irq, nvt);
1142 free_irq(nvt->cir_wake_irq, nvt);
1143 release_region(nvt->cir_addr, CIR_IOREG_LENGTH);
1144 release_region(nvt->cir_wake_addr, CIR_IOREG_LENGTH);
1145
1146 ir_input_unregister(nvt->rdev);
1147
1148 kfree(nvt->props);
1149 kfree(nvt);
1150}
1151
1152static int nvt_suspend(struct pnp_dev *pdev, pm_message_t state)
1153{
1154 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1155 unsigned long flags;
1156
1157 nvt_dbg("%s called", __func__);
1158
1159 /* zero out misc state tracking */
1160 spin_lock_irqsave(&nvt->nvt_lock, flags);
1161 nvt->study_state = ST_STUDY_NONE;
1162 nvt->wake_state = ST_WAKE_NONE;
1163 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1164
1165 spin_lock_irqsave(&nvt->tx.lock, flags);
1166 nvt->tx.tx_state = ST_TX_NONE;
1167 spin_unlock_irqrestore(&nvt->tx.lock, flags);
1168
1169 /* disable all CIR interrupts */
1170 nvt_cir_reg_write(nvt, 0, CIR_IREN);
1171
1172 nvt_efm_enable(nvt);
1173
1174 /* disable cir logical dev */
1175 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
1176 nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN);
1177
1178 nvt_efm_disable(nvt);
1179
1180 /* make sure wake is enabled */
1181 nvt_enable_wake(nvt);
1182
1183 return 0;
1184}
1185
1186static int nvt_resume(struct pnp_dev *pdev)
1187{
1188 int ret = 0;
1189 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1190
1191 nvt_dbg("%s called", __func__);
1192
1193 /* open interrupt */
fbdc781c 1194 nvt_set_cir_iren(nvt);
6d2f5c27
JW		 1195
1196 /* Enable CIR logical device */
1197 nvt_efm_enable(nvt);
1198 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
1199 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
1200
1201 nvt_efm_disable(nvt);
1202
1203 nvt_cir_regs_init(nvt);
1204 nvt_cir_wake_regs_init(nvt);
1205
1206 return ret;
1207}
1208
1209static void nvt_shutdown(struct pnp_dev *pdev)
1210{
1211 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1212 nvt_enable_wake(nvt);
1213}
1214
1215static const struct pnp_device_id nvt_ids[] = {
1216 { "WEC0530", 0 }, /* CIR */
1217 { "NTN0530", 0 }, /* CIR for new chip's pnp id*/
1218 { "", 0 },
1219};
1220
1221static struct pnp_driver nvt_driver = {
1222 .name = NVT_DRIVER_NAME,
1223 .id_table = nvt_ids,
1224 .flags = PNP_DRIVER_RES_DO_NOT_CHANGE,
1225 .probe = nvt_probe,
1226 .remove = __devexit_p(nvt_remove),
1227 .suspend = nvt_suspend,
1228 .resume = nvt_resume,
1229 .shutdown = nvt_shutdown,
1230};
1231
1232int nvt_init(void)
1233{
1234 return pnp_register_driver(&nvt_driver);
1235}
1236
1237void nvt_exit(void)
1238{
1239 pnp_unregister_driver(&nvt_driver);
1240}
1241
1242module_param(debug, int, S_IRUGO | S_IWUSR);
1243MODULE_PARM_DESC(debug, "Enable debugging output");
1244
1245MODULE_DEVICE_TABLE(pnp, nvt_ids);
1246MODULE_DESCRIPTION("Nuvoton W83667HG-A & W83677HG-I CIR driver");
1247
1248MODULE_AUTHOR("Jarod Wilson <jarod@redhat.com>");
1249MODULE_LICENSE("GPL");
1250
1251module_init(nvt_init);
1252module_exit(nvt_exit);
kernel source for telekom puls (alcatel/mediatek)