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[PATCH] via82cxxx: fix cable detection
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
18#include "kvm.h"
19#include "vmx.h"
20#include "kvm_vmx.h"
21#include <linux/module.h>
22#include <linux/mm.h>
23#include <linux/highmem.h>
24#include <asm/io.h>
3b3be0d1 25#include <asm/desc.h>
6aa8b732
AK		 26
27#include "segment_descriptor.h"
28
6aa8b732
AK		 29
30MODULE_AUTHOR("Qumranet");
31MODULE_LICENSE("GPL");
32
33static DEFINE_PER_CPU(struct vmcs *, vmxarea);
34static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
35
05b3e0c2 36#ifdef CONFIG_X86_64
6aa8b732
AK		 37#define HOST_IS_64 1
38#else
39#define HOST_IS_64 0
40#endif
41
42static struct vmcs_descriptor {
43 int size;
44 int order;
45 u32 revision_id;
46} vmcs_descriptor;
47
48#define VMX_SEGMENT_FIELD(seg) \
49 [VCPU_SREG_##seg] = { \
50 .selector = GUEST_##seg##_SELECTOR, \
51 .base = GUEST_##seg##_BASE, \
52 .limit = GUEST_##seg##_LIMIT, \
53 .ar_bytes = GUEST_##seg##_AR_BYTES, \
54 }
55
56static struct kvm_vmx_segment_field {
57 unsigned selector;
58 unsigned base;
59 unsigned limit;
60 unsigned ar_bytes;
61} kvm_vmx_segment_fields[] = {
62 VMX_SEGMENT_FIELD(CS),
63 VMX_SEGMENT_FIELD(DS),
64 VMX_SEGMENT_FIELD(ES),
65 VMX_SEGMENT_FIELD(FS),
66 VMX_SEGMENT_FIELD(GS),
67 VMX_SEGMENT_FIELD(SS),
68 VMX_SEGMENT_FIELD(TR),
69 VMX_SEGMENT_FIELD(LDTR),
70};
71
72static const u32 vmx_msr_index[] = {
05b3e0c2 73#ifdef CONFIG_X86_64
6aa8b732
AK		 74 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
75#endif
76 MSR_EFER, MSR_K6_STAR,
77};
78#define NR_VMX_MSR (sizeof(vmx_msr_index) / sizeof(*vmx_msr_index))
79
6aa8b732
AK		 80static inline int is_page_fault(u32 intr_info)
81{
82 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
83 INTR_INFO_VALID_MASK)) ==
84 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
85}
86
87static inline int is_external_interrupt(u32 intr_info)
88{
89 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
90 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
91}
92
7725f0ba
AK		 93static struct vmx_msr_entry *find_msr_entry(struct kvm_vcpu *vcpu, u32 msr)
94{
95 int i;
96
97 for (i = 0; i < vcpu->nmsrs; ++i)
98 if (vcpu->guest_msrs[i].index == msr)
99 return &vcpu->guest_msrs[i];
100 return 0;
101}
102
6aa8b732
AK		 103static void vmcs_clear(struct vmcs *vmcs)
104{
105 u64 phys_addr = __pa(vmcs);
106 u8 error;
107
108 asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0"
109 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
110 : "cc", "memory");
111 if (error)
112 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
113 vmcs, phys_addr);
114}
115
116static void __vcpu_clear(void *arg)
117{
118 struct kvm_vcpu *vcpu = arg;
119 int cpu = smp_processor_id();
120
121 if (vcpu->cpu == cpu)
122 vmcs_clear(vcpu->vmcs);
123 if (per_cpu(current_vmcs, cpu) == vcpu->vmcs)
124 per_cpu(current_vmcs, cpu) = NULL;
125}
126
127static unsigned long vmcs_readl(unsigned long field)
128{
129 unsigned long value;
130
131 asm volatile (ASM_VMX_VMREAD_RDX_RAX
132 : "=a"(value) : "d"(field) : "cc");
133 return value;
134}
135
136static u16 vmcs_read16(unsigned long field)
137{
138 return vmcs_readl(field);
139}
140
141static u32 vmcs_read32(unsigned long field)
142{
143 return vmcs_readl(field);
144}
145
146static u64 vmcs_read64(unsigned long field)
147{
05b3e0c2 148#ifdef CONFIG_X86_64
6aa8b732
AK		 149 return vmcs_readl(field);
150#else
151 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
152#endif
153}
154
155static void vmcs_writel(unsigned long field, unsigned long value)
156{
157 u8 error;
158
159 asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0"
160 : "=q"(error) : "a"(value), "d"(field) : "cc" );
161 if (error)
162 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
163 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
164}
165
166static void vmcs_write16(unsigned long field, u16 value)
167{
168 vmcs_writel(field, value);
169}
170
171static void vmcs_write32(unsigned long field, u32 value)
172{
173 vmcs_writel(field, value);
174}
175
176static void vmcs_write64(unsigned long field, u64 value)
177{
05b3e0c2 178#ifdef CONFIG_X86_64
6aa8b732
AK		 179 vmcs_writel(field, value);
180#else
181 vmcs_writel(field, value);
182 asm volatile ("");
183 vmcs_writel(field+1, value >> 32);
184#endif
185}
186
187/*
188 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
189 * vcpu mutex is already taken.
190 */
191static struct kvm_vcpu *vmx_vcpu_load(struct kvm_vcpu *vcpu)
192{
193 u64 phys_addr = __pa(vcpu->vmcs);
194 int cpu;
195
196 cpu = get_cpu();
197
198 if (vcpu->cpu != cpu) {
199 smp_call_function(__vcpu_clear, vcpu, 0, 1);
200 vcpu->launched = 0;
201 }
202
203 if (per_cpu(current_vmcs, cpu) != vcpu->vmcs) {
204 u8 error;
205
206 per_cpu(current_vmcs, cpu) = vcpu->vmcs;
207 asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0"
208 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
209 : "cc");
210 if (error)
211 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
212 vcpu->vmcs, phys_addr);
213 }
214
215 if (vcpu->cpu != cpu) {
216 struct descriptor_table dt;
217 unsigned long sysenter_esp;
218
219 vcpu->cpu = cpu;
220 /*
221 * Linux uses per-cpu TSS and GDT, so set these when switching
222 * processors.
223 */
224 vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */
225 get_gdt(&dt);
226 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
227
228 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
229 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
230 }
231 return vcpu;
232}
233
234static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
235{
236 put_cpu();
237}
238
239static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
240{
241 return vmcs_readl(GUEST_RFLAGS);
242}
243
244static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
245{
246 vmcs_writel(GUEST_RFLAGS, rflags);
247}
248
249static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
250{
251 unsigned long rip;
252 u32 interruptibility;
253
254 rip = vmcs_readl(GUEST_RIP);
255 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
256 vmcs_writel(GUEST_RIP, rip);
257
258 /*
259 * We emulated an instruction, so temporary interrupt blocking
260 * should be removed, if set.
261 */
262 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
263 if (interruptibility & 3)
264 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
265 interruptibility & ~3);
266}
267
268static void vmx_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code)
269{
270 printk(KERN_DEBUG "inject_general_protection: rip 0x%lx\n",
271 vmcs_readl(GUEST_RIP));
272 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
273 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
274 GP_VECTOR |
275 INTR_TYPE_EXCEPTION |
276 INTR_INFO_DELIEVER_CODE_MASK |
277 INTR_INFO_VALID_MASK);
278}
279
280/*
281 * reads and returns guest's timestamp counter "register"
282 * guest_tsc = host_tsc + tsc_offset -- 21.3
283 */
284static u64 guest_read_tsc(void)
285{
286 u64 host_tsc, tsc_offset;
287
288 rdtscll(host_tsc);
289 tsc_offset = vmcs_read64(TSC_OFFSET);
290 return host_tsc + tsc_offset;
291}
292
293/*
294 * writes 'guest_tsc' into guest's timestamp counter "register"
295 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
296 */
297static void guest_write_tsc(u64 guest_tsc)
298{
299 u64 host_tsc;
300
301 rdtscll(host_tsc);
302 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
303}
304
305static void reload_tss(void)
306{
05b3e0c2 307#ifndef CONFIG_X86_64
6aa8b732
AK		 308
309 /*
310 * VT restores TR but not its size. Useless.
311 */
312 struct descriptor_table gdt;
313 struct segment_descriptor *descs;
314
315 get_gdt(&gdt);
316 descs = (void *)gdt.base;
317 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
318 load_TR_desc();
319#endif
320}
321
322/*
323 * Reads an msr value (of 'msr_index') into 'pdata'.
324 * Returns 0 on success, non-0 otherwise.
325 * Assumes vcpu_load() was already called.
326 */
327static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
328{
329 u64 data;
330 struct vmx_msr_entry *msr;
331
332 if (!pdata) {
333 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
334 return -EINVAL;
335 }
336
337 switch (msr_index) {
05b3e0c2 338#ifdef CONFIG_X86_64
6aa8b732
AK		 339 case MSR_FS_BASE:
340 data = vmcs_readl(GUEST_FS_BASE);
341 break;
342 case MSR_GS_BASE:
343 data = vmcs_readl(GUEST_GS_BASE);
344 break;
345 case MSR_EFER:
3bab1f5d 346 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 347#endif
348 case MSR_IA32_TIME_STAMP_COUNTER:
349 data = guest_read_tsc();
350 break;
351 case MSR_IA32_SYSENTER_CS:
352 data = vmcs_read32(GUEST_SYSENTER_CS);
353 break;
354 case MSR_IA32_SYSENTER_EIP:
355 data = vmcs_read32(GUEST_SYSENTER_EIP);
356 break;
357 case MSR_IA32_SYSENTER_ESP:
358 data = vmcs_read32(GUEST_SYSENTER_ESP);
359 break;
6aa8b732
AK		 360 default:
361 msr = find_msr_entry(vcpu, msr_index);
3bab1f5d
AK		 362 if (msr) {
363 data = msr->data;
364 break;
6aa8b732 365 }
3bab1f5d 366 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 367 }
368
369 *pdata = data;
370 return 0;
371}
372
373/*
374 * Writes msr value into into the appropriate "register".
375 * Returns 0 on success, non-0 otherwise.
376 * Assumes vcpu_load() was already called.
377 */
378static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
379{
380 struct vmx_msr_entry *msr;
381 switch (msr_index) {
05b3e0c2 382#ifdef CONFIG_X86_64
3bab1f5d
AK		 383 case MSR_EFER:
384 return kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 385 case MSR_FS_BASE:
386 vmcs_writel(GUEST_FS_BASE, data);
387 break;
388 case MSR_GS_BASE:
389 vmcs_writel(GUEST_GS_BASE, data);
390 break;
391#endif
392 case MSR_IA32_SYSENTER_CS:
393 vmcs_write32(GUEST_SYSENTER_CS, data);
394 break;
395 case MSR_IA32_SYSENTER_EIP:
396 vmcs_write32(GUEST_SYSENTER_EIP, data);
397 break;
398 case MSR_IA32_SYSENTER_ESP:
399 vmcs_write32(GUEST_SYSENTER_ESP, data);
400 break;
6aa8b732
AK		 401 case MSR_IA32_TIME_STAMP_COUNTER: {
402 guest_write_tsc(data);
403 break;
404 }
6aa8b732
AK		 405 default:
406 msr = find_msr_entry(vcpu, msr_index);
3bab1f5d
AK		 407 if (msr) {
408 msr->data = data;
409 break;
6aa8b732 410 }
3bab1f5d 411 return kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 412 msr->data = data;
413 break;
414 }
415
416 return 0;
417}
418
419/*
420 * Sync the rsp and rip registers into the vcpu structure. This allows
421 * registers to be accessed by indexing vcpu->regs.
422 */
423static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu)
424{
425 vcpu->regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
426 vcpu->rip = vmcs_readl(GUEST_RIP);
427}
428
429/*
430 * Syncs rsp and rip back into the vmcs. Should be called after possible
431 * modification.
432 */
433static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu)
434{
435 vmcs_writel(GUEST_RSP, vcpu->regs[VCPU_REGS_RSP]);
436 vmcs_writel(GUEST_RIP, vcpu->rip);
437}
438
439static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
440{
441 unsigned long dr7 = 0x400;
442 u32 exception_bitmap;
443 int old_singlestep;
444
445 exception_bitmap = vmcs_read32(EXCEPTION_BITMAP);
446 old_singlestep = vcpu->guest_debug.singlestep;
447
448 vcpu->guest_debug.enabled = dbg->enabled;
449 if (vcpu->guest_debug.enabled) {
450 int i;
451
452 dr7 |= 0x200; /* exact */
453 for (i = 0; i < 4; ++i) {
454 if (!dbg->breakpoints[i].enabled)
455 continue;
456 vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
457 dr7 |= 2 << (i*2); /* global enable */
458 dr7 |= 0 << (i*4+16); /* execution breakpoint */
459 }
460
461 exception_bitmap |= (1u << 1); /* Trap debug exceptions */
462
463 vcpu->guest_debug.singlestep = dbg->singlestep;
464 } else {
465 exception_bitmap &= ~(1u << 1); /* Ignore debug exceptions */
466 vcpu->guest_debug.singlestep = 0;
467 }
468
469 if (old_singlestep && !vcpu->guest_debug.singlestep) {
470 unsigned long flags;
471
472 flags = vmcs_readl(GUEST_RFLAGS);
473 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
474 vmcs_writel(GUEST_RFLAGS, flags);
475 }
476
477 vmcs_write32(EXCEPTION_BITMAP, exception_bitmap);
478 vmcs_writel(GUEST_DR7, dr7);
479
480 return 0;
481}
482
483static __init int cpu_has_kvm_support(void)
484{
485 unsigned long ecx = cpuid_ecx(1);
486 return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
487}
488
489static __init int vmx_disabled_by_bios(void)
490{
491 u64 msr;
492
493 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
494 return (msr & 5) == 1; /* locked but not enabled */
495}
496
497static __init void hardware_enable(void *garbage)
498{
499 int cpu = raw_smp_processor_id();
500 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
501 u64 old;
502
503 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
bfdc0c28 504 if ((old & 5) != 5)
6aa8b732
AK		 505 /* enable and lock */
506 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | 5);
507 write_cr4(read_cr4() | CR4_VMXE); /* FIXME: not cpu hotplug safe */
508 asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr)
509 : "memory", "cc");
510}
511
512static void hardware_disable(void *garbage)
513{
514 asm volatile (ASM_VMX_VMXOFF : : : "cc");
515}
516
517static __init void setup_vmcs_descriptor(void)
518{
519 u32 vmx_msr_low, vmx_msr_high;
520
c68876fd 521 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
6aa8b732
AK		 522 vmcs_descriptor.size = vmx_msr_high & 0x1fff;
523 vmcs_descriptor.order = get_order(vmcs_descriptor.size);
524 vmcs_descriptor.revision_id = vmx_msr_low;
c68876fd 525}
6aa8b732
AK		 526
527static struct vmcs *alloc_vmcs_cpu(int cpu)
528{
529 int node = cpu_to_node(cpu);
530 struct page *pages;
531 struct vmcs *vmcs;
532
533 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_descriptor.order);
534 if (!pages)
535 return NULL;
536 vmcs = page_address(pages);
537 memset(vmcs, 0, vmcs_descriptor.size);
538 vmcs->revision_id = vmcs_descriptor.revision_id; /* vmcs revision id */
539 return vmcs;
540}
541
542static struct vmcs *alloc_vmcs(void)
543{
544 return alloc_vmcs_cpu(smp_processor_id());
545}
546
547static void free_vmcs(struct vmcs *vmcs)
548{
549 free_pages((unsigned long)vmcs, vmcs_descriptor.order);
550}
551
552static __exit void free_kvm_area(void)
553{
554 int cpu;
555
556 for_each_online_cpu(cpu)
557 free_vmcs(per_cpu(vmxarea, cpu));
558}
559
560extern struct vmcs *alloc_vmcs_cpu(int cpu);
561
562static __init int alloc_kvm_area(void)
563{
564 int cpu;
565
566 for_each_online_cpu(cpu) {
567 struct vmcs *vmcs;
568
569 vmcs = alloc_vmcs_cpu(cpu);
570 if (!vmcs) {
571 free_kvm_area();
572 return -ENOMEM;
573 }
574
575 per_cpu(vmxarea, cpu) = vmcs;
576 }
577 return 0;
578}
579
580static __init int hardware_setup(void)
581{
582 setup_vmcs_descriptor();
583 return alloc_kvm_area();
584}
585
586static __exit void hardware_unsetup(void)
587{
588 free_kvm_area();
589}
590
591static void update_exception_bitmap(struct kvm_vcpu *vcpu)
592{
593 if (vcpu->rmode.active)
594 vmcs_write32(EXCEPTION_BITMAP, ~0);
595 else
596 vmcs_write32(EXCEPTION_BITMAP, 1 << PF_VECTOR);
597}
598
599static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
600{
601 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
602
603 if (vmcs_readl(sf->base) == save->base) {
604 vmcs_write16(sf->selector, save->selector);
605 vmcs_writel(sf->base, save->base);
606 vmcs_write32(sf->limit, save->limit);
607 vmcs_write32(sf->ar_bytes, save->ar);
608 } else {
609 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
610 << AR_DPL_SHIFT;
611 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
612 }
613}
614
615static void enter_pmode(struct kvm_vcpu *vcpu)
616{
617 unsigned long flags;
618
619 vcpu->rmode.active = 0;
620
621 vmcs_writel(GUEST_TR_BASE, vcpu->rmode.tr.base);
622 vmcs_write32(GUEST_TR_LIMIT, vcpu->rmode.tr.limit);
623 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->rmode.tr.ar);
624
625 flags = vmcs_readl(GUEST_RFLAGS);
626 flags &= ~(IOPL_MASK | X86_EFLAGS_VM);
627 flags |= (vcpu->rmode.save_iopl << IOPL_SHIFT);
628 vmcs_writel(GUEST_RFLAGS, flags);
629
630 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~CR4_VME_MASK) |
631 (vmcs_readl(CR4_READ_SHADOW) & CR4_VME_MASK));
632
633 update_exception_bitmap(vcpu);
634
635 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->rmode.es);
636 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->rmode.ds);
637 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->rmode.gs);
638 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->rmode.fs);
639
640 vmcs_write16(GUEST_SS_SELECTOR, 0);
641 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
642
643 vmcs_write16(GUEST_CS_SELECTOR,
644 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
645 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
646}
647
648static int rmode_tss_base(struct kvm* kvm)
649{
650 gfn_t base_gfn = kvm->memslots[0].base_gfn + kvm->memslots[0].npages - 3;
651 return base_gfn << PAGE_SHIFT;
652}
653
654static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
655{
656 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
657
658 save->selector = vmcs_read16(sf->selector);
659 save->base = vmcs_readl(sf->base);
660 save->limit = vmcs_read32(sf->limit);
661 save->ar = vmcs_read32(sf->ar_bytes);
662 vmcs_write16(sf->selector, vmcs_readl(sf->base) >> 4);
663 vmcs_write32(sf->limit, 0xffff);
664 vmcs_write32(sf->ar_bytes, 0xf3);
665}
666
667static void enter_rmode(struct kvm_vcpu *vcpu)
668{
669 unsigned long flags;
670
671 vcpu->rmode.active = 1;
672
673 vcpu->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
674 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
675
676 vcpu->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
677 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
678
679 vcpu->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
680 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
681
682 flags = vmcs_readl(GUEST_RFLAGS);
683 vcpu->rmode.save_iopl = (flags & IOPL_MASK) >> IOPL_SHIFT;
684
685 flags |= IOPL_MASK | X86_EFLAGS_VM;
686
687 vmcs_writel(GUEST_RFLAGS, flags);
688 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | CR4_VME_MASK);
689 update_exception_bitmap(vcpu);
690
691 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
692 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
693 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
694
695 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 696 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
6aa8b732
AK		 697 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
698
699 fix_rmode_seg(VCPU_SREG_ES, &vcpu->rmode.es);
700 fix_rmode_seg(VCPU_SREG_DS, &vcpu->rmode.ds);
701 fix_rmode_seg(VCPU_SREG_GS, &vcpu->rmode.gs);
702 fix_rmode_seg(VCPU_SREG_FS, &vcpu->rmode.fs);
703}
704
05b3e0c2 705#ifdef CONFIG_X86_64
6aa8b732
AK		 706
707static void enter_lmode(struct kvm_vcpu *vcpu)
708{
709 u32 guest_tr_ar;
710
711 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
712 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
713 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
714 __FUNCTION__);
715 vmcs_write32(GUEST_TR_AR_BYTES,
716 (guest_tr_ar & ~AR_TYPE_MASK)
717 | AR_TYPE_BUSY_64_TSS);
718 }
719
720 vcpu->shadow_efer |= EFER_LMA;
721
722 find_msr_entry(vcpu, MSR_EFER)->data |= EFER_LMA | EFER_LME;
723 vmcs_write32(VM_ENTRY_CONTROLS,
724 vmcs_read32(VM_ENTRY_CONTROLS)
725 | VM_ENTRY_CONTROLS_IA32E_MASK);
726}
727
728static void exit_lmode(struct kvm_vcpu *vcpu)
729{
730 vcpu->shadow_efer &= ~EFER_LMA;
731
732 vmcs_write32(VM_ENTRY_CONTROLS,
733 vmcs_read32(VM_ENTRY_CONTROLS)
734 & ~VM_ENTRY_CONTROLS_IA32E_MASK);
735}
736
737#endif
738
739static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
740{
741 if (vcpu->rmode.active && (cr0 & CR0_PE_MASK))
742 enter_pmode(vcpu);
743
744 if (!vcpu->rmode.active && !(cr0 & CR0_PE_MASK))
745 enter_rmode(vcpu);
746
05b3e0c2 747#ifdef CONFIG_X86_64
6aa8b732
AK		 748 if (vcpu->shadow_efer & EFER_LME) {
749 if (!is_paging(vcpu) && (cr0 & CR0_PG_MASK))
750 enter_lmode(vcpu);
751 if (is_paging(vcpu) && !(cr0 & CR0_PG_MASK))
752 exit_lmode(vcpu);
753 }
754#endif
755
756 vmcs_writel(CR0_READ_SHADOW, cr0);
757 vmcs_writel(GUEST_CR0,
758 (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
759 vcpu->cr0 = cr0;
760}
761
762/*
763 * Used when restoring the VM to avoid corrupting segment registers
764 */
765static void vmx_set_cr0_no_modeswitch(struct kvm_vcpu *vcpu, unsigned long cr0)
766{
767 vcpu->rmode.active = ((cr0 & CR0_PE_MASK) == 0);
768 update_exception_bitmap(vcpu);
769 vmcs_writel(CR0_READ_SHADOW, cr0);
770 vmcs_writel(GUEST_CR0,
771 (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
772 vcpu->cr0 = cr0;
773}
774
775static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
776{
777 vmcs_writel(GUEST_CR3, cr3);
778}
779
780static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
781{
782 vmcs_writel(CR4_READ_SHADOW, cr4);
783 vmcs_writel(GUEST_CR4, cr4 | (vcpu->rmode.active ?
784 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON));
785 vcpu->cr4 = cr4;
786}
787
05b3e0c2 788#ifdef CONFIG_X86_64
6aa8b732
AK		 789
790static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
791{
792 struct vmx_msr_entry *msr = find_msr_entry(vcpu, MSR_EFER);
793
794 vcpu->shadow_efer = efer;
795 if (efer & EFER_LMA) {
796 vmcs_write32(VM_ENTRY_CONTROLS,
797 vmcs_read32(VM_ENTRY_CONTROLS) |
798 VM_ENTRY_CONTROLS_IA32E_MASK);
799 msr->data = efer;
800
801 } else {
802 vmcs_write32(VM_ENTRY_CONTROLS,
803 vmcs_read32(VM_ENTRY_CONTROLS) &
804 ~VM_ENTRY_CONTROLS_IA32E_MASK);
805
806 msr->data = efer & ~EFER_LME;
807 }
808}
809
810#endif
811
812static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
813{
814 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
815
816 return vmcs_readl(sf->base);
817}
818
819static void vmx_get_segment(struct kvm_vcpu *vcpu,
820 struct kvm_segment *var, int seg)
821{
822 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
823 u32 ar;
824
825 var->base = vmcs_readl(sf->base);
826 var->limit = vmcs_read32(sf->limit);
827 var->selector = vmcs_read16(sf->selector);
828 ar = vmcs_read32(sf->ar_bytes);
829 if (ar & AR_UNUSABLE_MASK)
830 ar = 0;
831 var->type = ar & 15;
832 var->s = (ar >> 4) & 1;
833 var->dpl = (ar >> 5) & 3;
834 var->present = (ar >> 7) & 1;
835 var->avl = (ar >> 12) & 1;
836 var->l = (ar >> 13) & 1;
837 var->db = (ar >> 14) & 1;
838 var->g = (ar >> 15) & 1;
839 var->unusable = (ar >> 16) & 1;
840}
841
842static void vmx_set_segment(struct kvm_vcpu *vcpu,
843 struct kvm_segment *var, int seg)
844{
845 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
846 u32 ar;
847
848 vmcs_writel(sf->base, var->base);
849 vmcs_write32(sf->limit, var->limit);
850 vmcs_write16(sf->selector, var->selector);
851 if (var->unusable)
852 ar = 1 << 16;
853 else {
854 ar = var->type & 15;
855 ar |= (var->s & 1) << 4;
856 ar |= (var->dpl & 3) << 5;
857 ar |= (var->present & 1) << 7;
858 ar |= (var->avl & 1) << 12;
859 ar |= (var->l & 1) << 13;
860 ar |= (var->db & 1) << 14;
861 ar |= (var->g & 1) << 15;
862 }
f7fbf1fd
UL		 863 if (ar == 0) /* a 0 value means unusable */
864 ar = AR_UNUSABLE_MASK;
6aa8b732
AK		 865 vmcs_write32(sf->ar_bytes, ar);
866}
867
6aa8b732
AK		 868static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
869{
870 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
871
872 *db = (ar >> 14) & 1;
873 *l = (ar >> 13) & 1;
874}
875
876static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
877{
878 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
879 dt->base = vmcs_readl(GUEST_IDTR_BASE);
880}
881
882static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
883{
884 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
885 vmcs_writel(GUEST_IDTR_BASE, dt->base);
886}
887
888static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
889{
890 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
891 dt->base = vmcs_readl(GUEST_GDTR_BASE);
892}
893
894static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
895{
896 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
897 vmcs_writel(GUEST_GDTR_BASE, dt->base);
898}
899
900static int init_rmode_tss(struct kvm* kvm)
901{
902 struct page *p1, *p2, *p3;
903 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
904 char *page;
905
906 p1 = _gfn_to_page(kvm, fn++);
907 p2 = _gfn_to_page(kvm, fn++);
908 p3 = _gfn_to_page(kvm, fn);
909
910 if (!p1 || !p2 || !p3) {
911 kvm_printf(kvm,"%s: gfn_to_page failed\n", __FUNCTION__);
912 return 0;
913 }
914
915 page = kmap_atomic(p1, KM_USER0);
916 memset(page, 0, PAGE_SIZE);
917 *(u16*)(page + 0x66) = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
918 kunmap_atomic(page, KM_USER0);
919
920 page = kmap_atomic(p2, KM_USER0);
921 memset(page, 0, PAGE_SIZE);
922 kunmap_atomic(page, KM_USER0);
923
924 page = kmap_atomic(p3, KM_USER0);
925 memset(page, 0, PAGE_SIZE);
926 *(page + RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1) = ~0;
927 kunmap_atomic(page, KM_USER0);
928
929 return 1;
930}
931
932static void vmcs_write32_fixedbits(u32 msr, u32 vmcs_field, u32 val)
933{
934 u32 msr_high, msr_low;
935
936 rdmsr(msr, msr_low, msr_high);
937
938 val &= msr_high;
939 val |= msr_low;
940 vmcs_write32(vmcs_field, val);
941}
942
943static void seg_setup(int seg)
944{
945 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
946
947 vmcs_write16(sf->selector, 0);
948 vmcs_writel(sf->base, 0);
949 vmcs_write32(sf->limit, 0xffff);
950 vmcs_write32(sf->ar_bytes, 0x93);
951}
952
953/*
954 * Sets up the vmcs for emulated real mode.
955 */
956static int vmx_vcpu_setup(struct kvm_vcpu *vcpu)
957{
958 u32 host_sysenter_cs;
959 u32 junk;
960 unsigned long a;
961 struct descriptor_table dt;
962 int i;
963 int ret = 0;
964 int nr_good_msrs;
965 extern asmlinkage void kvm_vmx_return(void);
966
967 if (!init_rmode_tss(vcpu->kvm)) {
968 ret = -ENOMEM;
969 goto out;
970 }
971
972 memset(vcpu->regs, 0, sizeof(vcpu->regs));
973 vcpu->regs[VCPU_REGS_RDX] = get_rdx_init_val();
974 vcpu->cr8 = 0;
975 vcpu->apic_base = 0xfee00000 |
976 /*for vcpu 0*/ MSR_IA32_APICBASE_BSP |
977 MSR_IA32_APICBASE_ENABLE;
978
979 fx_init(vcpu);
980
981 /*
982 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
983 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
984 */
985 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
986 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
987 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
988 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
989
990 seg_setup(VCPU_SREG_DS);
991 seg_setup(VCPU_SREG_ES);
992 seg_setup(VCPU_SREG_FS);
993 seg_setup(VCPU_SREG_GS);
994 seg_setup(VCPU_SREG_SS);
995
996 vmcs_write16(GUEST_TR_SELECTOR, 0);
997 vmcs_writel(GUEST_TR_BASE, 0);
998 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
999 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1000
1001 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
1002 vmcs_writel(GUEST_LDTR_BASE, 0);
1003 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
1004 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
1005
1006 vmcs_write32(GUEST_SYSENTER_CS, 0);
1007 vmcs_writel(GUEST_SYSENTER_ESP, 0);
1008 vmcs_writel(GUEST_SYSENTER_EIP, 0);
1009
1010 vmcs_writel(GUEST_RFLAGS, 0x02);
1011 vmcs_writel(GUEST_RIP, 0xfff0);
1012 vmcs_writel(GUEST_RSP, 0);
1013
1014 vmcs_writel(GUEST_CR3, 0);
1015
1016 //todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0
1017 vmcs_writel(GUEST_DR7, 0x400);
1018
1019 vmcs_writel(GUEST_GDTR_BASE, 0);
1020 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
1021
1022 vmcs_writel(GUEST_IDTR_BASE, 0);
1023 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
1024
1025 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
1026 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
1027 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
1028
1029 /* I/O */
1030 vmcs_write64(IO_BITMAP_A, 0);
1031 vmcs_write64(IO_BITMAP_B, 0);
1032
1033 guest_write_tsc(0);
1034
1035 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1036
1037 /* Special registers */
1038 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
1039
1040 /* Control */
c68876fd 1041 vmcs_write32_fixedbits(MSR_IA32_VMX_PINBASED_CTLS,
6aa8b732
AK		 1042 PIN_BASED_VM_EXEC_CONTROL,
1043 PIN_BASED_EXT_INTR_MASK /* 20.6.1 */
1044 | PIN_BASED_NMI_EXITING /* 20.6.1 */
1045 );
c68876fd 1046 vmcs_write32_fixedbits(MSR_IA32_VMX_PROCBASED_CTLS,
6aa8b732
AK		 1047 CPU_BASED_VM_EXEC_CONTROL,
1048 CPU_BASED_HLT_EXITING /* 20.6.2 */
1049 | CPU_BASED_CR8_LOAD_EXITING /* 20.6.2 */
1050 | CPU_BASED_CR8_STORE_EXITING /* 20.6.2 */
1051 | CPU_BASED_UNCOND_IO_EXITING /* 20.6.2 */
1052 | CPU_BASED_INVDPG_EXITING
1053 | CPU_BASED_MOV_DR_EXITING
1054 | CPU_BASED_USE_TSC_OFFSETING /* 21.3 */
1055 );
1056
1057 vmcs_write32(EXCEPTION_BITMAP, 1 << PF_VECTOR);
1058 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
1059 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
1060 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
1061
1062 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
1063 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
1064 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
1065
1066 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
1067 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1068 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1069 vmcs_write16(HOST_FS_SELECTOR, read_fs()); /* 22.2.4 */
1070 vmcs_write16(HOST_GS_SELECTOR, read_gs()); /* 22.2.4 */
1071 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 1072#ifdef CONFIG_X86_64
6aa8b732
AK		 1073 rdmsrl(MSR_FS_BASE, a);
1074 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1075 rdmsrl(MSR_GS_BASE, a);
1076 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1077#else
1078 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1079 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1080#endif
1081
1082 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
1083
1084 get_idt(&dt);
1085 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
1086
1087
1088 vmcs_writel(HOST_RIP, (unsigned long)kvm_vmx_return); /* 22.2.5 */
1089
1090 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1091 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1092 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1093 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
1094 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1095 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
1096
1097 ret = -ENOMEM;
1098 vcpu->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
1099 if (!vcpu->guest_msrs)
1100 goto out;
1101 vcpu->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
1102 if (!vcpu->host_msrs)
1103 goto out_free_guest_msrs;
1104
1105 for (i = 0; i < NR_VMX_MSR; ++i) {
1106 u32 index = vmx_msr_index[i];
1107 u32 data_low, data_high;
1108 u64 data;
1109 int j = vcpu->nmsrs;
1110
1111 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1112 continue;
1113 data = data_low | ((u64)data_high << 32);
1114 vcpu->host_msrs[j].index = index;
1115 vcpu->host_msrs[j].reserved = 0;
1116 vcpu->host_msrs[j].data = data;
1117 vcpu->guest_msrs[j] = vcpu->host_msrs[j];
1118 ++vcpu->nmsrs;
1119 }
1120 printk(KERN_DEBUG "kvm: msrs: %d\n", vcpu->nmsrs);
1121
1122 nr_good_msrs = vcpu->nmsrs - NR_BAD_MSRS;
1123 vmcs_writel(VM_ENTRY_MSR_LOAD_ADDR,
1124 virt_to_phys(vcpu->guest_msrs + NR_BAD_MSRS));
1125 vmcs_writel(VM_EXIT_MSR_STORE_ADDR,
1126 virt_to_phys(vcpu->guest_msrs + NR_BAD_MSRS));
1127 vmcs_writel(VM_EXIT_MSR_LOAD_ADDR,
1128 virt_to_phys(vcpu->host_msrs + NR_BAD_MSRS));
c68876fd 1129 vmcs_write32_fixedbits(MSR_IA32_VMX_EXIT_CTLS, VM_EXIT_CONTROLS,
6aa8b732
AK		 1130 (HOST_IS_64 << 9)); /* 22.2,1, 20.7.1 */
1131 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, nr_good_msrs); /* 22.2.2 */
1132 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, nr_good_msrs); /* 22.2.2 */
1133 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, nr_good_msrs); /* 22.2.2 */
1134
1135
1136 /* 22.2.1, 20.8.1 */
c68876fd 1137 vmcs_write32_fixedbits(MSR_IA32_VMX_ENTRY_CTLS,
6aa8b732
AK		 1138 VM_ENTRY_CONTROLS, 0);
1139 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
1140
3b99ab24 1141#ifdef CONFIG_X86_64
6aa8b732
AK		 1142 vmcs_writel(VIRTUAL_APIC_PAGE_ADDR, 0);
1143 vmcs_writel(TPR_THRESHOLD, 0);
3b99ab24 1144#endif
6aa8b732
AK		 1145
1146 vmcs_writel(CR0_GUEST_HOST_MASK, KVM_GUEST_CR0_MASK);
1147 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1148
1149 vcpu->cr0 = 0x60000010;
1150 vmx_set_cr0(vcpu, vcpu->cr0); // enter rmode
1151 vmx_set_cr4(vcpu, 0);
05b3e0c2 1152#ifdef CONFIG_X86_64
6aa8b732
AK		 1153 vmx_set_efer(vcpu, 0);
1154#endif
1155
1156 return 0;
1157
1158out_free_guest_msrs:
1159 kfree(vcpu->guest_msrs);
1160out:
1161 return ret;
1162}
1163
1164static void inject_rmode_irq(struct kvm_vcpu *vcpu, int irq)
1165{
1166 u16 ent[2];
1167 u16 cs;
1168 u16 ip;
1169 unsigned long flags;
1170 unsigned long ss_base = vmcs_readl(GUEST_SS_BASE);
1171 u16 sp = vmcs_readl(GUEST_RSP);
1172 u32 ss_limit = vmcs_read32(GUEST_SS_LIMIT);
1173
1174 if (sp > ss_limit || sp - 6 > sp) {
1175 vcpu_printf(vcpu, "%s: #SS, rsp 0x%lx ss 0x%lx limit 0x%x\n",
1176 __FUNCTION__,
1177 vmcs_readl(GUEST_RSP),
1178 vmcs_readl(GUEST_SS_BASE),
1179 vmcs_read32(GUEST_SS_LIMIT));
1180 return;
1181 }
1182
1183 if (kvm_read_guest(vcpu, irq * sizeof(ent), sizeof(ent), &ent) !=
1184 sizeof(ent)) {
1185 vcpu_printf(vcpu, "%s: read guest err\n", __FUNCTION__);
1186 return;
1187 }
1188
1189 flags = vmcs_readl(GUEST_RFLAGS);
1190 cs = vmcs_readl(GUEST_CS_BASE) >> 4;
1191 ip = vmcs_readl(GUEST_RIP);
1192
1193
1194 if (kvm_write_guest(vcpu, ss_base + sp - 2, 2, &flags) != 2 ||
1195 kvm_write_guest(vcpu, ss_base + sp - 4, 2, &cs) != 2 ||
1196 kvm_write_guest(vcpu, ss_base + sp - 6, 2, &ip) != 2) {
1197 vcpu_printf(vcpu, "%s: write guest err\n", __FUNCTION__);
1198 return;
1199 }
1200
1201 vmcs_writel(GUEST_RFLAGS, flags &
1202 ~( X86_EFLAGS_IF | X86_EFLAGS_AC | X86_EFLAGS_TF));
1203 vmcs_write16(GUEST_CS_SELECTOR, ent[1]) ;
1204 vmcs_writel(GUEST_CS_BASE, ent[1] << 4);
1205 vmcs_writel(GUEST_RIP, ent[0]);
1206 vmcs_writel(GUEST_RSP, (vmcs_readl(GUEST_RSP) & ~0xffff) | (sp - 6));
1207}
1208
1209static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
1210{
1211 int word_index = __ffs(vcpu->irq_summary);
1212 int bit_index = __ffs(vcpu->irq_pending[word_index]);
1213 int irq = word_index * BITS_PER_LONG + bit_index;
1214
1215 clear_bit(bit_index, &vcpu->irq_pending[word_index]);
1216 if (!vcpu->irq_pending[word_index])
1217 clear_bit(word_index, &vcpu->irq_summary);
1218
1219 if (vcpu->rmode.active) {
1220 inject_rmode_irq(vcpu, irq);
1221 return;
1222 }
1223 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1224 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1225}
1226
1227static void kvm_try_inject_irq(struct kvm_vcpu *vcpu)
1228{
1229 if ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF)
1230 && (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0)
1231 /*
1232 * Interrupts enabled, and not blocked by sti or mov ss. Good.
1233 */
1234 kvm_do_inject_irq(vcpu);
1235 else
1236 /*
1237 * Interrupts blocked. Wait for unblock.
1238 */
1239 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1240 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL)
1241 | CPU_BASED_VIRTUAL_INTR_PENDING);
1242}
1243
1244static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
1245{
1246 struct kvm_guest_debug *dbg = &vcpu->guest_debug;
1247
1248 set_debugreg(dbg->bp[0], 0);
1249 set_debugreg(dbg->bp[1], 1);
1250 set_debugreg(dbg->bp[2], 2);
1251 set_debugreg(dbg->bp[3], 3);
1252
1253 if (dbg->singlestep) {
1254 unsigned long flags;
1255
1256 flags = vmcs_readl(GUEST_RFLAGS);
1257 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1258 vmcs_writel(GUEST_RFLAGS, flags);
1259 }
1260}
1261
1262static int handle_rmode_exception(struct kvm_vcpu *vcpu,
1263 int vec, u32 err_code)
1264{
1265 if (!vcpu->rmode.active)
1266 return 0;
1267
1268 if (vec == GP_VECTOR && err_code == 0)
1269 if (emulate_instruction(vcpu, NULL, 0, 0) == EMULATE_DONE)
1270 return 1;
1271 return 0;
1272}
1273
1274static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1275{
1276 u32 intr_info, error_code;
1277 unsigned long cr2, rip;
1278 u32 vect_info;
1279 enum emulation_result er;
1280
1281 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
1282 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
1283
1284 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
1285 !is_page_fault(intr_info)) {
1286 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
1287 "intr info 0x%x\n", __FUNCTION__, vect_info, intr_info);
1288 }
1289
1290 if (is_external_interrupt(vect_info)) {
1291 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
1292 set_bit(irq, vcpu->irq_pending);
1293 set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
1294 }
1295
1296 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) { /* nmi */
1297 asm ("int $2");
1298 return 1;
1299 }
1300 error_code = 0;
1301 rip = vmcs_readl(GUEST_RIP);
1302 if (intr_info & INTR_INFO_DELIEVER_CODE_MASK)
1303 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
1304 if (is_page_fault(intr_info)) {
1305 cr2 = vmcs_readl(EXIT_QUALIFICATION);
1306
1307 spin_lock(&vcpu->kvm->lock);
1308 if (!vcpu->mmu.page_fault(vcpu, cr2, error_code)) {
1309 spin_unlock(&vcpu->kvm->lock);
1310 return 1;
1311 }
1312
1313 er = emulate_instruction(vcpu, kvm_run, cr2, error_code);
1314 spin_unlock(&vcpu->kvm->lock);
1315
1316 switch (er) {
1317 case EMULATE_DONE:
1318 return 1;
1319 case EMULATE_DO_MMIO:
1320 ++kvm_stat.mmio_exits;
1321 kvm_run->exit_reason = KVM_EXIT_MMIO;
1322 return 0;
1323 case EMULATE_FAIL:
1324 vcpu_printf(vcpu, "%s: emulate fail\n", __FUNCTION__);
1325 break;
1326 default:
1327 BUG();
1328 }
1329 }
1330
1331 if (vcpu->rmode.active &&
1332 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
1333 error_code))
1334 return 1;
1335
1336 if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) == (INTR_TYPE_EXCEPTION | 1)) {
1337 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1338 return 0;
1339 }
1340 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
1341 kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
1342 kvm_run->ex.error_code = error_code;
1343 return 0;
1344}
1345
1346static int handle_external_interrupt(struct kvm_vcpu *vcpu,
1347 struct kvm_run *kvm_run)
1348{
1349 ++kvm_stat.irq_exits;
1350 return 1;
1351}
1352
1353
1354static int get_io_count(struct kvm_vcpu *vcpu, u64 *count)
1355{
1356 u64 inst;
1357 gva_t rip;
1358 int countr_size;
1359 int i, n;
1360
1361 if ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_VM)) {
1362 countr_size = 2;
1363 } else {
1364 u32 cs_ar = vmcs_read32(GUEST_CS_AR_BYTES);
1365
1366 countr_size = (cs_ar & AR_L_MASK) ? 8:
1367 (cs_ar & AR_DB_MASK) ? 4: 2;
1368 }
1369
1370 rip = vmcs_readl(GUEST_RIP);
1371 if (countr_size != 8)
1372 rip += vmcs_readl(GUEST_CS_BASE);
1373
1374 n = kvm_read_guest(vcpu, rip, sizeof(inst), &inst);
1375
1376 for (i = 0; i < n; i++) {
1377 switch (((u8*)&inst)[i]) {
1378 case 0xf0:
1379 case 0xf2:
1380 case 0xf3:
1381 case 0x2e:
1382 case 0x36:
1383 case 0x3e:
1384 case 0x26:
1385 case 0x64:
1386 case 0x65:
1387 case 0x66:
1388 break;
1389 case 0x67:
1390 countr_size = (countr_size == 2) ? 4: (countr_size >> 1);
1391 default:
1392 goto done;
1393 }
1394 }
1395 return 0;
1396done:
1397 countr_size *= 8;
1398 *count = vcpu->regs[VCPU_REGS_RCX] & (~0ULL >> (64 - countr_size));
1399 return 1;
1400}
1401
1402static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1403{
1404 u64 exit_qualification;
1405
1406 ++kvm_stat.io_exits;
1407 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
1408 kvm_run->exit_reason = KVM_EXIT_IO;
1409 if (exit_qualification & 8)
1410 kvm_run->io.direction = KVM_EXIT_IO_IN;
1411 else
1412 kvm_run->io.direction = KVM_EXIT_IO_OUT;
1413 kvm_run->io.size = (exit_qualification & 7) + 1;
1414 kvm_run->io.string = (exit_qualification & 16) != 0;
1415 kvm_run->io.string_down
1416 = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
1417 kvm_run->io.rep = (exit_qualification & 32) != 0;
1418 kvm_run->io.port = exit_qualification >> 16;
1419 if (kvm_run->io.string) {
1420 if (!get_io_count(vcpu, &kvm_run->io.count))
1421 return 1;
1422 kvm_run->io.address = vmcs_readl(GUEST_LINEAR_ADDRESS);
1423 } else
1424 kvm_run->io.value = vcpu->regs[VCPU_REGS_RAX]; /* rax */
1425 return 0;
1426}
1427
1428static int handle_invlpg(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1429{
1430 u64 address = vmcs_read64(EXIT_QUALIFICATION);
1431 int instruction_length = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1432 spin_lock(&vcpu->kvm->lock);
1433 vcpu->mmu.inval_page(vcpu, address);
1434 spin_unlock(&vcpu->kvm->lock);
1435 vmcs_writel(GUEST_RIP, vmcs_readl(GUEST_RIP) + instruction_length);
1436 return 1;
1437}
1438
1439static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1440{
1441 u64 exit_qualification;
1442 int cr;
1443 int reg;
1444
1445 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
1446 cr = exit_qualification & 15;
1447 reg = (exit_qualification >> 8) & 15;
1448 switch ((exit_qualification >> 4) & 3) {
1449 case 0: /* mov to cr */
1450 switch (cr) {
1451 case 0:
1452 vcpu_load_rsp_rip(vcpu);
1453 set_cr0(vcpu, vcpu->regs[reg]);
1454 skip_emulated_instruction(vcpu);
1455 return 1;
1456 case 3:
1457 vcpu_load_rsp_rip(vcpu);
1458 set_cr3(vcpu, vcpu->regs[reg]);
1459 skip_emulated_instruction(vcpu);
1460 return 1;
1461 case 4:
1462 vcpu_load_rsp_rip(vcpu);
1463 set_cr4(vcpu, vcpu->regs[reg]);
1464 skip_emulated_instruction(vcpu);
1465 return 1;
1466 case 8:
1467 vcpu_load_rsp_rip(vcpu);
1468 set_cr8(vcpu, vcpu->regs[reg]);
1469 skip_emulated_instruction(vcpu);
1470 return 1;
1471 };
1472 break;
1473 case 1: /*mov from cr*/
1474 switch (cr) {
1475 case 3:
1476 vcpu_load_rsp_rip(vcpu);
1477 vcpu->regs[reg] = vcpu->cr3;
1478 vcpu_put_rsp_rip(vcpu);
1479 skip_emulated_instruction(vcpu);
1480 return 1;
1481 case 8:
1482 printk(KERN_DEBUG "handle_cr: read CR8 "
1483 "cpu erratum AA15\n");
1484 vcpu_load_rsp_rip(vcpu);
1485 vcpu->regs[reg] = vcpu->cr8;
1486 vcpu_put_rsp_rip(vcpu);
1487 skip_emulated_instruction(vcpu);
1488 return 1;
1489 }
1490 break;
1491 case 3: /* lmsw */
1492 lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
1493
1494 skip_emulated_instruction(vcpu);
1495 return 1;
1496 default:
1497 break;
1498 }
1499 kvm_run->exit_reason = 0;
1500 printk(KERN_ERR "kvm: unhandled control register: op %d cr %d\n",
1501 (int)(exit_qualification >> 4) & 3, cr);
1502 return 0;
1503}
1504
1505static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1506{
1507 u64 exit_qualification;
1508 unsigned long val;
1509 int dr, reg;
1510
1511 /*
1512 * FIXME: this code assumes the host is debugging the guest.
1513 * need to deal with guest debugging itself too.
1514 */
1515 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
1516 dr = exit_qualification & 7;
1517 reg = (exit_qualification >> 8) & 15;
1518 vcpu_load_rsp_rip(vcpu);
1519 if (exit_qualification & 16) {
1520 /* mov from dr */
1521 switch (dr) {
1522 case 6:
1523 val = 0xffff0ff0;
1524 break;
1525 case 7:
1526 val = 0x400;
1527 break;
1528 default:
1529 val = 0;
1530 }
1531 vcpu->regs[reg] = val;
1532 } else {
1533 /* mov to dr */
1534 }
1535 vcpu_put_rsp_rip(vcpu);
1536 skip_emulated_instruction(vcpu);
1537 return 1;
1538}
1539
1540static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1541{
1542 kvm_run->exit_reason = KVM_EXIT_CPUID;
1543 return 0;
1544}
1545
1546static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1547{
1548 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1549 u64 data;
1550
1551 if (vmx_get_msr(vcpu, ecx, &data)) {
1552 vmx_inject_gp(vcpu, 0);
1553 return 1;
1554 }
1555
1556 /* FIXME: handling of bits 32:63 of rax, rdx */
1557 vcpu->regs[VCPU_REGS_RAX] = data & -1u;
1558 vcpu->regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
1559 skip_emulated_instruction(vcpu);
1560 return 1;
1561}
1562
1563static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1564{
1565 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1566 u64 data = (vcpu->regs[VCPU_REGS_RAX] & -1u)
1567 | ((u64)(vcpu->regs[VCPU_REGS_RDX] & -1u) << 32);
1568
1569 if (vmx_set_msr(vcpu, ecx, data) != 0) {
1570 vmx_inject_gp(vcpu, 0);
1571 return 1;
1572 }
1573
1574 skip_emulated_instruction(vcpu);
1575 return 1;
1576}
1577
1578static int handle_interrupt_window(struct kvm_vcpu *vcpu,
1579 struct kvm_run *kvm_run)
1580{
1581 /* Turn off interrupt window reporting. */
1582 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1583 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL)
1584 & ~CPU_BASED_VIRTUAL_INTR_PENDING);
1585 return 1;
1586}
1587
1588static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1589{
1590 skip_emulated_instruction(vcpu);
1591 if (vcpu->irq_summary && (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF))
1592 return 1;
1593
1594 kvm_run->exit_reason = KVM_EXIT_HLT;
1595 return 0;
1596}
1597
1598/*
1599 * The exit handlers return 1 if the exit was handled fully and guest execution
1600 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
1601 * to be done to userspace and return 0.
1602 */
1603static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
1604 struct kvm_run *kvm_run) = {
1605 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
1606 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
1607 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
1608 [EXIT_REASON_INVLPG] = handle_invlpg,
1609 [EXIT_REASON_CR_ACCESS] = handle_cr,
1610 [EXIT_REASON_DR_ACCESS] = handle_dr,
1611 [EXIT_REASON_CPUID] = handle_cpuid,
1612 [EXIT_REASON_MSR_READ] = handle_rdmsr,
1613 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
1614 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
1615 [EXIT_REASON_HLT] = handle_halt,
1616};
1617
1618static const int kvm_vmx_max_exit_handlers =
1619 sizeof(kvm_vmx_exit_handlers) / sizeof(*kvm_vmx_exit_handlers);
1620
1621/*
1622 * The guest has exited. See if we can fix it or if we need userspace
1623 * assistance.
1624 */
1625static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
1626{
1627 u32 vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
1628 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
1629
1630 if ( (vectoring_info & VECTORING_INFO_VALID_MASK) &&
1631 exit_reason != EXIT_REASON_EXCEPTION_NMI )
1632 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
1633 "exit reason is 0x%x\n", __FUNCTION__, exit_reason);
1634 kvm_run->instruction_length = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1635 if (exit_reason < kvm_vmx_max_exit_handlers
1636 && kvm_vmx_exit_handlers[exit_reason])
1637 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
1638 else {
1639 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1640 kvm_run->hw.hardware_exit_reason = exit_reason;
1641 }
1642 return 0;
1643}
1644
1645static int vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1646{
1647 u8 fail;
1648 u16 fs_sel, gs_sel, ldt_sel;
1649 int fs_gs_ldt_reload_needed;
1650
1651again:
1652 /*
1653 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1654 * allow segment selectors with cpl > 0 or ti == 1.
1655 */
1656 fs_sel = read_fs();
1657 gs_sel = read_gs();
1658 ldt_sel = read_ldt();
1659 fs_gs_ldt_reload_needed = (fs_sel & 7) | (gs_sel & 7) | ldt_sel;
1660 if (!fs_gs_ldt_reload_needed) {
1661 vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1662 vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1663 } else {
1664 vmcs_write16(HOST_FS_SELECTOR, 0);
1665 vmcs_write16(HOST_GS_SELECTOR, 0);
1666 }
1667
05b3e0c2 1668#ifdef CONFIG_X86_64
6aa8b732
AK		 1669 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1670 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1671#else
1672 vmcs_writel(HOST_FS_BASE, segment_base(fs_sel));
1673 vmcs_writel(HOST_GS_BASE, segment_base(gs_sel));
1674#endif
1675
1676 if (vcpu->irq_summary &&
1677 !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
1678 kvm_try_inject_irq(vcpu);
1679
1680 if (vcpu->guest_debug.enabled)
1681 kvm_guest_debug_pre(vcpu);
1682
1683 fx_save(vcpu->host_fx_image);
1684 fx_restore(vcpu->guest_fx_image);
1685
1686 save_msrs(vcpu->host_msrs, vcpu->nmsrs);
1687 load_msrs(vcpu->guest_msrs, NR_BAD_MSRS);
1688
1689 asm (
1690 /* Store host registers */
1691 "pushf \n\t"
05b3e0c2 1692#ifdef CONFIG_X86_64
6aa8b732
AK		 1693 "push %%rax; push %%rbx; push %%rdx;"
1694 "push %%rsi; push %%rdi; push %%rbp;"
1695 "push %%r8; push %%r9; push %%r10; push %%r11;"
1696 "push %%r12; push %%r13; push %%r14; push %%r15;"
1697 "push %%rcx \n\t"
1698 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
1699#else
1700 "pusha; push %%ecx \n\t"
1701 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
1702#endif
1703 /* Check if vmlaunch of vmresume is needed */
1704 "cmp $0, %1 \n\t"
1705 /* Load guest registers. Don't clobber flags. */
05b3e0c2 1706#ifdef CONFIG_X86_64
6aa8b732
AK		 1707 "mov %c[cr2](%3), %%rax \n\t"
1708 "mov %%rax, %%cr2 \n\t"
1709 "mov %c[rax](%3), %%rax \n\t"
1710 "mov %c[rbx](%3), %%rbx \n\t"
1711 "mov %c[rdx](%3), %%rdx \n\t"
1712 "mov %c[rsi](%3), %%rsi \n\t"
1713 "mov %c[rdi](%3), %%rdi \n\t"
1714 "mov %c[rbp](%3), %%rbp \n\t"
1715 "mov %c[r8](%3), %%r8 \n\t"
1716 "mov %c[r9](%3), %%r9 \n\t"
1717 "mov %c[r10](%3), %%r10 \n\t"
1718 "mov %c[r11](%3), %%r11 \n\t"
1719 "mov %c[r12](%3), %%r12 \n\t"
1720 "mov %c[r13](%3), %%r13 \n\t"
1721 "mov %c[r14](%3), %%r14 \n\t"
1722 "mov %c[r15](%3), %%r15 \n\t"
1723 "mov %c[rcx](%3), %%rcx \n\t" /* kills %3 (rcx) */
1724#else
1725 "mov %c[cr2](%3), %%eax \n\t"
1726 "mov %%eax, %%cr2 \n\t"
1727 "mov %c[rax](%3), %%eax \n\t"
1728 "mov %c[rbx](%3), %%ebx \n\t"
1729 "mov %c[rdx](%3), %%edx \n\t"
1730 "mov %c[rsi](%3), %%esi \n\t"
1731 "mov %c[rdi](%3), %%edi \n\t"
1732 "mov %c[rbp](%3), %%ebp \n\t"
1733 "mov %c[rcx](%3), %%ecx \n\t" /* kills %3 (ecx) */
1734#endif
1735 /* Enter guest mode */
1736 "jne launched \n\t"
1737 ASM_VMX_VMLAUNCH "\n\t"
1738 "jmp kvm_vmx_return \n\t"
1739 "launched: " ASM_VMX_VMRESUME "\n\t"
1740 ".globl kvm_vmx_return \n\t"
1741 "kvm_vmx_return: "
1742 /* Save guest registers, load host registers, keep flags */
05b3e0c2 1743#ifdef CONFIG_X86_64
6aa8b732
AK		 1744 "xchg %3, 0(%%rsp) \n\t"
1745 "mov %%rax, %c[rax](%3) \n\t"
1746 "mov %%rbx, %c[rbx](%3) \n\t"
1747 "pushq 0(%%rsp); popq %c[rcx](%3) \n\t"
1748 "mov %%rdx, %c[rdx](%3) \n\t"
1749 "mov %%rsi, %c[rsi](%3) \n\t"
1750 "mov %%rdi, %c[rdi](%3) \n\t"
1751 "mov %%rbp, %c[rbp](%3) \n\t"
1752 "mov %%r8, %c[r8](%3) \n\t"
1753 "mov %%r9, %c[r9](%3) \n\t"
1754 "mov %%r10, %c[r10](%3) \n\t"
1755 "mov %%r11, %c[r11](%3) \n\t"
1756 "mov %%r12, %c[r12](%3) \n\t"
1757 "mov %%r13, %c[r13](%3) \n\t"
1758 "mov %%r14, %c[r14](%3) \n\t"
1759 "mov %%r15, %c[r15](%3) \n\t"
1760 "mov %%cr2, %%rax \n\t"
1761 "mov %%rax, %c[cr2](%3) \n\t"
1762 "mov 0(%%rsp), %3 \n\t"
1763
1764 "pop %%rcx; pop %%r15; pop %%r14; pop %%r13; pop %%r12;"
1765 "pop %%r11; pop %%r10; pop %%r9; pop %%r8;"
1766 "pop %%rbp; pop %%rdi; pop %%rsi;"
1767 "pop %%rdx; pop %%rbx; pop %%rax \n\t"
1768#else
1769 "xchg %3, 0(%%esp) \n\t"
1770 "mov %%eax, %c[rax](%3) \n\t"
1771 "mov %%ebx, %c[rbx](%3) \n\t"
1772 "pushl 0(%%esp); popl %c[rcx](%3) \n\t"
1773 "mov %%edx, %c[rdx](%3) \n\t"
1774 "mov %%esi, %c[rsi](%3) \n\t"
1775 "mov %%edi, %c[rdi](%3) \n\t"
1776 "mov %%ebp, %c[rbp](%3) \n\t"
1777 "mov %%cr2, %%eax \n\t"
1778 "mov %%eax, %c[cr2](%3) \n\t"
1779 "mov 0(%%esp), %3 \n\t"
1780
1781 "pop %%ecx; popa \n\t"
1782#endif
1783 "setbe %0 \n\t"
1784 "popf \n\t"
1785 : "=g" (fail)
1786 : "r"(vcpu->launched), "d"((unsigned long)HOST_RSP),
1787 "c"(vcpu),
1788 [rax]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RAX])),
1789 [rbx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBX])),
1790 [rcx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RCX])),
1791 [rdx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDX])),
1792 [rsi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RSI])),
1793 [rdi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDI])),
1794 [rbp]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBP])),
05b3e0c2 1795#ifdef CONFIG_X86_64
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AK		 1796 [r8 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R8 ])),
1797 [r9 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R9 ])),
1798 [r10]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R10])),
1799 [r11]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R11])),
1800 [r12]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R12])),
1801 [r13]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R13])),
1802 [r14]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R14])),
1803 [r15]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R15])),
1804#endif
1805 [cr2]"i"(offsetof(struct kvm_vcpu, cr2))
1806 : "cc", "memory" );
1807
1808 ++kvm_stat.exits;
1809
1810 save_msrs(vcpu->guest_msrs, NR_BAD_MSRS);
1811 load_msrs(vcpu->host_msrs, NR_BAD_MSRS);
1812
1813 fx_save(vcpu->guest_fx_image);
1814 fx_restore(vcpu->host_fx_image);
1815
05b3e0c2 1816#ifndef CONFIG_X86_64
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AK		 1817 asm ("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
1818#endif
1819
1820 kvm_run->exit_type = 0;
1821 if (fail) {
1822 kvm_run->exit_type = KVM_EXIT_TYPE_FAIL_ENTRY;
1823 kvm_run->exit_reason = vmcs_read32(VM_INSTRUCTION_ERROR);
1824 } else {
1825 if (fs_gs_ldt_reload_needed) {
1826 load_ldt(ldt_sel);
1827 load_fs(fs_sel);
1828 /*
1829 * If we have to reload gs, we must take care to
1830 * preserve our gs base.
1831 */
1832 local_irq_disable();
1833 load_gs(gs_sel);
05b3e0c2 1834#ifdef CONFIG_X86_64
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AK		 1835 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
1836#endif
1837 local_irq_enable();
1838
1839 reload_tss();
1840 }
1841 vcpu->launched = 1;
1842 kvm_run->exit_type = KVM_EXIT_TYPE_VM_EXIT;
1843 if (kvm_handle_exit(kvm_run, vcpu)) {
1844 /* Give scheduler a change to reschedule. */
1845 if (signal_pending(current)) {
1846 ++kvm_stat.signal_exits;
1847 return -EINTR;
1848 }
1849 kvm_resched(vcpu);
1850 goto again;
1851 }
1852 }
1853 return 0;
1854}
1855
1856static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1857{
1858 vmcs_writel(GUEST_CR3, vmcs_readl(GUEST_CR3));
1859}
1860
1861static void vmx_inject_page_fault(struct kvm_vcpu *vcpu,
1862 unsigned long addr,
1863 u32 err_code)
1864{
1865 u32 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
1866
1867 ++kvm_stat.pf_guest;
1868
1869 if (is_page_fault(vect_info)) {
1870 printk(KERN_DEBUG "inject_page_fault: "
1871 "double fault 0x%lx @ 0x%lx\n",
1872 addr, vmcs_readl(GUEST_RIP));
1873 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, 0);
1874 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1875 DF_VECTOR |
1876 INTR_TYPE_EXCEPTION |
1877 INTR_INFO_DELIEVER_CODE_MASK |
1878 INTR_INFO_VALID_MASK);
1879 return;
1880 }
1881 vcpu->cr2 = addr;
1882 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, err_code);
1883 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1884 PF_VECTOR |
1885 INTR_TYPE_EXCEPTION |
1886 INTR_INFO_DELIEVER_CODE_MASK |
1887 INTR_INFO_VALID_MASK);
1888
1889}
1890
1891static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
1892{
1893 if (vcpu->vmcs) {
1894 on_each_cpu(__vcpu_clear, vcpu, 0, 1);
1895 free_vmcs(vcpu->vmcs);
1896 vcpu->vmcs = NULL;
1897 }
1898}
1899
1900static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
1901{
1902 vmx_free_vmcs(vcpu);
1903}
1904
1905static int vmx_create_vcpu(struct kvm_vcpu *vcpu)
1906{
1907 struct vmcs *vmcs;
1908
1909 vmcs = alloc_vmcs();
1910 if (!vmcs)
1911 return -ENOMEM;
1912 vmcs_clear(vmcs);
1913 vcpu->vmcs = vmcs;
1914 vcpu->launched = 0;
1915 return 0;
1916}
1917
1918static struct kvm_arch_ops vmx_arch_ops = {
1919 .cpu_has_kvm_support = cpu_has_kvm_support,
1920 .disabled_by_bios = vmx_disabled_by_bios,
1921 .hardware_setup = hardware_setup,
1922 .hardware_unsetup = hardware_unsetup,
1923 .hardware_enable = hardware_enable,
1924 .hardware_disable = hardware_disable,
1925
1926 .vcpu_create = vmx_create_vcpu,
1927 .vcpu_free = vmx_free_vcpu,
1928
1929 .vcpu_load = vmx_vcpu_load,
1930 .vcpu_put = vmx_vcpu_put,
1931
1932 .set_guest_debug = set_guest_debug,
1933 .get_msr = vmx_get_msr,
1934 .set_msr = vmx_set_msr,
1935 .get_segment_base = vmx_get_segment_base,
1936 .get_segment = vmx_get_segment,
1937 .set_segment = vmx_set_segment,
6aa8b732
AK		 1938 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
1939 .set_cr0 = vmx_set_cr0,
1940 .set_cr0_no_modeswitch = vmx_set_cr0_no_modeswitch,
1941 .set_cr3 = vmx_set_cr3,
1942 .set_cr4 = vmx_set_cr4,
05b3e0c2 1943#ifdef CONFIG_X86_64
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AK		 1944 .set_efer = vmx_set_efer,
1945#endif
1946 .get_idt = vmx_get_idt,
1947 .set_idt = vmx_set_idt,
1948 .get_gdt = vmx_get_gdt,
1949 .set_gdt = vmx_set_gdt,
1950 .cache_regs = vcpu_load_rsp_rip,
1951 .decache_regs = vcpu_put_rsp_rip,
1952 .get_rflags = vmx_get_rflags,
1953 .set_rflags = vmx_set_rflags,
1954
1955 .tlb_flush = vmx_flush_tlb,
1956 .inject_page_fault = vmx_inject_page_fault,
1957
1958 .inject_gp = vmx_inject_gp,
1959
1960 .run = vmx_vcpu_run,
1961 .skip_emulated_instruction = skip_emulated_instruction,
1962 .vcpu_setup = vmx_vcpu_setup,
1963};
1964
1965static int __init vmx_init(void)
1966{
873a7c42 1967 return kvm_init_arch(&vmx_arch_ops, THIS_MODULE);
6aa8b732
AK		 1968}
1969
1970static void __exit vmx_exit(void)
1971{
1972 kvm_exit_arch();
1973}
1974
1975module_init(vmx_init)
1976module_exit(vmx_exit)
kernel source for telekom puls (alcatel/mediatek)