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[PATCH] KVM: Disallow the kvm-amd module on intel hardware, and vice versa
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
18#include "kvm.h"
19#include "vmx.h"
20#include "kvm_vmx.h"
21#include <linux/module.h>
22#include <linux/mm.h>
23#include <linux/highmem.h>
24#include <asm/io.h>
3b3be0d1 25#include <asm/desc.h>
6aa8b732
AK		 26
27#include "segment_descriptor.h"
28
29#define MSR_IA32_FEATURE_CONTROL 0x03a
30
31MODULE_AUTHOR("Qumranet");
32MODULE_LICENSE("GPL");
33
34static DEFINE_PER_CPU(struct vmcs *, vmxarea);
35static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
36
05b3e0c2 37#ifdef CONFIG_X86_64
6aa8b732
AK		 38#define HOST_IS_64 1
39#else
40#define HOST_IS_64 0
41#endif
42
43static struct vmcs_descriptor {
44 int size;
45 int order;
46 u32 revision_id;
47} vmcs_descriptor;
48
49#define VMX_SEGMENT_FIELD(seg) \
50 [VCPU_SREG_##seg] = { \
51 .selector = GUEST_##seg##_SELECTOR, \
52 .base = GUEST_##seg##_BASE, \
53 .limit = GUEST_##seg##_LIMIT, \
54 .ar_bytes = GUEST_##seg##_AR_BYTES, \
55 }
56
57static struct kvm_vmx_segment_field {
58 unsigned selector;
59 unsigned base;
60 unsigned limit;
61 unsigned ar_bytes;
62} kvm_vmx_segment_fields[] = {
63 VMX_SEGMENT_FIELD(CS),
64 VMX_SEGMENT_FIELD(DS),
65 VMX_SEGMENT_FIELD(ES),
66 VMX_SEGMENT_FIELD(FS),
67 VMX_SEGMENT_FIELD(GS),
68 VMX_SEGMENT_FIELD(SS),
69 VMX_SEGMENT_FIELD(TR),
70 VMX_SEGMENT_FIELD(LDTR),
71};
72
73static const u32 vmx_msr_index[] = {
05b3e0c2 74#ifdef CONFIG_X86_64
6aa8b732
AK		 75 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
76#endif
77 MSR_EFER, MSR_K6_STAR,
78};
79#define NR_VMX_MSR (sizeof(vmx_msr_index) / sizeof(*vmx_msr_index))
80
6aa8b732
AK		 81static inline int is_page_fault(u32 intr_info)
82{
83 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
84 INTR_INFO_VALID_MASK)) ==
85 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
86}
87
88static inline int is_external_interrupt(u32 intr_info)
89{
90 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
91 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
92}
93
7725f0ba
AK		 94static struct vmx_msr_entry *find_msr_entry(struct kvm_vcpu *vcpu, u32 msr)
95{
96 int i;
97
98 for (i = 0; i < vcpu->nmsrs; ++i)
99 if (vcpu->guest_msrs[i].index == msr)
100 return &vcpu->guest_msrs[i];
101 return 0;
102}
103
6aa8b732
AK		 104static void vmcs_clear(struct vmcs *vmcs)
105{
106 u64 phys_addr = __pa(vmcs);
107 u8 error;
108
109 asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0"
110 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
111 : "cc", "memory");
112 if (error)
113 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
114 vmcs, phys_addr);
115}
116
117static void __vcpu_clear(void *arg)
118{
119 struct kvm_vcpu *vcpu = arg;
120 int cpu = smp_processor_id();
121
122 if (vcpu->cpu == cpu)
123 vmcs_clear(vcpu->vmcs);
124 if (per_cpu(current_vmcs, cpu) == vcpu->vmcs)
125 per_cpu(current_vmcs, cpu) = NULL;
126}
127
128static unsigned long vmcs_readl(unsigned long field)
129{
130 unsigned long value;
131
132 asm volatile (ASM_VMX_VMREAD_RDX_RAX
133 : "=a"(value) : "d"(field) : "cc");
134 return value;
135}
136
137static u16 vmcs_read16(unsigned long field)
138{
139 return vmcs_readl(field);
140}
141
142static u32 vmcs_read32(unsigned long field)
143{
144 return vmcs_readl(field);
145}
146
147static u64 vmcs_read64(unsigned long field)
148{
05b3e0c2 149#ifdef CONFIG_X86_64
6aa8b732
AK		 150 return vmcs_readl(field);
151#else
152 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
153#endif
154}
155
156static void vmcs_writel(unsigned long field, unsigned long value)
157{
158 u8 error;
159
160 asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0"
161 : "=q"(error) : "a"(value), "d"(field) : "cc" );
162 if (error)
163 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
164 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
165}
166
167static void vmcs_write16(unsigned long field, u16 value)
168{
169 vmcs_writel(field, value);
170}
171
172static void vmcs_write32(unsigned long field, u32 value)
173{
174 vmcs_writel(field, value);
175}
176
177static void vmcs_write64(unsigned long field, u64 value)
178{
05b3e0c2 179#ifdef CONFIG_X86_64
6aa8b732
AK		 180 vmcs_writel(field, value);
181#else
182 vmcs_writel(field, value);
183 asm volatile ("");
184 vmcs_writel(field+1, value >> 32);
185#endif
186}
187
188/*
189 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
190 * vcpu mutex is already taken.
191 */
192static struct kvm_vcpu *vmx_vcpu_load(struct kvm_vcpu *vcpu)
193{
194 u64 phys_addr = __pa(vcpu->vmcs);
195 int cpu;
196
197 cpu = get_cpu();
198
199 if (vcpu->cpu != cpu) {
200 smp_call_function(__vcpu_clear, vcpu, 0, 1);
201 vcpu->launched = 0;
202 }
203
204 if (per_cpu(current_vmcs, cpu) != vcpu->vmcs) {
205 u8 error;
206
207 per_cpu(current_vmcs, cpu) = vcpu->vmcs;
208 asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0"
209 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
210 : "cc");
211 if (error)
212 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
213 vcpu->vmcs, phys_addr);
214 }
215
216 if (vcpu->cpu != cpu) {
217 struct descriptor_table dt;
218 unsigned long sysenter_esp;
219
220 vcpu->cpu = cpu;
221 /*
222 * Linux uses per-cpu TSS and GDT, so set these when switching
223 * processors.
224 */
225 vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */
226 get_gdt(&dt);
227 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
228
229 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
230 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
231 }
232 return vcpu;
233}
234
235static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
236{
237 put_cpu();
238}
239
240static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
241{
242 return vmcs_readl(GUEST_RFLAGS);
243}
244
245static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
246{
247 vmcs_writel(GUEST_RFLAGS, rflags);
248}
249
250static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
251{
252 unsigned long rip;
253 u32 interruptibility;
254
255 rip = vmcs_readl(GUEST_RIP);
256 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
257 vmcs_writel(GUEST_RIP, rip);
258
259 /*
260 * We emulated an instruction, so temporary interrupt blocking
261 * should be removed, if set.
262 */
263 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
264 if (interruptibility & 3)
265 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
266 interruptibility & ~3);
267}
268
269static void vmx_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code)
270{
271 printk(KERN_DEBUG "inject_general_protection: rip 0x%lx\n",
272 vmcs_readl(GUEST_RIP));
273 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
274 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
275 GP_VECTOR |
276 INTR_TYPE_EXCEPTION |
277 INTR_INFO_DELIEVER_CODE_MASK |
278 INTR_INFO_VALID_MASK);
279}
280
281/*
282 * reads and returns guest's timestamp counter "register"
283 * guest_tsc = host_tsc + tsc_offset -- 21.3
284 */
285static u64 guest_read_tsc(void)
286{
287 u64 host_tsc, tsc_offset;
288
289 rdtscll(host_tsc);
290 tsc_offset = vmcs_read64(TSC_OFFSET);
291 return host_tsc + tsc_offset;
292}
293
294/*
295 * writes 'guest_tsc' into guest's timestamp counter "register"
296 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
297 */
298static void guest_write_tsc(u64 guest_tsc)
299{
300 u64 host_tsc;
301
302 rdtscll(host_tsc);
303 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
304}
305
306static void reload_tss(void)
307{
05b3e0c2 308#ifndef CONFIG_X86_64
6aa8b732
AK		 309
310 /*
311 * VT restores TR but not its size. Useless.
312 */
313 struct descriptor_table gdt;
314 struct segment_descriptor *descs;
315
316 get_gdt(&gdt);
317 descs = (void *)gdt.base;
318 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
319 load_TR_desc();
320#endif
321}
322
323/*
324 * Reads an msr value (of 'msr_index') into 'pdata'.
325 * Returns 0 on success, non-0 otherwise.
326 * Assumes vcpu_load() was already called.
327 */
328static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
329{
330 u64 data;
331 struct vmx_msr_entry *msr;
332
333 if (!pdata) {
334 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
335 return -EINVAL;
336 }
337
338 switch (msr_index) {
05b3e0c2 339#ifdef CONFIG_X86_64
6aa8b732
AK		 340 case MSR_FS_BASE:
341 data = vmcs_readl(GUEST_FS_BASE);
342 break;
343 case MSR_GS_BASE:
344 data = vmcs_readl(GUEST_GS_BASE);
345 break;
346 case MSR_EFER:
347 data = vcpu->shadow_efer;
348 break;
349#endif
350 case MSR_IA32_TIME_STAMP_COUNTER:
351 data = guest_read_tsc();
352 break;
353 case MSR_IA32_SYSENTER_CS:
354 data = vmcs_read32(GUEST_SYSENTER_CS);
355 break;
356 case MSR_IA32_SYSENTER_EIP:
357 data = vmcs_read32(GUEST_SYSENTER_EIP);
358 break;
359 case MSR_IA32_SYSENTER_ESP:
360 data = vmcs_read32(GUEST_SYSENTER_ESP);
361 break;
362 case MSR_IA32_MC0_CTL:
363 case MSR_IA32_MCG_STATUS:
364 case MSR_IA32_MCG_CAP:
365 case MSR_IA32_MC0_MISC:
366 case MSR_IA32_MC0_MISC+4:
367 case MSR_IA32_MC0_MISC+8:
368 case MSR_IA32_MC0_MISC+12:
369 case MSR_IA32_MC0_MISC+16:
370 case MSR_IA32_UCODE_REV:
371 /* MTRR registers */
372 case 0xfe:
373 case 0x200 ... 0x2ff:
374 data = 0;
375 break;
376 case MSR_IA32_APICBASE:
377 data = vcpu->apic_base;
378 break;
379 default:
380 msr = find_msr_entry(vcpu, msr_index);
381 if (!msr) {
382 printk(KERN_ERR "kvm: unhandled rdmsr: %x\n", msr_index);
383 return 1;
384 }
385 data = msr->data;
386 break;
387 }
388
389 *pdata = data;
390 return 0;
391}
392
393/*
394 * Writes msr value into into the appropriate "register".
395 * Returns 0 on success, non-0 otherwise.
396 * Assumes vcpu_load() was already called.
397 */
398static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
399{
400 struct vmx_msr_entry *msr;
401 switch (msr_index) {
05b3e0c2 402#ifdef CONFIG_X86_64
6aa8b732
AK		 403 case MSR_FS_BASE:
404 vmcs_writel(GUEST_FS_BASE, data);
405 break;
406 case MSR_GS_BASE:
407 vmcs_writel(GUEST_GS_BASE, data);
408 break;
409#endif
410 case MSR_IA32_SYSENTER_CS:
411 vmcs_write32(GUEST_SYSENTER_CS, data);
412 break;
413 case MSR_IA32_SYSENTER_EIP:
414 vmcs_write32(GUEST_SYSENTER_EIP, data);
415 break;
416 case MSR_IA32_SYSENTER_ESP:
417 vmcs_write32(GUEST_SYSENTER_ESP, data);
418 break;
419#ifdef __x86_64
420 case MSR_EFER:
421 set_efer(vcpu, data);
422 break;
423 case MSR_IA32_MC0_STATUS:
424 printk(KERN_WARNING "%s: MSR_IA32_MC0_STATUS 0x%llx, nop\n"
425 , __FUNCTION__, data);
426 break;
427#endif
428 case MSR_IA32_TIME_STAMP_COUNTER: {
429 guest_write_tsc(data);
430 break;
431 }
432 case MSR_IA32_UCODE_REV:
433 case MSR_IA32_UCODE_WRITE:
434 case 0x200 ... 0x2ff: /* MTRRs */
435 break;
436 case MSR_IA32_APICBASE:
437 vcpu->apic_base = data;
438 break;
439 default:
440 msr = find_msr_entry(vcpu, msr_index);
441 if (!msr) {
442 printk(KERN_ERR "kvm: unhandled wrmsr: 0x%x\n", msr_index);
443 return 1;
444 }
445 msr->data = data;
446 break;
447 }
448
449 return 0;
450}
451
452/*
453 * Sync the rsp and rip registers into the vcpu structure. This allows
454 * registers to be accessed by indexing vcpu->regs.
455 */
456static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu)
457{
458 vcpu->regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
459 vcpu->rip = vmcs_readl(GUEST_RIP);
460}
461
462/*
463 * Syncs rsp and rip back into the vmcs. Should be called after possible
464 * modification.
465 */
466static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu)
467{
468 vmcs_writel(GUEST_RSP, vcpu->regs[VCPU_REGS_RSP]);
469 vmcs_writel(GUEST_RIP, vcpu->rip);
470}
471
472static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
473{
474 unsigned long dr7 = 0x400;
475 u32 exception_bitmap;
476 int old_singlestep;
477
478 exception_bitmap = vmcs_read32(EXCEPTION_BITMAP);
479 old_singlestep = vcpu->guest_debug.singlestep;
480
481 vcpu->guest_debug.enabled = dbg->enabled;
482 if (vcpu->guest_debug.enabled) {
483 int i;
484
485 dr7 |= 0x200; /* exact */
486 for (i = 0; i < 4; ++i) {
487 if (!dbg->breakpoints[i].enabled)
488 continue;
489 vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
490 dr7 |= 2 << (i*2); /* global enable */
491 dr7 |= 0 << (i*4+16); /* execution breakpoint */
492 }
493
494 exception_bitmap |= (1u << 1); /* Trap debug exceptions */
495
496 vcpu->guest_debug.singlestep = dbg->singlestep;
497 } else {
498 exception_bitmap &= ~(1u << 1); /* Ignore debug exceptions */
499 vcpu->guest_debug.singlestep = 0;
500 }
501
502 if (old_singlestep && !vcpu->guest_debug.singlestep) {
503 unsigned long flags;
504
505 flags = vmcs_readl(GUEST_RFLAGS);
506 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
507 vmcs_writel(GUEST_RFLAGS, flags);
508 }
509
510 vmcs_write32(EXCEPTION_BITMAP, exception_bitmap);
511 vmcs_writel(GUEST_DR7, dr7);
512
513 return 0;
514}
515
516static __init int cpu_has_kvm_support(void)
517{
518 unsigned long ecx = cpuid_ecx(1);
519 return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
520}
521
522static __init int vmx_disabled_by_bios(void)
523{
524 u64 msr;
525
526 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
527 return (msr & 5) == 1; /* locked but not enabled */
528}
529
530static __init void hardware_enable(void *garbage)
531{
532 int cpu = raw_smp_processor_id();
533 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
534 u64 old;
535
536 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
537 if ((old & 5) == 0)
538 /* enable and lock */
539 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | 5);
540 write_cr4(read_cr4() | CR4_VMXE); /* FIXME: not cpu hotplug safe */
541 asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr)
542 : "memory", "cc");
543}
544
545static void hardware_disable(void *garbage)
546{
547 asm volatile (ASM_VMX_VMXOFF : : : "cc");
548}
549
550static __init void setup_vmcs_descriptor(void)
551{
552 u32 vmx_msr_low, vmx_msr_high;
553
554 rdmsr(MSR_IA32_VMX_BASIC_MSR, vmx_msr_low, vmx_msr_high);
555 vmcs_descriptor.size = vmx_msr_high & 0x1fff;
556 vmcs_descriptor.order = get_order(vmcs_descriptor.size);
557 vmcs_descriptor.revision_id = vmx_msr_low;
558};
559
560static struct vmcs *alloc_vmcs_cpu(int cpu)
561{
562 int node = cpu_to_node(cpu);
563 struct page *pages;
564 struct vmcs *vmcs;
565
566 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_descriptor.order);
567 if (!pages)
568 return NULL;
569 vmcs = page_address(pages);
570 memset(vmcs, 0, vmcs_descriptor.size);
571 vmcs->revision_id = vmcs_descriptor.revision_id; /* vmcs revision id */
572 return vmcs;
573}
574
575static struct vmcs *alloc_vmcs(void)
576{
577 return alloc_vmcs_cpu(smp_processor_id());
578}
579
580static void free_vmcs(struct vmcs *vmcs)
581{
582 free_pages((unsigned long)vmcs, vmcs_descriptor.order);
583}
584
585static __exit void free_kvm_area(void)
586{
587 int cpu;
588
589 for_each_online_cpu(cpu)
590 free_vmcs(per_cpu(vmxarea, cpu));
591}
592
593extern struct vmcs *alloc_vmcs_cpu(int cpu);
594
595static __init int alloc_kvm_area(void)
596{
597 int cpu;
598
599 for_each_online_cpu(cpu) {
600 struct vmcs *vmcs;
601
602 vmcs = alloc_vmcs_cpu(cpu);
603 if (!vmcs) {
604 free_kvm_area();
605 return -ENOMEM;
606 }
607
608 per_cpu(vmxarea, cpu) = vmcs;
609 }
610 return 0;
611}
612
613static __init int hardware_setup(void)
614{
615 setup_vmcs_descriptor();
616 return alloc_kvm_area();
617}
618
619static __exit void hardware_unsetup(void)
620{
621 free_kvm_area();
622}
623
624static void update_exception_bitmap(struct kvm_vcpu *vcpu)
625{
626 if (vcpu->rmode.active)
627 vmcs_write32(EXCEPTION_BITMAP, ~0);
628 else
629 vmcs_write32(EXCEPTION_BITMAP, 1 << PF_VECTOR);
630}
631
632static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
633{
634 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
635
636 if (vmcs_readl(sf->base) == save->base) {
637 vmcs_write16(sf->selector, save->selector);
638 vmcs_writel(sf->base, save->base);
639 vmcs_write32(sf->limit, save->limit);
640 vmcs_write32(sf->ar_bytes, save->ar);
641 } else {
642 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
643 << AR_DPL_SHIFT;
644 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
645 }
646}
647
648static void enter_pmode(struct kvm_vcpu *vcpu)
649{
650 unsigned long flags;
651
652 vcpu->rmode.active = 0;
653
654 vmcs_writel(GUEST_TR_BASE, vcpu->rmode.tr.base);
655 vmcs_write32(GUEST_TR_LIMIT, vcpu->rmode.tr.limit);
656 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->rmode.tr.ar);
657
658 flags = vmcs_readl(GUEST_RFLAGS);
659 flags &= ~(IOPL_MASK | X86_EFLAGS_VM);
660 flags |= (vcpu->rmode.save_iopl << IOPL_SHIFT);
661 vmcs_writel(GUEST_RFLAGS, flags);
662
663 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~CR4_VME_MASK) |
664 (vmcs_readl(CR4_READ_SHADOW) & CR4_VME_MASK));
665
666 update_exception_bitmap(vcpu);
667
668 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->rmode.es);
669 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->rmode.ds);
670 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->rmode.gs);
671 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->rmode.fs);
672
673 vmcs_write16(GUEST_SS_SELECTOR, 0);
674 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
675
676 vmcs_write16(GUEST_CS_SELECTOR,
677 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
678 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
679}
680
681static int rmode_tss_base(struct kvm* kvm)
682{
683 gfn_t base_gfn = kvm->memslots[0].base_gfn + kvm->memslots[0].npages - 3;
684 return base_gfn << PAGE_SHIFT;
685}
686
687static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
688{
689 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
690
691 save->selector = vmcs_read16(sf->selector);
692 save->base = vmcs_readl(sf->base);
693 save->limit = vmcs_read32(sf->limit);
694 save->ar = vmcs_read32(sf->ar_bytes);
695 vmcs_write16(sf->selector, vmcs_readl(sf->base) >> 4);
696 vmcs_write32(sf->limit, 0xffff);
697 vmcs_write32(sf->ar_bytes, 0xf3);
698}
699
700static void enter_rmode(struct kvm_vcpu *vcpu)
701{
702 unsigned long flags;
703
704 vcpu->rmode.active = 1;
705
706 vcpu->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
707 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
708
709 vcpu->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
710 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
711
712 vcpu->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
713 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
714
715 flags = vmcs_readl(GUEST_RFLAGS);
716 vcpu->rmode.save_iopl = (flags & IOPL_MASK) >> IOPL_SHIFT;
717
718 flags |= IOPL_MASK | X86_EFLAGS_VM;
719
720 vmcs_writel(GUEST_RFLAGS, flags);
721 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | CR4_VME_MASK);
722 update_exception_bitmap(vcpu);
723
724 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
725 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
726 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
727
728 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
729 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
730
731 fix_rmode_seg(VCPU_SREG_ES, &vcpu->rmode.es);
732 fix_rmode_seg(VCPU_SREG_DS, &vcpu->rmode.ds);
733 fix_rmode_seg(VCPU_SREG_GS, &vcpu->rmode.gs);
734 fix_rmode_seg(VCPU_SREG_FS, &vcpu->rmode.fs);
735}
736
05b3e0c2 737#ifdef CONFIG_X86_64
6aa8b732
AK		 738
739static void enter_lmode(struct kvm_vcpu *vcpu)
740{
741 u32 guest_tr_ar;
742
743 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
744 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
745 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
746 __FUNCTION__);
747 vmcs_write32(GUEST_TR_AR_BYTES,
748 (guest_tr_ar & ~AR_TYPE_MASK)
749 | AR_TYPE_BUSY_64_TSS);
750 }
751
752 vcpu->shadow_efer |= EFER_LMA;
753
754 find_msr_entry(vcpu, MSR_EFER)->data |= EFER_LMA | EFER_LME;
755 vmcs_write32(VM_ENTRY_CONTROLS,
756 vmcs_read32(VM_ENTRY_CONTROLS)
757 | VM_ENTRY_CONTROLS_IA32E_MASK);
758}
759
760static void exit_lmode(struct kvm_vcpu *vcpu)
761{
762 vcpu->shadow_efer &= ~EFER_LMA;
763
764 vmcs_write32(VM_ENTRY_CONTROLS,
765 vmcs_read32(VM_ENTRY_CONTROLS)
766 & ~VM_ENTRY_CONTROLS_IA32E_MASK);
767}
768
769#endif
770
771static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
772{
773 if (vcpu->rmode.active && (cr0 & CR0_PE_MASK))
774 enter_pmode(vcpu);
775
776 if (!vcpu->rmode.active && !(cr0 & CR0_PE_MASK))
777 enter_rmode(vcpu);
778
05b3e0c2 779#ifdef CONFIG_X86_64
6aa8b732
AK		 780 if (vcpu->shadow_efer & EFER_LME) {
781 if (!is_paging(vcpu) && (cr0 & CR0_PG_MASK))
782 enter_lmode(vcpu);
783 if (is_paging(vcpu) && !(cr0 & CR0_PG_MASK))
784 exit_lmode(vcpu);
785 }
786#endif
787
788 vmcs_writel(CR0_READ_SHADOW, cr0);
789 vmcs_writel(GUEST_CR0,
790 (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
791 vcpu->cr0 = cr0;
792}
793
794/*
795 * Used when restoring the VM to avoid corrupting segment registers
796 */
797static void vmx_set_cr0_no_modeswitch(struct kvm_vcpu *vcpu, unsigned long cr0)
798{
799 vcpu->rmode.active = ((cr0 & CR0_PE_MASK) == 0);
800 update_exception_bitmap(vcpu);
801 vmcs_writel(CR0_READ_SHADOW, cr0);
802 vmcs_writel(GUEST_CR0,
803 (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
804 vcpu->cr0 = cr0;
805}
806
807static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
808{
809 vmcs_writel(GUEST_CR3, cr3);
810}
811
812static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
813{
814 vmcs_writel(CR4_READ_SHADOW, cr4);
815 vmcs_writel(GUEST_CR4, cr4 | (vcpu->rmode.active ?
816 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON));
817 vcpu->cr4 = cr4;
818}
819
05b3e0c2 820#ifdef CONFIG_X86_64
6aa8b732
AK		 821
822static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
823{
824 struct vmx_msr_entry *msr = find_msr_entry(vcpu, MSR_EFER);
825
826 vcpu->shadow_efer = efer;
827 if (efer & EFER_LMA) {
828 vmcs_write32(VM_ENTRY_CONTROLS,
829 vmcs_read32(VM_ENTRY_CONTROLS) |
830 VM_ENTRY_CONTROLS_IA32E_MASK);
831 msr->data = efer;
832
833 } else {
834 vmcs_write32(VM_ENTRY_CONTROLS,
835 vmcs_read32(VM_ENTRY_CONTROLS) &
836 ~VM_ENTRY_CONTROLS_IA32E_MASK);
837
838 msr->data = efer & ~EFER_LME;
839 }
840}
841
842#endif
843
844static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
845{
846 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
847
848 return vmcs_readl(sf->base);
849}
850
851static void vmx_get_segment(struct kvm_vcpu *vcpu,
852 struct kvm_segment *var, int seg)
853{
854 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
855 u32 ar;
856
857 var->base = vmcs_readl(sf->base);
858 var->limit = vmcs_read32(sf->limit);
859 var->selector = vmcs_read16(sf->selector);
860 ar = vmcs_read32(sf->ar_bytes);
861 if (ar & AR_UNUSABLE_MASK)
862 ar = 0;
863 var->type = ar & 15;
864 var->s = (ar >> 4) & 1;
865 var->dpl = (ar >> 5) & 3;
866 var->present = (ar >> 7) & 1;
867 var->avl = (ar >> 12) & 1;
868 var->l = (ar >> 13) & 1;
869 var->db = (ar >> 14) & 1;
870 var->g = (ar >> 15) & 1;
871 var->unusable = (ar >> 16) & 1;
872}
873
874static void vmx_set_segment(struct kvm_vcpu *vcpu,
875 struct kvm_segment *var, int seg)
876{
877 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
878 u32 ar;
879
880 vmcs_writel(sf->base, var->base);
881 vmcs_write32(sf->limit, var->limit);
882 vmcs_write16(sf->selector, var->selector);
883 if (var->unusable)
884 ar = 1 << 16;
885 else {
886 ar = var->type & 15;
887 ar |= (var->s & 1) << 4;
888 ar |= (var->dpl & 3) << 5;
889 ar |= (var->present & 1) << 7;
890 ar |= (var->avl & 1) << 12;
891 ar |= (var->l & 1) << 13;
892 ar |= (var->db & 1) << 14;
893 ar |= (var->g & 1) << 15;
894 }
f7fbf1fd
UL		 895 if (ar == 0) /* a 0 value means unusable */
896 ar = AR_UNUSABLE_MASK;
6aa8b732
AK		 897 vmcs_write32(sf->ar_bytes, ar);
898}
899
900static int vmx_is_long_mode(struct kvm_vcpu *vcpu)
901{
902 return vmcs_read32(VM_ENTRY_CONTROLS) & VM_ENTRY_CONTROLS_IA32E_MASK;
903}
904
905static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
906{
907 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
908
909 *db = (ar >> 14) & 1;
910 *l = (ar >> 13) & 1;
911}
912
913static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
914{
915 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
916 dt->base = vmcs_readl(GUEST_IDTR_BASE);
917}
918
919static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
920{
921 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
922 vmcs_writel(GUEST_IDTR_BASE, dt->base);
923}
924
925static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
926{
927 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
928 dt->base = vmcs_readl(GUEST_GDTR_BASE);
929}
930
931static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
932{
933 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
934 vmcs_writel(GUEST_GDTR_BASE, dt->base);
935}
936
937static int init_rmode_tss(struct kvm* kvm)
938{
939 struct page *p1, *p2, *p3;
940 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
941 char *page;
942
943 p1 = _gfn_to_page(kvm, fn++);
944 p2 = _gfn_to_page(kvm, fn++);
945 p3 = _gfn_to_page(kvm, fn);
946
947 if (!p1 || !p2 || !p3) {
948 kvm_printf(kvm,"%s: gfn_to_page failed\n", __FUNCTION__);
949 return 0;
950 }
951
952 page = kmap_atomic(p1, KM_USER0);
953 memset(page, 0, PAGE_SIZE);
954 *(u16*)(page + 0x66) = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
955 kunmap_atomic(page, KM_USER0);
956
957 page = kmap_atomic(p2, KM_USER0);
958 memset(page, 0, PAGE_SIZE);
959 kunmap_atomic(page, KM_USER0);
960
961 page = kmap_atomic(p3, KM_USER0);
962 memset(page, 0, PAGE_SIZE);
963 *(page + RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1) = ~0;
964 kunmap_atomic(page, KM_USER0);
965
966 return 1;
967}
968
969static void vmcs_write32_fixedbits(u32 msr, u32 vmcs_field, u32 val)
970{
971 u32 msr_high, msr_low;
972
973 rdmsr(msr, msr_low, msr_high);
974
975 val &= msr_high;
976 val |= msr_low;
977 vmcs_write32(vmcs_field, val);
978}
979
980static void seg_setup(int seg)
981{
982 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
983
984 vmcs_write16(sf->selector, 0);
985 vmcs_writel(sf->base, 0);
986 vmcs_write32(sf->limit, 0xffff);
987 vmcs_write32(sf->ar_bytes, 0x93);
988}
989
990/*
991 * Sets up the vmcs for emulated real mode.
992 */
993static int vmx_vcpu_setup(struct kvm_vcpu *vcpu)
994{
995 u32 host_sysenter_cs;
996 u32 junk;
997 unsigned long a;
998 struct descriptor_table dt;
999 int i;
1000 int ret = 0;
1001 int nr_good_msrs;
1002 extern asmlinkage void kvm_vmx_return(void);
1003
1004 if (!init_rmode_tss(vcpu->kvm)) {
1005 ret = -ENOMEM;
1006 goto out;
1007 }
1008
1009 memset(vcpu->regs, 0, sizeof(vcpu->regs));
1010 vcpu->regs[VCPU_REGS_RDX] = get_rdx_init_val();
1011 vcpu->cr8 = 0;
1012 vcpu->apic_base = 0xfee00000 |
1013 /*for vcpu 0*/ MSR_IA32_APICBASE_BSP |
1014 MSR_IA32_APICBASE_ENABLE;
1015
1016 fx_init(vcpu);
1017
1018 /*
1019 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
1020 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
1021 */
1022 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
1023 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
1024 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1025 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1026
1027 seg_setup(VCPU_SREG_DS);
1028 seg_setup(VCPU_SREG_ES);
1029 seg_setup(VCPU_SREG_FS);
1030 seg_setup(VCPU_SREG_GS);
1031 seg_setup(VCPU_SREG_SS);
1032
1033 vmcs_write16(GUEST_TR_SELECTOR, 0);
1034 vmcs_writel(GUEST_TR_BASE, 0);
1035 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
1036 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1037
1038 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
1039 vmcs_writel(GUEST_LDTR_BASE, 0);
1040 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
1041 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
1042
1043 vmcs_write32(GUEST_SYSENTER_CS, 0);
1044 vmcs_writel(GUEST_SYSENTER_ESP, 0);
1045 vmcs_writel(GUEST_SYSENTER_EIP, 0);
1046
1047 vmcs_writel(GUEST_RFLAGS, 0x02);
1048 vmcs_writel(GUEST_RIP, 0xfff0);
1049 vmcs_writel(GUEST_RSP, 0);
1050
1051 vmcs_writel(GUEST_CR3, 0);
1052
1053 //todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0
1054 vmcs_writel(GUEST_DR7, 0x400);
1055
1056 vmcs_writel(GUEST_GDTR_BASE, 0);
1057 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
1058
1059 vmcs_writel(GUEST_IDTR_BASE, 0);
1060 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
1061
1062 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
1063 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
1064 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
1065
1066 /* I/O */
1067 vmcs_write64(IO_BITMAP_A, 0);
1068 vmcs_write64(IO_BITMAP_B, 0);
1069
1070 guest_write_tsc(0);
1071
1072 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1073
1074 /* Special registers */
1075 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
1076
1077 /* Control */
1078 vmcs_write32_fixedbits(MSR_IA32_VMX_PINBASED_CTLS_MSR,
1079 PIN_BASED_VM_EXEC_CONTROL,
1080 PIN_BASED_EXT_INTR_MASK /* 20.6.1 */
1081 | PIN_BASED_NMI_EXITING /* 20.6.1 */
1082 );
1083 vmcs_write32_fixedbits(MSR_IA32_VMX_PROCBASED_CTLS_MSR,
1084 CPU_BASED_VM_EXEC_CONTROL,
1085 CPU_BASED_HLT_EXITING /* 20.6.2 */
1086 | CPU_BASED_CR8_LOAD_EXITING /* 20.6.2 */
1087 | CPU_BASED_CR8_STORE_EXITING /* 20.6.2 */
1088 | CPU_BASED_UNCOND_IO_EXITING /* 20.6.2 */
1089 | CPU_BASED_INVDPG_EXITING
1090 | CPU_BASED_MOV_DR_EXITING
1091 | CPU_BASED_USE_TSC_OFFSETING /* 21.3 */
1092 );
1093
1094 vmcs_write32(EXCEPTION_BITMAP, 1 << PF_VECTOR);
1095 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
1096 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
1097 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
1098
1099 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
1100 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
1101 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
1102
1103 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
1104 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1105 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1106 vmcs_write16(HOST_FS_SELECTOR, read_fs()); /* 22.2.4 */
1107 vmcs_write16(HOST_GS_SELECTOR, read_gs()); /* 22.2.4 */
1108 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 1109#ifdef CONFIG_X86_64
6aa8b732
AK		 1110 rdmsrl(MSR_FS_BASE, a);
1111 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1112 rdmsrl(MSR_GS_BASE, a);
1113 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1114#else
1115 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1116 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1117#endif
1118
1119 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
1120
1121 get_idt(&dt);
1122 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
1123
1124
1125 vmcs_writel(HOST_RIP, (unsigned long)kvm_vmx_return); /* 22.2.5 */
1126
1127 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1128 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1129 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1130 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
1131 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1132 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
1133
1134 ret = -ENOMEM;
1135 vcpu->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
1136 if (!vcpu->guest_msrs)
1137 goto out;
1138 vcpu->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
1139 if (!vcpu->host_msrs)
1140 goto out_free_guest_msrs;
1141
1142 for (i = 0; i < NR_VMX_MSR; ++i) {
1143 u32 index = vmx_msr_index[i];
1144 u32 data_low, data_high;
1145 u64 data;
1146 int j = vcpu->nmsrs;
1147
1148 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1149 continue;
1150 data = data_low | ((u64)data_high << 32);
1151 vcpu->host_msrs[j].index = index;
1152 vcpu->host_msrs[j].reserved = 0;
1153 vcpu->host_msrs[j].data = data;
1154 vcpu->guest_msrs[j] = vcpu->host_msrs[j];
1155 ++vcpu->nmsrs;
1156 }
1157 printk(KERN_DEBUG "kvm: msrs: %d\n", vcpu->nmsrs);
1158
1159 nr_good_msrs = vcpu->nmsrs - NR_BAD_MSRS;
1160 vmcs_writel(VM_ENTRY_MSR_LOAD_ADDR,
1161 virt_to_phys(vcpu->guest_msrs + NR_BAD_MSRS));
1162 vmcs_writel(VM_EXIT_MSR_STORE_ADDR,
1163 virt_to_phys(vcpu->guest_msrs + NR_BAD_MSRS));
1164 vmcs_writel(VM_EXIT_MSR_LOAD_ADDR,
1165 virt_to_phys(vcpu->host_msrs + NR_BAD_MSRS));
1166 vmcs_write32_fixedbits(MSR_IA32_VMX_EXIT_CTLS_MSR, VM_EXIT_CONTROLS,
1167 (HOST_IS_64 << 9)); /* 22.2,1, 20.7.1 */
1168 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, nr_good_msrs); /* 22.2.2 */
1169 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, nr_good_msrs); /* 22.2.2 */
1170 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, nr_good_msrs); /* 22.2.2 */
1171
1172
1173 /* 22.2.1, 20.8.1 */
1174 vmcs_write32_fixedbits(MSR_IA32_VMX_ENTRY_CTLS_MSR,
1175 VM_ENTRY_CONTROLS, 0);
1176 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
1177
1178 vmcs_writel(VIRTUAL_APIC_PAGE_ADDR, 0);
1179 vmcs_writel(TPR_THRESHOLD, 0);
1180
1181 vmcs_writel(CR0_GUEST_HOST_MASK, KVM_GUEST_CR0_MASK);
1182 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1183
1184 vcpu->cr0 = 0x60000010;
1185 vmx_set_cr0(vcpu, vcpu->cr0); // enter rmode
1186 vmx_set_cr4(vcpu, 0);
05b3e0c2 1187#ifdef CONFIG_X86_64
6aa8b732
AK		 1188 vmx_set_efer(vcpu, 0);
1189#endif
1190
1191 return 0;
1192
1193out_free_guest_msrs:
1194 kfree(vcpu->guest_msrs);
1195out:
1196 return ret;
1197}
1198
1199static void inject_rmode_irq(struct kvm_vcpu *vcpu, int irq)
1200{
1201 u16 ent[2];
1202 u16 cs;
1203 u16 ip;
1204 unsigned long flags;
1205 unsigned long ss_base = vmcs_readl(GUEST_SS_BASE);
1206 u16 sp = vmcs_readl(GUEST_RSP);
1207 u32 ss_limit = vmcs_read32(GUEST_SS_LIMIT);
1208
1209 if (sp > ss_limit || sp - 6 > sp) {
1210 vcpu_printf(vcpu, "%s: #SS, rsp 0x%lx ss 0x%lx limit 0x%x\n",
1211 __FUNCTION__,
1212 vmcs_readl(GUEST_RSP),
1213 vmcs_readl(GUEST_SS_BASE),
1214 vmcs_read32(GUEST_SS_LIMIT));
1215 return;
1216 }
1217
1218 if (kvm_read_guest(vcpu, irq * sizeof(ent), sizeof(ent), &ent) !=
1219 sizeof(ent)) {
1220 vcpu_printf(vcpu, "%s: read guest err\n", __FUNCTION__);
1221 return;
1222 }
1223
1224 flags = vmcs_readl(GUEST_RFLAGS);
1225 cs = vmcs_readl(GUEST_CS_BASE) >> 4;
1226 ip = vmcs_readl(GUEST_RIP);
1227
1228
1229 if (kvm_write_guest(vcpu, ss_base + sp - 2, 2, &flags) != 2 ||
1230 kvm_write_guest(vcpu, ss_base + sp - 4, 2, &cs) != 2 ||
1231 kvm_write_guest(vcpu, ss_base + sp - 6, 2, &ip) != 2) {
1232 vcpu_printf(vcpu, "%s: write guest err\n", __FUNCTION__);
1233 return;
1234 }
1235
1236 vmcs_writel(GUEST_RFLAGS, flags &
1237 ~( X86_EFLAGS_IF | X86_EFLAGS_AC | X86_EFLAGS_TF));
1238 vmcs_write16(GUEST_CS_SELECTOR, ent[1]) ;
1239 vmcs_writel(GUEST_CS_BASE, ent[1] << 4);
1240 vmcs_writel(GUEST_RIP, ent[0]);
1241 vmcs_writel(GUEST_RSP, (vmcs_readl(GUEST_RSP) & ~0xffff) | (sp - 6));
1242}
1243
1244static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
1245{
1246 int word_index = __ffs(vcpu->irq_summary);
1247 int bit_index = __ffs(vcpu->irq_pending[word_index]);
1248 int irq = word_index * BITS_PER_LONG + bit_index;
1249
1250 clear_bit(bit_index, &vcpu->irq_pending[word_index]);
1251 if (!vcpu->irq_pending[word_index])
1252 clear_bit(word_index, &vcpu->irq_summary);
1253
1254 if (vcpu->rmode.active) {
1255 inject_rmode_irq(vcpu, irq);
1256 return;
1257 }
1258 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1259 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1260}
1261
1262static void kvm_try_inject_irq(struct kvm_vcpu *vcpu)
1263{
1264 if ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF)
1265 && (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0)
1266 /*
1267 * Interrupts enabled, and not blocked by sti or mov ss. Good.
1268 */
1269 kvm_do_inject_irq(vcpu);
1270 else
1271 /*
1272 * Interrupts blocked. Wait for unblock.
1273 */
1274 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1275 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL)
1276 | CPU_BASED_VIRTUAL_INTR_PENDING);
1277}
1278
1279static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
1280{
1281 struct kvm_guest_debug *dbg = &vcpu->guest_debug;
1282
1283 set_debugreg(dbg->bp[0], 0);
1284 set_debugreg(dbg->bp[1], 1);
1285 set_debugreg(dbg->bp[2], 2);
1286 set_debugreg(dbg->bp[3], 3);
1287
1288 if (dbg->singlestep) {
1289 unsigned long flags;
1290
1291 flags = vmcs_readl(GUEST_RFLAGS);
1292 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1293 vmcs_writel(GUEST_RFLAGS, flags);
1294 }
1295}
1296
1297static int handle_rmode_exception(struct kvm_vcpu *vcpu,
1298 int vec, u32 err_code)
1299{
1300 if (!vcpu->rmode.active)
1301 return 0;
1302
1303 if (vec == GP_VECTOR && err_code == 0)
1304 if (emulate_instruction(vcpu, NULL, 0, 0) == EMULATE_DONE)
1305 return 1;
1306 return 0;
1307}
1308
1309static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1310{
1311 u32 intr_info, error_code;
1312 unsigned long cr2, rip;
1313 u32 vect_info;
1314 enum emulation_result er;
1315
1316 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
1317 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
1318
1319 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
1320 !is_page_fault(intr_info)) {
1321 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
1322 "intr info 0x%x\n", __FUNCTION__, vect_info, intr_info);
1323 }
1324
1325 if (is_external_interrupt(vect_info)) {
1326 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
1327 set_bit(irq, vcpu->irq_pending);
1328 set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
1329 }
1330
1331 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) { /* nmi */
1332 asm ("int $2");
1333 return 1;
1334 }
1335 error_code = 0;
1336 rip = vmcs_readl(GUEST_RIP);
1337 if (intr_info & INTR_INFO_DELIEVER_CODE_MASK)
1338 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
1339 if (is_page_fault(intr_info)) {
1340 cr2 = vmcs_readl(EXIT_QUALIFICATION);
1341
1342 spin_lock(&vcpu->kvm->lock);
1343 if (!vcpu->mmu.page_fault(vcpu, cr2, error_code)) {
1344 spin_unlock(&vcpu->kvm->lock);
1345 return 1;
1346 }
1347
1348 er = emulate_instruction(vcpu, kvm_run, cr2, error_code);
1349 spin_unlock(&vcpu->kvm->lock);
1350
1351 switch (er) {
1352 case EMULATE_DONE:
1353 return 1;
1354 case EMULATE_DO_MMIO:
1355 ++kvm_stat.mmio_exits;
1356 kvm_run->exit_reason = KVM_EXIT_MMIO;
1357 return 0;
1358 case EMULATE_FAIL:
1359 vcpu_printf(vcpu, "%s: emulate fail\n", __FUNCTION__);
1360 break;
1361 default:
1362 BUG();
1363 }
1364 }
1365
1366 if (vcpu->rmode.active &&
1367 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
1368 error_code))
1369 return 1;
1370
1371 if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) == (INTR_TYPE_EXCEPTION | 1)) {
1372 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1373 return 0;
1374 }
1375 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
1376 kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
1377 kvm_run->ex.error_code = error_code;
1378 return 0;
1379}
1380
1381static int handle_external_interrupt(struct kvm_vcpu *vcpu,
1382 struct kvm_run *kvm_run)
1383{
1384 ++kvm_stat.irq_exits;
1385 return 1;
1386}
1387
1388
1389static int get_io_count(struct kvm_vcpu *vcpu, u64 *count)
1390{
1391 u64 inst;
1392 gva_t rip;
1393 int countr_size;
1394 int i, n;
1395
1396 if ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_VM)) {
1397 countr_size = 2;
1398 } else {
1399 u32 cs_ar = vmcs_read32(GUEST_CS_AR_BYTES);
1400
1401 countr_size = (cs_ar & AR_L_MASK) ? 8:
1402 (cs_ar & AR_DB_MASK) ? 4: 2;
1403 }
1404
1405 rip = vmcs_readl(GUEST_RIP);
1406 if (countr_size != 8)
1407 rip += vmcs_readl(GUEST_CS_BASE);
1408
1409 n = kvm_read_guest(vcpu, rip, sizeof(inst), &inst);
1410
1411 for (i = 0; i < n; i++) {
1412 switch (((u8*)&inst)[i]) {
1413 case 0xf0:
1414 case 0xf2:
1415 case 0xf3:
1416 case 0x2e:
1417 case 0x36:
1418 case 0x3e:
1419 case 0x26:
1420 case 0x64:
1421 case 0x65:
1422 case 0x66:
1423 break;
1424 case 0x67:
1425 countr_size = (countr_size == 2) ? 4: (countr_size >> 1);
1426 default:
1427 goto done;
1428 }
1429 }
1430 return 0;
1431done:
1432 countr_size *= 8;
1433 *count = vcpu->regs[VCPU_REGS_RCX] & (~0ULL >> (64 - countr_size));
1434 return 1;
1435}
1436
1437static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1438{
1439 u64 exit_qualification;
1440
1441 ++kvm_stat.io_exits;
1442 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
1443 kvm_run->exit_reason = KVM_EXIT_IO;
1444 if (exit_qualification & 8)
1445 kvm_run->io.direction = KVM_EXIT_IO_IN;
1446 else
1447 kvm_run->io.direction = KVM_EXIT_IO_OUT;
1448 kvm_run->io.size = (exit_qualification & 7) + 1;
1449 kvm_run->io.string = (exit_qualification & 16) != 0;
1450 kvm_run->io.string_down
1451 = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
1452 kvm_run->io.rep = (exit_qualification & 32) != 0;
1453 kvm_run->io.port = exit_qualification >> 16;
1454 if (kvm_run->io.string) {
1455 if (!get_io_count(vcpu, &kvm_run->io.count))
1456 return 1;
1457 kvm_run->io.address = vmcs_readl(GUEST_LINEAR_ADDRESS);
1458 } else
1459 kvm_run->io.value = vcpu->regs[VCPU_REGS_RAX]; /* rax */
1460 return 0;
1461}
1462
1463static int handle_invlpg(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1464{
1465 u64 address = vmcs_read64(EXIT_QUALIFICATION);
1466 int instruction_length = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1467 spin_lock(&vcpu->kvm->lock);
1468 vcpu->mmu.inval_page(vcpu, address);
1469 spin_unlock(&vcpu->kvm->lock);
1470 vmcs_writel(GUEST_RIP, vmcs_readl(GUEST_RIP) + instruction_length);
1471 return 1;
1472}
1473
1474static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1475{
1476 u64 exit_qualification;
1477 int cr;
1478 int reg;
1479
1480 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
1481 cr = exit_qualification & 15;
1482 reg = (exit_qualification >> 8) & 15;
1483 switch ((exit_qualification >> 4) & 3) {
1484 case 0: /* mov to cr */
1485 switch (cr) {
1486 case 0:
1487 vcpu_load_rsp_rip(vcpu);
1488 set_cr0(vcpu, vcpu->regs[reg]);
1489 skip_emulated_instruction(vcpu);
1490 return 1;
1491 case 3:
1492 vcpu_load_rsp_rip(vcpu);
1493 set_cr3(vcpu, vcpu->regs[reg]);
1494 skip_emulated_instruction(vcpu);
1495 return 1;
1496 case 4:
1497 vcpu_load_rsp_rip(vcpu);
1498 set_cr4(vcpu, vcpu->regs[reg]);
1499 skip_emulated_instruction(vcpu);
1500 return 1;
1501 case 8:
1502 vcpu_load_rsp_rip(vcpu);
1503 set_cr8(vcpu, vcpu->regs[reg]);
1504 skip_emulated_instruction(vcpu);
1505 return 1;
1506 };
1507 break;
1508 case 1: /*mov from cr*/
1509 switch (cr) {
1510 case 3:
1511 vcpu_load_rsp_rip(vcpu);
1512 vcpu->regs[reg] = vcpu->cr3;
1513 vcpu_put_rsp_rip(vcpu);
1514 skip_emulated_instruction(vcpu);
1515 return 1;
1516 case 8:
1517 printk(KERN_DEBUG "handle_cr: read CR8 "
1518 "cpu erratum AA15\n");
1519 vcpu_load_rsp_rip(vcpu);
1520 vcpu->regs[reg] = vcpu->cr8;
1521 vcpu_put_rsp_rip(vcpu);
1522 skip_emulated_instruction(vcpu);
1523 return 1;
1524 }
1525 break;
1526 case 3: /* lmsw */
1527 lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
1528
1529 skip_emulated_instruction(vcpu);
1530 return 1;
1531 default:
1532 break;
1533 }
1534 kvm_run->exit_reason = 0;
1535 printk(KERN_ERR "kvm: unhandled control register: op %d cr %d\n",
1536 (int)(exit_qualification >> 4) & 3, cr);
1537 return 0;
1538}
1539
1540static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1541{
1542 u64 exit_qualification;
1543 unsigned long val;
1544 int dr, reg;
1545
1546 /*
1547 * FIXME: this code assumes the host is debugging the guest.
1548 * need to deal with guest debugging itself too.
1549 */
1550 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
1551 dr = exit_qualification & 7;
1552 reg = (exit_qualification >> 8) & 15;
1553 vcpu_load_rsp_rip(vcpu);
1554 if (exit_qualification & 16) {
1555 /* mov from dr */
1556 switch (dr) {
1557 case 6:
1558 val = 0xffff0ff0;
1559 break;
1560 case 7:
1561 val = 0x400;
1562 break;
1563 default:
1564 val = 0;
1565 }
1566 vcpu->regs[reg] = val;
1567 } else {
1568 /* mov to dr */
1569 }
1570 vcpu_put_rsp_rip(vcpu);
1571 skip_emulated_instruction(vcpu);
1572 return 1;
1573}
1574
1575static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1576{
1577 kvm_run->exit_reason = KVM_EXIT_CPUID;
1578 return 0;
1579}
1580
1581static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1582{
1583 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1584 u64 data;
1585
1586 if (vmx_get_msr(vcpu, ecx, &data)) {
1587 vmx_inject_gp(vcpu, 0);
1588 return 1;
1589 }
1590
1591 /* FIXME: handling of bits 32:63 of rax, rdx */
1592 vcpu->regs[VCPU_REGS_RAX] = data & -1u;
1593 vcpu->regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
1594 skip_emulated_instruction(vcpu);
1595 return 1;
1596}
1597
1598static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1599{
1600 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1601 u64 data = (vcpu->regs[VCPU_REGS_RAX] & -1u)
1602 | ((u64)(vcpu->regs[VCPU_REGS_RDX] & -1u) << 32);
1603
1604 if (vmx_set_msr(vcpu, ecx, data) != 0) {
1605 vmx_inject_gp(vcpu, 0);
1606 return 1;
1607 }
1608
1609 skip_emulated_instruction(vcpu);
1610 return 1;
1611}
1612
1613static int handle_interrupt_window(struct kvm_vcpu *vcpu,
1614 struct kvm_run *kvm_run)
1615{
1616 /* Turn off interrupt window reporting. */
1617 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1618 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL)
1619 & ~CPU_BASED_VIRTUAL_INTR_PENDING);
1620 return 1;
1621}
1622
1623static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1624{
1625 skip_emulated_instruction(vcpu);
1626 if (vcpu->irq_summary && (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF))
1627 return 1;
1628
1629 kvm_run->exit_reason = KVM_EXIT_HLT;
1630 return 0;
1631}
1632
1633/*
1634 * The exit handlers return 1 if the exit was handled fully and guest execution
1635 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
1636 * to be done to userspace and return 0.
1637 */
1638static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
1639 struct kvm_run *kvm_run) = {
1640 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
1641 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
1642 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
1643 [EXIT_REASON_INVLPG] = handle_invlpg,
1644 [EXIT_REASON_CR_ACCESS] = handle_cr,
1645 [EXIT_REASON_DR_ACCESS] = handle_dr,
1646 [EXIT_REASON_CPUID] = handle_cpuid,
1647 [EXIT_REASON_MSR_READ] = handle_rdmsr,
1648 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
1649 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
1650 [EXIT_REASON_HLT] = handle_halt,
1651};
1652
1653static const int kvm_vmx_max_exit_handlers =
1654 sizeof(kvm_vmx_exit_handlers) / sizeof(*kvm_vmx_exit_handlers);
1655
1656/*
1657 * The guest has exited. See if we can fix it or if we need userspace
1658 * assistance.
1659 */
1660static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
1661{
1662 u32 vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
1663 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
1664
1665 if ( (vectoring_info & VECTORING_INFO_VALID_MASK) &&
1666 exit_reason != EXIT_REASON_EXCEPTION_NMI )
1667 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
1668 "exit reason is 0x%x\n", __FUNCTION__, exit_reason);
1669 kvm_run->instruction_length = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1670 if (exit_reason < kvm_vmx_max_exit_handlers
1671 && kvm_vmx_exit_handlers[exit_reason])
1672 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
1673 else {
1674 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1675 kvm_run->hw.hardware_exit_reason = exit_reason;
1676 }
1677 return 0;
1678}
1679
1680static int vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1681{
1682 u8 fail;
1683 u16 fs_sel, gs_sel, ldt_sel;
1684 int fs_gs_ldt_reload_needed;
1685
1686again:
1687 /*
1688 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1689 * allow segment selectors with cpl > 0 or ti == 1.
1690 */
1691 fs_sel = read_fs();
1692 gs_sel = read_gs();
1693 ldt_sel = read_ldt();
1694 fs_gs_ldt_reload_needed = (fs_sel & 7) | (gs_sel & 7) | ldt_sel;
1695 if (!fs_gs_ldt_reload_needed) {
1696 vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1697 vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1698 } else {
1699 vmcs_write16(HOST_FS_SELECTOR, 0);
1700 vmcs_write16(HOST_GS_SELECTOR, 0);
1701 }
1702
05b3e0c2 1703#ifdef CONFIG_X86_64
6aa8b732
AK		 1704 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1705 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1706#else
1707 vmcs_writel(HOST_FS_BASE, segment_base(fs_sel));
1708 vmcs_writel(HOST_GS_BASE, segment_base(gs_sel));
1709#endif
1710
1711 if (vcpu->irq_summary &&
1712 !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
1713 kvm_try_inject_irq(vcpu);
1714
1715 if (vcpu->guest_debug.enabled)
1716 kvm_guest_debug_pre(vcpu);
1717
1718 fx_save(vcpu->host_fx_image);
1719 fx_restore(vcpu->guest_fx_image);
1720
1721 save_msrs(vcpu->host_msrs, vcpu->nmsrs);
1722 load_msrs(vcpu->guest_msrs, NR_BAD_MSRS);
1723
1724 asm (
1725 /* Store host registers */
1726 "pushf \n\t"
05b3e0c2 1727#ifdef CONFIG_X86_64
6aa8b732
AK		 1728 "push %%rax; push %%rbx; push %%rdx;"
1729 "push %%rsi; push %%rdi; push %%rbp;"
1730 "push %%r8; push %%r9; push %%r10; push %%r11;"
1731 "push %%r12; push %%r13; push %%r14; push %%r15;"
1732 "push %%rcx \n\t"
1733 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
1734#else
1735 "pusha; push %%ecx \n\t"
1736 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
1737#endif
1738 /* Check if vmlaunch of vmresume is needed */
1739 "cmp $0, %1 \n\t"
1740 /* Load guest registers. Don't clobber flags. */
05b3e0c2 1741#ifdef CONFIG_X86_64
6aa8b732
AK		 1742 "mov %c[cr2](%3), %%rax \n\t"
1743 "mov %%rax, %%cr2 \n\t"
1744 "mov %c[rax](%3), %%rax \n\t"
1745 "mov %c[rbx](%3), %%rbx \n\t"
1746 "mov %c[rdx](%3), %%rdx \n\t"
1747 "mov %c[rsi](%3), %%rsi \n\t"
1748 "mov %c[rdi](%3), %%rdi \n\t"
1749 "mov %c[rbp](%3), %%rbp \n\t"
1750 "mov %c[r8](%3), %%r8 \n\t"
1751 "mov %c[r9](%3), %%r9 \n\t"
1752 "mov %c[r10](%3), %%r10 \n\t"
1753 "mov %c[r11](%3), %%r11 \n\t"
1754 "mov %c[r12](%3), %%r12 \n\t"
1755 "mov %c[r13](%3), %%r13 \n\t"
1756 "mov %c[r14](%3), %%r14 \n\t"
1757 "mov %c[r15](%3), %%r15 \n\t"
1758 "mov %c[rcx](%3), %%rcx \n\t" /* kills %3 (rcx) */
1759#else
1760 "mov %c[cr2](%3), %%eax \n\t"
1761 "mov %%eax, %%cr2 \n\t"
1762 "mov %c[rax](%3), %%eax \n\t"
1763 "mov %c[rbx](%3), %%ebx \n\t"
1764 "mov %c[rdx](%3), %%edx \n\t"
1765 "mov %c[rsi](%3), %%esi \n\t"
1766 "mov %c[rdi](%3), %%edi \n\t"
1767 "mov %c[rbp](%3), %%ebp \n\t"
1768 "mov %c[rcx](%3), %%ecx \n\t" /* kills %3 (ecx) */
1769#endif
1770 /* Enter guest mode */
1771 "jne launched \n\t"
1772 ASM_VMX_VMLAUNCH "\n\t"
1773 "jmp kvm_vmx_return \n\t"
1774 "launched: " ASM_VMX_VMRESUME "\n\t"
1775 ".globl kvm_vmx_return \n\t"
1776 "kvm_vmx_return: "
1777 /* Save guest registers, load host registers, keep flags */
05b3e0c2 1778#ifdef CONFIG_X86_64
6aa8b732
AK		 1779 "xchg %3, 0(%%rsp) \n\t"
1780 "mov %%rax, %c[rax](%3) \n\t"
1781 "mov %%rbx, %c[rbx](%3) \n\t"
1782 "pushq 0(%%rsp); popq %c[rcx](%3) \n\t"
1783 "mov %%rdx, %c[rdx](%3) \n\t"
1784 "mov %%rsi, %c[rsi](%3) \n\t"
1785 "mov %%rdi, %c[rdi](%3) \n\t"
1786 "mov %%rbp, %c[rbp](%3) \n\t"
1787 "mov %%r8, %c[r8](%3) \n\t"
1788 "mov %%r9, %c[r9](%3) \n\t"
1789 "mov %%r10, %c[r10](%3) \n\t"
1790 "mov %%r11, %c[r11](%3) \n\t"
1791 "mov %%r12, %c[r12](%3) \n\t"
1792 "mov %%r13, %c[r13](%3) \n\t"
1793 "mov %%r14, %c[r14](%3) \n\t"
1794 "mov %%r15, %c[r15](%3) \n\t"
1795 "mov %%cr2, %%rax \n\t"
1796 "mov %%rax, %c[cr2](%3) \n\t"
1797 "mov 0(%%rsp), %3 \n\t"
1798
1799 "pop %%rcx; pop %%r15; pop %%r14; pop %%r13; pop %%r12;"
1800 "pop %%r11; pop %%r10; pop %%r9; pop %%r8;"
1801 "pop %%rbp; pop %%rdi; pop %%rsi;"
1802 "pop %%rdx; pop %%rbx; pop %%rax \n\t"
1803#else
1804 "xchg %3, 0(%%esp) \n\t"
1805 "mov %%eax, %c[rax](%3) \n\t"
1806 "mov %%ebx, %c[rbx](%3) \n\t"
1807 "pushl 0(%%esp); popl %c[rcx](%3) \n\t"
1808 "mov %%edx, %c[rdx](%3) \n\t"
1809 "mov %%esi, %c[rsi](%3) \n\t"
1810 "mov %%edi, %c[rdi](%3) \n\t"
1811 "mov %%ebp, %c[rbp](%3) \n\t"
1812 "mov %%cr2, %%eax \n\t"
1813 "mov %%eax, %c[cr2](%3) \n\t"
1814 "mov 0(%%esp), %3 \n\t"
1815
1816 "pop %%ecx; popa \n\t"
1817#endif
1818 "setbe %0 \n\t"
1819 "popf \n\t"
1820 : "=g" (fail)
1821 : "r"(vcpu->launched), "d"((unsigned long)HOST_RSP),
1822 "c"(vcpu),
1823 [rax]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RAX])),
1824 [rbx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBX])),
1825 [rcx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RCX])),
1826 [rdx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDX])),
1827 [rsi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RSI])),
1828 [rdi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDI])),
1829 [rbp]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBP])),
05b3e0c2 1830#ifdef CONFIG_X86_64
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AK		 1831 [r8 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R8 ])),
1832 [r9 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R9 ])),
1833 [r10]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R10])),
1834 [r11]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R11])),
1835 [r12]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R12])),
1836 [r13]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R13])),
1837 [r14]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R14])),
1838 [r15]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R15])),
1839#endif
1840 [cr2]"i"(offsetof(struct kvm_vcpu, cr2))
1841 : "cc", "memory" );
1842
1843 ++kvm_stat.exits;
1844
1845 save_msrs(vcpu->guest_msrs, NR_BAD_MSRS);
1846 load_msrs(vcpu->host_msrs, NR_BAD_MSRS);
1847
1848 fx_save(vcpu->guest_fx_image);
1849 fx_restore(vcpu->host_fx_image);
1850
05b3e0c2 1851#ifndef CONFIG_X86_64
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AK		 1852 asm ("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
1853#endif
1854
1855 kvm_run->exit_type = 0;
1856 if (fail) {
1857 kvm_run->exit_type = KVM_EXIT_TYPE_FAIL_ENTRY;
1858 kvm_run->exit_reason = vmcs_read32(VM_INSTRUCTION_ERROR);
1859 } else {
1860 if (fs_gs_ldt_reload_needed) {
1861 load_ldt(ldt_sel);
1862 load_fs(fs_sel);
1863 /*
1864 * If we have to reload gs, we must take care to
1865 * preserve our gs base.
1866 */
1867 local_irq_disable();
1868 load_gs(gs_sel);
05b3e0c2 1869#ifdef CONFIG_X86_64
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AK		 1870 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
1871#endif
1872 local_irq_enable();
1873
1874 reload_tss();
1875 }
1876 vcpu->launched = 1;
1877 kvm_run->exit_type = KVM_EXIT_TYPE_VM_EXIT;
1878 if (kvm_handle_exit(kvm_run, vcpu)) {
1879 /* Give scheduler a change to reschedule. */
1880 if (signal_pending(current)) {
1881 ++kvm_stat.signal_exits;
1882 return -EINTR;
1883 }
1884 kvm_resched(vcpu);
1885 goto again;
1886 }
1887 }
1888 return 0;
1889}
1890
1891static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1892{
1893 vmcs_writel(GUEST_CR3, vmcs_readl(GUEST_CR3));
1894}
1895
1896static void vmx_inject_page_fault(struct kvm_vcpu *vcpu,
1897 unsigned long addr,
1898 u32 err_code)
1899{
1900 u32 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
1901
1902 ++kvm_stat.pf_guest;
1903
1904 if (is_page_fault(vect_info)) {
1905 printk(KERN_DEBUG "inject_page_fault: "
1906 "double fault 0x%lx @ 0x%lx\n",
1907 addr, vmcs_readl(GUEST_RIP));
1908 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, 0);
1909 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1910 DF_VECTOR |
1911 INTR_TYPE_EXCEPTION |
1912 INTR_INFO_DELIEVER_CODE_MASK |
1913 INTR_INFO_VALID_MASK);
1914 return;
1915 }
1916 vcpu->cr2 = addr;
1917 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, err_code);
1918 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1919 PF_VECTOR |
1920 INTR_TYPE_EXCEPTION |
1921 INTR_INFO_DELIEVER_CODE_MASK |
1922 INTR_INFO_VALID_MASK);
1923
1924}
1925
1926static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
1927{
1928 if (vcpu->vmcs) {
1929 on_each_cpu(__vcpu_clear, vcpu, 0, 1);
1930 free_vmcs(vcpu->vmcs);
1931 vcpu->vmcs = NULL;
1932 }
1933}
1934
1935static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
1936{
1937 vmx_free_vmcs(vcpu);
1938}
1939
1940static int vmx_create_vcpu(struct kvm_vcpu *vcpu)
1941{
1942 struct vmcs *vmcs;
1943
1944 vmcs = alloc_vmcs();
1945 if (!vmcs)
1946 return -ENOMEM;
1947 vmcs_clear(vmcs);
1948 vcpu->vmcs = vmcs;
1949 vcpu->launched = 0;
1950 return 0;
1951}
1952
1953static struct kvm_arch_ops vmx_arch_ops = {
1954 .cpu_has_kvm_support = cpu_has_kvm_support,
1955 .disabled_by_bios = vmx_disabled_by_bios,
1956 .hardware_setup = hardware_setup,
1957 .hardware_unsetup = hardware_unsetup,
1958 .hardware_enable = hardware_enable,
1959 .hardware_disable = hardware_disable,
1960
1961 .vcpu_create = vmx_create_vcpu,
1962 .vcpu_free = vmx_free_vcpu,
1963
1964 .vcpu_load = vmx_vcpu_load,
1965 .vcpu_put = vmx_vcpu_put,
1966
1967 .set_guest_debug = set_guest_debug,
1968 .get_msr = vmx_get_msr,
1969 .set_msr = vmx_set_msr,
1970 .get_segment_base = vmx_get_segment_base,
1971 .get_segment = vmx_get_segment,
1972 .set_segment = vmx_set_segment,
1973 .is_long_mode = vmx_is_long_mode,
1974 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
1975 .set_cr0 = vmx_set_cr0,
1976 .set_cr0_no_modeswitch = vmx_set_cr0_no_modeswitch,
1977 .set_cr3 = vmx_set_cr3,
1978 .set_cr4 = vmx_set_cr4,
05b3e0c2 1979#ifdef CONFIG_X86_64
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AK		 1980 .set_efer = vmx_set_efer,
1981#endif
1982 .get_idt = vmx_get_idt,
1983 .set_idt = vmx_set_idt,
1984 .get_gdt = vmx_get_gdt,
1985 .set_gdt = vmx_set_gdt,
1986 .cache_regs = vcpu_load_rsp_rip,
1987 .decache_regs = vcpu_put_rsp_rip,
1988 .get_rflags = vmx_get_rflags,
1989 .set_rflags = vmx_set_rflags,
1990
1991 .tlb_flush = vmx_flush_tlb,
1992 .inject_page_fault = vmx_inject_page_fault,
1993
1994 .inject_gp = vmx_inject_gp,
1995
1996 .run = vmx_vcpu_run,
1997 .skip_emulated_instruction = skip_emulated_instruction,
1998 .vcpu_setup = vmx_vcpu_setup,
1999};
2000
2001static int __init vmx_init(void)
2002{
873a7c42 2003 return kvm_init_arch(&vmx_arch_ops, THIS_MODULE);
6aa8b732
AK		 2004}
2005
2006static void __exit vmx_exit(void)
2007{
2008 kvm_exit_arch();
2009}
2010
2011module_init(vmx_init)
2012module_exit(vmx_exit)
kernel source for telekom puls (alcatel/mediatek)