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KVM: Don't complain about cpu erratum AA15
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
16
17#include <linux/module.h>
9d8f549d 18#include <linux/kernel.h>
6aa8b732
AK		 19#include <linux/vmalloc.h>
20#include <linux/highmem.h>
07031e14 21#include <linux/profile.h>
6aa8b732
AK		 22#include <asm/desc.h>
23
24#include "kvm_svm.h"
25#include "x86_emulate.h"
26
27MODULE_AUTHOR("Qumranet");
28MODULE_LICENSE("GPL");
29
30#define IOPM_ALLOC_ORDER 2
31#define MSRPM_ALLOC_ORDER 1
32
33#define DB_VECTOR 1
34#define UD_VECTOR 6
35#define GP_VECTOR 13
36
37#define DR7_GD_MASK (1 << 13)
38#define DR6_BD_MASK (1 << 13)
39#define CR4_DE_MASK (1UL << 3)
40
41#define SEG_TYPE_LDT 2
42#define SEG_TYPE_BUSY_TSS16 3
43
44#define KVM_EFER_LMA (1 << 10)
45#define KVM_EFER_LME (1 << 8)
46
80b7706e
JR		 47#define SVM_FEATURE_NPT (1 << 0)
48#define SVM_FEATURE_LBRV (1 << 1)
49#define SVM_DEATURE_SVML (1 << 2)
50
6aa8b732
AK		 51unsigned long iopm_base;
52unsigned long msrpm_base;
53
54struct kvm_ldttss_desc {
55 u16 limit0;
56 u16 base0;
57 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
58 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
59 u32 base3;
60 u32 zero1;
61} __attribute__((packed));
62
63struct svm_cpu_data {
64 int cpu;
65
5008fdf5
AK		 66 u64 asid_generation;
67 u32 max_asid;
68 u32 next_asid;
6aa8b732
AK		 69 struct kvm_ldttss_desc *tss_desc;
70
71 struct page *save_area;
72};
73
74static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80b7706e 75static uint32_t svm_features;
6aa8b732
AK		 76
77struct svm_init_data {
78 int cpu;
79 int r;
80};
81
82static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
83
9d8f549d 84#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 85#define MSRS_RANGE_SIZE 2048
86#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
87
88#define MAX_INST_SIZE 15
89
80b7706e
JR		 90static inline u32 svm_has(u32 feat)
91{
92 return svm_features & feat;
93}
94
6aa8b732
AK		 95static unsigned get_addr_size(struct kvm_vcpu *vcpu)
96{
97 struct vmcb_save_area *sa = &vcpu->svm->vmcb->save;
98 u16 cs_attrib;
99
100 if (!(sa->cr0 & CR0_PE_MASK) || (sa->rflags & X86_EFLAGS_VM))
101 return 2;
102
103 cs_attrib = sa->cs.attrib;
104
105 return (cs_attrib & SVM_SELECTOR_L_MASK) ? 8 :
106 (cs_attrib & SVM_SELECTOR_DB_MASK) ? 4 : 2;
107}
108
109static inline u8 pop_irq(struct kvm_vcpu *vcpu)
110{
111 int word_index = __ffs(vcpu->irq_summary);
112 int bit_index = __ffs(vcpu->irq_pending[word_index]);
113 int irq = word_index * BITS_PER_LONG + bit_index;
114
115 clear_bit(bit_index, &vcpu->irq_pending[word_index]);
116 if (!vcpu->irq_pending[word_index])
117 clear_bit(word_index, &vcpu->irq_summary);
118 return irq;
119}
120
121static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq)
122{
123 set_bit(irq, vcpu->irq_pending);
124 set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
125}
126
127static inline void clgi(void)
128{
129 asm volatile (SVM_CLGI);
130}
131
132static inline void stgi(void)
133{
134 asm volatile (SVM_STGI);
135}
136
137static inline void invlpga(unsigned long addr, u32 asid)
138{
139 asm volatile (SVM_INVLPGA :: "a"(addr), "c"(asid));
140}
141
142static inline unsigned long kvm_read_cr2(void)
143{
144 unsigned long cr2;
145
146 asm volatile ("mov %%cr2, %0" : "=r" (cr2));
147 return cr2;
148}
149
150static inline void kvm_write_cr2(unsigned long val)
151{
152 asm volatile ("mov %0, %%cr2" :: "r" (val));
153}
154
155static inline unsigned long read_dr6(void)
156{
157 unsigned long dr6;
158
159 asm volatile ("mov %%dr6, %0" : "=r" (dr6));
160 return dr6;
161}
162
163static inline void write_dr6(unsigned long val)
164{
165 asm volatile ("mov %0, %%dr6" :: "r" (val));
166}
167
168static inline unsigned long read_dr7(void)
169{
170 unsigned long dr7;
171
172 asm volatile ("mov %%dr7, %0" : "=r" (dr7));
173 return dr7;
174}
175
176static inline void write_dr7(unsigned long val)
177{
178 asm volatile ("mov %0, %%dr7" :: "r" (val));
179}
180
6aa8b732
AK		 181static inline void force_new_asid(struct kvm_vcpu *vcpu)
182{
183 vcpu->svm->asid_generation--;
184}
185
186static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
187{
188 force_new_asid(vcpu);
189}
190
191static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
192{
193 if (!(efer & KVM_EFER_LMA))
194 efer &= ~KVM_EFER_LME;
195
196 vcpu->svm->vmcb->save.efer = efer | MSR_EFER_SVME_MASK;
197 vcpu->shadow_efer = efer;
198}
199
200static void svm_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code)
201{
202 vcpu->svm->vmcb->control.event_inj = SVM_EVTINJ_VALID |
203 SVM_EVTINJ_VALID_ERR |
204 SVM_EVTINJ_TYPE_EXEPT |
205 GP_VECTOR;
206 vcpu->svm->vmcb->control.event_inj_err = error_code;
207}
208
209static void inject_ud(struct kvm_vcpu *vcpu)
210{
211 vcpu->svm->vmcb->control.event_inj = SVM_EVTINJ_VALID |
212 SVM_EVTINJ_TYPE_EXEPT |
213 UD_VECTOR;
214}
215
6aa8b732
AK		 216static int is_page_fault(uint32_t info)
217{
218 info &= SVM_EVTINJ_VEC_MASK | SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
219 return info == (PF_VECTOR | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_EXEPT);
220}
221
222static int is_external_interrupt(u32 info)
223{
224 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
225 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
226}
227
228static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
229{
230 if (!vcpu->svm->next_rip) {
231 printk(KERN_DEBUG "%s: NOP\n", __FUNCTION__);
232 return;
233 }
234 if (vcpu->svm->next_rip - vcpu->svm->vmcb->save.rip > 15) {
235 printk(KERN_ERR "%s: ip 0x%llx next 0x%llx\n",
236 __FUNCTION__,
237 vcpu->svm->vmcb->save.rip,
238 vcpu->svm->next_rip);
239 }
240
241 vcpu->rip = vcpu->svm->vmcb->save.rip = vcpu->svm->next_rip;
242 vcpu->svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
c1150d8c
DL		 243
244 vcpu->interrupt_window_open = 1;
6aa8b732
AK		 245}
246
247static int has_svm(void)
248{
249 uint32_t eax, ebx, ecx, edx;
250
1e885461 251 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
6aa8b732
AK		 252 printk(KERN_INFO "has_svm: not amd\n");
253 return 0;
254 }
255
256 cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
257 if (eax < SVM_CPUID_FUNC) {
258 printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n");
259 return 0;
260 }
261
262 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
263 if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) {
264 printk(KERN_DEBUG "has_svm: svm not available\n");
265 return 0;
266 }
267 return 1;
268}
269
270static void svm_hardware_disable(void *garbage)
271{
272 struct svm_cpu_data *svm_data
273 = per_cpu(svm_data, raw_smp_processor_id());
274
275 if (svm_data) {
276 uint64_t efer;
277
278 wrmsrl(MSR_VM_HSAVE_PA, 0);
279 rdmsrl(MSR_EFER, efer);
280 wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK);
8b6d44c7 281 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
6aa8b732
AK		 282 __free_page(svm_data->save_area);
283 kfree(svm_data);
284 }
285}
286
287static void svm_hardware_enable(void *garbage)
288{
289
290 struct svm_cpu_data *svm_data;
291 uint64_t efer;
05b3e0c2 292#ifdef CONFIG_X86_64
6aa8b732
AK		 293 struct desc_ptr gdt_descr;
294#else
295 struct Xgt_desc_struct gdt_descr;
296#endif
297 struct desc_struct *gdt;
298 int me = raw_smp_processor_id();
299
300 if (!has_svm()) {
301 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
302 return;
303 }
304 svm_data = per_cpu(svm_data, me);
305
306 if (!svm_data) {
307 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
308 me);
309 return;
310 }
311
312 svm_data->asid_generation = 1;
313 svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
314 svm_data->next_asid = svm_data->max_asid + 1;
80b7706e 315 svm_features = cpuid_edx(SVM_CPUID_FUNC);
6aa8b732
AK		 316
317 asm volatile ( "sgdt %0" : "=m"(gdt_descr) );
318 gdt = (struct desc_struct *)gdt_descr.address;
319 svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
320
321 rdmsrl(MSR_EFER, efer);
322 wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK);
323
324 wrmsrl(MSR_VM_HSAVE_PA,
325 page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
326}
327
328static int svm_cpu_init(int cpu)
329{
330 struct svm_cpu_data *svm_data;
331 int r;
332
333 svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
334 if (!svm_data)
335 return -ENOMEM;
336 svm_data->cpu = cpu;
337 svm_data->save_area = alloc_page(GFP_KERNEL);
338 r = -ENOMEM;
339 if (!svm_data->save_area)
340 goto err_1;
341
342 per_cpu(svm_data, cpu) = svm_data;
343
344 return 0;
345
346err_1:
347 kfree(svm_data);
348 return r;
349
350}
351
352static int set_msr_interception(u32 *msrpm, unsigned msr,
353 int read, int write)
354{
355 int i;
356
357 for (i = 0; i < NUM_MSR_MAPS; i++) {
358 if (msr >= msrpm_ranges[i] &&
359 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
360 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
361 msrpm_ranges[i]) * 2;
362
363 u32 *base = msrpm + (msr_offset / 32);
364 u32 msr_shift = msr_offset % 32;
365 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
366 *base = (*base & ~(0x3 << msr_shift)) |
367 (mask << msr_shift);
368 return 1;
369 }
370 }
371 printk(KERN_DEBUG "%s: not found 0x%x\n", __FUNCTION__, msr);
372 return 0;
373}
374
375static __init int svm_hardware_setup(void)
376{
377 int cpu;
378 struct page *iopm_pages;
379 struct page *msrpm_pages;
380 void *msrpm_va;
381 int r;
382
873a7c42 383 kvm_emulator_want_group7_invlpg();
6aa8b732
AK		 384
385 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
386
387 if (!iopm_pages)
388 return -ENOMEM;
389 memset(page_address(iopm_pages), 0xff,
390 PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
391 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
392
393
394 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
395
396 r = -ENOMEM;
397 if (!msrpm_pages)
398 goto err_1;
399
400 msrpm_va = page_address(msrpm_pages);
401 memset(msrpm_va, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
402 msrpm_base = page_to_pfn(msrpm_pages) << PAGE_SHIFT;
403
05b3e0c2 404#ifdef CONFIG_X86_64
6aa8b732
AK		 405 set_msr_interception(msrpm_va, MSR_GS_BASE, 1, 1);
406 set_msr_interception(msrpm_va, MSR_FS_BASE, 1, 1);
407 set_msr_interception(msrpm_va, MSR_KERNEL_GS_BASE, 1, 1);
6aa8b732
AK		 408 set_msr_interception(msrpm_va, MSR_LSTAR, 1, 1);
409 set_msr_interception(msrpm_va, MSR_CSTAR, 1, 1);
410 set_msr_interception(msrpm_va, MSR_SYSCALL_MASK, 1, 1);
411#endif
0e859cac 412 set_msr_interception(msrpm_va, MSR_K6_STAR, 1, 1);
6aa8b732
AK		 413 set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_CS, 1, 1);
414 set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_ESP, 1, 1);
415 set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_EIP, 1, 1);
416
417 for_each_online_cpu(cpu) {
418 r = svm_cpu_init(cpu);
419 if (r)
420 goto err_2;
421 }
422 return 0;
423
424err_2:
425 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
426 msrpm_base = 0;
427err_1:
428 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
429 iopm_base = 0;
430 return r;
431}
432
433static __exit void svm_hardware_unsetup(void)
434{
435 __free_pages(pfn_to_page(msrpm_base >> PAGE_SHIFT), MSRPM_ALLOC_ORDER);
436 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
437 iopm_base = msrpm_base = 0;
438}
439
440static void init_seg(struct vmcb_seg *seg)
441{
442 seg->selector = 0;
443 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
444 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
445 seg->limit = 0xffff;
446 seg->base = 0;
447}
448
449static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
450{
451 seg->selector = 0;
452 seg->attrib = SVM_SELECTOR_P_MASK | type;
453 seg->limit = 0xffff;
454 seg->base = 0;
455}
456
457static int svm_vcpu_setup(struct kvm_vcpu *vcpu)
458{
459 return 0;
460}
461
462static void init_vmcb(struct vmcb *vmcb)
463{
464 struct vmcb_control_area *control = &vmcb->control;
465 struct vmcb_save_area *save = &vmcb->save;
6aa8b732
AK		 466
467 control->intercept_cr_read = INTERCEPT_CR0_MASK |
468 INTERCEPT_CR3_MASK |
469 INTERCEPT_CR4_MASK;
470
471 control->intercept_cr_write = INTERCEPT_CR0_MASK |
472 INTERCEPT_CR3_MASK |
473 INTERCEPT_CR4_MASK;
474
475 control->intercept_dr_read = INTERCEPT_DR0_MASK |
476 INTERCEPT_DR1_MASK |
477 INTERCEPT_DR2_MASK |
478 INTERCEPT_DR3_MASK;
479
480 control->intercept_dr_write = INTERCEPT_DR0_MASK |
481 INTERCEPT_DR1_MASK |
482 INTERCEPT_DR2_MASK |
483 INTERCEPT_DR3_MASK |
484 INTERCEPT_DR5_MASK |
485 INTERCEPT_DR7_MASK;
486
487 control->intercept_exceptions = 1 << PF_VECTOR;
488
489
490 control->intercept = (1ULL << INTERCEPT_INTR) |
491 (1ULL << INTERCEPT_NMI) |
0152527b 492 (1ULL << INTERCEPT_SMI) |
6aa8b732
AK		 493 /*
494 * selective cr0 intercept bug?
495 * 0: 0f 22 d8 mov %eax,%cr3
496 * 3: 0f 20 c0 mov %cr0,%eax
497 * 6: 0d 00 00 00 80 or $0x80000000,%eax
498 * b: 0f 22 c0 mov %eax,%cr0
499 * set cr3 ->interception
500 * get cr0 ->interception
501 * set cr0 -> no interception
502 */
503 /* (1ULL << INTERCEPT_SELECTIVE_CR0) | */
504 (1ULL << INTERCEPT_CPUID) |
505 (1ULL << INTERCEPT_HLT) |
6aa8b732
AK		 506 (1ULL << INTERCEPT_INVLPGA) |
507 (1ULL << INTERCEPT_IOIO_PROT) |
508 (1ULL << INTERCEPT_MSR_PROT) |
509 (1ULL << INTERCEPT_TASK_SWITCH) |
46fe4ddd 510 (1ULL << INTERCEPT_SHUTDOWN) |
6aa8b732
AK		 511 (1ULL << INTERCEPT_VMRUN) |
512 (1ULL << INTERCEPT_VMMCALL) |
513 (1ULL << INTERCEPT_VMLOAD) |
514 (1ULL << INTERCEPT_VMSAVE) |
515 (1ULL << INTERCEPT_STGI) |
516 (1ULL << INTERCEPT_CLGI) |
916ce236
JR		 517 (1ULL << INTERCEPT_SKINIT) |
518 (1ULL << INTERCEPT_MONITOR) |
519 (1ULL << INTERCEPT_MWAIT);
6aa8b732
AK		 520
521 control->iopm_base_pa = iopm_base;
522 control->msrpm_base_pa = msrpm_base;
0cc5064d 523 control->tsc_offset = 0;
6aa8b732 524 control->int_ctl = V_INTR_MASKING_MASK;
80b7706e
JR		 525 if (svm_has(SVM_FEATURE_LBRV))
526 control->lbr_ctl = 1ULL;
6aa8b732
AK		 527
528 init_seg(&save->es);
529 init_seg(&save->ss);
530 init_seg(&save->ds);
531 init_seg(&save->fs);
532 init_seg(&save->gs);
533
534 save->cs.selector = 0xf000;
535 /* Executable/Readable Code Segment */
536 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
537 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
538 save->cs.limit = 0xffff;
d92899a0
AK		 539 /*
540 * cs.base should really be 0xffff0000, but vmx can't handle that, so
541 * be consistent with it.
542 *
543 * Replace when we have real mode working for vmx.
544 */
545 save->cs.base = 0xf0000;
6aa8b732
AK		 546
547 save->gdtr.limit = 0xffff;
548 save->idtr.limit = 0xffff;
549
550 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
551 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
552
553 save->efer = MSR_EFER_SVME_MASK;
554
555 save->dr6 = 0xffff0ff0;
556 save->dr7 = 0x400;
557 save->rflags = 2;
558 save->rip = 0x0000fff0;
559
560 /*
561 * cr0 val on cpu init should be 0x60000010, we enable cpu
562 * cache by default. the orderly way is to enable cache in bios.
563 */
cd205625 564 save->cr0 = 0x00000010 | CR0_PG_MASK | CR0_WP_MASK;
6aa8b732
AK		 565 save->cr4 = CR4_PAE_MASK;
566 /* rdx = ?? */
567}
568
569static int svm_create_vcpu(struct kvm_vcpu *vcpu)
570{
571 struct page *page;
572 int r;
573
574 r = -ENOMEM;
575 vcpu->svm = kzalloc(sizeof *vcpu->svm, GFP_KERNEL);
576 if (!vcpu->svm)
577 goto out1;
578 page = alloc_page(GFP_KERNEL);
579 if (!page)
580 goto out2;
581
582 vcpu->svm->vmcb = page_address(page);
583 memset(vcpu->svm->vmcb, 0, PAGE_SIZE);
584 vcpu->svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
6aa8b732
AK		 585 vcpu->svm->asid_generation = 0;
586 memset(vcpu->svm->db_regs, 0, sizeof(vcpu->svm->db_regs));
587 init_vmcb(vcpu->svm->vmcb);
588
36241b8c 589 fx_init(vcpu);
7807fa6c 590 vcpu->fpu_active = 1;
6722c51c
AK		 591 vcpu->apic_base = 0xfee00000 |
592 /*for vcpu 0*/ MSR_IA32_APICBASE_BSP |
593 MSR_IA32_APICBASE_ENABLE;
36241b8c 594
6aa8b732
AK		 595 return 0;
596
597out2:
598 kfree(vcpu->svm);
599out1:
600 return r;
601}
602
603static void svm_free_vcpu(struct kvm_vcpu *vcpu)
604{
605 if (!vcpu->svm)
606 return;
607 if (vcpu->svm->vmcb)
608 __free_page(pfn_to_page(vcpu->svm->vmcb_pa >> PAGE_SHIFT));
609 kfree(vcpu->svm);
610}
611
bccf2150 612static void svm_vcpu_load(struct kvm_vcpu *vcpu)
6aa8b732 613{
0cc5064d
AK		 614 int cpu;
615
616 cpu = get_cpu();
617 if (unlikely(cpu != vcpu->cpu)) {
618 u64 tsc_this, delta;
619
620 /*
621 * Make sure that the guest sees a monotonically
622 * increasing TSC.
623 */
624 rdtscll(tsc_this);
625 delta = vcpu->host_tsc - tsc_this;
626 vcpu->svm->vmcb->control.tsc_offset += delta;
627 vcpu->cpu = cpu;
628 }
6aa8b732
AK		 629}
630
631static void svm_vcpu_put(struct kvm_vcpu *vcpu)
632{
0cc5064d 633 rdtscll(vcpu->host_tsc);
6aa8b732
AK		 634 put_cpu();
635}
636
774c47f1
AK		 637static void svm_vcpu_decache(struct kvm_vcpu *vcpu)
638{
639}
640
6aa8b732
AK		 641static void svm_cache_regs(struct kvm_vcpu *vcpu)
642{
643 vcpu->regs[VCPU_REGS_RAX] = vcpu->svm->vmcb->save.rax;
644 vcpu->regs[VCPU_REGS_RSP] = vcpu->svm->vmcb->save.rsp;
645 vcpu->rip = vcpu->svm->vmcb->save.rip;
646}
647
648static void svm_decache_regs(struct kvm_vcpu *vcpu)
649{
650 vcpu->svm->vmcb->save.rax = vcpu->regs[VCPU_REGS_RAX];
651 vcpu->svm->vmcb->save.rsp = vcpu->regs[VCPU_REGS_RSP];
652 vcpu->svm->vmcb->save.rip = vcpu->rip;
653}
654
655static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
656{
657 return vcpu->svm->vmcb->save.rflags;
658}
659
660static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
661{
662 vcpu->svm->vmcb->save.rflags = rflags;
663}
664
665static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
666{
667 struct vmcb_save_area *save = &vcpu->svm->vmcb->save;
668
669 switch (seg) {
670 case VCPU_SREG_CS: return &save->cs;
671 case VCPU_SREG_DS: return &save->ds;
672 case VCPU_SREG_ES: return &save->es;
673 case VCPU_SREG_FS: return &save->fs;
674 case VCPU_SREG_GS: return &save->gs;
675 case VCPU_SREG_SS: return &save->ss;
676 case VCPU_SREG_TR: return &save->tr;
677 case VCPU_SREG_LDTR: return &save->ldtr;
678 }
679 BUG();
8b6d44c7 680 return NULL;
6aa8b732
AK		 681}
682
683static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
684{
685 struct vmcb_seg *s = svm_seg(vcpu, seg);
686
687 return s->base;
688}
689
690static void svm_get_segment(struct kvm_vcpu *vcpu,
691 struct kvm_segment *var, int seg)
692{
693 struct vmcb_seg *s = svm_seg(vcpu, seg);
694
695 var->base = s->base;
696 var->limit = s->limit;
697 var->selector = s->selector;
698 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
699 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
700 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
701 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
702 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
703 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
704 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
705 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
706 var->unusable = !var->present;
707}
708
709static void svm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
710{
711 struct vmcb_seg *s = svm_seg(vcpu, VCPU_SREG_CS);
712
713 *db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
714 *l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
715}
716
717static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
718{
bce66ca4
LN		 719 dt->limit = vcpu->svm->vmcb->save.idtr.limit;
720 dt->base = vcpu->svm->vmcb->save.idtr.base;
6aa8b732
AK		 721}
722
723static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
724{
bce66ca4
LN		 725 vcpu->svm->vmcb->save.idtr.limit = dt->limit;
726 vcpu->svm->vmcb->save.idtr.base = dt->base ;
6aa8b732
AK		 727}
728
729static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
730{
731 dt->limit = vcpu->svm->vmcb->save.gdtr.limit;
732 dt->base = vcpu->svm->vmcb->save.gdtr.base;
733}
734
735static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
736{
737 vcpu->svm->vmcb->save.gdtr.limit = dt->limit;
738 vcpu->svm->vmcb->save.gdtr.base = dt->base ;
739}
740
399badf3
AK		 741static void svm_decache_cr0_cr4_guest_bits(struct kvm_vcpu *vcpu)
742{
743}
744
6aa8b732
AK		 745static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
746{
05b3e0c2 747#ifdef CONFIG_X86_64
6aa8b732
AK		 748 if (vcpu->shadow_efer & KVM_EFER_LME) {
749 if (!is_paging(vcpu) && (cr0 & CR0_PG_MASK)) {
750 vcpu->shadow_efer |= KVM_EFER_LMA;
751 vcpu->svm->vmcb->save.efer |= KVM_EFER_LMA | KVM_EFER_LME;
752 }
753
754 if (is_paging(vcpu) && !(cr0 & CR0_PG_MASK) ) {
755 vcpu->shadow_efer &= ~KVM_EFER_LMA;
756 vcpu->svm->vmcb->save.efer &= ~(KVM_EFER_LMA | KVM_EFER_LME);
757 }
758 }
759#endif
7807fa6c
AL		 760 if ((vcpu->cr0 & CR0_TS_MASK) && !(cr0 & CR0_TS_MASK)) {
761 vcpu->svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
762 vcpu->fpu_active = 1;
763 }
764
6aa8b732 765 vcpu->cr0 = cr0;
6da63cf9
AK		 766 cr0 |= CR0_PG_MASK | CR0_WP_MASK;
767 cr0 &= ~(CR0_CD_MASK | CR0_NW_MASK);
768 vcpu->svm->vmcb->save.cr0 = cr0;
6aa8b732
AK		 769}
770
771static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
772{
773 vcpu->cr4 = cr4;
774 vcpu->svm->vmcb->save.cr4 = cr4 | CR4_PAE_MASK;
775}
776
777static void svm_set_segment(struct kvm_vcpu *vcpu,
778 struct kvm_segment *var, int seg)
779{
780 struct vmcb_seg *s = svm_seg(vcpu, seg);
781
782 s->base = var->base;
783 s->limit = var->limit;
784 s->selector = var->selector;
785 if (var->unusable)
786 s->attrib = 0;
787 else {
788 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
789 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
790 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
791 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
792 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
793 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
794 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
795 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
796 }
797 if (seg == VCPU_SREG_CS)
798 vcpu->svm->vmcb->save.cpl
799 = (vcpu->svm->vmcb->save.cs.attrib
800 >> SVM_SELECTOR_DPL_SHIFT) & 3;
801
802}
803
804/* FIXME:
805
806 vcpu->svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
807 vcpu->svm->vmcb->control.int_ctl |= (sregs->cr8 & V_TPR_MASK);
808
809*/
810
811static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
812{
813 return -EOPNOTSUPP;
814}
815
816static void load_host_msrs(struct kvm_vcpu *vcpu)
817{
818 int i;
819
820 for ( i = 0; i < NR_HOST_SAVE_MSRS; i++)
821 wrmsrl(host_save_msrs[i], vcpu->svm->host_msrs[i]);
822}
823
824static void save_host_msrs(struct kvm_vcpu *vcpu)
825{
826 int i;
827
828 for ( i = 0; i < NR_HOST_SAVE_MSRS; i++)
829 rdmsrl(host_save_msrs[i], vcpu->svm->host_msrs[i]);
830}
831
832static void new_asid(struct kvm_vcpu *vcpu, struct svm_cpu_data *svm_data)
833{
834 if (svm_data->next_asid > svm_data->max_asid) {
835 ++svm_data->asid_generation;
836 svm_data->next_asid = 1;
837 vcpu->svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
838 }
839
840 vcpu->cpu = svm_data->cpu;
841 vcpu->svm->asid_generation = svm_data->asid_generation;
842 vcpu->svm->vmcb->control.asid = svm_data->next_asid++;
843}
844
845static void svm_invlpg(struct kvm_vcpu *vcpu, gva_t address)
846{
847 invlpga(address, vcpu->svm->vmcb->control.asid); // is needed?
848}
849
850static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
851{
852 return vcpu->svm->db_regs[dr];
853}
854
855static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
856 int *exception)
857{
858 *exception = 0;
859
860 if (vcpu->svm->vmcb->save.dr7 & DR7_GD_MASK) {
861 vcpu->svm->vmcb->save.dr7 &= ~DR7_GD_MASK;
862 vcpu->svm->vmcb->save.dr6 |= DR6_BD_MASK;
863 *exception = DB_VECTOR;
864 return;
865 }
866
867 switch (dr) {
868 case 0 ... 3:
869 vcpu->svm->db_regs[dr] = value;
870 return;
871 case 4 ... 5:
872 if (vcpu->cr4 & CR4_DE_MASK) {
873 *exception = UD_VECTOR;
874 return;
875 }
876 case 7: {
877 if (value & ~((1ULL << 32) - 1)) {
878 *exception = GP_VECTOR;
879 return;
880 }
881 vcpu->svm->vmcb->save.dr7 = value;
882 return;
883 }
884 default:
885 printk(KERN_DEBUG "%s: unexpected dr %u\n",
886 __FUNCTION__, dr);
887 *exception = UD_VECTOR;
888 return;
889 }
890}
891
892static int pf_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
893{
894 u32 exit_int_info = vcpu->svm->vmcb->control.exit_int_info;
895 u64 fault_address;
896 u32 error_code;
897 enum emulation_result er;
e2dec939 898 int r;
6aa8b732
AK		 899
900 if (is_external_interrupt(exit_int_info))
901 push_irq(vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK);
902
903 spin_lock(&vcpu->kvm->lock);
904
905 fault_address = vcpu->svm->vmcb->control.exit_info_2;
906 error_code = vcpu->svm->vmcb->control.exit_info_1;
e2dec939
AK		 907 r = kvm_mmu_page_fault(vcpu, fault_address, error_code);
908 if (r < 0) {
909 spin_unlock(&vcpu->kvm->lock);
910 return r;
911 }
912 if (!r) {
6aa8b732
AK		 913 spin_unlock(&vcpu->kvm->lock);
914 return 1;
915 }
916 er = emulate_instruction(vcpu, kvm_run, fault_address, error_code);
917 spin_unlock(&vcpu->kvm->lock);
918
919 switch (er) {
920 case EMULATE_DONE:
921 return 1;
922 case EMULATE_DO_MMIO:
1165f5fe 923 ++vcpu->stat.mmio_exits;
6aa8b732
AK		 924 kvm_run->exit_reason = KVM_EXIT_MMIO;
925 return 0;
926 case EMULATE_FAIL:
927 vcpu_printf(vcpu, "%s: emulate fail\n", __FUNCTION__);
928 break;
929 default:
930 BUG();
931 }
932
933 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
934 return 0;
935}
936
7807fa6c
AL		 937static int nm_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
938{
939 vcpu->svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
940 if (!(vcpu->cr0 & CR0_TS_MASK))
941 vcpu->svm->vmcb->save.cr0 &= ~CR0_TS_MASK;
942 vcpu->fpu_active = 1;
943
944 return 1;
945}
946
46fe4ddd
JR		 947static int shutdown_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
948{
949 /*
950 * VMCB is undefined after a SHUTDOWN intercept
951 * so reinitialize it.
952 */
953 memset(vcpu->svm->vmcb, 0, PAGE_SIZE);
954 init_vmcb(vcpu->svm->vmcb);
955
956 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
957 return 0;
958}
959
6aa8b732
AK		 960static int io_get_override(struct kvm_vcpu *vcpu,
961 struct vmcb_seg **seg,
962 int *addr_override)
963{
964 u8 inst[MAX_INST_SIZE];
965 unsigned ins_length;
966 gva_t rip;
967 int i;
968
969 rip = vcpu->svm->vmcb->save.rip;
970 ins_length = vcpu->svm->next_rip - rip;
971 rip += vcpu->svm->vmcb->save.cs.base;
972
973 if (ins_length > MAX_INST_SIZE)
974 printk(KERN_DEBUG
975 "%s: inst length err, cs base 0x%llx rip 0x%llx "
976 "next rip 0x%llx ins_length %u\n",
977 __FUNCTION__,
978 vcpu->svm->vmcb->save.cs.base,
979 vcpu->svm->vmcb->save.rip,
980 vcpu->svm->vmcb->control.exit_info_2,
981 ins_length);
982
983 if (kvm_read_guest(vcpu, rip, ins_length, inst) != ins_length)
984 /* #PF */
985 return 0;
986
987 *addr_override = 0;
8b6d44c7 988 *seg = NULL;
6aa8b732
AK		 989 for (i = 0; i < ins_length; i++)
990 switch (inst[i]) {
991 case 0xf0:
992 case 0xf2:
993 case 0xf3:
994 case 0x66:
995 continue;
996 case 0x67:
997 *addr_override = 1;
998 continue;
999 case 0x2e:
1000 *seg = &vcpu->svm->vmcb->save.cs;
1001 continue;
1002 case 0x36:
1003 *seg = &vcpu->svm->vmcb->save.ss;
1004 continue;
1005 case 0x3e:
1006 *seg = &vcpu->svm->vmcb->save.ds;
1007 continue;
1008 case 0x26:
1009 *seg = &vcpu->svm->vmcb->save.es;
1010 continue;
1011 case 0x64:
1012 *seg = &vcpu->svm->vmcb->save.fs;
1013 continue;
1014 case 0x65:
1015 *seg = &vcpu->svm->vmcb->save.gs;
1016 continue;
1017 default:
1018 return 1;
1019 }
1020 printk(KERN_DEBUG "%s: unexpected\n", __FUNCTION__);
1021 return 0;
1022}
1023
039576c0 1024static unsigned long io_adress(struct kvm_vcpu *vcpu, int ins, gva_t *address)
6aa8b732
AK		 1025{
1026 unsigned long addr_mask;
1027 unsigned long *reg;
1028 struct vmcb_seg *seg;
1029 int addr_override;
1030 struct vmcb_save_area *save_area = &vcpu->svm->vmcb->save;
1031 u16 cs_attrib = save_area->cs.attrib;
1032 unsigned addr_size = get_addr_size(vcpu);
1033
1034 if (!io_get_override(vcpu, &seg, &addr_override))
1035 return 0;
1036
1037 if (addr_override)
1038 addr_size = (addr_size == 2) ? 4: (addr_size >> 1);
1039
1040 if (ins) {
1041 reg = &vcpu->regs[VCPU_REGS_RDI];
1042 seg = &vcpu->svm->vmcb->save.es;
1043 } else {
1044 reg = &vcpu->regs[VCPU_REGS_RSI];
1045 seg = (seg) ? seg : &vcpu->svm->vmcb->save.ds;
1046 }
1047
1048 addr_mask = ~0ULL >> (64 - (addr_size * 8));
1049
1050 if ((cs_attrib & SVM_SELECTOR_L_MASK) &&
1051 !(vcpu->svm->vmcb->save.rflags & X86_EFLAGS_VM)) {
1052 *address = (*reg & addr_mask);
1053 return addr_mask;
1054 }
1055
1056 if (!(seg->attrib & SVM_SELECTOR_P_SHIFT)) {
1057 svm_inject_gp(vcpu, 0);
1058 return 0;
1059 }
1060
1061 *address = (*reg & addr_mask) + seg->base;
1062 return addr_mask;
1063}
1064
1065static int io_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1066{
1067 u32 io_info = vcpu->svm->vmcb->control.exit_info_1; //address size bug?
039576c0
AK		 1068 int size, down, in, string, rep;
1069 unsigned port;
1070 unsigned long count;
1071 gva_t address = 0;
6aa8b732 1072
1165f5fe 1073 ++vcpu->stat.io_exits;
6aa8b732
AK		 1074
1075 vcpu->svm->next_rip = vcpu->svm->vmcb->control.exit_info_2;
1076
039576c0
AK		 1077 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1078 port = io_info >> 16;
1079 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1080 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1081 rep = (io_info & SVM_IOIO_REP_MASK) != 0;
1082 count = 1;
1083 down = (vcpu->svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0;
6aa8b732 1084
039576c0 1085 if (string) {
6aa8b732
AK		 1086 unsigned addr_mask;
1087
039576c0 1088 addr_mask = io_adress(vcpu, in, &address);
6aa8b732 1089 if (!addr_mask) {
d27d4aca
AK		 1090 printk(KERN_DEBUG "%s: get io address failed\n",
1091 __FUNCTION__);
6aa8b732
AK		 1092 return 1;
1093 }
1094
039576c0
AK		 1095 if (rep)
1096 count = vcpu->regs[VCPU_REGS_RCX] & addr_mask;
1097 }
1098 return kvm_setup_pio(vcpu, kvm_run, in, size, count, string, down,
1099 address, rep, port);
6aa8b732
AK		 1100}
1101
6aa8b732
AK		 1102static int nop_on_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1103{
1104 return 1;
1105}
1106
1107static int halt_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1108{
1109 vcpu->svm->next_rip = vcpu->svm->vmcb->save.rip + 1;
1110 skip_emulated_instruction(vcpu);
c1150d8c 1111 if (vcpu->irq_summary)
6aa8b732
AK		 1112 return 1;
1113
1114 kvm_run->exit_reason = KVM_EXIT_HLT;
1165f5fe 1115 ++vcpu->stat.halt_exits;
6aa8b732
AK		 1116 return 0;
1117}
1118
02e235bc
AK		 1119static int vmmcall_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1120{
510043da
DL		 1121 vcpu->svm->next_rip = vcpu->svm->vmcb->save.rip + 3;
1122 skip_emulated_instruction(vcpu);
270fd9b9 1123 return kvm_hypercall(vcpu, kvm_run);
02e235bc
AK		 1124}
1125
6aa8b732
AK		 1126static int invalid_op_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1127{
1128 inject_ud(vcpu);
1129 return 1;
1130}
1131
1132static int task_switch_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1133{
1134 printk(KERN_DEBUG "%s: task swiche is unsupported\n", __FUNCTION__);
1135 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1136 return 0;
1137}
1138
1139static int cpuid_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1140{
1141 vcpu->svm->next_rip = vcpu->svm->vmcb->save.rip + 2;
06465c5a
AK		 1142 kvm_emulate_cpuid(vcpu);
1143 return 1;
6aa8b732
AK		 1144}
1145
1146static int emulate_on_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1147{
8b6d44c7 1148 if (emulate_instruction(vcpu, NULL, 0, 0) != EMULATE_DONE)
6aa8b732
AK		 1149 printk(KERN_ERR "%s: failed\n", __FUNCTION__);
1150 return 1;
1151}
1152
1153static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1154{
1155 switch (ecx) {
6aa8b732
AK		 1156 case MSR_IA32_TIME_STAMP_COUNTER: {
1157 u64 tsc;
1158
1159 rdtscll(tsc);
1160 *data = vcpu->svm->vmcb->control.tsc_offset + tsc;
1161 break;
1162 }
0e859cac 1163 case MSR_K6_STAR:
6aa8b732
AK		 1164 *data = vcpu->svm->vmcb->save.star;
1165 break;
0e859cac 1166#ifdef CONFIG_X86_64
6aa8b732
AK		 1167 case MSR_LSTAR:
1168 *data = vcpu->svm->vmcb->save.lstar;
1169 break;
1170 case MSR_CSTAR:
1171 *data = vcpu->svm->vmcb->save.cstar;
1172 break;
1173 case MSR_KERNEL_GS_BASE:
1174 *data = vcpu->svm->vmcb->save.kernel_gs_base;
1175 break;
1176 case MSR_SYSCALL_MASK:
1177 *data = vcpu->svm->vmcb->save.sfmask;
1178 break;
1179#endif
1180 case MSR_IA32_SYSENTER_CS:
1181 *data = vcpu->svm->vmcb->save.sysenter_cs;
1182 break;
1183 case MSR_IA32_SYSENTER_EIP:
1184 *data = vcpu->svm->vmcb->save.sysenter_eip;
1185 break;
1186 case MSR_IA32_SYSENTER_ESP:
1187 *data = vcpu->svm->vmcb->save.sysenter_esp;
1188 break;
1189 default:
3bab1f5d 1190 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 1191 }
1192 return 0;
1193}
1194
1195static int rdmsr_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1196{
1197 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1198 u64 data;
1199
1200 if (svm_get_msr(vcpu, ecx, &data))
1201 svm_inject_gp(vcpu, 0);
1202 else {
1203 vcpu->svm->vmcb->save.rax = data & 0xffffffff;
1204 vcpu->regs[VCPU_REGS_RDX] = data >> 32;
1205 vcpu->svm->next_rip = vcpu->svm->vmcb->save.rip + 2;
1206 skip_emulated_instruction(vcpu);
1207 }
1208 return 1;
1209}
1210
1211static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1212{
1213 switch (ecx) {
6aa8b732
AK		 1214 case MSR_IA32_TIME_STAMP_COUNTER: {
1215 u64 tsc;
1216
1217 rdtscll(tsc);
1218 vcpu->svm->vmcb->control.tsc_offset = data - tsc;
1219 break;
1220 }
0e859cac 1221 case MSR_K6_STAR:
6aa8b732
AK		 1222 vcpu->svm->vmcb->save.star = data;
1223 break;
49b14f24 1224#ifdef CONFIG_X86_64
6aa8b732
AK		 1225 case MSR_LSTAR:
1226 vcpu->svm->vmcb->save.lstar = data;
1227 break;
1228 case MSR_CSTAR:
1229 vcpu->svm->vmcb->save.cstar = data;
1230 break;
1231 case MSR_KERNEL_GS_BASE:
1232 vcpu->svm->vmcb->save.kernel_gs_base = data;
1233 break;
1234 case MSR_SYSCALL_MASK:
1235 vcpu->svm->vmcb->save.sfmask = data;
1236 break;
1237#endif
1238 case MSR_IA32_SYSENTER_CS:
1239 vcpu->svm->vmcb->save.sysenter_cs = data;
1240 break;
1241 case MSR_IA32_SYSENTER_EIP:
1242 vcpu->svm->vmcb->save.sysenter_eip = data;
1243 break;
1244 case MSR_IA32_SYSENTER_ESP:
1245 vcpu->svm->vmcb->save.sysenter_esp = data;
1246 break;
1247 default:
3bab1f5d 1248 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 1249 }
1250 return 0;
1251}
1252
1253static int wrmsr_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1254{
1255 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1256 u64 data = (vcpu->svm->vmcb->save.rax & -1u)
1257 | ((u64)(vcpu->regs[VCPU_REGS_RDX] & -1u) << 32);
1258 vcpu->svm->next_rip = vcpu->svm->vmcb->save.rip + 2;
1259 if (svm_set_msr(vcpu, ecx, data))
1260 svm_inject_gp(vcpu, 0);
1261 else
1262 skip_emulated_instruction(vcpu);
1263 return 1;
1264}
1265
1266static int msr_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1267{
1268 if (vcpu->svm->vmcb->control.exit_info_1)
1269 return wrmsr_interception(vcpu, kvm_run);
1270 else
1271 return rdmsr_interception(vcpu, kvm_run);
1272}
1273
c1150d8c
DL		 1274static int interrupt_window_interception(struct kvm_vcpu *vcpu,
1275 struct kvm_run *kvm_run)
1276{
1277 /*
1278 * If the user space waits to inject interrupts, exit as soon as
1279 * possible
1280 */
1281 if (kvm_run->request_interrupt_window &&
022a9308 1282 !vcpu->irq_summary) {
1165f5fe 1283 ++vcpu->stat.irq_window_exits;
c1150d8c
DL		 1284 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1285 return 0;
1286 }
1287
1288 return 1;
1289}
1290
6aa8b732
AK		 1291static int (*svm_exit_handlers[])(struct kvm_vcpu *vcpu,
1292 struct kvm_run *kvm_run) = {
1293 [SVM_EXIT_READ_CR0] = emulate_on_interception,
1294 [SVM_EXIT_READ_CR3] = emulate_on_interception,
1295 [SVM_EXIT_READ_CR4] = emulate_on_interception,
1296 /* for now: */
1297 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
1298 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
1299 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
1300 [SVM_EXIT_READ_DR0] = emulate_on_interception,
1301 [SVM_EXIT_READ_DR1] = emulate_on_interception,
1302 [SVM_EXIT_READ_DR2] = emulate_on_interception,
1303 [SVM_EXIT_READ_DR3] = emulate_on_interception,
1304 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
1305 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
1306 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
1307 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
1308 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
1309 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
1310 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
7807fa6c 1311 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
6aa8b732
AK		 1312 [SVM_EXIT_INTR] = nop_on_interception,
1313 [SVM_EXIT_NMI] = nop_on_interception,
1314 [SVM_EXIT_SMI] = nop_on_interception,
1315 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 1316 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732
AK		 1317 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
1318 [SVM_EXIT_CPUID] = cpuid_interception,
1319 [SVM_EXIT_HLT] = halt_interception,
1320 [SVM_EXIT_INVLPG] = emulate_on_interception,
1321 [SVM_EXIT_INVLPGA] = invalid_op_interception,
1322 [SVM_EXIT_IOIO] = io_interception,
1323 [SVM_EXIT_MSR] = msr_interception,
1324 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 1325 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
6aa8b732 1326 [SVM_EXIT_VMRUN] = invalid_op_interception,
02e235bc 1327 [SVM_EXIT_VMMCALL] = vmmcall_interception,
6aa8b732
AK		 1328 [SVM_EXIT_VMLOAD] = invalid_op_interception,
1329 [SVM_EXIT_VMSAVE] = invalid_op_interception,
1330 [SVM_EXIT_STGI] = invalid_op_interception,
1331 [SVM_EXIT_CLGI] = invalid_op_interception,
1332 [SVM_EXIT_SKINIT] = invalid_op_interception,
916ce236
JR		 1333 [SVM_EXIT_MONITOR] = invalid_op_interception,
1334 [SVM_EXIT_MWAIT] = invalid_op_interception,
6aa8b732
AK		 1335};
1336
1337
1338static int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1339{
1340 u32 exit_code = vcpu->svm->vmcb->control.exit_code;
1341
6aa8b732
AK		 1342 if (is_external_interrupt(vcpu->svm->vmcb->control.exit_int_info) &&
1343 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR)
1344 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
1345 "exit_code 0x%x\n",
1346 __FUNCTION__, vcpu->svm->vmcb->control.exit_int_info,
1347 exit_code);
1348
9d8f549d 1349 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
6aa8b732
AK		 1350 || svm_exit_handlers[exit_code] == 0) {
1351 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 1352 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 1353 return 0;
1354 }
1355
1356 return svm_exit_handlers[exit_code](vcpu, kvm_run);
1357}
1358
1359static void reload_tss(struct kvm_vcpu *vcpu)
1360{
1361 int cpu = raw_smp_processor_id();
1362
1363 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1364 svm_data->tss_desc->type = 9; //available 32/64-bit TSS
1365 load_TR_desc();
1366}
1367
1368static void pre_svm_run(struct kvm_vcpu *vcpu)
1369{
1370 int cpu = raw_smp_processor_id();
1371
1372 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1373
1374 vcpu->svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
1375 if (vcpu->cpu != cpu ||
1376 vcpu->svm->asid_generation != svm_data->asid_generation)
1377 new_asid(vcpu, svm_data);
1378}
1379
1380
c1150d8c 1381static inline void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
6aa8b732
AK		 1382{
1383 struct vmcb_control_area *control;
1384
6aa8b732 1385 control = &vcpu->svm->vmcb->control;
6aa8b732
AK		 1386 control->int_vector = pop_irq(vcpu);
1387 control->int_ctl &= ~V_INTR_PRIO_MASK;
1388 control->int_ctl |= V_IRQ_MASK |
1389 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1390}
1391
1392static void kvm_reput_irq(struct kvm_vcpu *vcpu)
1393{
1394 struct vmcb_control_area *control = &vcpu->svm->vmcb->control;
1395
1396 if (control->int_ctl & V_IRQ_MASK) {
1397 control->int_ctl &= ~V_IRQ_MASK;
1398 push_irq(vcpu, control->int_vector);
1399 }
c1150d8c
DL		 1400
1401 vcpu->interrupt_window_open =
1402 !(control->int_state & SVM_INTERRUPT_SHADOW_MASK);
1403}
1404
1405static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1406 struct kvm_run *kvm_run)
1407{
1408 struct vmcb_control_area *control = &vcpu->svm->vmcb->control;
1409
1410 vcpu->interrupt_window_open =
1411 (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
1412 (vcpu->svm->vmcb->save.rflags & X86_EFLAGS_IF));
1413
1414 if (vcpu->interrupt_window_open && vcpu->irq_summary)
1415 /*
1416 * If interrupts enabled, and not blocked by sti or mov ss. Good.
1417 */
1418 kvm_do_inject_irq(vcpu);
1419
1420 /*
1421 * Interrupts blocked. Wait for unblock.
1422 */
1423 if (!vcpu->interrupt_window_open &&
1424 (vcpu->irq_summary || kvm_run->request_interrupt_window)) {
1425 control->intercept |= 1ULL << INTERCEPT_VINTR;
1426 } else
1427 control->intercept &= ~(1ULL << INTERCEPT_VINTR);
1428}
1429
1430static void post_kvm_run_save(struct kvm_vcpu *vcpu,
1431 struct kvm_run *kvm_run)
1432{
1433 kvm_run->ready_for_interrupt_injection = (vcpu->interrupt_window_open &&
1434 vcpu->irq_summary == 0);
1435 kvm_run->if_flag = (vcpu->svm->vmcb->save.rflags & X86_EFLAGS_IF) != 0;
1436 kvm_run->cr8 = vcpu->cr8;
1437 kvm_run->apic_base = vcpu->apic_base;
1438}
1439
1440/*
1441 * Check if userspace requested an interrupt window, and that the
1442 * interrupt window is open.
1443 *
1444 * No need to exit to userspace if we already have an interrupt queued.
1445 */
1446static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
1447 struct kvm_run *kvm_run)
1448{
1449 return (!vcpu->irq_summary &&
1450 kvm_run->request_interrupt_window &&
1451 vcpu->interrupt_window_open &&
1452 (vcpu->svm->vmcb->save.rflags & X86_EFLAGS_IF));
6aa8b732
AK		 1453}
1454
1455static void save_db_regs(unsigned long *db_regs)
1456{
5aff458e
AK		 1457 asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0]));
1458 asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1]));
1459 asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2]));
1460 asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3]));
6aa8b732
AK		 1461}
1462
1463static void load_db_regs(unsigned long *db_regs)
1464{
5aff458e
AK		 1465 asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0]));
1466 asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1]));
1467 asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2]));
1468 asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3]));
6aa8b732
AK		 1469}
1470
1471static int svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1472{
1473 u16 fs_selector;
1474 u16 gs_selector;
1475 u16 ldt_selector;
e2dec939 1476 int r;
6aa8b732
AK		 1477
1478again:
cccf748b
AK		 1479 if (!vcpu->mmio_read_completed)
1480 do_interrupt_requests(vcpu, kvm_run);
6aa8b732
AK		 1481
1482 clgi();
1483
1484 pre_svm_run(vcpu);
1485
1486 save_host_msrs(vcpu);
1487 fs_selector = read_fs();
1488 gs_selector = read_gs();
1489 ldt_selector = read_ldt();
1490 vcpu->svm->host_cr2 = kvm_read_cr2();
1491 vcpu->svm->host_dr6 = read_dr6();
1492 vcpu->svm->host_dr7 = read_dr7();
1493 vcpu->svm->vmcb->save.cr2 = vcpu->cr2;
1494
1495 if (vcpu->svm->vmcb->save.dr7 & 0xff) {
1496 write_dr7(0);
1497 save_db_regs(vcpu->svm->host_db_regs);
1498 load_db_regs(vcpu->svm->db_regs);
1499 }
36241b8c 1500
7807fa6c
AL		 1501 if (vcpu->fpu_active) {
1502 fx_save(vcpu->host_fx_image);
1503 fx_restore(vcpu->guest_fx_image);
1504 }
36241b8c 1505
6aa8b732 1506 asm volatile (
05b3e0c2 1507#ifdef CONFIG_X86_64
6aa8b732
AK		 1508 "push %%rbx; push %%rcx; push %%rdx;"
1509 "push %%rsi; push %%rdi; push %%rbp;"
1510 "push %%r8; push %%r9; push %%r10; push %%r11;"
1511 "push %%r12; push %%r13; push %%r14; push %%r15;"
1512#else
1513 "push %%ebx; push %%ecx; push %%edx;"
1514 "push %%esi; push %%edi; push %%ebp;"
1515#endif
1516
05b3e0c2 1517#ifdef CONFIG_X86_64
6aa8b732
AK		 1518 "mov %c[rbx](%[vcpu]), %%rbx \n\t"
1519 "mov %c[rcx](%[vcpu]), %%rcx \n\t"
1520 "mov %c[rdx](%[vcpu]), %%rdx \n\t"
1521 "mov %c[rsi](%[vcpu]), %%rsi \n\t"
1522 "mov %c[rdi](%[vcpu]), %%rdi \n\t"
1523 "mov %c[rbp](%[vcpu]), %%rbp \n\t"
1524 "mov %c[r8](%[vcpu]), %%r8 \n\t"
1525 "mov %c[r9](%[vcpu]), %%r9 \n\t"
1526 "mov %c[r10](%[vcpu]), %%r10 \n\t"
1527 "mov %c[r11](%[vcpu]), %%r11 \n\t"
1528 "mov %c[r12](%[vcpu]), %%r12 \n\t"
1529 "mov %c[r13](%[vcpu]), %%r13 \n\t"
1530 "mov %c[r14](%[vcpu]), %%r14 \n\t"
1531 "mov %c[r15](%[vcpu]), %%r15 \n\t"
1532#else
1533 "mov %c[rbx](%[vcpu]), %%ebx \n\t"
1534 "mov %c[rcx](%[vcpu]), %%ecx \n\t"
1535 "mov %c[rdx](%[vcpu]), %%edx \n\t"
1536 "mov %c[rsi](%[vcpu]), %%esi \n\t"
1537 "mov %c[rdi](%[vcpu]), %%edi \n\t"
1538 "mov %c[rbp](%[vcpu]), %%ebp \n\t"
1539#endif
1540
05b3e0c2 1541#ifdef CONFIG_X86_64
6aa8b732
AK		 1542 /* Enter guest mode */
1543 "push %%rax \n\t"
1544 "mov %c[svm](%[vcpu]), %%rax \n\t"
1545 "mov %c[vmcb](%%rax), %%rax \n\t"
1546 SVM_VMLOAD "\n\t"
1547 SVM_VMRUN "\n\t"
1548 SVM_VMSAVE "\n\t"
1549 "pop %%rax \n\t"
1550#else
1551 /* Enter guest mode */
1552 "push %%eax \n\t"
1553 "mov %c[svm](%[vcpu]), %%eax \n\t"
1554 "mov %c[vmcb](%%eax), %%eax \n\t"
1555 SVM_VMLOAD "\n\t"
1556 SVM_VMRUN "\n\t"
1557 SVM_VMSAVE "\n\t"
1558 "pop %%eax \n\t"
1559#endif
1560
1561 /* Save guest registers, load host registers */
05b3e0c2 1562#ifdef CONFIG_X86_64
6aa8b732
AK		 1563 "mov %%rbx, %c[rbx](%[vcpu]) \n\t"
1564 "mov %%rcx, %c[rcx](%[vcpu]) \n\t"
1565 "mov %%rdx, %c[rdx](%[vcpu]) \n\t"
1566 "mov %%rsi, %c[rsi](%[vcpu]) \n\t"
1567 "mov %%rdi, %c[rdi](%[vcpu]) \n\t"
1568 "mov %%rbp, %c[rbp](%[vcpu]) \n\t"
1569 "mov %%r8, %c[r8](%[vcpu]) \n\t"
1570 "mov %%r9, %c[r9](%[vcpu]) \n\t"
1571 "mov %%r10, %c[r10](%[vcpu]) \n\t"
1572 "mov %%r11, %c[r11](%[vcpu]) \n\t"
1573 "mov %%r12, %c[r12](%[vcpu]) \n\t"
1574 "mov %%r13, %c[r13](%[vcpu]) \n\t"
1575 "mov %%r14, %c[r14](%[vcpu]) \n\t"
1576 "mov %%r15, %c[r15](%[vcpu]) \n\t"
1577
1578 "pop %%r15; pop %%r14; pop %%r13; pop %%r12;"
1579 "pop %%r11; pop %%r10; pop %%r9; pop %%r8;"
1580 "pop %%rbp; pop %%rdi; pop %%rsi;"
1581 "pop %%rdx; pop %%rcx; pop %%rbx; \n\t"
1582#else
1583 "mov %%ebx, %c[rbx](%[vcpu]) \n\t"
1584 "mov %%ecx, %c[rcx](%[vcpu]) \n\t"
1585 "mov %%edx, %c[rdx](%[vcpu]) \n\t"
1586 "mov %%esi, %c[rsi](%[vcpu]) \n\t"
1587 "mov %%edi, %c[rdi](%[vcpu]) \n\t"
1588 "mov %%ebp, %c[rbp](%[vcpu]) \n\t"
1589
1590 "pop %%ebp; pop %%edi; pop %%esi;"
1591 "pop %%edx; pop %%ecx; pop %%ebx; \n\t"
1592#endif
1593 :
1594 : [vcpu]"a"(vcpu),
1595 [svm]"i"(offsetof(struct kvm_vcpu, svm)),
1596 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
1597 [rbx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBX])),
1598 [rcx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RCX])),
1599 [rdx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDX])),
1600 [rsi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RSI])),
1601 [rdi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDI])),
1602 [rbp]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBP]))
05b3e0c2 1603#ifdef CONFIG_X86_64
6aa8b732
AK		 1604 ,[r8 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R8 ])),
1605 [r9 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R9 ])),
1606 [r10]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R10])),
1607 [r11]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R11])),
1608 [r12]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R12])),
1609 [r13]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R13])),
1610 [r14]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R14])),
1611 [r15]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R15]))
1612#endif
1613 : "cc", "memory" );
1614
7807fa6c
AL		 1615 if (vcpu->fpu_active) {
1616 fx_save(vcpu->guest_fx_image);
1617 fx_restore(vcpu->host_fx_image);
1618 }
36241b8c 1619
6aa8b732
AK		 1620 if ((vcpu->svm->vmcb->save.dr7 & 0xff))
1621 load_db_regs(vcpu->svm->host_db_regs);
1622
1623 vcpu->cr2 = vcpu->svm->vmcb->save.cr2;
1624
1625 write_dr6(vcpu->svm->host_dr6);
1626 write_dr7(vcpu->svm->host_dr7);
1627 kvm_write_cr2(vcpu->svm->host_cr2);
1628
1629 load_fs(fs_selector);
1630 load_gs(gs_selector);
1631 load_ldt(ldt_selector);
1632 load_host_msrs(vcpu);
1633
1634 reload_tss(vcpu);
1635
07031e14
IM		 1636 /*
1637 * Profile KVM exit RIPs:
1638 */
1639 if (unlikely(prof_on == KVM_PROFILING))
1640 profile_hit(KVM_PROFILING,
1641 (void *)(unsigned long)vcpu->svm->vmcb->save.rip);
1642
6aa8b732
AK		 1643 stgi();
1644
1645 kvm_reput_irq(vcpu);
1646
1647 vcpu->svm->next_rip = 0;
1648
1649 if (vcpu->svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
8eb7d334
AK		 1650 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
1651 kvm_run->fail_entry.hardware_entry_failure_reason
1652 = vcpu->svm->vmcb->control.exit_code;
c1150d8c 1653 post_kvm_run_save(vcpu, kvm_run);
6aa8b732
AK		 1654 return 0;
1655 }
1656
e2dec939
AK		 1657 r = handle_exit(vcpu, kvm_run);
1658 if (r > 0) {
6aa8b732 1659 if (signal_pending(current)) {
1165f5fe 1660 ++vcpu->stat.signal_exits;
c1150d8c 1661 post_kvm_run_save(vcpu, kvm_run);
1b19f3e6 1662 kvm_run->exit_reason = KVM_EXIT_INTR;
c1150d8c
DL		 1663 return -EINTR;
1664 }
1665
1666 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
1165f5fe 1667 ++vcpu->stat.request_irq_exits;
c1150d8c 1668 post_kvm_run_save(vcpu, kvm_run);
1b19f3e6 1669 kvm_run->exit_reason = KVM_EXIT_INTR;
6aa8b732
AK		 1670 return -EINTR;
1671 }
1672 kvm_resched(vcpu);
1673 goto again;
1674 }
c1150d8c 1675 post_kvm_run_save(vcpu, kvm_run);
e2dec939 1676 return r;
6aa8b732
AK		 1677}
1678
1679static void svm_flush_tlb(struct kvm_vcpu *vcpu)
1680{
1681 force_new_asid(vcpu);
1682}
1683
1684static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
1685{
1686 vcpu->svm->vmcb->save.cr3 = root;
1687 force_new_asid(vcpu);
7807fa6c
AL		 1688
1689 if (vcpu->fpu_active) {
1690 vcpu->svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
1691 vcpu->svm->vmcb->save.cr0 |= CR0_TS_MASK;
1692 vcpu->fpu_active = 0;
1693 }
6aa8b732
AK		 1694}
1695
1696static void svm_inject_page_fault(struct kvm_vcpu *vcpu,
1697 unsigned long addr,
1698 uint32_t err_code)
1699{
1700 uint32_t exit_int_info = vcpu->svm->vmcb->control.exit_int_info;
1701
1165f5fe 1702 ++vcpu->stat.pf_guest;
6aa8b732
AK		 1703
1704 if (is_page_fault(exit_int_info)) {
1705
1706 vcpu->svm->vmcb->control.event_inj_err = 0;
1707 vcpu->svm->vmcb->control.event_inj = SVM_EVTINJ_VALID |
1708 SVM_EVTINJ_VALID_ERR |
1709 SVM_EVTINJ_TYPE_EXEPT |
1710 DF_VECTOR;
1711 return;
1712 }
1713 vcpu->cr2 = addr;
1714 vcpu->svm->vmcb->save.cr2 = addr;
1715 vcpu->svm->vmcb->control.event_inj = SVM_EVTINJ_VALID |
1716 SVM_EVTINJ_VALID_ERR |
1717 SVM_EVTINJ_TYPE_EXEPT |
1718 PF_VECTOR;
1719 vcpu->svm->vmcb->control.event_inj_err = err_code;
1720}
1721
1722
1723static int is_disabled(void)
1724{
1725 return 0;
1726}
1727
102d8325
IM		 1728static void
1729svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1730{
1731 /*
1732 * Patch in the VMMCALL instruction:
1733 */
1734 hypercall[0] = 0x0f;
1735 hypercall[1] = 0x01;
1736 hypercall[2] = 0xd9;
1737 hypercall[3] = 0xc3;
1738}
1739
6aa8b732
AK		 1740static struct kvm_arch_ops svm_arch_ops = {
1741 .cpu_has_kvm_support = has_svm,
1742 .disabled_by_bios = is_disabled,
1743 .hardware_setup = svm_hardware_setup,
1744 .hardware_unsetup = svm_hardware_unsetup,
1745 .hardware_enable = svm_hardware_enable,
1746 .hardware_disable = svm_hardware_disable,
1747
1748 .vcpu_create = svm_create_vcpu,
1749 .vcpu_free = svm_free_vcpu,
1750
1751 .vcpu_load = svm_vcpu_load,
1752 .vcpu_put = svm_vcpu_put,
774c47f1 1753 .vcpu_decache = svm_vcpu_decache,
6aa8b732
AK		 1754
1755 .set_guest_debug = svm_guest_debug,
1756 .get_msr = svm_get_msr,
1757 .set_msr = svm_set_msr,
1758 .get_segment_base = svm_get_segment_base,
1759 .get_segment = svm_get_segment,
1760 .set_segment = svm_set_segment,
6aa8b732 1761 .get_cs_db_l_bits = svm_get_cs_db_l_bits,
399badf3 1762 .decache_cr0_cr4_guest_bits = svm_decache_cr0_cr4_guest_bits,
6aa8b732 1763 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 1764 .set_cr3 = svm_set_cr3,
1765 .set_cr4 = svm_set_cr4,
1766 .set_efer = svm_set_efer,
1767 .get_idt = svm_get_idt,
1768 .set_idt = svm_set_idt,
1769 .get_gdt = svm_get_gdt,
1770 .set_gdt = svm_set_gdt,
1771 .get_dr = svm_get_dr,
1772 .set_dr = svm_set_dr,
1773 .cache_regs = svm_cache_regs,
1774 .decache_regs = svm_decache_regs,
1775 .get_rflags = svm_get_rflags,
1776 .set_rflags = svm_set_rflags,
1777
1778 .invlpg = svm_invlpg,
1779 .tlb_flush = svm_flush_tlb,
1780 .inject_page_fault = svm_inject_page_fault,
1781
1782 .inject_gp = svm_inject_gp,
1783
1784 .run = svm_vcpu_run,
1785 .skip_emulated_instruction = skip_emulated_instruction,
1786 .vcpu_setup = svm_vcpu_setup,
102d8325 1787 .patch_hypercall = svm_patch_hypercall,
6aa8b732
AK		 1788};
1789
1790static int __init svm_init(void)
1791{
873a7c42 1792 return kvm_init_arch(&svm_arch_ops, THIS_MODULE);
6aa8b732
AK		 1793}
1794
1795static void __exit svm_exit(void)
1796{
1797 kvm_exit_arch();
1798}
1799
1800module_init(svm_init)
1801module_exit(svm_exit)
kernel source for telekom puls (alcatel/mediatek)