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KVM: load_pdptrs() cleanups
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
16
e495606d
AK		 17#include "kvm_svm.h"
18#include "x86_emulate.h"
19
6aa8b732 20#include <linux/module.h>
9d8f549d 21#include <linux/kernel.h>
6aa8b732
AK		 22#include <linux/vmalloc.h>
23#include <linux/highmem.h>
07031e14 24#include <linux/profile.h>
e8edc6e0 25#include <linux/sched.h>
6aa8b732 26
e495606d 27#include <asm/desc.h>
6aa8b732
AK		 28
29MODULE_AUTHOR("Qumranet");
30MODULE_LICENSE("GPL");
31
32#define IOPM_ALLOC_ORDER 2
33#define MSRPM_ALLOC_ORDER 1
34
35#define DB_VECTOR 1
36#define UD_VECTOR 6
37#define GP_VECTOR 13
38
39#define DR7_GD_MASK (1 << 13)
40#define DR6_BD_MASK (1 << 13)
6aa8b732
AK		 41
42#define SEG_TYPE_LDT 2
43#define SEG_TYPE_BUSY_TSS16 3
44
45#define KVM_EFER_LMA (1 << 10)
46#define KVM_EFER_LME (1 << 8)
47
80b7706e
JR		 48#define SVM_FEATURE_NPT (1 << 0)
49#define SVM_FEATURE_LBRV (1 << 1)
50#define SVM_DEATURE_SVML (1 << 2)
51
6aa8b732
AK		 52unsigned long iopm_base;
53unsigned long msrpm_base;
54
55struct kvm_ldttss_desc {
56 u16 limit0;
57 u16 base0;
58 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
59 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
60 u32 base3;
61 u32 zero1;
62} __attribute__((packed));
63
64struct svm_cpu_data {
65 int cpu;
66
5008fdf5
AK		 67 u64 asid_generation;
68 u32 max_asid;
69 u32 next_asid;
6aa8b732
AK		 70 struct kvm_ldttss_desc *tss_desc;
71
72 struct page *save_area;
73};
74
75static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80b7706e 76static uint32_t svm_features;
6aa8b732
AK		 77
78struct svm_init_data {
79 int cpu;
80 int r;
81};
82
83static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
84
9d8f549d 85#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 86#define MSRS_RANGE_SIZE 2048
87#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
88
89#define MAX_INST_SIZE 15
90
80b7706e
JR		 91static inline u32 svm_has(u32 feat)
92{
93 return svm_features & feat;
94}
95
6aa8b732
AK		 96static unsigned get_addr_size(struct kvm_vcpu *vcpu)
97{
98 struct vmcb_save_area *sa = &vcpu->svm->vmcb->save;
99 u16 cs_attrib;
100
707d92fa 101 if (!(sa->cr0 & X86_CR0_PE) || (sa->rflags & X86_EFLAGS_VM))
6aa8b732
AK		 102 return 2;
103
104 cs_attrib = sa->cs.attrib;
105
106 return (cs_attrib & SVM_SELECTOR_L_MASK) ? 8 :
107 (cs_attrib & SVM_SELECTOR_DB_MASK) ? 4 : 2;
108}
109
110static inline u8 pop_irq(struct kvm_vcpu *vcpu)
111{
112 int word_index = __ffs(vcpu->irq_summary);
113 int bit_index = __ffs(vcpu->irq_pending[word_index]);
114 int irq = word_index * BITS_PER_LONG + bit_index;
115
116 clear_bit(bit_index, &vcpu->irq_pending[word_index]);
117 if (!vcpu->irq_pending[word_index])
118 clear_bit(word_index, &vcpu->irq_summary);
119 return irq;
120}
121
122static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq)
123{
124 set_bit(irq, vcpu->irq_pending);
125 set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
126}
127
128static inline void clgi(void)
129{
130 asm volatile (SVM_CLGI);
131}
132
133static inline void stgi(void)
134{
135 asm volatile (SVM_STGI);
136}
137
138static inline void invlpga(unsigned long addr, u32 asid)
139{
140 asm volatile (SVM_INVLPGA :: "a"(addr), "c"(asid));
141}
142
143static inline unsigned long kvm_read_cr2(void)
144{
145 unsigned long cr2;
146
147 asm volatile ("mov %%cr2, %0" : "=r" (cr2));
148 return cr2;
149}
150
151static inline void kvm_write_cr2(unsigned long val)
152{
153 asm volatile ("mov %0, %%cr2" :: "r" (val));
154}
155
156static inline unsigned long read_dr6(void)
157{
158 unsigned long dr6;
159
160 asm volatile ("mov %%dr6, %0" : "=r" (dr6));
161 return dr6;
162}
163
164static inline void write_dr6(unsigned long val)
165{
166 asm volatile ("mov %0, %%dr6" :: "r" (val));
167}
168
169static inline unsigned long read_dr7(void)
170{
171 unsigned long dr7;
172
173 asm volatile ("mov %%dr7, %0" : "=r" (dr7));
174 return dr7;
175}
176
177static inline void write_dr7(unsigned long val)
178{
179 asm volatile ("mov %0, %%dr7" :: "r" (val));
180}
181
6aa8b732
AK		 182static inline void force_new_asid(struct kvm_vcpu *vcpu)
183{
184 vcpu->svm->asid_generation--;
185}
186
187static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
188{
189 force_new_asid(vcpu);
190}
191
192static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
193{
194 if (!(efer & KVM_EFER_LMA))
195 efer &= ~KVM_EFER_LME;
196
197 vcpu->svm->vmcb->save.efer = efer | MSR_EFER_SVME_MASK;
198 vcpu->shadow_efer = efer;
199}
200
201static void svm_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code)
202{
203 vcpu->svm->vmcb->control.event_inj = SVM_EVTINJ_VALID |
204 SVM_EVTINJ_VALID_ERR |
205 SVM_EVTINJ_TYPE_EXEPT |
206 GP_VECTOR;
207 vcpu->svm->vmcb->control.event_inj_err = error_code;
208}
209
210static void inject_ud(struct kvm_vcpu *vcpu)
211{
212 vcpu->svm->vmcb->control.event_inj = SVM_EVTINJ_VALID |
213 SVM_EVTINJ_TYPE_EXEPT |
214 UD_VECTOR;
215}
216
6aa8b732
AK		 217static int is_page_fault(uint32_t info)
218{
219 info &= SVM_EVTINJ_VEC_MASK | SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
220 return info == (PF_VECTOR | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_EXEPT);
221}
222
223static int is_external_interrupt(u32 info)
224{
225 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
226 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
227}
228
229static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
230{
231 if (!vcpu->svm->next_rip) {
232 printk(KERN_DEBUG "%s: NOP\n", __FUNCTION__);
233 return;
234 }
235 if (vcpu->svm->next_rip - vcpu->svm->vmcb->save.rip > 15) {
236 printk(KERN_ERR "%s: ip 0x%llx next 0x%llx\n",
237 __FUNCTION__,
238 vcpu->svm->vmcb->save.rip,
239 vcpu->svm->next_rip);
240 }
241
242 vcpu->rip = vcpu->svm->vmcb->save.rip = vcpu->svm->next_rip;
243 vcpu->svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
c1150d8c
DL		 244
245 vcpu->interrupt_window_open = 1;
6aa8b732
AK		 246}
247
248static int has_svm(void)
249{
250 uint32_t eax, ebx, ecx, edx;
251
1e885461 252 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
6aa8b732
AK		 253 printk(KERN_INFO "has_svm: not amd\n");
254 return 0;
255 }
256
257 cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
258 if (eax < SVM_CPUID_FUNC) {
259 printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n");
260 return 0;
261 }
262
263 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
264 if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) {
265 printk(KERN_DEBUG "has_svm: svm not available\n");
266 return 0;
267 }
268 return 1;
269}
270
271static void svm_hardware_disable(void *garbage)
272{
273 struct svm_cpu_data *svm_data
274 = per_cpu(svm_data, raw_smp_processor_id());
275
276 if (svm_data) {
277 uint64_t efer;
278
279 wrmsrl(MSR_VM_HSAVE_PA, 0);
280 rdmsrl(MSR_EFER, efer);
281 wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK);
8b6d44c7 282 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
6aa8b732
AK		 283 __free_page(svm_data->save_area);
284 kfree(svm_data);
285 }
286}
287
288static void svm_hardware_enable(void *garbage)
289{
290
291 struct svm_cpu_data *svm_data;
292 uint64_t efer;
05b3e0c2 293#ifdef CONFIG_X86_64
6aa8b732
AK		 294 struct desc_ptr gdt_descr;
295#else
296 struct Xgt_desc_struct gdt_descr;
297#endif
298 struct desc_struct *gdt;
299 int me = raw_smp_processor_id();
300
301 if (!has_svm()) {
302 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
303 return;
304 }
305 svm_data = per_cpu(svm_data, me);
306
307 if (!svm_data) {
308 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
309 me);
310 return;
311 }
312
313 svm_data->asid_generation = 1;
314 svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
315 svm_data->next_asid = svm_data->max_asid + 1;
80b7706e 316 svm_features = cpuid_edx(SVM_CPUID_FUNC);
6aa8b732
AK		 317
318 asm volatile ( "sgdt %0" : "=m"(gdt_descr) );
319 gdt = (struct desc_struct *)gdt_descr.address;
320 svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
321
322 rdmsrl(MSR_EFER, efer);
323 wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK);
324
325 wrmsrl(MSR_VM_HSAVE_PA,
326 page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
327}
328
329static int svm_cpu_init(int cpu)
330{
331 struct svm_cpu_data *svm_data;
332 int r;
333
334 svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
335 if (!svm_data)
336 return -ENOMEM;
337 svm_data->cpu = cpu;
338 svm_data->save_area = alloc_page(GFP_KERNEL);
339 r = -ENOMEM;
340 if (!svm_data->save_area)
341 goto err_1;
342
343 per_cpu(svm_data, cpu) = svm_data;
344
345 return 0;
346
347err_1:
348 kfree(svm_data);
349 return r;
350
351}
352
353static int set_msr_interception(u32 *msrpm, unsigned msr,
354 int read, int write)
355{
356 int i;
357
358 for (i = 0; i < NUM_MSR_MAPS; i++) {
359 if (msr >= msrpm_ranges[i] &&
360 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
361 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
362 msrpm_ranges[i]) * 2;
363
364 u32 *base = msrpm + (msr_offset / 32);
365 u32 msr_shift = msr_offset % 32;
366 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
367 *base = (*base & ~(0x3 << msr_shift)) |
368 (mask << msr_shift);
369 return 1;
370 }
371 }
372 printk(KERN_DEBUG "%s: not found 0x%x\n", __FUNCTION__, msr);
373 return 0;
374}
375
376static __init int svm_hardware_setup(void)
377{
378 int cpu;
379 struct page *iopm_pages;
380 struct page *msrpm_pages;
c8681339 381 void *iopm_va, *msrpm_va;
6aa8b732
AK		 382 int r;
383
873a7c42 384 kvm_emulator_want_group7_invlpg();
6aa8b732
AK		 385
386 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
387
388 if (!iopm_pages)
389 return -ENOMEM;
c8681339
AL		 390
391 iopm_va = page_address(iopm_pages);
392 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
393 clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */
6aa8b732
AK		 394 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
395
396
397 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
398
399 r = -ENOMEM;
400 if (!msrpm_pages)
401 goto err_1;
402
403 msrpm_va = page_address(msrpm_pages);
404 memset(msrpm_va, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
405 msrpm_base = page_to_pfn(msrpm_pages) << PAGE_SHIFT;
406
05b3e0c2 407#ifdef CONFIG_X86_64
6aa8b732
AK		 408 set_msr_interception(msrpm_va, MSR_GS_BASE, 1, 1);
409 set_msr_interception(msrpm_va, MSR_FS_BASE, 1, 1);
410 set_msr_interception(msrpm_va, MSR_KERNEL_GS_BASE, 1, 1);
6aa8b732
AK		 411 set_msr_interception(msrpm_va, MSR_LSTAR, 1, 1);
412 set_msr_interception(msrpm_va, MSR_CSTAR, 1, 1);
413 set_msr_interception(msrpm_va, MSR_SYSCALL_MASK, 1, 1);
414#endif
0e859cac 415 set_msr_interception(msrpm_va, MSR_K6_STAR, 1, 1);
6aa8b732
AK		 416 set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_CS, 1, 1);
417 set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_ESP, 1, 1);
418 set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_EIP, 1, 1);
419
420 for_each_online_cpu(cpu) {
421 r = svm_cpu_init(cpu);
422 if (r)
423 goto err_2;
424 }
425 return 0;
426
427err_2:
428 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
429 msrpm_base = 0;
430err_1:
431 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
432 iopm_base = 0;
433 return r;
434}
435
436static __exit void svm_hardware_unsetup(void)
437{
438 __free_pages(pfn_to_page(msrpm_base >> PAGE_SHIFT), MSRPM_ALLOC_ORDER);
439 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
440 iopm_base = msrpm_base = 0;
441}
442
443static void init_seg(struct vmcb_seg *seg)
444{
445 seg->selector = 0;
446 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
447 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
448 seg->limit = 0xffff;
449 seg->base = 0;
450}
451
452static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
453{
454 seg->selector = 0;
455 seg->attrib = SVM_SELECTOR_P_MASK | type;
456 seg->limit = 0xffff;
457 seg->base = 0;
458}
459
460static int svm_vcpu_setup(struct kvm_vcpu *vcpu)
461{
462 return 0;
463}
464
465static void init_vmcb(struct vmcb *vmcb)
466{
467 struct vmcb_control_area *control = &vmcb->control;
468 struct vmcb_save_area *save = &vmcb->save;
6aa8b732
AK		 469
470 control->intercept_cr_read = INTERCEPT_CR0_MASK |
471 INTERCEPT_CR3_MASK |
472 INTERCEPT_CR4_MASK;
473
474 control->intercept_cr_write = INTERCEPT_CR0_MASK |
475 INTERCEPT_CR3_MASK |
476 INTERCEPT_CR4_MASK;
477
478 control->intercept_dr_read = INTERCEPT_DR0_MASK |
479 INTERCEPT_DR1_MASK |
480 INTERCEPT_DR2_MASK |
481 INTERCEPT_DR3_MASK;
482
483 control->intercept_dr_write = INTERCEPT_DR0_MASK |
484 INTERCEPT_DR1_MASK |
485 INTERCEPT_DR2_MASK |
486 INTERCEPT_DR3_MASK |
487 INTERCEPT_DR5_MASK |
488 INTERCEPT_DR7_MASK;
489
490 control->intercept_exceptions = 1 << PF_VECTOR;
491
492
493 control->intercept = (1ULL << INTERCEPT_INTR) |
494 (1ULL << INTERCEPT_NMI) |
0152527b 495 (1ULL << INTERCEPT_SMI) |
6aa8b732
AK		 496 /*
497 * selective cr0 intercept bug?
498 * 0: 0f 22 d8 mov %eax,%cr3
499 * 3: 0f 20 c0 mov %cr0,%eax
500 * 6: 0d 00 00 00 80 or $0x80000000,%eax
501 * b: 0f 22 c0 mov %eax,%cr0
502 * set cr3 ->interception
503 * get cr0 ->interception
504 * set cr0 -> no interception
505 */
506 /* (1ULL << INTERCEPT_SELECTIVE_CR0) | */
507 (1ULL << INTERCEPT_CPUID) |
508 (1ULL << INTERCEPT_HLT) |
6aa8b732
AK		 509 (1ULL << INTERCEPT_INVLPGA) |
510 (1ULL << INTERCEPT_IOIO_PROT) |
511 (1ULL << INTERCEPT_MSR_PROT) |
512 (1ULL << INTERCEPT_TASK_SWITCH) |
46fe4ddd 513 (1ULL << INTERCEPT_SHUTDOWN) |
6aa8b732
AK		 514 (1ULL << INTERCEPT_VMRUN) |
515 (1ULL << INTERCEPT_VMMCALL) |
516 (1ULL << INTERCEPT_VMLOAD) |
517 (1ULL << INTERCEPT_VMSAVE) |
518 (1ULL << INTERCEPT_STGI) |
519 (1ULL << INTERCEPT_CLGI) |
916ce236
JR		 520 (1ULL << INTERCEPT_SKINIT) |
521 (1ULL << INTERCEPT_MONITOR) |
522 (1ULL << INTERCEPT_MWAIT);
6aa8b732
AK		 523
524 control->iopm_base_pa = iopm_base;
525 control->msrpm_base_pa = msrpm_base;
0cc5064d 526 control->tsc_offset = 0;
6aa8b732
AK		 527 control->int_ctl = V_INTR_MASKING_MASK;
528
529 init_seg(&save->es);
530 init_seg(&save->ss);
531 init_seg(&save->ds);
532 init_seg(&save->fs);
533 init_seg(&save->gs);
534
535 save->cs.selector = 0xf000;
536 /* Executable/Readable Code Segment */
537 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
538 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
539 save->cs.limit = 0xffff;
d92899a0
AK		 540 /*
541 * cs.base should really be 0xffff0000, but vmx can't handle that, so
542 * be consistent with it.
543 *
544 * Replace when we have real mode working for vmx.
545 */
546 save->cs.base = 0xf0000;
6aa8b732
AK		 547
548 save->gdtr.limit = 0xffff;
549 save->idtr.limit = 0xffff;
550
551 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
552 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
553
554 save->efer = MSR_EFER_SVME_MASK;
555
556 save->dr6 = 0xffff0ff0;
557 save->dr7 = 0x400;
558 save->rflags = 2;
559 save->rip = 0x0000fff0;
560
561 /*
562 * cr0 val on cpu init should be 0x60000010, we enable cpu
563 * cache by default. the orderly way is to enable cache in bios.
564 */
707d92fa 565 save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
66aee91a 566 save->cr4 = X86_CR4_PAE;
6aa8b732
AK		 567 /* rdx = ?? */
568}
569
570static int svm_create_vcpu(struct kvm_vcpu *vcpu)
571{
572 struct page *page;
573 int r;
574
575 r = -ENOMEM;
576 vcpu->svm = kzalloc(sizeof *vcpu->svm, GFP_KERNEL);
577 if (!vcpu->svm)
578 goto out1;
579 page = alloc_page(GFP_KERNEL);
580 if (!page)
581 goto out2;
582
583 vcpu->svm->vmcb = page_address(page);
129ee910 584 clear_page(vcpu->svm->vmcb);
6aa8b732 585 vcpu->svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
6aa8b732
AK		 586 vcpu->svm->asid_generation = 0;
587 memset(vcpu->svm->db_regs, 0, sizeof(vcpu->svm->db_regs));
588 init_vmcb(vcpu->svm->vmcb);
589
36241b8c 590 fx_init(vcpu);
7807fa6c 591 vcpu->fpu_active = 1;
94cea1bb 592 vcpu->apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
dad3795d 593 if (vcpu->vcpu_id == 0)
94cea1bb 594 vcpu->apic_base |= MSR_IA32_APICBASE_BSP;
36241b8c 595
6aa8b732
AK		 596 return 0;
597
598out2:
599 kfree(vcpu->svm);
600out1:
601 return r;
602}
603
604static void svm_free_vcpu(struct kvm_vcpu *vcpu)
605{
606 if (!vcpu->svm)
607 return;
608 if (vcpu->svm->vmcb)
609 __free_page(pfn_to_page(vcpu->svm->vmcb_pa >> PAGE_SHIFT));
610 kfree(vcpu->svm);
611}
612
bccf2150 613static void svm_vcpu_load(struct kvm_vcpu *vcpu)
6aa8b732 614{
94dfbdb3 615 int cpu, i;
0cc5064d
AK		 616
617 cpu = get_cpu();
618 if (unlikely(cpu != vcpu->cpu)) {
619 u64 tsc_this, delta;
620
621 /*
622 * Make sure that the guest sees a monotonically
623 * increasing TSC.
624 */
625 rdtscll(tsc_this);
626 delta = vcpu->host_tsc - tsc_this;
627 vcpu->svm->vmcb->control.tsc_offset += delta;
628 vcpu->cpu = cpu;
629 }
94dfbdb3
AL		 630
631 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
632 rdmsrl(host_save_user_msrs[i], vcpu->svm->host_user_msrs[i]);
6aa8b732
AK		 633}
634
635static void svm_vcpu_put(struct kvm_vcpu *vcpu)
636{
94dfbdb3
AL		 637 int i;
638
639 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
640 wrmsrl(host_save_user_msrs[i], vcpu->svm->host_user_msrs[i]);
641
0cc5064d 642 rdtscll(vcpu->host_tsc);
6aa8b732
AK		 643 put_cpu();
644}
645
774c47f1
AK		 646static void svm_vcpu_decache(struct kvm_vcpu *vcpu)
647{
648}
649
6aa8b732
AK		 650static void svm_cache_regs(struct kvm_vcpu *vcpu)
651{
652 vcpu->regs[VCPU_REGS_RAX] = vcpu->svm->vmcb->save.rax;
653 vcpu->regs[VCPU_REGS_RSP] = vcpu->svm->vmcb->save.rsp;
654 vcpu->rip = vcpu->svm->vmcb->save.rip;
655}
656
657static void svm_decache_regs(struct kvm_vcpu *vcpu)
658{
659 vcpu->svm->vmcb->save.rax = vcpu->regs[VCPU_REGS_RAX];
660 vcpu->svm->vmcb->save.rsp = vcpu->regs[VCPU_REGS_RSP];
661 vcpu->svm->vmcb->save.rip = vcpu->rip;
662}
663
664static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
665{
666 return vcpu->svm->vmcb->save.rflags;
667}
668
669static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
670{
671 vcpu->svm->vmcb->save.rflags = rflags;
672}
673
674static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
675{
676 struct vmcb_save_area *save = &vcpu->svm->vmcb->save;
677
678 switch (seg) {
679 case VCPU_SREG_CS: return &save->cs;
680 case VCPU_SREG_DS: return &save->ds;
681 case VCPU_SREG_ES: return &save->es;
682 case VCPU_SREG_FS: return &save->fs;
683 case VCPU_SREG_GS: return &save->gs;
684 case VCPU_SREG_SS: return &save->ss;
685 case VCPU_SREG_TR: return &save->tr;
686 case VCPU_SREG_LDTR: return &save->ldtr;
687 }
688 BUG();
8b6d44c7 689 return NULL;
6aa8b732
AK		 690}
691
692static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
693{
694 struct vmcb_seg *s = svm_seg(vcpu, seg);
695
696 return s->base;
697}
698
699static void svm_get_segment(struct kvm_vcpu *vcpu,
700 struct kvm_segment *var, int seg)
701{
702 struct vmcb_seg *s = svm_seg(vcpu, seg);
703
704 var->base = s->base;
705 var->limit = s->limit;
706 var->selector = s->selector;
707 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
708 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
709 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
710 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
711 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
712 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
713 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
714 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
715 var->unusable = !var->present;
716}
717
718static void svm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
719{
720 struct vmcb_seg *s = svm_seg(vcpu, VCPU_SREG_CS);
721
722 *db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
723 *l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
724}
725
726static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
727{
bce66ca4
LN		 728 dt->limit = vcpu->svm->vmcb->save.idtr.limit;
729 dt->base = vcpu->svm->vmcb->save.idtr.base;
6aa8b732
AK		 730}
731
732static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
733{
bce66ca4
LN		 734 vcpu->svm->vmcb->save.idtr.limit = dt->limit;
735 vcpu->svm->vmcb->save.idtr.base = dt->base ;
6aa8b732
AK		 736}
737
738static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
739{
740 dt->limit = vcpu->svm->vmcb->save.gdtr.limit;
741 dt->base = vcpu->svm->vmcb->save.gdtr.base;
742}
743
744static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
745{
746 vcpu->svm->vmcb->save.gdtr.limit = dt->limit;
747 vcpu->svm->vmcb->save.gdtr.base = dt->base ;
748}
749
25c4c276 750static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3
AK		 751{
752}
753
6aa8b732
AK		 754static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
755{
05b3e0c2 756#ifdef CONFIG_X86_64
6aa8b732 757 if (vcpu->shadow_efer & KVM_EFER_LME) {
707d92fa 758 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
6aa8b732
AK		 759 vcpu->shadow_efer |= KVM_EFER_LMA;
760 vcpu->svm->vmcb->save.efer |= KVM_EFER_LMA | KVM_EFER_LME;
761 }
762
707d92fa 763 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG) ) {
6aa8b732
AK		 764 vcpu->shadow_efer &= ~KVM_EFER_LMA;
765 vcpu->svm->vmcb->save.efer &= ~(KVM_EFER_LMA | KVM_EFER_LME);
766 }
767 }
768#endif
707d92fa 769 if ((vcpu->cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
7807fa6c
AL		 770 vcpu->svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
771 vcpu->fpu_active = 1;
772 }
773
6aa8b732 774 vcpu->cr0 = cr0;
707d92fa
RR		 775 cr0 |= X86_CR0_PG | X86_CR0_WP;
776 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
6da63cf9 777 vcpu->svm->vmcb->save.cr0 = cr0;
6aa8b732
AK		 778}
779
780static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
781{
782 vcpu->cr4 = cr4;
66aee91a 783 vcpu->svm->vmcb->save.cr4 = cr4 | X86_CR4_PAE;
6aa8b732
AK		 784}
785
786static void svm_set_segment(struct kvm_vcpu *vcpu,
787 struct kvm_segment *var, int seg)
788{
789 struct vmcb_seg *s = svm_seg(vcpu, seg);
790
791 s->base = var->base;
792 s->limit = var->limit;
793 s->selector = var->selector;
794 if (var->unusable)
795 s->attrib = 0;
796 else {
797 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
798 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
799 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
800 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
801 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
802 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
803 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
804 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
805 }
806 if (seg == VCPU_SREG_CS)
807 vcpu->svm->vmcb->save.cpl
808 = (vcpu->svm->vmcb->save.cs.attrib
809 >> SVM_SELECTOR_DPL_SHIFT) & 3;
810
811}
812
813/* FIXME:
814
815 vcpu->svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
816 vcpu->svm->vmcb->control.int_ctl |= (sregs->cr8 & V_TPR_MASK);
817
818*/
819
820static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
821{
822 return -EOPNOTSUPP;
823}
824
825static void load_host_msrs(struct kvm_vcpu *vcpu)
826{
94dfbdb3
AL		 827#ifdef CONFIG_X86_64
828 wrmsrl(MSR_GS_BASE, vcpu->svm->host_gs_base);
829#endif
6aa8b732
AK		 830}
831
832static void save_host_msrs(struct kvm_vcpu *vcpu)
833{
94dfbdb3
AL		 834#ifdef CONFIG_X86_64
835 rdmsrl(MSR_GS_BASE, vcpu->svm->host_gs_base);
836#endif
6aa8b732
AK		 837}
838
839static void new_asid(struct kvm_vcpu *vcpu, struct svm_cpu_data *svm_data)
840{
841 if (svm_data->next_asid > svm_data->max_asid) {
842 ++svm_data->asid_generation;
843 svm_data->next_asid = 1;
844 vcpu->svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
845 }
846
847 vcpu->cpu = svm_data->cpu;
848 vcpu->svm->asid_generation = svm_data->asid_generation;
849 vcpu->svm->vmcb->control.asid = svm_data->next_asid++;
850}
851
852static void svm_invlpg(struct kvm_vcpu *vcpu, gva_t address)
853{
854 invlpga(address, vcpu->svm->vmcb->control.asid); // is needed?
855}
856
857static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
858{
859 return vcpu->svm->db_regs[dr];
860}
861
862static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
863 int *exception)
864{
865 *exception = 0;
866
867 if (vcpu->svm->vmcb->save.dr7 & DR7_GD_MASK) {
868 vcpu->svm->vmcb->save.dr7 &= ~DR7_GD_MASK;
869 vcpu->svm->vmcb->save.dr6 |= DR6_BD_MASK;
870 *exception = DB_VECTOR;
871 return;
872 }
873
874 switch (dr) {
875 case 0 ... 3:
876 vcpu->svm->db_regs[dr] = value;
877 return;
878 case 4 ... 5:
66aee91a 879 if (vcpu->cr4 & X86_CR4_DE) {
6aa8b732
AK		 880 *exception = UD_VECTOR;
881 return;
882 }
883 case 7: {
884 if (value & ~((1ULL << 32) - 1)) {
885 *exception = GP_VECTOR;
886 return;
887 }
888 vcpu->svm->vmcb->save.dr7 = value;
889 return;
890 }
891 default:
892 printk(KERN_DEBUG "%s: unexpected dr %u\n",
893 __FUNCTION__, dr);
894 *exception = UD_VECTOR;
895 return;
896 }
897}
898
899static int pf_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
900{
901 u32 exit_int_info = vcpu->svm->vmcb->control.exit_int_info;
902 u64 fault_address;
903 u32 error_code;
904 enum emulation_result er;
e2dec939 905 int r;
6aa8b732
AK		 906
907 if (is_external_interrupt(exit_int_info))
908 push_irq(vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK);
909
910 spin_lock(&vcpu->kvm->lock);
911
912 fault_address = vcpu->svm->vmcb->control.exit_info_2;
913 error_code = vcpu->svm->vmcb->control.exit_info_1;
e2dec939
AK		 914 r = kvm_mmu_page_fault(vcpu, fault_address, error_code);
915 if (r < 0) {
916 spin_unlock(&vcpu->kvm->lock);
917 return r;
918 }
919 if (!r) {
6aa8b732
AK		 920 spin_unlock(&vcpu->kvm->lock);
921 return 1;
922 }
923 er = emulate_instruction(vcpu, kvm_run, fault_address, error_code);
924 spin_unlock(&vcpu->kvm->lock);
925
926 switch (er) {
927 case EMULATE_DONE:
928 return 1;
929 case EMULATE_DO_MMIO:
1165f5fe 930 ++vcpu->stat.mmio_exits;
6aa8b732
AK		 931 return 0;
932 case EMULATE_FAIL:
933 vcpu_printf(vcpu, "%s: emulate fail\n", __FUNCTION__);
934 break;
935 default:
936 BUG();
937 }
938
939 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
940 return 0;
941}
942
7807fa6c
AL		 943static int nm_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
944{
945 vcpu->svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
707d92fa
RR		 946 if (!(vcpu->cr0 & X86_CR0_TS))
947 vcpu->svm->vmcb->save.cr0 &= ~X86_CR0_TS;
7807fa6c
AL		 948 vcpu->fpu_active = 1;
949
950 return 1;
951}
952
46fe4ddd
JR		 953static int shutdown_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
954{
955 /*
956 * VMCB is undefined after a SHUTDOWN intercept
957 * so reinitialize it.
958 */
129ee910 959 clear_page(vcpu->svm->vmcb);
46fe4ddd
JR		 960 init_vmcb(vcpu->svm->vmcb);
961
962 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
963 return 0;
964}
965
6aa8b732
AK		 966static int io_get_override(struct kvm_vcpu *vcpu,
967 struct vmcb_seg **seg,
968 int *addr_override)
969{
970 u8 inst[MAX_INST_SIZE];
971 unsigned ins_length;
972 gva_t rip;
973 int i;
974
975 rip = vcpu->svm->vmcb->save.rip;
976 ins_length = vcpu->svm->next_rip - rip;
977 rip += vcpu->svm->vmcb->save.cs.base;
978
979 if (ins_length > MAX_INST_SIZE)
980 printk(KERN_DEBUG
981 "%s: inst length err, cs base 0x%llx rip 0x%llx "
982 "next rip 0x%llx ins_length %u\n",
983 __FUNCTION__,
984 vcpu->svm->vmcb->save.cs.base,
985 vcpu->svm->vmcb->save.rip,
986 vcpu->svm->vmcb->control.exit_info_2,
987 ins_length);
988
989 if (kvm_read_guest(vcpu, rip, ins_length, inst) != ins_length)
990 /* #PF */
991 return 0;
992
993 *addr_override = 0;
8b6d44c7 994 *seg = NULL;
6aa8b732
AK		 995 for (i = 0; i < ins_length; i++)
996 switch (inst[i]) {
997 case 0xf0:
998 case 0xf2:
999 case 0xf3:
1000 case 0x66:
1001 continue;
1002 case 0x67:
1003 *addr_override = 1;
1004 continue;
1005 case 0x2e:
1006 *seg = &vcpu->svm->vmcb->save.cs;
1007 continue;
1008 case 0x36:
1009 *seg = &vcpu->svm->vmcb->save.ss;
1010 continue;
1011 case 0x3e:
1012 *seg = &vcpu->svm->vmcb->save.ds;
1013 continue;
1014 case 0x26:
1015 *seg = &vcpu->svm->vmcb->save.es;
1016 continue;
1017 case 0x64:
1018 *seg = &vcpu->svm->vmcb->save.fs;
1019 continue;
1020 case 0x65:
1021 *seg = &vcpu->svm->vmcb->save.gs;
1022 continue;
1023 default:
1024 return 1;
1025 }
1026 printk(KERN_DEBUG "%s: unexpected\n", __FUNCTION__);
1027 return 0;
1028}
1029
039576c0 1030static unsigned long io_adress(struct kvm_vcpu *vcpu, int ins, gva_t *address)
6aa8b732
AK		 1031{
1032 unsigned long addr_mask;
1033 unsigned long *reg;
1034 struct vmcb_seg *seg;
1035 int addr_override;
1036 struct vmcb_save_area *save_area = &vcpu->svm->vmcb->save;
1037 u16 cs_attrib = save_area->cs.attrib;
1038 unsigned addr_size = get_addr_size(vcpu);
1039
1040 if (!io_get_override(vcpu, &seg, &addr_override))
1041 return 0;
1042
1043 if (addr_override)
1044 addr_size = (addr_size == 2) ? 4: (addr_size >> 1);
1045
1046 if (ins) {
1047 reg = &vcpu->regs[VCPU_REGS_RDI];
1048 seg = &vcpu->svm->vmcb->save.es;
1049 } else {
1050 reg = &vcpu->regs[VCPU_REGS_RSI];
1051 seg = (seg) ? seg : &vcpu->svm->vmcb->save.ds;
1052 }
1053
1054 addr_mask = ~0ULL >> (64 - (addr_size * 8));
1055
1056 if ((cs_attrib & SVM_SELECTOR_L_MASK) &&
1057 !(vcpu->svm->vmcb->save.rflags & X86_EFLAGS_VM)) {
1058 *address = (*reg & addr_mask);
1059 return addr_mask;
1060 }
1061
1062 if (!(seg->attrib & SVM_SELECTOR_P_SHIFT)) {
1063 svm_inject_gp(vcpu, 0);
1064 return 0;
1065 }
1066
1067 *address = (*reg & addr_mask) + seg->base;
1068 return addr_mask;
1069}
1070
1071static int io_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1072{
1073 u32 io_info = vcpu->svm->vmcb->control.exit_info_1; //address size bug?
039576c0
AK		 1074 int size, down, in, string, rep;
1075 unsigned port;
1076 unsigned long count;
1077 gva_t address = 0;
6aa8b732 1078
1165f5fe 1079 ++vcpu->stat.io_exits;
6aa8b732
AK		 1080
1081 vcpu->svm->next_rip = vcpu->svm->vmcb->control.exit_info_2;
1082
039576c0
AK		 1083 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1084 port = io_info >> 16;
1085 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1086 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1087 rep = (io_info & SVM_IOIO_REP_MASK) != 0;
1088 count = 1;
1089 down = (vcpu->svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0;
6aa8b732 1090
039576c0 1091 if (string) {
6aa8b732
AK		 1092 unsigned addr_mask;
1093
039576c0 1094 addr_mask = io_adress(vcpu, in, &address);
6aa8b732 1095 if (!addr_mask) {
d27d4aca
AK		 1096 printk(KERN_DEBUG "%s: get io address failed\n",
1097 __FUNCTION__);
6aa8b732
AK		 1098 return 1;
1099 }
1100
039576c0
AK		 1101 if (rep)
1102 count = vcpu->regs[VCPU_REGS_RCX] & addr_mask;
1103 }
1104 return kvm_setup_pio(vcpu, kvm_run, in, size, count, string, down,
1105 address, rep, port);
6aa8b732
AK		 1106}
1107
6aa8b732
AK		 1108static int nop_on_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1109{
1110 return 1;
1111}
1112
1113static int halt_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1114{
1115 vcpu->svm->next_rip = vcpu->svm->vmcb->save.rip + 1;
1116 skip_emulated_instruction(vcpu);
d3bef15f 1117 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 1118}
1119
02e235bc
AK		 1120static int vmmcall_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1121{
510043da
DL		 1122 vcpu->svm->next_rip = vcpu->svm->vmcb->save.rip + 3;
1123 skip_emulated_instruction(vcpu);
270fd9b9 1124 return kvm_hypercall(vcpu, kvm_run);
02e235bc
AK		 1125}
1126
6aa8b732
AK		 1127static int invalid_op_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1128{
1129 inject_ud(vcpu);
1130 return 1;
1131}
1132
1133static int task_switch_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1134{
1135 printk(KERN_DEBUG "%s: task swiche is unsupported\n", __FUNCTION__);
1136 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1137 return 0;
1138}
1139
1140static int cpuid_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1141{
1142 vcpu->svm->next_rip = vcpu->svm->vmcb->save.rip + 2;
06465c5a
AK		 1143 kvm_emulate_cpuid(vcpu);
1144 return 1;
6aa8b732
AK		 1145}
1146
1147static int emulate_on_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1148{
8b6d44c7 1149 if (emulate_instruction(vcpu, NULL, 0, 0) != EMULATE_DONE)
6aa8b732
AK		 1150 printk(KERN_ERR "%s: failed\n", __FUNCTION__);
1151 return 1;
1152}
1153
1154static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1155{
1156 switch (ecx) {
6aa8b732
AK		 1157 case MSR_IA32_TIME_STAMP_COUNTER: {
1158 u64 tsc;
1159
1160 rdtscll(tsc);
1161 *data = vcpu->svm->vmcb->control.tsc_offset + tsc;
1162 break;
1163 }
0e859cac 1164 case MSR_K6_STAR:
6aa8b732
AK		 1165 *data = vcpu->svm->vmcb->save.star;
1166 break;
0e859cac 1167#ifdef CONFIG_X86_64
6aa8b732
AK		 1168 case MSR_LSTAR:
1169 *data = vcpu->svm->vmcb->save.lstar;
1170 break;
1171 case MSR_CSTAR:
1172 *data = vcpu->svm->vmcb->save.cstar;
1173 break;
1174 case MSR_KERNEL_GS_BASE:
1175 *data = vcpu->svm->vmcb->save.kernel_gs_base;
1176 break;
1177 case MSR_SYSCALL_MASK:
1178 *data = vcpu->svm->vmcb->save.sfmask;
1179 break;
1180#endif
1181 case MSR_IA32_SYSENTER_CS:
1182 *data = vcpu->svm->vmcb->save.sysenter_cs;
1183 break;
1184 case MSR_IA32_SYSENTER_EIP:
1185 *data = vcpu->svm->vmcb->save.sysenter_eip;
1186 break;
1187 case MSR_IA32_SYSENTER_ESP:
1188 *data = vcpu->svm->vmcb->save.sysenter_esp;
1189 break;
1190 default:
3bab1f5d 1191 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 1192 }
1193 return 0;
1194}
1195
1196static int rdmsr_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1197{
1198 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1199 u64 data;
1200
1201 if (svm_get_msr(vcpu, ecx, &data))
1202 svm_inject_gp(vcpu, 0);
1203 else {
1204 vcpu->svm->vmcb->save.rax = data & 0xffffffff;
1205 vcpu->regs[VCPU_REGS_RDX] = data >> 32;
1206 vcpu->svm->next_rip = vcpu->svm->vmcb->save.rip + 2;
1207 skip_emulated_instruction(vcpu);
1208 }
1209 return 1;
1210}
1211
1212static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1213{
1214 switch (ecx) {
6aa8b732
AK		 1215 case MSR_IA32_TIME_STAMP_COUNTER: {
1216 u64 tsc;
1217
1218 rdtscll(tsc);
1219 vcpu->svm->vmcb->control.tsc_offset = data - tsc;
1220 break;
1221 }
0e859cac 1222 case MSR_K6_STAR:
6aa8b732
AK		 1223 vcpu->svm->vmcb->save.star = data;
1224 break;
49b14f24 1225#ifdef CONFIG_X86_64
6aa8b732
AK		 1226 case MSR_LSTAR:
1227 vcpu->svm->vmcb->save.lstar = data;
1228 break;
1229 case MSR_CSTAR:
1230 vcpu->svm->vmcb->save.cstar = data;
1231 break;
1232 case MSR_KERNEL_GS_BASE:
1233 vcpu->svm->vmcb->save.kernel_gs_base = data;
1234 break;
1235 case MSR_SYSCALL_MASK:
1236 vcpu->svm->vmcb->save.sfmask = data;
1237 break;
1238#endif
1239 case MSR_IA32_SYSENTER_CS:
1240 vcpu->svm->vmcb->save.sysenter_cs = data;
1241 break;
1242 case MSR_IA32_SYSENTER_EIP:
1243 vcpu->svm->vmcb->save.sysenter_eip = data;
1244 break;
1245 case MSR_IA32_SYSENTER_ESP:
1246 vcpu->svm->vmcb->save.sysenter_esp = data;
1247 break;
1248 default:
3bab1f5d 1249 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 1250 }
1251 return 0;
1252}
1253
1254static int wrmsr_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1255{
1256 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1257 u64 data = (vcpu->svm->vmcb->save.rax & -1u)
1258 | ((u64)(vcpu->regs[VCPU_REGS_RDX] & -1u) << 32);
1259 vcpu->svm->next_rip = vcpu->svm->vmcb->save.rip + 2;
1260 if (svm_set_msr(vcpu, ecx, data))
1261 svm_inject_gp(vcpu, 0);
1262 else
1263 skip_emulated_instruction(vcpu);
1264 return 1;
1265}
1266
1267static int msr_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1268{
1269 if (vcpu->svm->vmcb->control.exit_info_1)
1270 return wrmsr_interception(vcpu, kvm_run);
1271 else
1272 return rdmsr_interception(vcpu, kvm_run);
1273}
1274
c1150d8c
DL		 1275static int interrupt_window_interception(struct kvm_vcpu *vcpu,
1276 struct kvm_run *kvm_run)
1277{
1278 /*
1279 * If the user space waits to inject interrupts, exit as soon as
1280 * possible
1281 */
1282 if (kvm_run->request_interrupt_window &&
022a9308 1283 !vcpu->irq_summary) {
1165f5fe 1284 ++vcpu->stat.irq_window_exits;
c1150d8c
DL		 1285 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1286 return 0;
1287 }
1288
1289 return 1;
1290}
1291
6aa8b732
AK		 1292static int (*svm_exit_handlers[])(struct kvm_vcpu *vcpu,
1293 struct kvm_run *kvm_run) = {
1294 [SVM_EXIT_READ_CR0] = emulate_on_interception,
1295 [SVM_EXIT_READ_CR3] = emulate_on_interception,
1296 [SVM_EXIT_READ_CR4] = emulate_on_interception,
1297 /* for now: */
1298 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
1299 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
1300 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
1301 [SVM_EXIT_READ_DR0] = emulate_on_interception,
1302 [SVM_EXIT_READ_DR1] = emulate_on_interception,
1303 [SVM_EXIT_READ_DR2] = emulate_on_interception,
1304 [SVM_EXIT_READ_DR3] = emulate_on_interception,
1305 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
1306 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
1307 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
1308 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
1309 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
1310 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
1311 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
7807fa6c 1312 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
6aa8b732
AK		 1313 [SVM_EXIT_INTR] = nop_on_interception,
1314 [SVM_EXIT_NMI] = nop_on_interception,
1315 [SVM_EXIT_SMI] = nop_on_interception,
1316 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 1317 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732
AK		 1318 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
1319 [SVM_EXIT_CPUID] = cpuid_interception,
1320 [SVM_EXIT_HLT] = halt_interception,
1321 [SVM_EXIT_INVLPG] = emulate_on_interception,
1322 [SVM_EXIT_INVLPGA] = invalid_op_interception,
1323 [SVM_EXIT_IOIO] = io_interception,
1324 [SVM_EXIT_MSR] = msr_interception,
1325 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 1326 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
6aa8b732 1327 [SVM_EXIT_VMRUN] = invalid_op_interception,
02e235bc 1328 [SVM_EXIT_VMMCALL] = vmmcall_interception,
6aa8b732
AK		 1329 [SVM_EXIT_VMLOAD] = invalid_op_interception,
1330 [SVM_EXIT_VMSAVE] = invalid_op_interception,
1331 [SVM_EXIT_STGI] = invalid_op_interception,
1332 [SVM_EXIT_CLGI] = invalid_op_interception,
1333 [SVM_EXIT_SKINIT] = invalid_op_interception,
916ce236
JR		 1334 [SVM_EXIT_MONITOR] = invalid_op_interception,
1335 [SVM_EXIT_MWAIT] = invalid_op_interception,
6aa8b732
AK		 1336};
1337
1338
1339static int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1340{
1341 u32 exit_code = vcpu->svm->vmcb->control.exit_code;
1342
6aa8b732
AK		 1343 if (is_external_interrupt(vcpu->svm->vmcb->control.exit_int_info) &&
1344 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR)
1345 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
1346 "exit_code 0x%x\n",
1347 __FUNCTION__, vcpu->svm->vmcb->control.exit_int_info,
1348 exit_code);
1349
9d8f549d 1350 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
6aa8b732
AK		 1351 || svm_exit_handlers[exit_code] == 0) {
1352 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 1353 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 1354 return 0;
1355 }
1356
1357 return svm_exit_handlers[exit_code](vcpu, kvm_run);
1358}
1359
1360static void reload_tss(struct kvm_vcpu *vcpu)
1361{
1362 int cpu = raw_smp_processor_id();
1363
1364 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1365 svm_data->tss_desc->type = 9; //available 32/64-bit TSS
1366 load_TR_desc();
1367}
1368
1369static void pre_svm_run(struct kvm_vcpu *vcpu)
1370{
1371 int cpu = raw_smp_processor_id();
1372
1373 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1374
1375 vcpu->svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
1376 if (vcpu->cpu != cpu ||
1377 vcpu->svm->asid_generation != svm_data->asid_generation)
1378 new_asid(vcpu, svm_data);
1379}
1380
1381
c1150d8c 1382static inline void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
6aa8b732
AK		 1383{
1384 struct vmcb_control_area *control;
1385
6aa8b732 1386 control = &vcpu->svm->vmcb->control;
6aa8b732
AK		 1387 control->int_vector = pop_irq(vcpu);
1388 control->int_ctl &= ~V_INTR_PRIO_MASK;
1389 control->int_ctl |= V_IRQ_MASK |
1390 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1391}
1392
1393static void kvm_reput_irq(struct kvm_vcpu *vcpu)
1394{
1395 struct vmcb_control_area *control = &vcpu->svm->vmcb->control;
1396
1397 if (control->int_ctl & V_IRQ_MASK) {
1398 control->int_ctl &= ~V_IRQ_MASK;
1399 push_irq(vcpu, control->int_vector);
1400 }
c1150d8c
DL		 1401
1402 vcpu->interrupt_window_open =
1403 !(control->int_state & SVM_INTERRUPT_SHADOW_MASK);
1404}
1405
1406static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1407 struct kvm_run *kvm_run)
1408{
1409 struct vmcb_control_area *control = &vcpu->svm->vmcb->control;
1410
1411 vcpu->interrupt_window_open =
1412 (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
1413 (vcpu->svm->vmcb->save.rflags & X86_EFLAGS_IF));
1414
1415 if (vcpu->interrupt_window_open && vcpu->irq_summary)
1416 /*
1417 * If interrupts enabled, and not blocked by sti or mov ss. Good.
1418 */
1419 kvm_do_inject_irq(vcpu);
1420
1421 /*
1422 * Interrupts blocked. Wait for unblock.
1423 */
1424 if (!vcpu->interrupt_window_open &&
1425 (vcpu->irq_summary || kvm_run->request_interrupt_window)) {
1426 control->intercept |= 1ULL << INTERCEPT_VINTR;
1427 } else
1428 control->intercept &= ~(1ULL << INTERCEPT_VINTR);
1429}
1430
1431static void post_kvm_run_save(struct kvm_vcpu *vcpu,
1432 struct kvm_run *kvm_run)
1433{
1434 kvm_run->ready_for_interrupt_injection = (vcpu->interrupt_window_open &&
1435 vcpu->irq_summary == 0);
1436 kvm_run->if_flag = (vcpu->svm->vmcb->save.rflags & X86_EFLAGS_IF) != 0;
1437 kvm_run->cr8 = vcpu->cr8;
1438 kvm_run->apic_base = vcpu->apic_base;
1439}
1440
1441/*
1442 * Check if userspace requested an interrupt window, and that the
1443 * interrupt window is open.
1444 *
1445 * No need to exit to userspace if we already have an interrupt queued.
1446 */
1447static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
1448 struct kvm_run *kvm_run)
1449{
1450 return (!vcpu->irq_summary &&
1451 kvm_run->request_interrupt_window &&
1452 vcpu->interrupt_window_open &&
1453 (vcpu->svm->vmcb->save.rflags & X86_EFLAGS_IF));
6aa8b732
AK		 1454}
1455
1456static void save_db_regs(unsigned long *db_regs)
1457{
5aff458e
AK		 1458 asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0]));
1459 asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1]));
1460 asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2]));
1461 asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3]));
6aa8b732
AK		 1462}
1463
1464static void load_db_regs(unsigned long *db_regs)
1465{
5aff458e
AK		 1466 asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0]));
1467 asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1]));
1468 asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2]));
1469 asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3]));
6aa8b732
AK		 1470}
1471
d9e368d6
AK		 1472static void svm_flush_tlb(struct kvm_vcpu *vcpu)
1473{
1474 force_new_asid(vcpu);
1475}
1476
6aa8b732
AK		 1477static int svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1478{
1479 u16 fs_selector;
1480 u16 gs_selector;
1481 u16 ldt_selector;
e2dec939 1482 int r;
6aa8b732
AK		 1483
1484again:
17c3ba9d
AK		 1485 r = kvm_mmu_reload(vcpu);
1486 if (unlikely(r))
1487 return r;
1488
cccf748b
AK		 1489 if (!vcpu->mmio_read_completed)
1490 do_interrupt_requests(vcpu, kvm_run);
6aa8b732
AK		 1491
1492 clgi();
1493
d9e368d6
AK		 1494 vcpu->guest_mode = 1;
1495 if (vcpu->requests)
1496 if (test_and_clear_bit(KVM_TLB_FLUSH, &vcpu->requests))
1497 svm_flush_tlb(vcpu);
1498
6aa8b732
AK		 1499 pre_svm_run(vcpu);
1500
1501 save_host_msrs(vcpu);
1502 fs_selector = read_fs();
1503 gs_selector = read_gs();
1504 ldt_selector = read_ldt();
1505 vcpu->svm->host_cr2 = kvm_read_cr2();
1506 vcpu->svm->host_dr6 = read_dr6();
1507 vcpu->svm->host_dr7 = read_dr7();
1508 vcpu->svm->vmcb->save.cr2 = vcpu->cr2;
1509
1510 if (vcpu->svm->vmcb->save.dr7 & 0xff) {
1511 write_dr7(0);
1512 save_db_regs(vcpu->svm->host_db_regs);
1513 load_db_regs(vcpu->svm->db_regs);
1514 }
36241b8c 1515
7807fa6c
AL		 1516 if (vcpu->fpu_active) {
1517 fx_save(vcpu->host_fx_image);
1518 fx_restore(vcpu->guest_fx_image);
1519 }
36241b8c 1520
6aa8b732 1521 asm volatile (
05b3e0c2 1522#ifdef CONFIG_X86_64
6aa8b732
AK		 1523 "push %%rbx; push %%rcx; push %%rdx;"
1524 "push %%rsi; push %%rdi; push %%rbp;"
1525 "push %%r8; push %%r9; push %%r10; push %%r11;"
1526 "push %%r12; push %%r13; push %%r14; push %%r15;"
1527#else
1528 "push %%ebx; push %%ecx; push %%edx;"
1529 "push %%esi; push %%edi; push %%ebp;"
1530#endif
1531
05b3e0c2 1532#ifdef CONFIG_X86_64
6aa8b732
AK		 1533 "mov %c[rbx](%[vcpu]), %%rbx \n\t"
1534 "mov %c[rcx](%[vcpu]), %%rcx \n\t"
1535 "mov %c[rdx](%[vcpu]), %%rdx \n\t"
1536 "mov %c[rsi](%[vcpu]), %%rsi \n\t"
1537 "mov %c[rdi](%[vcpu]), %%rdi \n\t"
1538 "mov %c[rbp](%[vcpu]), %%rbp \n\t"
1539 "mov %c[r8](%[vcpu]), %%r8 \n\t"
1540 "mov %c[r9](%[vcpu]), %%r9 \n\t"
1541 "mov %c[r10](%[vcpu]), %%r10 \n\t"
1542 "mov %c[r11](%[vcpu]), %%r11 \n\t"
1543 "mov %c[r12](%[vcpu]), %%r12 \n\t"
1544 "mov %c[r13](%[vcpu]), %%r13 \n\t"
1545 "mov %c[r14](%[vcpu]), %%r14 \n\t"
1546 "mov %c[r15](%[vcpu]), %%r15 \n\t"
1547#else
1548 "mov %c[rbx](%[vcpu]), %%ebx \n\t"
1549 "mov %c[rcx](%[vcpu]), %%ecx \n\t"
1550 "mov %c[rdx](%[vcpu]), %%edx \n\t"
1551 "mov %c[rsi](%[vcpu]), %%esi \n\t"
1552 "mov %c[rdi](%[vcpu]), %%edi \n\t"
1553 "mov %c[rbp](%[vcpu]), %%ebp \n\t"
1554#endif
1555
05b3e0c2 1556#ifdef CONFIG_X86_64
6aa8b732
AK		 1557 /* Enter guest mode */
1558 "push %%rax \n\t"
1559 "mov %c[svm](%[vcpu]), %%rax \n\t"
1560 "mov %c[vmcb](%%rax), %%rax \n\t"
1561 SVM_VMLOAD "\n\t"
1562 SVM_VMRUN "\n\t"
1563 SVM_VMSAVE "\n\t"
1564 "pop %%rax \n\t"
1565#else
1566 /* Enter guest mode */
1567 "push %%eax \n\t"
1568 "mov %c[svm](%[vcpu]), %%eax \n\t"
1569 "mov %c[vmcb](%%eax), %%eax \n\t"
1570 SVM_VMLOAD "\n\t"
1571 SVM_VMRUN "\n\t"
1572 SVM_VMSAVE "\n\t"
1573 "pop %%eax \n\t"
1574#endif
1575
1576 /* Save guest registers, load host registers */
05b3e0c2 1577#ifdef CONFIG_X86_64
6aa8b732
AK		 1578 "mov %%rbx, %c[rbx](%[vcpu]) \n\t"
1579 "mov %%rcx, %c[rcx](%[vcpu]) \n\t"
1580 "mov %%rdx, %c[rdx](%[vcpu]) \n\t"
1581 "mov %%rsi, %c[rsi](%[vcpu]) \n\t"
1582 "mov %%rdi, %c[rdi](%[vcpu]) \n\t"
1583 "mov %%rbp, %c[rbp](%[vcpu]) \n\t"
1584 "mov %%r8, %c[r8](%[vcpu]) \n\t"
1585 "mov %%r9, %c[r9](%[vcpu]) \n\t"
1586 "mov %%r10, %c[r10](%[vcpu]) \n\t"
1587 "mov %%r11, %c[r11](%[vcpu]) \n\t"
1588 "mov %%r12, %c[r12](%[vcpu]) \n\t"
1589 "mov %%r13, %c[r13](%[vcpu]) \n\t"
1590 "mov %%r14, %c[r14](%[vcpu]) \n\t"
1591 "mov %%r15, %c[r15](%[vcpu]) \n\t"
1592
1593 "pop %%r15; pop %%r14; pop %%r13; pop %%r12;"
1594 "pop %%r11; pop %%r10; pop %%r9; pop %%r8;"
1595 "pop %%rbp; pop %%rdi; pop %%rsi;"
1596 "pop %%rdx; pop %%rcx; pop %%rbx; \n\t"
1597#else
1598 "mov %%ebx, %c[rbx](%[vcpu]) \n\t"
1599 "mov %%ecx, %c[rcx](%[vcpu]) \n\t"
1600 "mov %%edx, %c[rdx](%[vcpu]) \n\t"
1601 "mov %%esi, %c[rsi](%[vcpu]) \n\t"
1602 "mov %%edi, %c[rdi](%[vcpu]) \n\t"
1603 "mov %%ebp, %c[rbp](%[vcpu]) \n\t"
1604
1605 "pop %%ebp; pop %%edi; pop %%esi;"
1606 "pop %%edx; pop %%ecx; pop %%ebx; \n\t"
1607#endif
1608 :
1609 : [vcpu]"a"(vcpu),
1610 [svm]"i"(offsetof(struct kvm_vcpu, svm)),
1611 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
1612 [rbx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBX])),
1613 [rcx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RCX])),
1614 [rdx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDX])),
1615 [rsi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RSI])),
1616 [rdi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDI])),
1617 [rbp]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBP]))
05b3e0c2 1618#ifdef CONFIG_X86_64
6aa8b732
AK		 1619 ,[r8 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R8 ])),
1620 [r9 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R9 ])),
1621 [r10]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R10])),
1622 [r11]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R11])),
1623 [r12]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R12])),
1624 [r13]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R13])),
1625 [r14]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R14])),
1626 [r15]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R15]))
1627#endif
1628 : "cc", "memory" );
1629
d9e368d6
AK		 1630 vcpu->guest_mode = 0;
1631
7807fa6c
AL		 1632 if (vcpu->fpu_active) {
1633 fx_save(vcpu->guest_fx_image);
1634 fx_restore(vcpu->host_fx_image);
1635 }
36241b8c 1636
6aa8b732
AK		 1637 if ((vcpu->svm->vmcb->save.dr7 & 0xff))
1638 load_db_regs(vcpu->svm->host_db_regs);
1639
1640 vcpu->cr2 = vcpu->svm->vmcb->save.cr2;
1641
1642 write_dr6(vcpu->svm->host_dr6);
1643 write_dr7(vcpu->svm->host_dr7);
1644 kvm_write_cr2(vcpu->svm->host_cr2);
1645
1646 load_fs(fs_selector);
1647 load_gs(gs_selector);
1648 load_ldt(ldt_selector);
1649 load_host_msrs(vcpu);
1650
1651 reload_tss(vcpu);
1652
07031e14
IM		 1653 /*
1654 * Profile KVM exit RIPs:
1655 */
1656 if (unlikely(prof_on == KVM_PROFILING))
1657 profile_hit(KVM_PROFILING,
1658 (void *)(unsigned long)vcpu->svm->vmcb->save.rip);
1659
6aa8b732
AK		 1660 stgi();
1661
1662 kvm_reput_irq(vcpu);
1663
1664 vcpu->svm->next_rip = 0;
1665
1666 if (vcpu->svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
8eb7d334
AK		 1667 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
1668 kvm_run->fail_entry.hardware_entry_failure_reason
1669 = vcpu->svm->vmcb->control.exit_code;
c1150d8c 1670 post_kvm_run_save(vcpu, kvm_run);
6aa8b732
AK		 1671 return 0;
1672 }
1673
e2dec939
AK		 1674 r = handle_exit(vcpu, kvm_run);
1675 if (r > 0) {
6aa8b732 1676 if (signal_pending(current)) {
1165f5fe 1677 ++vcpu->stat.signal_exits;
c1150d8c 1678 post_kvm_run_save(vcpu, kvm_run);
1b19f3e6 1679 kvm_run->exit_reason = KVM_EXIT_INTR;
c1150d8c
DL		 1680 return -EINTR;
1681 }
1682
1683 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
1165f5fe 1684 ++vcpu->stat.request_irq_exits;
c1150d8c 1685 post_kvm_run_save(vcpu, kvm_run);
1b19f3e6 1686 kvm_run->exit_reason = KVM_EXIT_INTR;
6aa8b732
AK		 1687 return -EINTR;
1688 }
1689 kvm_resched(vcpu);
1690 goto again;
1691 }
c1150d8c 1692 post_kvm_run_save(vcpu, kvm_run);
e2dec939 1693 return r;
6aa8b732
AK		 1694}
1695
6aa8b732
AK		 1696static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
1697{
1698 vcpu->svm->vmcb->save.cr3 = root;
1699 force_new_asid(vcpu);
7807fa6c
AL		 1700
1701 if (vcpu->fpu_active) {
1702 vcpu->svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
707d92fa 1703 vcpu->svm->vmcb->save.cr0 |= X86_CR0_TS;
7807fa6c
AL		 1704 vcpu->fpu_active = 0;
1705 }
6aa8b732
AK		 1706}
1707
1708static void svm_inject_page_fault(struct kvm_vcpu *vcpu,
1709 unsigned long addr,
1710 uint32_t err_code)
1711{
1712 uint32_t exit_int_info = vcpu->svm->vmcb->control.exit_int_info;
1713
1165f5fe 1714 ++vcpu->stat.pf_guest;
6aa8b732
AK		 1715
1716 if (is_page_fault(exit_int_info)) {
1717
1718 vcpu->svm->vmcb->control.event_inj_err = 0;
1719 vcpu->svm->vmcb->control.event_inj = SVM_EVTINJ_VALID |
1720 SVM_EVTINJ_VALID_ERR |
1721 SVM_EVTINJ_TYPE_EXEPT |
1722 DF_VECTOR;
1723 return;
1724 }
1725 vcpu->cr2 = addr;
1726 vcpu->svm->vmcb->save.cr2 = addr;
1727 vcpu->svm->vmcb->control.event_inj = SVM_EVTINJ_VALID |
1728 SVM_EVTINJ_VALID_ERR |
1729 SVM_EVTINJ_TYPE_EXEPT |
1730 PF_VECTOR;
1731 vcpu->svm->vmcb->control.event_inj_err = err_code;
1732}
1733
1734
1735static int is_disabled(void)
1736{
6031a61c
JR		 1737 u64 vm_cr;
1738
1739 rdmsrl(MSR_VM_CR, vm_cr);
1740 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
1741 return 1;
1742
6aa8b732
AK		 1743 return 0;
1744}
1745
102d8325
IM		 1746static void
1747svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1748{
1749 /*
1750 * Patch in the VMMCALL instruction:
1751 */
1752 hypercall[0] = 0x0f;
1753 hypercall[1] = 0x01;
1754 hypercall[2] = 0xd9;
1755 hypercall[3] = 0xc3;
1756}
1757
6aa8b732
AK		 1758static struct kvm_arch_ops svm_arch_ops = {
1759 .cpu_has_kvm_support = has_svm,
1760 .disabled_by_bios = is_disabled,
1761 .hardware_setup = svm_hardware_setup,
1762 .hardware_unsetup = svm_hardware_unsetup,
1763 .hardware_enable = svm_hardware_enable,
1764 .hardware_disable = svm_hardware_disable,
1765
1766 .vcpu_create = svm_create_vcpu,
1767 .vcpu_free = svm_free_vcpu,
1768
1769 .vcpu_load = svm_vcpu_load,
1770 .vcpu_put = svm_vcpu_put,
774c47f1 1771 .vcpu_decache = svm_vcpu_decache,
6aa8b732
AK		 1772
1773 .set_guest_debug = svm_guest_debug,
1774 .get_msr = svm_get_msr,
1775 .set_msr = svm_set_msr,
1776 .get_segment_base = svm_get_segment_base,
1777 .get_segment = svm_get_segment,
1778 .set_segment = svm_set_segment,
6aa8b732 1779 .get_cs_db_l_bits = svm_get_cs_db_l_bits,
25c4c276 1780 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
6aa8b732 1781 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 1782 .set_cr3 = svm_set_cr3,
1783 .set_cr4 = svm_set_cr4,
1784 .set_efer = svm_set_efer,
1785 .get_idt = svm_get_idt,
1786 .set_idt = svm_set_idt,
1787 .get_gdt = svm_get_gdt,
1788 .set_gdt = svm_set_gdt,
1789 .get_dr = svm_get_dr,
1790 .set_dr = svm_set_dr,
1791 .cache_regs = svm_cache_regs,
1792 .decache_regs = svm_decache_regs,
1793 .get_rflags = svm_get_rflags,
1794 .set_rflags = svm_set_rflags,
1795
1796 .invlpg = svm_invlpg,
1797 .tlb_flush = svm_flush_tlb,
1798 .inject_page_fault = svm_inject_page_fault,
1799
1800 .inject_gp = svm_inject_gp,
1801
1802 .run = svm_vcpu_run,
1803 .skip_emulated_instruction = skip_emulated_instruction,
1804 .vcpu_setup = svm_vcpu_setup,
102d8325 1805 .patch_hypercall = svm_patch_hypercall,
6aa8b732
AK		 1806};
1807
1808static int __init svm_init(void)
1809{
873a7c42 1810 return kvm_init_arch(&svm_arch_ops, THIS_MODULE);
6aa8b732
AK		 1811}
1812
1813static void __exit svm_exit(void)
1814{
1815 kvm_exit_arch();
1816}
1817
1818module_init(svm_init)
1819module_exit(svm_exit)
kernel source for telekom puls (alcatel/mediatek)