Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * AMD SVM support | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
7 | * | |
8 | * Authors: | |
9 | * Yaniv Kamay <yaniv@qumranet.com> | |
10 | * Avi Kivity <avi@qumranet.com> | |
11 | * | |
12 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
13 | * the COPYING file in the top-level directory. | |
14 | * | |
15 | */ | |
34c16eec | 16 | #include "x86.h" |
e495606d AK |
17 | #include "kvm_svm.h" |
18 | #include "x86_emulate.h" | |
85f455f7 | 19 | #include "irq.h" |
e495606d | 20 | |
6aa8b732 | 21 | #include <linux/module.h> |
9d8f549d | 22 | #include <linux/kernel.h> |
6aa8b732 AK |
23 | #include <linux/vmalloc.h> |
24 | #include <linux/highmem.h> | |
e8edc6e0 | 25 | #include <linux/sched.h> |
6aa8b732 | 26 | |
e495606d | 27 | #include <asm/desc.h> |
6aa8b732 AK |
28 | |
29 | MODULE_AUTHOR("Qumranet"); | |
30 | MODULE_LICENSE("GPL"); | |
31 | ||
32 | #define IOPM_ALLOC_ORDER 2 | |
33 | #define MSRPM_ALLOC_ORDER 1 | |
34 | ||
35 | #define DB_VECTOR 1 | |
36 | #define UD_VECTOR 6 | |
37 | #define GP_VECTOR 13 | |
38 | ||
39 | #define DR7_GD_MASK (1 << 13) | |
40 | #define DR6_BD_MASK (1 << 13) | |
6aa8b732 AK |
41 | |
42 | #define SEG_TYPE_LDT 2 | |
43 | #define SEG_TYPE_BUSY_TSS16 3 | |
44 | ||
80b7706e JR |
45 | #define SVM_FEATURE_NPT (1 << 0) |
46 | #define SVM_FEATURE_LBRV (1 << 1) | |
47 | #define SVM_DEATURE_SVML (1 << 2) | |
48 | ||
04d2cc77 AK |
49 | static void kvm_reput_irq(struct vcpu_svm *svm); |
50 | ||
a2fa3e9f GH |
51 | static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) |
52 | { | |
fb3f0f51 | 53 | return container_of(vcpu, struct vcpu_svm, vcpu); |
a2fa3e9f GH |
54 | } |
55 | ||
6aa8b732 AK |
56 | unsigned long iopm_base; |
57 | unsigned long msrpm_base; | |
58 | ||
59 | struct kvm_ldttss_desc { | |
60 | u16 limit0; | |
61 | u16 base0; | |
62 | unsigned base1 : 8, type : 5, dpl : 2, p : 1; | |
63 | unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8; | |
64 | u32 base3; | |
65 | u32 zero1; | |
66 | } __attribute__((packed)); | |
67 | ||
68 | struct svm_cpu_data { | |
69 | int cpu; | |
70 | ||
5008fdf5 AK |
71 | u64 asid_generation; |
72 | u32 max_asid; | |
73 | u32 next_asid; | |
6aa8b732 AK |
74 | struct kvm_ldttss_desc *tss_desc; |
75 | ||
76 | struct page *save_area; | |
77 | }; | |
78 | ||
79 | static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data); | |
80b7706e | 80 | static uint32_t svm_features; |
6aa8b732 AK |
81 | |
82 | struct svm_init_data { | |
83 | int cpu; | |
84 | int r; | |
85 | }; | |
86 | ||
87 | static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000}; | |
88 | ||
9d8f549d | 89 | #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges) |
6aa8b732 AK |
90 | #define MSRS_RANGE_SIZE 2048 |
91 | #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2) | |
92 | ||
93 | #define MAX_INST_SIZE 15 | |
94 | ||
80b7706e JR |
95 | static inline u32 svm_has(u32 feat) |
96 | { | |
97 | return svm_features & feat; | |
98 | } | |
99 | ||
6aa8b732 AK |
100 | static inline u8 pop_irq(struct kvm_vcpu *vcpu) |
101 | { | |
102 | int word_index = __ffs(vcpu->irq_summary); | |
103 | int bit_index = __ffs(vcpu->irq_pending[word_index]); | |
104 | int irq = word_index * BITS_PER_LONG + bit_index; | |
105 | ||
106 | clear_bit(bit_index, &vcpu->irq_pending[word_index]); | |
107 | if (!vcpu->irq_pending[word_index]) | |
108 | clear_bit(word_index, &vcpu->irq_summary); | |
109 | return irq; | |
110 | } | |
111 | ||
112 | static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq) | |
113 | { | |
114 | set_bit(irq, vcpu->irq_pending); | |
115 | set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary); | |
116 | } | |
117 | ||
118 | static inline void clgi(void) | |
119 | { | |
120 | asm volatile (SVM_CLGI); | |
121 | } | |
122 | ||
123 | static inline void stgi(void) | |
124 | { | |
125 | asm volatile (SVM_STGI); | |
126 | } | |
127 | ||
128 | static inline void invlpga(unsigned long addr, u32 asid) | |
129 | { | |
130 | asm volatile (SVM_INVLPGA :: "a"(addr), "c"(asid)); | |
131 | } | |
132 | ||
133 | static inline unsigned long kvm_read_cr2(void) | |
134 | { | |
135 | unsigned long cr2; | |
136 | ||
137 | asm volatile ("mov %%cr2, %0" : "=r" (cr2)); | |
138 | return cr2; | |
139 | } | |
140 | ||
141 | static inline void kvm_write_cr2(unsigned long val) | |
142 | { | |
143 | asm volatile ("mov %0, %%cr2" :: "r" (val)); | |
144 | } | |
145 | ||
146 | static inline unsigned long read_dr6(void) | |
147 | { | |
148 | unsigned long dr6; | |
149 | ||
150 | asm volatile ("mov %%dr6, %0" : "=r" (dr6)); | |
151 | return dr6; | |
152 | } | |
153 | ||
154 | static inline void write_dr6(unsigned long val) | |
155 | { | |
156 | asm volatile ("mov %0, %%dr6" :: "r" (val)); | |
157 | } | |
158 | ||
159 | static inline unsigned long read_dr7(void) | |
160 | { | |
161 | unsigned long dr7; | |
162 | ||
163 | asm volatile ("mov %%dr7, %0" : "=r" (dr7)); | |
164 | return dr7; | |
165 | } | |
166 | ||
167 | static inline void write_dr7(unsigned long val) | |
168 | { | |
169 | asm volatile ("mov %0, %%dr7" :: "r" (val)); | |
170 | } | |
171 | ||
6aa8b732 AK |
172 | static inline void force_new_asid(struct kvm_vcpu *vcpu) |
173 | { | |
a2fa3e9f | 174 | to_svm(vcpu)->asid_generation--; |
6aa8b732 AK |
175 | } |
176 | ||
177 | static inline void flush_guest_tlb(struct kvm_vcpu *vcpu) | |
178 | { | |
179 | force_new_asid(vcpu); | |
180 | } | |
181 | ||
182 | static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer) | |
183 | { | |
2b5203ee CMAB |
184 | if (!(efer & EFER_LMA)) |
185 | efer &= ~EFER_LME; | |
6aa8b732 | 186 | |
a2fa3e9f | 187 | to_svm(vcpu)->vmcb->save.efer = efer | MSR_EFER_SVME_MASK; |
6aa8b732 AK |
188 | vcpu->shadow_efer = efer; |
189 | } | |
190 | ||
191 | static void svm_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code) | |
192 | { | |
a2fa3e9f GH |
193 | struct vcpu_svm *svm = to_svm(vcpu); |
194 | ||
195 | svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | | |
6aa8b732 AK |
196 | SVM_EVTINJ_VALID_ERR | |
197 | SVM_EVTINJ_TYPE_EXEPT | | |
198 | GP_VECTOR; | |
a2fa3e9f | 199 | svm->vmcb->control.event_inj_err = error_code; |
6aa8b732 AK |
200 | } |
201 | ||
202 | static void inject_ud(struct kvm_vcpu *vcpu) | |
203 | { | |
a2fa3e9f | 204 | to_svm(vcpu)->vmcb->control.event_inj = SVM_EVTINJ_VALID | |
6aa8b732 AK |
205 | SVM_EVTINJ_TYPE_EXEPT | |
206 | UD_VECTOR; | |
207 | } | |
208 | ||
6aa8b732 AK |
209 | static int is_page_fault(uint32_t info) |
210 | { | |
211 | info &= SVM_EVTINJ_VEC_MASK | SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
212 | return info == (PF_VECTOR | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_EXEPT); | |
213 | } | |
214 | ||
215 | static int is_external_interrupt(u32 info) | |
216 | { | |
217 | info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
218 | return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR); | |
219 | } | |
220 | ||
221 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) | |
222 | { | |
a2fa3e9f GH |
223 | struct vcpu_svm *svm = to_svm(vcpu); |
224 | ||
225 | if (!svm->next_rip) { | |
6aa8b732 AK |
226 | printk(KERN_DEBUG "%s: NOP\n", __FUNCTION__); |
227 | return; | |
228 | } | |
d77c26fc | 229 | if (svm->next_rip - svm->vmcb->save.rip > MAX_INST_SIZE) |
6aa8b732 AK |
230 | printk(KERN_ERR "%s: ip 0x%llx next 0x%llx\n", |
231 | __FUNCTION__, | |
a2fa3e9f GH |
232 | svm->vmcb->save.rip, |
233 | svm->next_rip); | |
6aa8b732 | 234 | |
a2fa3e9f GH |
235 | vcpu->rip = svm->vmcb->save.rip = svm->next_rip; |
236 | svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK; | |
c1150d8c DL |
237 | |
238 | vcpu->interrupt_window_open = 1; | |
6aa8b732 AK |
239 | } |
240 | ||
241 | static int has_svm(void) | |
242 | { | |
243 | uint32_t eax, ebx, ecx, edx; | |
244 | ||
1e885461 | 245 | if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) { |
6aa8b732 AK |
246 | printk(KERN_INFO "has_svm: not amd\n"); |
247 | return 0; | |
248 | } | |
249 | ||
250 | cpuid(0x80000000, &eax, &ebx, &ecx, &edx); | |
251 | if (eax < SVM_CPUID_FUNC) { | |
252 | printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n"); | |
253 | return 0; | |
254 | } | |
255 | ||
256 | cpuid(0x80000001, &eax, &ebx, &ecx, &edx); | |
257 | if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) { | |
258 | printk(KERN_DEBUG "has_svm: svm not available\n"); | |
259 | return 0; | |
260 | } | |
261 | return 1; | |
262 | } | |
263 | ||
264 | static void svm_hardware_disable(void *garbage) | |
265 | { | |
266 | struct svm_cpu_data *svm_data | |
267 | = per_cpu(svm_data, raw_smp_processor_id()); | |
268 | ||
269 | if (svm_data) { | |
270 | uint64_t efer; | |
271 | ||
272 | wrmsrl(MSR_VM_HSAVE_PA, 0); | |
273 | rdmsrl(MSR_EFER, efer); | |
274 | wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK); | |
8b6d44c7 | 275 | per_cpu(svm_data, raw_smp_processor_id()) = NULL; |
6aa8b732 AK |
276 | __free_page(svm_data->save_area); |
277 | kfree(svm_data); | |
278 | } | |
279 | } | |
280 | ||
281 | static void svm_hardware_enable(void *garbage) | |
282 | { | |
283 | ||
284 | struct svm_cpu_data *svm_data; | |
285 | uint64_t efer; | |
05b3e0c2 | 286 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
287 | struct desc_ptr gdt_descr; |
288 | #else | |
6b68f01b | 289 | struct desc_ptr gdt_descr; |
6aa8b732 AK |
290 | #endif |
291 | struct desc_struct *gdt; | |
292 | int me = raw_smp_processor_id(); | |
293 | ||
294 | if (!has_svm()) { | |
295 | printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me); | |
296 | return; | |
297 | } | |
298 | svm_data = per_cpu(svm_data, me); | |
299 | ||
300 | if (!svm_data) { | |
301 | printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n", | |
302 | me); | |
303 | return; | |
304 | } | |
305 | ||
306 | svm_data->asid_generation = 1; | |
307 | svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1; | |
308 | svm_data->next_asid = svm_data->max_asid + 1; | |
80b7706e | 309 | svm_features = cpuid_edx(SVM_CPUID_FUNC); |
6aa8b732 | 310 | |
d77c26fc | 311 | asm volatile ("sgdt %0" : "=m"(gdt_descr)); |
6aa8b732 AK |
312 | gdt = (struct desc_struct *)gdt_descr.address; |
313 | svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS); | |
314 | ||
315 | rdmsrl(MSR_EFER, efer); | |
316 | wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK); | |
317 | ||
318 | wrmsrl(MSR_VM_HSAVE_PA, | |
319 | page_to_pfn(svm_data->save_area) << PAGE_SHIFT); | |
320 | } | |
321 | ||
322 | static int svm_cpu_init(int cpu) | |
323 | { | |
324 | struct svm_cpu_data *svm_data; | |
325 | int r; | |
326 | ||
327 | svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL); | |
328 | if (!svm_data) | |
329 | return -ENOMEM; | |
330 | svm_data->cpu = cpu; | |
331 | svm_data->save_area = alloc_page(GFP_KERNEL); | |
332 | r = -ENOMEM; | |
333 | if (!svm_data->save_area) | |
334 | goto err_1; | |
335 | ||
336 | per_cpu(svm_data, cpu) = svm_data; | |
337 | ||
338 | return 0; | |
339 | ||
340 | err_1: | |
341 | kfree(svm_data); | |
342 | return r; | |
343 | ||
344 | } | |
345 | ||
bfc733a7 RR |
346 | static void set_msr_interception(u32 *msrpm, unsigned msr, |
347 | int read, int write) | |
6aa8b732 AK |
348 | { |
349 | int i; | |
350 | ||
351 | for (i = 0; i < NUM_MSR_MAPS; i++) { | |
352 | if (msr >= msrpm_ranges[i] && | |
353 | msr < msrpm_ranges[i] + MSRS_IN_RANGE) { | |
354 | u32 msr_offset = (i * MSRS_IN_RANGE + msr - | |
355 | msrpm_ranges[i]) * 2; | |
356 | ||
357 | u32 *base = msrpm + (msr_offset / 32); | |
358 | u32 msr_shift = msr_offset % 32; | |
359 | u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1); | |
360 | *base = (*base & ~(0x3 << msr_shift)) | | |
361 | (mask << msr_shift); | |
bfc733a7 | 362 | return; |
6aa8b732 AK |
363 | } |
364 | } | |
bfc733a7 | 365 | BUG(); |
6aa8b732 AK |
366 | } |
367 | ||
368 | static __init int svm_hardware_setup(void) | |
369 | { | |
370 | int cpu; | |
371 | struct page *iopm_pages; | |
372 | struct page *msrpm_pages; | |
c8681339 | 373 | void *iopm_va, *msrpm_va; |
6aa8b732 AK |
374 | int r; |
375 | ||
6aa8b732 AK |
376 | iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER); |
377 | ||
378 | if (!iopm_pages) | |
379 | return -ENOMEM; | |
c8681339 AL |
380 | |
381 | iopm_va = page_address(iopm_pages); | |
382 | memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER)); | |
383 | clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */ | |
6aa8b732 AK |
384 | iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT; |
385 | ||
386 | ||
387 | msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); | |
388 | ||
389 | r = -ENOMEM; | |
390 | if (!msrpm_pages) | |
391 | goto err_1; | |
392 | ||
393 | msrpm_va = page_address(msrpm_pages); | |
394 | memset(msrpm_va, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER)); | |
395 | msrpm_base = page_to_pfn(msrpm_pages) << PAGE_SHIFT; | |
396 | ||
05b3e0c2 | 397 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
398 | set_msr_interception(msrpm_va, MSR_GS_BASE, 1, 1); |
399 | set_msr_interception(msrpm_va, MSR_FS_BASE, 1, 1); | |
400 | set_msr_interception(msrpm_va, MSR_KERNEL_GS_BASE, 1, 1); | |
6aa8b732 AK |
401 | set_msr_interception(msrpm_va, MSR_LSTAR, 1, 1); |
402 | set_msr_interception(msrpm_va, MSR_CSTAR, 1, 1); | |
403 | set_msr_interception(msrpm_va, MSR_SYSCALL_MASK, 1, 1); | |
404 | #endif | |
0e859cac | 405 | set_msr_interception(msrpm_va, MSR_K6_STAR, 1, 1); |
6aa8b732 AK |
406 | set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_CS, 1, 1); |
407 | set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_ESP, 1, 1); | |
408 | set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_EIP, 1, 1); | |
409 | ||
410 | for_each_online_cpu(cpu) { | |
411 | r = svm_cpu_init(cpu); | |
412 | if (r) | |
413 | goto err_2; | |
414 | } | |
415 | return 0; | |
416 | ||
417 | err_2: | |
418 | __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER); | |
419 | msrpm_base = 0; | |
420 | err_1: | |
421 | __free_pages(iopm_pages, IOPM_ALLOC_ORDER); | |
422 | iopm_base = 0; | |
423 | return r; | |
424 | } | |
425 | ||
426 | static __exit void svm_hardware_unsetup(void) | |
427 | { | |
428 | __free_pages(pfn_to_page(msrpm_base >> PAGE_SHIFT), MSRPM_ALLOC_ORDER); | |
429 | __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER); | |
430 | iopm_base = msrpm_base = 0; | |
431 | } | |
432 | ||
433 | static void init_seg(struct vmcb_seg *seg) | |
434 | { | |
435 | seg->selector = 0; | |
436 | seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK | | |
437 | SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */ | |
438 | seg->limit = 0xffff; | |
439 | seg->base = 0; | |
440 | } | |
441 | ||
442 | static void init_sys_seg(struct vmcb_seg *seg, uint32_t type) | |
443 | { | |
444 | seg->selector = 0; | |
445 | seg->attrib = SVM_SELECTOR_P_MASK | type; | |
446 | seg->limit = 0xffff; | |
447 | seg->base = 0; | |
448 | } | |
449 | ||
6aa8b732 AK |
450 | static void init_vmcb(struct vmcb *vmcb) |
451 | { | |
452 | struct vmcb_control_area *control = &vmcb->control; | |
453 | struct vmcb_save_area *save = &vmcb->save; | |
6aa8b732 AK |
454 | |
455 | control->intercept_cr_read = INTERCEPT_CR0_MASK | | |
456 | INTERCEPT_CR3_MASK | | |
457 | INTERCEPT_CR4_MASK; | |
458 | ||
459 | control->intercept_cr_write = INTERCEPT_CR0_MASK | | |
460 | INTERCEPT_CR3_MASK | | |
461 | INTERCEPT_CR4_MASK; | |
462 | ||
463 | control->intercept_dr_read = INTERCEPT_DR0_MASK | | |
464 | INTERCEPT_DR1_MASK | | |
465 | INTERCEPT_DR2_MASK | | |
466 | INTERCEPT_DR3_MASK; | |
467 | ||
468 | control->intercept_dr_write = INTERCEPT_DR0_MASK | | |
469 | INTERCEPT_DR1_MASK | | |
470 | INTERCEPT_DR2_MASK | | |
471 | INTERCEPT_DR3_MASK | | |
472 | INTERCEPT_DR5_MASK | | |
473 | INTERCEPT_DR7_MASK; | |
474 | ||
7aa81cc0 AL |
475 | control->intercept_exceptions = (1 << PF_VECTOR) | |
476 | (1 << UD_VECTOR); | |
6aa8b732 AK |
477 | |
478 | ||
479 | control->intercept = (1ULL << INTERCEPT_INTR) | | |
480 | (1ULL << INTERCEPT_NMI) | | |
0152527b | 481 | (1ULL << INTERCEPT_SMI) | |
6aa8b732 AK |
482 | /* |
483 | * selective cr0 intercept bug? | |
484 | * 0: 0f 22 d8 mov %eax,%cr3 | |
485 | * 3: 0f 20 c0 mov %cr0,%eax | |
486 | * 6: 0d 00 00 00 80 or $0x80000000,%eax | |
487 | * b: 0f 22 c0 mov %eax,%cr0 | |
488 | * set cr3 ->interception | |
489 | * get cr0 ->interception | |
490 | * set cr0 -> no interception | |
491 | */ | |
492 | /* (1ULL << INTERCEPT_SELECTIVE_CR0) | */ | |
493 | (1ULL << INTERCEPT_CPUID) | | |
cf5a94d1 | 494 | (1ULL << INTERCEPT_INVD) | |
6aa8b732 | 495 | (1ULL << INTERCEPT_HLT) | |
6aa8b732 AK |
496 | (1ULL << INTERCEPT_INVLPGA) | |
497 | (1ULL << INTERCEPT_IOIO_PROT) | | |
498 | (1ULL << INTERCEPT_MSR_PROT) | | |
499 | (1ULL << INTERCEPT_TASK_SWITCH) | | |
46fe4ddd | 500 | (1ULL << INTERCEPT_SHUTDOWN) | |
6aa8b732 AK |
501 | (1ULL << INTERCEPT_VMRUN) | |
502 | (1ULL << INTERCEPT_VMMCALL) | | |
503 | (1ULL << INTERCEPT_VMLOAD) | | |
504 | (1ULL << INTERCEPT_VMSAVE) | | |
505 | (1ULL << INTERCEPT_STGI) | | |
506 | (1ULL << INTERCEPT_CLGI) | | |
916ce236 | 507 | (1ULL << INTERCEPT_SKINIT) | |
cf5a94d1 | 508 | (1ULL << INTERCEPT_WBINVD) | |
916ce236 JR |
509 | (1ULL << INTERCEPT_MONITOR) | |
510 | (1ULL << INTERCEPT_MWAIT); | |
6aa8b732 AK |
511 | |
512 | control->iopm_base_pa = iopm_base; | |
513 | control->msrpm_base_pa = msrpm_base; | |
0cc5064d | 514 | control->tsc_offset = 0; |
6aa8b732 AK |
515 | control->int_ctl = V_INTR_MASKING_MASK; |
516 | ||
517 | init_seg(&save->es); | |
518 | init_seg(&save->ss); | |
519 | init_seg(&save->ds); | |
520 | init_seg(&save->fs); | |
521 | init_seg(&save->gs); | |
522 | ||
523 | save->cs.selector = 0xf000; | |
524 | /* Executable/Readable Code Segment */ | |
525 | save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK | | |
526 | SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK; | |
527 | save->cs.limit = 0xffff; | |
d92899a0 AK |
528 | /* |
529 | * cs.base should really be 0xffff0000, but vmx can't handle that, so | |
530 | * be consistent with it. | |
531 | * | |
532 | * Replace when we have real mode working for vmx. | |
533 | */ | |
534 | save->cs.base = 0xf0000; | |
6aa8b732 AK |
535 | |
536 | save->gdtr.limit = 0xffff; | |
537 | save->idtr.limit = 0xffff; | |
538 | ||
539 | init_sys_seg(&save->ldtr, SEG_TYPE_LDT); | |
540 | init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16); | |
541 | ||
542 | save->efer = MSR_EFER_SVME_MASK; | |
d77c26fc | 543 | save->dr6 = 0xffff0ff0; |
6aa8b732 AK |
544 | save->dr7 = 0x400; |
545 | save->rflags = 2; | |
546 | save->rip = 0x0000fff0; | |
547 | ||
548 | /* | |
549 | * cr0 val on cpu init should be 0x60000010, we enable cpu | |
550 | * cache by default. the orderly way is to enable cache in bios. | |
551 | */ | |
707d92fa | 552 | save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP; |
66aee91a | 553 | save->cr4 = X86_CR4_PAE; |
6aa8b732 AK |
554 | /* rdx = ?? */ |
555 | } | |
556 | ||
e00c8cf2 | 557 | static int svm_vcpu_reset(struct kvm_vcpu *vcpu) |
04d2cc77 AK |
558 | { |
559 | struct vcpu_svm *svm = to_svm(vcpu); | |
560 | ||
561 | init_vmcb(svm->vmcb); | |
70433389 AK |
562 | |
563 | if (vcpu->vcpu_id != 0) { | |
564 | svm->vmcb->save.rip = 0; | |
565 | svm->vmcb->save.cs.base = svm->vcpu.sipi_vector << 12; | |
566 | svm->vmcb->save.cs.selector = svm->vcpu.sipi_vector << 8; | |
567 | } | |
e00c8cf2 AK |
568 | |
569 | return 0; | |
04d2cc77 AK |
570 | } |
571 | ||
fb3f0f51 | 572 | static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 573 | { |
a2fa3e9f | 574 | struct vcpu_svm *svm; |
6aa8b732 | 575 | struct page *page; |
fb3f0f51 | 576 | int err; |
6aa8b732 | 577 | |
c16f862d | 578 | svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
fb3f0f51 RR |
579 | if (!svm) { |
580 | err = -ENOMEM; | |
581 | goto out; | |
582 | } | |
583 | ||
584 | err = kvm_vcpu_init(&svm->vcpu, kvm, id); | |
585 | if (err) | |
586 | goto free_svm; | |
587 | ||
6aa8b732 | 588 | page = alloc_page(GFP_KERNEL); |
fb3f0f51 RR |
589 | if (!page) { |
590 | err = -ENOMEM; | |
591 | goto uninit; | |
592 | } | |
6aa8b732 | 593 | |
a2fa3e9f GH |
594 | svm->vmcb = page_address(page); |
595 | clear_page(svm->vmcb); | |
596 | svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT; | |
597 | svm->asid_generation = 0; | |
598 | memset(svm->db_regs, 0, sizeof(svm->db_regs)); | |
599 | init_vmcb(svm->vmcb); | |
600 | ||
fb3f0f51 RR |
601 | fx_init(&svm->vcpu); |
602 | svm->vcpu.fpu_active = 1; | |
603 | svm->vcpu.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE; | |
604 | if (svm->vcpu.vcpu_id == 0) | |
605 | svm->vcpu.apic_base |= MSR_IA32_APICBASE_BSP; | |
6aa8b732 | 606 | |
fb3f0f51 | 607 | return &svm->vcpu; |
36241b8c | 608 | |
fb3f0f51 RR |
609 | uninit: |
610 | kvm_vcpu_uninit(&svm->vcpu); | |
611 | free_svm: | |
a4770347 | 612 | kmem_cache_free(kvm_vcpu_cache, svm); |
fb3f0f51 RR |
613 | out: |
614 | return ERR_PTR(err); | |
6aa8b732 AK |
615 | } |
616 | ||
617 | static void svm_free_vcpu(struct kvm_vcpu *vcpu) | |
618 | { | |
a2fa3e9f GH |
619 | struct vcpu_svm *svm = to_svm(vcpu); |
620 | ||
fb3f0f51 RR |
621 | __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT)); |
622 | kvm_vcpu_uninit(vcpu); | |
a4770347 | 623 | kmem_cache_free(kvm_vcpu_cache, svm); |
6aa8b732 AK |
624 | } |
625 | ||
15ad7146 | 626 | static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 627 | { |
a2fa3e9f | 628 | struct vcpu_svm *svm = to_svm(vcpu); |
15ad7146 | 629 | int i; |
0cc5064d | 630 | |
0cc5064d AK |
631 | if (unlikely(cpu != vcpu->cpu)) { |
632 | u64 tsc_this, delta; | |
633 | ||
634 | /* | |
635 | * Make sure that the guest sees a monotonically | |
636 | * increasing TSC. | |
637 | */ | |
638 | rdtscll(tsc_this); | |
639 | delta = vcpu->host_tsc - tsc_this; | |
a2fa3e9f | 640 | svm->vmcb->control.tsc_offset += delta; |
0cc5064d | 641 | vcpu->cpu = cpu; |
a3d7f85f | 642 | kvm_migrate_apic_timer(vcpu); |
0cc5064d | 643 | } |
94dfbdb3 AL |
644 | |
645 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) | |
a2fa3e9f | 646 | rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
6aa8b732 AK |
647 | } |
648 | ||
649 | static void svm_vcpu_put(struct kvm_vcpu *vcpu) | |
650 | { | |
a2fa3e9f | 651 | struct vcpu_svm *svm = to_svm(vcpu); |
94dfbdb3 AL |
652 | int i; |
653 | ||
e1beb1d3 | 654 | ++vcpu->stat.host_state_reload; |
94dfbdb3 | 655 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 656 | wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
94dfbdb3 | 657 | |
0cc5064d | 658 | rdtscll(vcpu->host_tsc); |
6aa8b732 AK |
659 | } |
660 | ||
774c47f1 AK |
661 | static void svm_vcpu_decache(struct kvm_vcpu *vcpu) |
662 | { | |
663 | } | |
664 | ||
6aa8b732 AK |
665 | static void svm_cache_regs(struct kvm_vcpu *vcpu) |
666 | { | |
a2fa3e9f GH |
667 | struct vcpu_svm *svm = to_svm(vcpu); |
668 | ||
669 | vcpu->regs[VCPU_REGS_RAX] = svm->vmcb->save.rax; | |
670 | vcpu->regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp; | |
671 | vcpu->rip = svm->vmcb->save.rip; | |
6aa8b732 AK |
672 | } |
673 | ||
674 | static void svm_decache_regs(struct kvm_vcpu *vcpu) | |
675 | { | |
a2fa3e9f GH |
676 | struct vcpu_svm *svm = to_svm(vcpu); |
677 | svm->vmcb->save.rax = vcpu->regs[VCPU_REGS_RAX]; | |
678 | svm->vmcb->save.rsp = vcpu->regs[VCPU_REGS_RSP]; | |
679 | svm->vmcb->save.rip = vcpu->rip; | |
6aa8b732 AK |
680 | } |
681 | ||
682 | static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu) | |
683 | { | |
a2fa3e9f | 684 | return to_svm(vcpu)->vmcb->save.rflags; |
6aa8b732 AK |
685 | } |
686 | ||
687 | static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
688 | { | |
a2fa3e9f | 689 | to_svm(vcpu)->vmcb->save.rflags = rflags; |
6aa8b732 AK |
690 | } |
691 | ||
692 | static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg) | |
693 | { | |
a2fa3e9f | 694 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; |
6aa8b732 AK |
695 | |
696 | switch (seg) { | |
697 | case VCPU_SREG_CS: return &save->cs; | |
698 | case VCPU_SREG_DS: return &save->ds; | |
699 | case VCPU_SREG_ES: return &save->es; | |
700 | case VCPU_SREG_FS: return &save->fs; | |
701 | case VCPU_SREG_GS: return &save->gs; | |
702 | case VCPU_SREG_SS: return &save->ss; | |
703 | case VCPU_SREG_TR: return &save->tr; | |
704 | case VCPU_SREG_LDTR: return &save->ldtr; | |
705 | } | |
706 | BUG(); | |
8b6d44c7 | 707 | return NULL; |
6aa8b732 AK |
708 | } |
709 | ||
710 | static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
711 | { | |
712 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
713 | ||
714 | return s->base; | |
715 | } | |
716 | ||
717 | static void svm_get_segment(struct kvm_vcpu *vcpu, | |
718 | struct kvm_segment *var, int seg) | |
719 | { | |
720 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
721 | ||
722 | var->base = s->base; | |
723 | var->limit = s->limit; | |
724 | var->selector = s->selector; | |
725 | var->type = s->attrib & SVM_SELECTOR_TYPE_MASK; | |
726 | var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1; | |
727 | var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
728 | var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1; | |
729 | var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1; | |
730 | var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1; | |
731 | var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; | |
732 | var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1; | |
733 | var->unusable = !var->present; | |
734 | } | |
735 | ||
6aa8b732 AK |
736 | static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) |
737 | { | |
a2fa3e9f GH |
738 | struct vcpu_svm *svm = to_svm(vcpu); |
739 | ||
740 | dt->limit = svm->vmcb->save.idtr.limit; | |
741 | dt->base = svm->vmcb->save.idtr.base; | |
6aa8b732 AK |
742 | } |
743 | ||
744 | static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
745 | { | |
a2fa3e9f GH |
746 | struct vcpu_svm *svm = to_svm(vcpu); |
747 | ||
748 | svm->vmcb->save.idtr.limit = dt->limit; | |
749 | svm->vmcb->save.idtr.base = dt->base ; | |
6aa8b732 AK |
750 | } |
751 | ||
752 | static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
753 | { | |
a2fa3e9f GH |
754 | struct vcpu_svm *svm = to_svm(vcpu); |
755 | ||
756 | dt->limit = svm->vmcb->save.gdtr.limit; | |
757 | dt->base = svm->vmcb->save.gdtr.base; | |
6aa8b732 AK |
758 | } |
759 | ||
760 | static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
761 | { | |
a2fa3e9f GH |
762 | struct vcpu_svm *svm = to_svm(vcpu); |
763 | ||
764 | svm->vmcb->save.gdtr.limit = dt->limit; | |
765 | svm->vmcb->save.gdtr.base = dt->base ; | |
6aa8b732 AK |
766 | } |
767 | ||
25c4c276 | 768 | static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 AK |
769 | { |
770 | } | |
771 | ||
6aa8b732 AK |
772 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
773 | { | |
a2fa3e9f GH |
774 | struct vcpu_svm *svm = to_svm(vcpu); |
775 | ||
05b3e0c2 | 776 | #ifdef CONFIG_X86_64 |
2b5203ee | 777 | if (vcpu->shadow_efer & EFER_LME) { |
707d92fa | 778 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { |
2b5203ee CMAB |
779 | vcpu->shadow_efer |= EFER_LMA; |
780 | svm->vmcb->save.efer |= EFER_LMA | EFER_LME; | |
6aa8b732 AK |
781 | } |
782 | ||
d77c26fc | 783 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) { |
2b5203ee CMAB |
784 | vcpu->shadow_efer &= ~EFER_LMA; |
785 | svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME); | |
6aa8b732 AK |
786 | } |
787 | } | |
788 | #endif | |
707d92fa | 789 | if ((vcpu->cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) { |
a2fa3e9f | 790 | svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR); |
7807fa6c AL |
791 | vcpu->fpu_active = 1; |
792 | } | |
793 | ||
6aa8b732 | 794 | vcpu->cr0 = cr0; |
707d92fa RR |
795 | cr0 |= X86_CR0_PG | X86_CR0_WP; |
796 | cr0 &= ~(X86_CR0_CD | X86_CR0_NW); | |
a2fa3e9f | 797 | svm->vmcb->save.cr0 = cr0; |
6aa8b732 AK |
798 | } |
799 | ||
800 | static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
801 | { | |
802 | vcpu->cr4 = cr4; | |
a2fa3e9f | 803 | to_svm(vcpu)->vmcb->save.cr4 = cr4 | X86_CR4_PAE; |
6aa8b732 AK |
804 | } |
805 | ||
806 | static void svm_set_segment(struct kvm_vcpu *vcpu, | |
807 | struct kvm_segment *var, int seg) | |
808 | { | |
a2fa3e9f | 809 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
810 | struct vmcb_seg *s = svm_seg(vcpu, seg); |
811 | ||
812 | s->base = var->base; | |
813 | s->limit = var->limit; | |
814 | s->selector = var->selector; | |
815 | if (var->unusable) | |
816 | s->attrib = 0; | |
817 | else { | |
818 | s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK); | |
819 | s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT; | |
820 | s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT; | |
821 | s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT; | |
822 | s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT; | |
823 | s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT; | |
824 | s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT; | |
825 | s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT; | |
826 | } | |
827 | if (seg == VCPU_SREG_CS) | |
a2fa3e9f GH |
828 | svm->vmcb->save.cpl |
829 | = (svm->vmcb->save.cs.attrib | |
6aa8b732 AK |
830 | >> SVM_SELECTOR_DPL_SHIFT) & 3; |
831 | ||
832 | } | |
833 | ||
834 | /* FIXME: | |
835 | ||
a2fa3e9f GH |
836 | svm(vcpu)->vmcb->control.int_ctl &= ~V_TPR_MASK; |
837 | svm(vcpu)->vmcb->control.int_ctl |= (sregs->cr8 & V_TPR_MASK); | |
6aa8b732 AK |
838 | |
839 | */ | |
840 | ||
841 | static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg) | |
842 | { | |
843 | return -EOPNOTSUPP; | |
844 | } | |
845 | ||
2a8067f1 ED |
846 | static int svm_get_irq(struct kvm_vcpu *vcpu) |
847 | { | |
848 | struct vcpu_svm *svm = to_svm(vcpu); | |
849 | u32 exit_int_info = svm->vmcb->control.exit_int_info; | |
850 | ||
851 | if (is_external_interrupt(exit_int_info)) | |
852 | return exit_int_info & SVM_EVTINJ_VEC_MASK; | |
853 | return -1; | |
854 | } | |
855 | ||
6aa8b732 AK |
856 | static void load_host_msrs(struct kvm_vcpu *vcpu) |
857 | { | |
94dfbdb3 | 858 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 859 | wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base); |
94dfbdb3 | 860 | #endif |
6aa8b732 AK |
861 | } |
862 | ||
863 | static void save_host_msrs(struct kvm_vcpu *vcpu) | |
864 | { | |
94dfbdb3 | 865 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 866 | rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base); |
94dfbdb3 | 867 | #endif |
6aa8b732 AK |
868 | } |
869 | ||
e756fc62 | 870 | static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data) |
6aa8b732 AK |
871 | { |
872 | if (svm_data->next_asid > svm_data->max_asid) { | |
873 | ++svm_data->asid_generation; | |
874 | svm_data->next_asid = 1; | |
a2fa3e9f | 875 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID; |
6aa8b732 AK |
876 | } |
877 | ||
e756fc62 | 878 | svm->vcpu.cpu = svm_data->cpu; |
a2fa3e9f GH |
879 | svm->asid_generation = svm_data->asid_generation; |
880 | svm->vmcb->control.asid = svm_data->next_asid++; | |
6aa8b732 AK |
881 | } |
882 | ||
6aa8b732 AK |
883 | static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr) |
884 | { | |
a2fa3e9f | 885 | return to_svm(vcpu)->db_regs[dr]; |
6aa8b732 AK |
886 | } |
887 | ||
888 | static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value, | |
889 | int *exception) | |
890 | { | |
a2fa3e9f GH |
891 | struct vcpu_svm *svm = to_svm(vcpu); |
892 | ||
6aa8b732 AK |
893 | *exception = 0; |
894 | ||
a2fa3e9f GH |
895 | if (svm->vmcb->save.dr7 & DR7_GD_MASK) { |
896 | svm->vmcb->save.dr7 &= ~DR7_GD_MASK; | |
897 | svm->vmcb->save.dr6 |= DR6_BD_MASK; | |
6aa8b732 AK |
898 | *exception = DB_VECTOR; |
899 | return; | |
900 | } | |
901 | ||
902 | switch (dr) { | |
903 | case 0 ... 3: | |
a2fa3e9f | 904 | svm->db_regs[dr] = value; |
6aa8b732 AK |
905 | return; |
906 | case 4 ... 5: | |
66aee91a | 907 | if (vcpu->cr4 & X86_CR4_DE) { |
6aa8b732 AK |
908 | *exception = UD_VECTOR; |
909 | return; | |
910 | } | |
911 | case 7: { | |
912 | if (value & ~((1ULL << 32) - 1)) { | |
913 | *exception = GP_VECTOR; | |
914 | return; | |
915 | } | |
a2fa3e9f | 916 | svm->vmcb->save.dr7 = value; |
6aa8b732 AK |
917 | return; |
918 | } | |
919 | default: | |
920 | printk(KERN_DEBUG "%s: unexpected dr %u\n", | |
921 | __FUNCTION__, dr); | |
922 | *exception = UD_VECTOR; | |
923 | return; | |
924 | } | |
925 | } | |
926 | ||
e756fc62 | 927 | static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 928 | { |
a2fa3e9f | 929 | u32 exit_int_info = svm->vmcb->control.exit_int_info; |
e756fc62 | 930 | struct kvm *kvm = svm->vcpu.kvm; |
6aa8b732 AK |
931 | u64 fault_address; |
932 | u32 error_code; | |
6aa8b732 | 933 | |
85f455f7 ED |
934 | if (!irqchip_in_kernel(kvm) && |
935 | is_external_interrupt(exit_int_info)) | |
e756fc62 | 936 | push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK); |
6aa8b732 | 937 | |
a2fa3e9f GH |
938 | fault_address = svm->vmcb->control.exit_info_2; |
939 | error_code = svm->vmcb->control.exit_info_1; | |
3067714c | 940 | return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code); |
6aa8b732 AK |
941 | } |
942 | ||
7aa81cc0 AL |
943 | static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
944 | { | |
945 | int er; | |
946 | ||
3427318f | 947 | er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, 0); |
7aa81cc0 AL |
948 | if (er != EMULATE_DONE) |
949 | inject_ud(&svm->vcpu); | |
950 | ||
951 | return 1; | |
952 | } | |
953 | ||
e756fc62 | 954 | static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
7807fa6c | 955 | { |
a2fa3e9f | 956 | svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR); |
e756fc62 | 957 | if (!(svm->vcpu.cr0 & X86_CR0_TS)) |
a2fa3e9f | 958 | svm->vmcb->save.cr0 &= ~X86_CR0_TS; |
e756fc62 | 959 | svm->vcpu.fpu_active = 1; |
a2fa3e9f GH |
960 | |
961 | return 1; | |
7807fa6c AL |
962 | } |
963 | ||
e756fc62 | 964 | static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
46fe4ddd JR |
965 | { |
966 | /* | |
967 | * VMCB is undefined after a SHUTDOWN intercept | |
968 | * so reinitialize it. | |
969 | */ | |
a2fa3e9f GH |
970 | clear_page(svm->vmcb); |
971 | init_vmcb(svm->vmcb); | |
46fe4ddd JR |
972 | |
973 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
974 | return 0; | |
975 | } | |
976 | ||
e756fc62 | 977 | static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 978 | { |
d77c26fc | 979 | u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */ |
039576c0 AK |
980 | int size, down, in, string, rep; |
981 | unsigned port; | |
6aa8b732 | 982 | |
e756fc62 | 983 | ++svm->vcpu.stat.io_exits; |
6aa8b732 | 984 | |
a2fa3e9f | 985 | svm->next_rip = svm->vmcb->control.exit_info_2; |
6aa8b732 | 986 | |
e70669ab LV |
987 | string = (io_info & SVM_IOIO_STR_MASK) != 0; |
988 | ||
989 | if (string) { | |
3427318f LV |
990 | if (emulate_instruction(&svm->vcpu, |
991 | kvm_run, 0, 0, 0) == EMULATE_DO_MMIO) | |
e70669ab LV |
992 | return 0; |
993 | return 1; | |
994 | } | |
995 | ||
039576c0 AK |
996 | in = (io_info & SVM_IOIO_TYPE_MASK) != 0; |
997 | port = io_info >> 16; | |
998 | size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT; | |
039576c0 | 999 | rep = (io_info & SVM_IOIO_REP_MASK) != 0; |
a2fa3e9f | 1000 | down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0; |
6aa8b732 | 1001 | |
3090dd73 | 1002 | return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port); |
6aa8b732 AK |
1003 | } |
1004 | ||
e756fc62 | 1005 | static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 AK |
1006 | { |
1007 | return 1; | |
1008 | } | |
1009 | ||
e756fc62 | 1010 | static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1011 | { |
a2fa3e9f | 1012 | svm->next_rip = svm->vmcb->save.rip + 1; |
e756fc62 RR |
1013 | skip_emulated_instruction(&svm->vcpu); |
1014 | return kvm_emulate_halt(&svm->vcpu); | |
6aa8b732 AK |
1015 | } |
1016 | ||
e756fc62 | 1017 | static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
02e235bc | 1018 | { |
a2fa3e9f | 1019 | svm->next_rip = svm->vmcb->save.rip + 3; |
e756fc62 | 1020 | skip_emulated_instruction(&svm->vcpu); |
7aa81cc0 AL |
1021 | kvm_emulate_hypercall(&svm->vcpu); |
1022 | return 1; | |
02e235bc AK |
1023 | } |
1024 | ||
e756fc62 RR |
1025 | static int invalid_op_interception(struct vcpu_svm *svm, |
1026 | struct kvm_run *kvm_run) | |
6aa8b732 | 1027 | { |
e756fc62 | 1028 | inject_ud(&svm->vcpu); |
6aa8b732 AK |
1029 | return 1; |
1030 | } | |
1031 | ||
e756fc62 RR |
1032 | static int task_switch_interception(struct vcpu_svm *svm, |
1033 | struct kvm_run *kvm_run) | |
6aa8b732 | 1034 | { |
f0242478 | 1035 | pr_unimpl(&svm->vcpu, "%s: task switch is unsupported\n", __FUNCTION__); |
6aa8b732 AK |
1036 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; |
1037 | return 0; | |
1038 | } | |
1039 | ||
e756fc62 | 1040 | static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1041 | { |
a2fa3e9f | 1042 | svm->next_rip = svm->vmcb->save.rip + 2; |
e756fc62 | 1043 | kvm_emulate_cpuid(&svm->vcpu); |
06465c5a | 1044 | return 1; |
6aa8b732 AK |
1045 | } |
1046 | ||
e756fc62 RR |
1047 | static int emulate_on_interception(struct vcpu_svm *svm, |
1048 | struct kvm_run *kvm_run) | |
6aa8b732 | 1049 | { |
3427318f | 1050 | if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE) |
f0242478 | 1051 | pr_unimpl(&svm->vcpu, "%s: failed\n", __FUNCTION__); |
6aa8b732 AK |
1052 | return 1; |
1053 | } | |
1054 | ||
1055 | static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data) | |
1056 | { | |
a2fa3e9f GH |
1057 | struct vcpu_svm *svm = to_svm(vcpu); |
1058 | ||
6aa8b732 | 1059 | switch (ecx) { |
6aa8b732 AK |
1060 | case MSR_IA32_TIME_STAMP_COUNTER: { |
1061 | u64 tsc; | |
1062 | ||
1063 | rdtscll(tsc); | |
a2fa3e9f | 1064 | *data = svm->vmcb->control.tsc_offset + tsc; |
6aa8b732 AK |
1065 | break; |
1066 | } | |
0e859cac | 1067 | case MSR_K6_STAR: |
a2fa3e9f | 1068 | *data = svm->vmcb->save.star; |
6aa8b732 | 1069 | break; |
0e859cac | 1070 | #ifdef CONFIG_X86_64 |
6aa8b732 | 1071 | case MSR_LSTAR: |
a2fa3e9f | 1072 | *data = svm->vmcb->save.lstar; |
6aa8b732 AK |
1073 | break; |
1074 | case MSR_CSTAR: | |
a2fa3e9f | 1075 | *data = svm->vmcb->save.cstar; |
6aa8b732 AK |
1076 | break; |
1077 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 1078 | *data = svm->vmcb->save.kernel_gs_base; |
6aa8b732 AK |
1079 | break; |
1080 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 1081 | *data = svm->vmcb->save.sfmask; |
6aa8b732 AK |
1082 | break; |
1083 | #endif | |
1084 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 1085 | *data = svm->vmcb->save.sysenter_cs; |
6aa8b732 AK |
1086 | break; |
1087 | case MSR_IA32_SYSENTER_EIP: | |
a2fa3e9f | 1088 | *data = svm->vmcb->save.sysenter_eip; |
6aa8b732 AK |
1089 | break; |
1090 | case MSR_IA32_SYSENTER_ESP: | |
a2fa3e9f | 1091 | *data = svm->vmcb->save.sysenter_esp; |
6aa8b732 AK |
1092 | break; |
1093 | default: | |
3bab1f5d | 1094 | return kvm_get_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
1095 | } |
1096 | return 0; | |
1097 | } | |
1098 | ||
e756fc62 | 1099 | static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1100 | { |
e756fc62 | 1101 | u32 ecx = svm->vcpu.regs[VCPU_REGS_RCX]; |
6aa8b732 AK |
1102 | u64 data; |
1103 | ||
e756fc62 RR |
1104 | if (svm_get_msr(&svm->vcpu, ecx, &data)) |
1105 | svm_inject_gp(&svm->vcpu, 0); | |
6aa8b732 | 1106 | else { |
a2fa3e9f | 1107 | svm->vmcb->save.rax = data & 0xffffffff; |
e756fc62 | 1108 | svm->vcpu.regs[VCPU_REGS_RDX] = data >> 32; |
a2fa3e9f | 1109 | svm->next_rip = svm->vmcb->save.rip + 2; |
e756fc62 | 1110 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
1111 | } |
1112 | return 1; | |
1113 | } | |
1114 | ||
1115 | static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data) | |
1116 | { | |
a2fa3e9f GH |
1117 | struct vcpu_svm *svm = to_svm(vcpu); |
1118 | ||
6aa8b732 | 1119 | switch (ecx) { |
6aa8b732 AK |
1120 | case MSR_IA32_TIME_STAMP_COUNTER: { |
1121 | u64 tsc; | |
1122 | ||
1123 | rdtscll(tsc); | |
a2fa3e9f | 1124 | svm->vmcb->control.tsc_offset = data - tsc; |
6aa8b732 AK |
1125 | break; |
1126 | } | |
0e859cac | 1127 | case MSR_K6_STAR: |
a2fa3e9f | 1128 | svm->vmcb->save.star = data; |
6aa8b732 | 1129 | break; |
49b14f24 | 1130 | #ifdef CONFIG_X86_64 |
6aa8b732 | 1131 | case MSR_LSTAR: |
a2fa3e9f | 1132 | svm->vmcb->save.lstar = data; |
6aa8b732 AK |
1133 | break; |
1134 | case MSR_CSTAR: | |
a2fa3e9f | 1135 | svm->vmcb->save.cstar = data; |
6aa8b732 AK |
1136 | break; |
1137 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 1138 | svm->vmcb->save.kernel_gs_base = data; |
6aa8b732 AK |
1139 | break; |
1140 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 1141 | svm->vmcb->save.sfmask = data; |
6aa8b732 AK |
1142 | break; |
1143 | #endif | |
1144 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 1145 | svm->vmcb->save.sysenter_cs = data; |
6aa8b732 AK |
1146 | break; |
1147 | case MSR_IA32_SYSENTER_EIP: | |
a2fa3e9f | 1148 | svm->vmcb->save.sysenter_eip = data; |
6aa8b732 AK |
1149 | break; |
1150 | case MSR_IA32_SYSENTER_ESP: | |
a2fa3e9f | 1151 | svm->vmcb->save.sysenter_esp = data; |
6aa8b732 AK |
1152 | break; |
1153 | default: | |
3bab1f5d | 1154 | return kvm_set_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
1155 | } |
1156 | return 0; | |
1157 | } | |
1158 | ||
e756fc62 | 1159 | static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1160 | { |
e756fc62 | 1161 | u32 ecx = svm->vcpu.regs[VCPU_REGS_RCX]; |
a2fa3e9f | 1162 | u64 data = (svm->vmcb->save.rax & -1u) |
e756fc62 | 1163 | | ((u64)(svm->vcpu.regs[VCPU_REGS_RDX] & -1u) << 32); |
a2fa3e9f | 1164 | svm->next_rip = svm->vmcb->save.rip + 2; |
e756fc62 RR |
1165 | if (svm_set_msr(&svm->vcpu, ecx, data)) |
1166 | svm_inject_gp(&svm->vcpu, 0); | |
6aa8b732 | 1167 | else |
e756fc62 | 1168 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
1169 | return 1; |
1170 | } | |
1171 | ||
e756fc62 | 1172 | static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1173 | { |
e756fc62 RR |
1174 | if (svm->vmcb->control.exit_info_1) |
1175 | return wrmsr_interception(svm, kvm_run); | |
6aa8b732 | 1176 | else |
e756fc62 | 1177 | return rdmsr_interception(svm, kvm_run); |
6aa8b732 AK |
1178 | } |
1179 | ||
e756fc62 | 1180 | static int interrupt_window_interception(struct vcpu_svm *svm, |
c1150d8c DL |
1181 | struct kvm_run *kvm_run) |
1182 | { | |
85f455f7 ED |
1183 | svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR); |
1184 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; | |
c1150d8c DL |
1185 | /* |
1186 | * If the user space waits to inject interrupts, exit as soon as | |
1187 | * possible | |
1188 | */ | |
1189 | if (kvm_run->request_interrupt_window && | |
e756fc62 RR |
1190 | !svm->vcpu.irq_summary) { |
1191 | ++svm->vcpu.stat.irq_window_exits; | |
c1150d8c DL |
1192 | kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
1193 | return 0; | |
1194 | } | |
1195 | ||
1196 | return 1; | |
1197 | } | |
1198 | ||
e756fc62 | 1199 | static int (*svm_exit_handlers[])(struct vcpu_svm *svm, |
6aa8b732 AK |
1200 | struct kvm_run *kvm_run) = { |
1201 | [SVM_EXIT_READ_CR0] = emulate_on_interception, | |
1202 | [SVM_EXIT_READ_CR3] = emulate_on_interception, | |
1203 | [SVM_EXIT_READ_CR4] = emulate_on_interception, | |
1204 | /* for now: */ | |
1205 | [SVM_EXIT_WRITE_CR0] = emulate_on_interception, | |
1206 | [SVM_EXIT_WRITE_CR3] = emulate_on_interception, | |
1207 | [SVM_EXIT_WRITE_CR4] = emulate_on_interception, | |
1208 | [SVM_EXIT_READ_DR0] = emulate_on_interception, | |
1209 | [SVM_EXIT_READ_DR1] = emulate_on_interception, | |
1210 | [SVM_EXIT_READ_DR2] = emulate_on_interception, | |
1211 | [SVM_EXIT_READ_DR3] = emulate_on_interception, | |
1212 | [SVM_EXIT_WRITE_DR0] = emulate_on_interception, | |
1213 | [SVM_EXIT_WRITE_DR1] = emulate_on_interception, | |
1214 | [SVM_EXIT_WRITE_DR2] = emulate_on_interception, | |
1215 | [SVM_EXIT_WRITE_DR3] = emulate_on_interception, | |
1216 | [SVM_EXIT_WRITE_DR5] = emulate_on_interception, | |
1217 | [SVM_EXIT_WRITE_DR7] = emulate_on_interception, | |
7aa81cc0 | 1218 | [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception, |
6aa8b732 | 1219 | [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception, |
7807fa6c | 1220 | [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception, |
6aa8b732 AK |
1221 | [SVM_EXIT_INTR] = nop_on_interception, |
1222 | [SVM_EXIT_NMI] = nop_on_interception, | |
1223 | [SVM_EXIT_SMI] = nop_on_interception, | |
1224 | [SVM_EXIT_INIT] = nop_on_interception, | |
c1150d8c | 1225 | [SVM_EXIT_VINTR] = interrupt_window_interception, |
6aa8b732 AK |
1226 | /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */ |
1227 | [SVM_EXIT_CPUID] = cpuid_interception, | |
cf5a94d1 | 1228 | [SVM_EXIT_INVD] = emulate_on_interception, |
6aa8b732 AK |
1229 | [SVM_EXIT_HLT] = halt_interception, |
1230 | [SVM_EXIT_INVLPG] = emulate_on_interception, | |
1231 | [SVM_EXIT_INVLPGA] = invalid_op_interception, | |
1232 | [SVM_EXIT_IOIO] = io_interception, | |
1233 | [SVM_EXIT_MSR] = msr_interception, | |
1234 | [SVM_EXIT_TASK_SWITCH] = task_switch_interception, | |
46fe4ddd | 1235 | [SVM_EXIT_SHUTDOWN] = shutdown_interception, |
6aa8b732 | 1236 | [SVM_EXIT_VMRUN] = invalid_op_interception, |
02e235bc | 1237 | [SVM_EXIT_VMMCALL] = vmmcall_interception, |
6aa8b732 AK |
1238 | [SVM_EXIT_VMLOAD] = invalid_op_interception, |
1239 | [SVM_EXIT_VMSAVE] = invalid_op_interception, | |
1240 | [SVM_EXIT_STGI] = invalid_op_interception, | |
1241 | [SVM_EXIT_CLGI] = invalid_op_interception, | |
1242 | [SVM_EXIT_SKINIT] = invalid_op_interception, | |
cf5a94d1 | 1243 | [SVM_EXIT_WBINVD] = emulate_on_interception, |
916ce236 JR |
1244 | [SVM_EXIT_MONITOR] = invalid_op_interception, |
1245 | [SVM_EXIT_MWAIT] = invalid_op_interception, | |
6aa8b732 AK |
1246 | }; |
1247 | ||
1248 | ||
04d2cc77 | 1249 | static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu) |
6aa8b732 | 1250 | { |
04d2cc77 | 1251 | struct vcpu_svm *svm = to_svm(vcpu); |
a2fa3e9f | 1252 | u32 exit_code = svm->vmcb->control.exit_code; |
6aa8b732 | 1253 | |
04d2cc77 AK |
1254 | kvm_reput_irq(svm); |
1255 | ||
1256 | if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) { | |
1257 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
1258 | kvm_run->fail_entry.hardware_entry_failure_reason | |
1259 | = svm->vmcb->control.exit_code; | |
1260 | return 0; | |
1261 | } | |
1262 | ||
a2fa3e9f | 1263 | if (is_external_interrupt(svm->vmcb->control.exit_int_info) && |
6aa8b732 AK |
1264 | exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR) |
1265 | printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x " | |
1266 | "exit_code 0x%x\n", | |
a2fa3e9f | 1267 | __FUNCTION__, svm->vmcb->control.exit_int_info, |
6aa8b732 AK |
1268 | exit_code); |
1269 | ||
9d8f549d | 1270 | if (exit_code >= ARRAY_SIZE(svm_exit_handlers) |
56919c5c | 1271 | || !svm_exit_handlers[exit_code]) { |
6aa8b732 | 1272 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; |
364b625b | 1273 | kvm_run->hw.hardware_exit_reason = exit_code; |
6aa8b732 AK |
1274 | return 0; |
1275 | } | |
1276 | ||
e756fc62 | 1277 | return svm_exit_handlers[exit_code](svm, kvm_run); |
6aa8b732 AK |
1278 | } |
1279 | ||
1280 | static void reload_tss(struct kvm_vcpu *vcpu) | |
1281 | { | |
1282 | int cpu = raw_smp_processor_id(); | |
1283 | ||
1284 | struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu); | |
d77c26fc | 1285 | svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */ |
6aa8b732 AK |
1286 | load_TR_desc(); |
1287 | } | |
1288 | ||
e756fc62 | 1289 | static void pre_svm_run(struct vcpu_svm *svm) |
6aa8b732 AK |
1290 | { |
1291 | int cpu = raw_smp_processor_id(); | |
1292 | ||
1293 | struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu); | |
1294 | ||
a2fa3e9f | 1295 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING; |
e756fc62 | 1296 | if (svm->vcpu.cpu != cpu || |
a2fa3e9f | 1297 | svm->asid_generation != svm_data->asid_generation) |
e756fc62 | 1298 | new_asid(svm, svm_data); |
6aa8b732 AK |
1299 | } |
1300 | ||
1301 | ||
85f455f7 | 1302 | static inline void svm_inject_irq(struct vcpu_svm *svm, int irq) |
6aa8b732 AK |
1303 | { |
1304 | struct vmcb_control_area *control; | |
1305 | ||
e756fc62 | 1306 | control = &svm->vmcb->control; |
85f455f7 | 1307 | control->int_vector = irq; |
6aa8b732 AK |
1308 | control->int_ctl &= ~V_INTR_PRIO_MASK; |
1309 | control->int_ctl |= V_IRQ_MASK | | |
1310 | ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT); | |
1311 | } | |
1312 | ||
2a8067f1 ED |
1313 | static void svm_set_irq(struct kvm_vcpu *vcpu, int irq) |
1314 | { | |
1315 | struct vcpu_svm *svm = to_svm(vcpu); | |
1316 | ||
1317 | svm_inject_irq(svm, irq); | |
1318 | } | |
1319 | ||
04d2cc77 | 1320 | static void svm_intr_assist(struct kvm_vcpu *vcpu) |
6aa8b732 | 1321 | { |
04d2cc77 | 1322 | struct vcpu_svm *svm = to_svm(vcpu); |
85f455f7 ED |
1323 | struct vmcb *vmcb = svm->vmcb; |
1324 | int intr_vector = -1; | |
1325 | ||
1326 | if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) && | |
1327 | ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) { | |
1328 | intr_vector = vmcb->control.exit_int_info & | |
1329 | SVM_EVTINJ_VEC_MASK; | |
1330 | vmcb->control.exit_int_info = 0; | |
1331 | svm_inject_irq(svm, intr_vector); | |
1332 | return; | |
1333 | } | |
1334 | ||
1335 | if (vmcb->control.int_ctl & V_IRQ_MASK) | |
1336 | return; | |
1337 | ||
1b9778da | 1338 | if (!kvm_cpu_has_interrupt(vcpu)) |
85f455f7 ED |
1339 | return; |
1340 | ||
1341 | if (!(vmcb->save.rflags & X86_EFLAGS_IF) || | |
1342 | (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) || | |
1343 | (vmcb->control.event_inj & SVM_EVTINJ_VALID)) { | |
1344 | /* unable to deliver irq, set pending irq */ | |
1345 | vmcb->control.intercept |= (1ULL << INTERCEPT_VINTR); | |
1346 | svm_inject_irq(svm, 0x0); | |
1347 | return; | |
1348 | } | |
1349 | /* Okay, we can deliver the interrupt: grab it and update PIC state. */ | |
1b9778da | 1350 | intr_vector = kvm_cpu_get_interrupt(vcpu); |
85f455f7 | 1351 | svm_inject_irq(svm, intr_vector); |
1b9778da | 1352 | kvm_timer_intr_post(vcpu, intr_vector); |
85f455f7 ED |
1353 | } |
1354 | ||
1355 | static void kvm_reput_irq(struct vcpu_svm *svm) | |
1356 | { | |
e756fc62 | 1357 | struct vmcb_control_area *control = &svm->vmcb->control; |
6aa8b732 | 1358 | |
7017fc3d ED |
1359 | if ((control->int_ctl & V_IRQ_MASK) |
1360 | && !irqchip_in_kernel(svm->vcpu.kvm)) { | |
6aa8b732 | 1361 | control->int_ctl &= ~V_IRQ_MASK; |
e756fc62 | 1362 | push_irq(&svm->vcpu, control->int_vector); |
6aa8b732 | 1363 | } |
c1150d8c | 1364 | |
e756fc62 | 1365 | svm->vcpu.interrupt_window_open = |
c1150d8c DL |
1366 | !(control->int_state & SVM_INTERRUPT_SHADOW_MASK); |
1367 | } | |
1368 | ||
85f455f7 ED |
1369 | static void svm_do_inject_vector(struct vcpu_svm *svm) |
1370 | { | |
1371 | struct kvm_vcpu *vcpu = &svm->vcpu; | |
1372 | int word_index = __ffs(vcpu->irq_summary); | |
1373 | int bit_index = __ffs(vcpu->irq_pending[word_index]); | |
1374 | int irq = word_index * BITS_PER_LONG + bit_index; | |
1375 | ||
1376 | clear_bit(bit_index, &vcpu->irq_pending[word_index]); | |
1377 | if (!vcpu->irq_pending[word_index]) | |
1378 | clear_bit(word_index, &vcpu->irq_summary); | |
1379 | svm_inject_irq(svm, irq); | |
1380 | } | |
1381 | ||
04d2cc77 | 1382 | static void do_interrupt_requests(struct kvm_vcpu *vcpu, |
c1150d8c DL |
1383 | struct kvm_run *kvm_run) |
1384 | { | |
04d2cc77 | 1385 | struct vcpu_svm *svm = to_svm(vcpu); |
a2fa3e9f | 1386 | struct vmcb_control_area *control = &svm->vmcb->control; |
c1150d8c | 1387 | |
e756fc62 | 1388 | svm->vcpu.interrupt_window_open = |
c1150d8c | 1389 | (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) && |
a2fa3e9f | 1390 | (svm->vmcb->save.rflags & X86_EFLAGS_IF)); |
c1150d8c | 1391 | |
e756fc62 | 1392 | if (svm->vcpu.interrupt_window_open && svm->vcpu.irq_summary) |
c1150d8c DL |
1393 | /* |
1394 | * If interrupts enabled, and not blocked by sti or mov ss. Good. | |
1395 | */ | |
85f455f7 | 1396 | svm_do_inject_vector(svm); |
c1150d8c DL |
1397 | |
1398 | /* | |
1399 | * Interrupts blocked. Wait for unblock. | |
1400 | */ | |
e756fc62 | 1401 | if (!svm->vcpu.interrupt_window_open && |
d77c26fc | 1402 | (svm->vcpu.irq_summary || kvm_run->request_interrupt_window)) |
c1150d8c | 1403 | control->intercept |= 1ULL << INTERCEPT_VINTR; |
d77c26fc | 1404 | else |
c1150d8c DL |
1405 | control->intercept &= ~(1ULL << INTERCEPT_VINTR); |
1406 | } | |
1407 | ||
cbc94022 IE |
1408 | static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr) |
1409 | { | |
1410 | return 0; | |
1411 | } | |
1412 | ||
6aa8b732 AK |
1413 | static void save_db_regs(unsigned long *db_regs) |
1414 | { | |
5aff458e AK |
1415 | asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0])); |
1416 | asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1])); | |
1417 | asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2])); | |
1418 | asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3])); | |
6aa8b732 AK |
1419 | } |
1420 | ||
1421 | static void load_db_regs(unsigned long *db_regs) | |
1422 | { | |
5aff458e AK |
1423 | asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0])); |
1424 | asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1])); | |
1425 | asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2])); | |
1426 | asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3])); | |
6aa8b732 AK |
1427 | } |
1428 | ||
d9e368d6 AK |
1429 | static void svm_flush_tlb(struct kvm_vcpu *vcpu) |
1430 | { | |
1431 | force_new_asid(vcpu); | |
1432 | } | |
1433 | ||
04d2cc77 AK |
1434 | static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu) |
1435 | { | |
1436 | } | |
1437 | ||
1438 | static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
6aa8b732 | 1439 | { |
a2fa3e9f | 1440 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
1441 | u16 fs_selector; |
1442 | u16 gs_selector; | |
1443 | u16 ldt_selector; | |
d9e368d6 | 1444 | |
e756fc62 | 1445 | pre_svm_run(svm); |
6aa8b732 AK |
1446 | |
1447 | save_host_msrs(vcpu); | |
1448 | fs_selector = read_fs(); | |
1449 | gs_selector = read_gs(); | |
1450 | ldt_selector = read_ldt(); | |
a2fa3e9f GH |
1451 | svm->host_cr2 = kvm_read_cr2(); |
1452 | svm->host_dr6 = read_dr6(); | |
1453 | svm->host_dr7 = read_dr7(); | |
1454 | svm->vmcb->save.cr2 = vcpu->cr2; | |
6aa8b732 | 1455 | |
a2fa3e9f | 1456 | if (svm->vmcb->save.dr7 & 0xff) { |
6aa8b732 | 1457 | write_dr7(0); |
a2fa3e9f GH |
1458 | save_db_regs(svm->host_db_regs); |
1459 | load_db_regs(svm->db_regs); | |
6aa8b732 | 1460 | } |
36241b8c | 1461 | |
04d2cc77 AK |
1462 | clgi(); |
1463 | ||
1464 | local_irq_enable(); | |
36241b8c | 1465 | |
6aa8b732 | 1466 | asm volatile ( |
05b3e0c2 | 1467 | #ifdef CONFIG_X86_64 |
54a08c04 | 1468 | "push %%rbp; \n\t" |
6aa8b732 | 1469 | #else |
fe7935d4 | 1470 | "push %%ebp; \n\t" |
6aa8b732 AK |
1471 | #endif |
1472 | ||
05b3e0c2 | 1473 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
1474 | "mov %c[rbx](%[svm]), %%rbx \n\t" |
1475 | "mov %c[rcx](%[svm]), %%rcx \n\t" | |
1476 | "mov %c[rdx](%[svm]), %%rdx \n\t" | |
1477 | "mov %c[rsi](%[svm]), %%rsi \n\t" | |
1478 | "mov %c[rdi](%[svm]), %%rdi \n\t" | |
1479 | "mov %c[rbp](%[svm]), %%rbp \n\t" | |
1480 | "mov %c[r8](%[svm]), %%r8 \n\t" | |
1481 | "mov %c[r9](%[svm]), %%r9 \n\t" | |
1482 | "mov %c[r10](%[svm]), %%r10 \n\t" | |
1483 | "mov %c[r11](%[svm]), %%r11 \n\t" | |
1484 | "mov %c[r12](%[svm]), %%r12 \n\t" | |
1485 | "mov %c[r13](%[svm]), %%r13 \n\t" | |
1486 | "mov %c[r14](%[svm]), %%r14 \n\t" | |
1487 | "mov %c[r15](%[svm]), %%r15 \n\t" | |
6aa8b732 | 1488 | #else |
fb3f0f51 RR |
1489 | "mov %c[rbx](%[svm]), %%ebx \n\t" |
1490 | "mov %c[rcx](%[svm]), %%ecx \n\t" | |
1491 | "mov %c[rdx](%[svm]), %%edx \n\t" | |
1492 | "mov %c[rsi](%[svm]), %%esi \n\t" | |
1493 | "mov %c[rdi](%[svm]), %%edi \n\t" | |
1494 | "mov %c[rbp](%[svm]), %%ebp \n\t" | |
6aa8b732 AK |
1495 | #endif |
1496 | ||
05b3e0c2 | 1497 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1498 | /* Enter guest mode */ |
1499 | "push %%rax \n\t" | |
fb3f0f51 | 1500 | "mov %c[vmcb](%[svm]), %%rax \n\t" |
6aa8b732 AK |
1501 | SVM_VMLOAD "\n\t" |
1502 | SVM_VMRUN "\n\t" | |
1503 | SVM_VMSAVE "\n\t" | |
1504 | "pop %%rax \n\t" | |
1505 | #else | |
1506 | /* Enter guest mode */ | |
1507 | "push %%eax \n\t" | |
fb3f0f51 | 1508 | "mov %c[vmcb](%[svm]), %%eax \n\t" |
6aa8b732 AK |
1509 | SVM_VMLOAD "\n\t" |
1510 | SVM_VMRUN "\n\t" | |
1511 | SVM_VMSAVE "\n\t" | |
1512 | "pop %%eax \n\t" | |
1513 | #endif | |
1514 | ||
1515 | /* Save guest registers, load host registers */ | |
05b3e0c2 | 1516 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
1517 | "mov %%rbx, %c[rbx](%[svm]) \n\t" |
1518 | "mov %%rcx, %c[rcx](%[svm]) \n\t" | |
1519 | "mov %%rdx, %c[rdx](%[svm]) \n\t" | |
1520 | "mov %%rsi, %c[rsi](%[svm]) \n\t" | |
1521 | "mov %%rdi, %c[rdi](%[svm]) \n\t" | |
1522 | "mov %%rbp, %c[rbp](%[svm]) \n\t" | |
1523 | "mov %%r8, %c[r8](%[svm]) \n\t" | |
1524 | "mov %%r9, %c[r9](%[svm]) \n\t" | |
1525 | "mov %%r10, %c[r10](%[svm]) \n\t" | |
1526 | "mov %%r11, %c[r11](%[svm]) \n\t" | |
1527 | "mov %%r12, %c[r12](%[svm]) \n\t" | |
1528 | "mov %%r13, %c[r13](%[svm]) \n\t" | |
1529 | "mov %%r14, %c[r14](%[svm]) \n\t" | |
1530 | "mov %%r15, %c[r15](%[svm]) \n\t" | |
6aa8b732 | 1531 | |
54a08c04 | 1532 | "pop %%rbp; \n\t" |
6aa8b732 | 1533 | #else |
fb3f0f51 RR |
1534 | "mov %%ebx, %c[rbx](%[svm]) \n\t" |
1535 | "mov %%ecx, %c[rcx](%[svm]) \n\t" | |
1536 | "mov %%edx, %c[rdx](%[svm]) \n\t" | |
1537 | "mov %%esi, %c[rsi](%[svm]) \n\t" | |
1538 | "mov %%edi, %c[rdi](%[svm]) \n\t" | |
1539 | "mov %%ebp, %c[rbp](%[svm]) \n\t" | |
6aa8b732 | 1540 | |
fe7935d4 | 1541 | "pop %%ebp; \n\t" |
6aa8b732 AK |
1542 | #endif |
1543 | : | |
fb3f0f51 | 1544 | : [svm]"a"(svm), |
6aa8b732 | 1545 | [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)), |
d77c26fc MD |
1546 | [rbx]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_RBX])), |
1547 | [rcx]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_RCX])), | |
1548 | [rdx]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_RDX])), | |
1549 | [rsi]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_RSI])), | |
1550 | [rdi]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_RDI])), | |
1551 | [rbp]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_RBP])) | |
05b3e0c2 | 1552 | #ifdef CONFIG_X86_64 |
d77c26fc MD |
1553 | , [r8]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_R8])), |
1554 | [r9]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_R9])), | |
1555 | [r10]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_R10])), | |
1556 | [r11]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_R11])), | |
1557 | [r12]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_R12])), | |
1558 | [r13]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_R13])), | |
1559 | [r14]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_R14])), | |
1560 | [r15]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_R15])) | |
6aa8b732 | 1561 | #endif |
54a08c04 LV |
1562 | : "cc", "memory" |
1563 | #ifdef CONFIG_X86_64 | |
1564 | , "rbx", "rcx", "rdx", "rsi", "rdi" | |
1565 | , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15" | |
fe7935d4 LV |
1566 | #else |
1567 | , "ebx", "ecx", "edx" , "esi", "edi" | |
54a08c04 LV |
1568 | #endif |
1569 | ); | |
6aa8b732 | 1570 | |
a2fa3e9f GH |
1571 | if ((svm->vmcb->save.dr7 & 0xff)) |
1572 | load_db_regs(svm->host_db_regs); | |
6aa8b732 | 1573 | |
a2fa3e9f | 1574 | vcpu->cr2 = svm->vmcb->save.cr2; |
6aa8b732 | 1575 | |
a2fa3e9f GH |
1576 | write_dr6(svm->host_dr6); |
1577 | write_dr7(svm->host_dr7); | |
1578 | kvm_write_cr2(svm->host_cr2); | |
6aa8b732 AK |
1579 | |
1580 | load_fs(fs_selector); | |
1581 | load_gs(gs_selector); | |
1582 | load_ldt(ldt_selector); | |
1583 | load_host_msrs(vcpu); | |
1584 | ||
1585 | reload_tss(vcpu); | |
1586 | ||
56ba47dd AK |
1587 | local_irq_disable(); |
1588 | ||
1589 | stgi(); | |
1590 | ||
a2fa3e9f | 1591 | svm->next_rip = 0; |
6aa8b732 AK |
1592 | } |
1593 | ||
6aa8b732 AK |
1594 | static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
1595 | { | |
a2fa3e9f GH |
1596 | struct vcpu_svm *svm = to_svm(vcpu); |
1597 | ||
1598 | svm->vmcb->save.cr3 = root; | |
6aa8b732 | 1599 | force_new_asid(vcpu); |
7807fa6c AL |
1600 | |
1601 | if (vcpu->fpu_active) { | |
a2fa3e9f GH |
1602 | svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR); |
1603 | svm->vmcb->save.cr0 |= X86_CR0_TS; | |
7807fa6c AL |
1604 | vcpu->fpu_active = 0; |
1605 | } | |
6aa8b732 AK |
1606 | } |
1607 | ||
1608 | static void svm_inject_page_fault(struct kvm_vcpu *vcpu, | |
1609 | unsigned long addr, | |
1610 | uint32_t err_code) | |
1611 | { | |
a2fa3e9f GH |
1612 | struct vcpu_svm *svm = to_svm(vcpu); |
1613 | uint32_t exit_int_info = svm->vmcb->control.exit_int_info; | |
6aa8b732 | 1614 | |
1165f5fe | 1615 | ++vcpu->stat.pf_guest; |
6aa8b732 AK |
1616 | |
1617 | if (is_page_fault(exit_int_info)) { | |
1618 | ||
a2fa3e9f GH |
1619 | svm->vmcb->control.event_inj_err = 0; |
1620 | svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | | |
1621 | SVM_EVTINJ_VALID_ERR | | |
1622 | SVM_EVTINJ_TYPE_EXEPT | | |
1623 | DF_VECTOR; | |
6aa8b732 AK |
1624 | return; |
1625 | } | |
1626 | vcpu->cr2 = addr; | |
a2fa3e9f GH |
1627 | svm->vmcb->save.cr2 = addr; |
1628 | svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | | |
1629 | SVM_EVTINJ_VALID_ERR | | |
1630 | SVM_EVTINJ_TYPE_EXEPT | | |
1631 | PF_VECTOR; | |
1632 | svm->vmcb->control.event_inj_err = err_code; | |
6aa8b732 AK |
1633 | } |
1634 | ||
1635 | ||
1636 | static int is_disabled(void) | |
1637 | { | |
6031a61c JR |
1638 | u64 vm_cr; |
1639 | ||
1640 | rdmsrl(MSR_VM_CR, vm_cr); | |
1641 | if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE)) | |
1642 | return 1; | |
1643 | ||
6aa8b732 AK |
1644 | return 0; |
1645 | } | |
1646 | ||
102d8325 IM |
1647 | static void |
1648 | svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
1649 | { | |
1650 | /* | |
1651 | * Patch in the VMMCALL instruction: | |
1652 | */ | |
1653 | hypercall[0] = 0x0f; | |
1654 | hypercall[1] = 0x01; | |
1655 | hypercall[2] = 0xd9; | |
102d8325 IM |
1656 | } |
1657 | ||
002c7f7c YS |
1658 | static void svm_check_processor_compat(void *rtn) |
1659 | { | |
1660 | *(int *)rtn = 0; | |
1661 | } | |
1662 | ||
cbdd1bea | 1663 | static struct kvm_x86_ops svm_x86_ops = { |
6aa8b732 AK |
1664 | .cpu_has_kvm_support = has_svm, |
1665 | .disabled_by_bios = is_disabled, | |
1666 | .hardware_setup = svm_hardware_setup, | |
1667 | .hardware_unsetup = svm_hardware_unsetup, | |
002c7f7c | 1668 | .check_processor_compatibility = svm_check_processor_compat, |
6aa8b732 AK |
1669 | .hardware_enable = svm_hardware_enable, |
1670 | .hardware_disable = svm_hardware_disable, | |
1671 | ||
1672 | .vcpu_create = svm_create_vcpu, | |
1673 | .vcpu_free = svm_free_vcpu, | |
04d2cc77 | 1674 | .vcpu_reset = svm_vcpu_reset, |
6aa8b732 | 1675 | |
04d2cc77 | 1676 | .prepare_guest_switch = svm_prepare_guest_switch, |
6aa8b732 AK |
1677 | .vcpu_load = svm_vcpu_load, |
1678 | .vcpu_put = svm_vcpu_put, | |
774c47f1 | 1679 | .vcpu_decache = svm_vcpu_decache, |
6aa8b732 AK |
1680 | |
1681 | .set_guest_debug = svm_guest_debug, | |
1682 | .get_msr = svm_get_msr, | |
1683 | .set_msr = svm_set_msr, | |
1684 | .get_segment_base = svm_get_segment_base, | |
1685 | .get_segment = svm_get_segment, | |
1686 | .set_segment = svm_set_segment, | |
1747fb71 | 1687 | .get_cs_db_l_bits = kvm_get_cs_db_l_bits, |
25c4c276 | 1688 | .decache_cr4_guest_bits = svm_decache_cr4_guest_bits, |
6aa8b732 | 1689 | .set_cr0 = svm_set_cr0, |
6aa8b732 AK |
1690 | .set_cr3 = svm_set_cr3, |
1691 | .set_cr4 = svm_set_cr4, | |
1692 | .set_efer = svm_set_efer, | |
1693 | .get_idt = svm_get_idt, | |
1694 | .set_idt = svm_set_idt, | |
1695 | .get_gdt = svm_get_gdt, | |
1696 | .set_gdt = svm_set_gdt, | |
1697 | .get_dr = svm_get_dr, | |
1698 | .set_dr = svm_set_dr, | |
1699 | .cache_regs = svm_cache_regs, | |
1700 | .decache_regs = svm_decache_regs, | |
1701 | .get_rflags = svm_get_rflags, | |
1702 | .set_rflags = svm_set_rflags, | |
1703 | ||
6aa8b732 AK |
1704 | .tlb_flush = svm_flush_tlb, |
1705 | .inject_page_fault = svm_inject_page_fault, | |
1706 | ||
1707 | .inject_gp = svm_inject_gp, | |
1708 | ||
1709 | .run = svm_vcpu_run, | |
04d2cc77 | 1710 | .handle_exit = handle_exit, |
6aa8b732 | 1711 | .skip_emulated_instruction = skip_emulated_instruction, |
102d8325 | 1712 | .patch_hypercall = svm_patch_hypercall, |
2a8067f1 ED |
1713 | .get_irq = svm_get_irq, |
1714 | .set_irq = svm_set_irq, | |
04d2cc77 AK |
1715 | .inject_pending_irq = svm_intr_assist, |
1716 | .inject_pending_vectors = do_interrupt_requests, | |
cbc94022 IE |
1717 | |
1718 | .set_tss_addr = svm_set_tss_addr, | |
6aa8b732 AK |
1719 | }; |
1720 | ||
1721 | static int __init svm_init(void) | |
1722 | { | |
cb498ea2 | 1723 | return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm), |
c16f862d | 1724 | THIS_MODULE); |
6aa8b732 AK |
1725 | } |
1726 | ||
1727 | static void __exit svm_exit(void) | |
1728 | { | |
cb498ea2 | 1729 | kvm_exit(); |
6aa8b732 AK |
1730 | } |
1731 | ||
1732 | module_init(svm_init) | |
1733 | module_exit(svm_exit) |