KVM: Keep an upper bound of initialized vcpus
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / kvm / kvm.h
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1#ifndef __KVM_H
2#define __KVM_H
3
4/*
5 * This work is licensed under the terms of the GNU GPL, version 2. See
6 * the COPYING file in the top-level directory.
7 */
8
9#include <linux/types.h>
10#include <linux/list.h>
11#include <linux/mutex.h>
12#include <linux/spinlock.h>
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13#include <linux/signal.h>
14#include <linux/sched.h>
6aa8b732 15#include <linux/mm.h>
e8edc6e0 16#include <asm/signal.h>
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17
18#include "vmx.h"
19#include <linux/kvm.h>
102d8325 20#include <linux/kvm_para.h>
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21
22#define CR0_PE_MASK (1ULL << 0)
a3a06367 23#define CR0_MP_MASK (1ULL << 1)
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24#define CR0_TS_MASK (1ULL << 3)
25#define CR0_NE_MASK (1ULL << 5)
26#define CR0_WP_MASK (1ULL << 16)
27#define CR0_NW_MASK (1ULL << 29)
28#define CR0_CD_MASK (1ULL << 30)
29#define CR0_PG_MASK (1ULL << 31)
30
31#define CR3_WPT_MASK (1ULL << 3)
32#define CR3_PCD_MASK (1ULL << 4)
33
34#define CR3_RESEVED_BITS 0x07ULL
35#define CR3_L_MODE_RESEVED_BITS (~((1ULL << 40) - 1) | 0x0fe7ULL)
36#define CR3_FLAGS_MASK ((1ULL << 5) - 1)
37
38#define CR4_VME_MASK (1ULL << 0)
39#define CR4_PSE_MASK (1ULL << 4)
40#define CR4_PAE_MASK (1ULL << 5)
41#define CR4_PGE_MASK (1ULL << 7)
42#define CR4_VMXE_MASK (1ULL << 13)
43
44#define KVM_GUEST_CR0_MASK \
45 (CR0_PG_MASK | CR0_PE_MASK | CR0_WP_MASK | CR0_NE_MASK \
46 | CR0_NW_MASK | CR0_CD_MASK)
47#define KVM_VM_CR0_ALWAYS_ON \
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48 (CR0_PG_MASK | CR0_PE_MASK | CR0_WP_MASK | CR0_NE_MASK | CR0_TS_MASK \
49 | CR0_MP_MASK)
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50#define KVM_GUEST_CR4_MASK \
51 (CR4_PSE_MASK | CR4_PAE_MASK | CR4_PGE_MASK | CR4_VMXE_MASK | CR4_VME_MASK)
52#define KVM_PMODE_VM_CR4_ALWAYS_ON (CR4_VMXE_MASK | CR4_PAE_MASK)
53#define KVM_RMODE_VM_CR4_ALWAYS_ON (CR4_VMXE_MASK | CR4_PAE_MASK | CR4_VME_MASK)
54
55#define INVALID_PAGE (~(hpa_t)0)
56#define UNMAPPED_GVA (~(gpa_t)0)
57
ef9254df 58#define KVM_MAX_VCPUS 4
e8207547 59#define KVM_ALIAS_SLOTS 4
6aa8b732 60#define KVM_MEMORY_SLOTS 4
7494c0cc 61#define KVM_NUM_MMU_PAGES 1024
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62#define KVM_MIN_FREE_MMU_PAGES 5
63#define KVM_REFILL_PAGES 25
06465c5a 64#define KVM_MAX_CPUID_ENTRIES 40
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65
66#define FX_IMAGE_SIZE 512
67#define FX_IMAGE_ALIGN 16
68#define FX_BUF_SIZE (2 * FX_IMAGE_SIZE + FX_IMAGE_ALIGN)
69
70#define DE_VECTOR 0
7807fa6c 71#define NM_VECTOR 7
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72#define DF_VECTOR 8
73#define TS_VECTOR 10
74#define NP_VECTOR 11
75#define SS_VECTOR 12
76#define GP_VECTOR 13
77#define PF_VECTOR 14
78
79#define SELECTOR_TI_MASK (1 << 2)
80#define SELECTOR_RPL_MASK 0x03
81
82#define IOPL_SHIFT 12
83
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84#define KVM_PIO_PAGE_OFFSET 1
85
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86/*
87 * Address types:
88 *
89 * gva - guest virtual address
90 * gpa - guest physical address
91 * gfn - guest frame number
92 * hva - host virtual address
93 * hpa - host physical address
94 * hfn - host frame number
95 */
96
97typedef unsigned long gva_t;
98typedef u64 gpa_t;
99typedef unsigned long gfn_t;
100
101typedef unsigned long hva_t;
102typedef u64 hpa_t;
103typedef unsigned long hfn_t;
104
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105#define NR_PTE_CHAIN_ENTRIES 5
106
107struct kvm_pte_chain {
108 u64 *parent_ptes[NR_PTE_CHAIN_ENTRIES];
109 struct hlist_node link;
110};
111
112/*
113 * kvm_mmu_page_role, below, is defined as:
114 *
115 * bits 0:3 - total guest paging levels (2-4, or zero for real mode)
116 * bits 4:7 - page table level for this shadow (1-4)
117 * bits 8:9 - page table quadrant for 2-level guests
118 * bit 16 - "metaphysical" - gfn is not a real page (huge page/real mode)
d28c6cfb 119 * bits 17:18 - "access" - the user and writable bits of a huge page pde
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120 */
121union kvm_mmu_page_role {
122 unsigned word;
123 struct {
124 unsigned glevels : 4;
125 unsigned level : 4;
126 unsigned quadrant : 2;
127 unsigned pad_for_nice_hex_output : 6;
128 unsigned metaphysical : 1;
d28c6cfb 129 unsigned hugepage_access : 2;
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130 };
131};
132
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133struct kvm_mmu_page {
134 struct list_head link;
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135 struct hlist_node hash_link;
136
137 /*
138 * The following two entries are used to key the shadow page in the
139 * hash table.
140 */
141 gfn_t gfn;
142 union kvm_mmu_page_role role;
143
47ad8e68 144 u64 *spt;
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145 unsigned long slot_bitmap; /* One bit set per slot which has memory
146 * in this shadow page.
147 */
cea0f0e7 148 int multimapped; /* More than one parent_pte? */
3bb65a22 149 int root_count; /* Currently serving as active root */
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150 union {
151 u64 *parent_pte; /* !multimapped */
152 struct hlist_head parent_ptes; /* multimapped, kvm_pte_chain */
153 };
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154};
155
156struct vmcs {
157 u32 revision_id;
158 u32 abort;
159 char data[0];
160};
161
162#define vmx_msr_entry kvm_msr_entry
163
164struct kvm_vcpu;
165
166/*
167 * x86 supports 3 paging modes (4-level 64-bit, 3-level 64-bit, and 2-level
168 * 32-bit). The kvm_mmu structure abstracts the details of the current mmu
169 * mode.
170 */
171struct kvm_mmu {
172 void (*new_cr3)(struct kvm_vcpu *vcpu);
173 int (*page_fault)(struct kvm_vcpu *vcpu, gva_t gva, u32 err);
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174 void (*free)(struct kvm_vcpu *vcpu);
175 gpa_t (*gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t gva);
176 hpa_t root_hpa;
177 int root_level;
178 int shadow_root_level;
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179
180 u64 *pae_root;
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181};
182
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183#define KVM_NR_MEM_OBJS 20
184
185struct kvm_mmu_memory_cache {
186 int nobjs;
187 void *objects[KVM_NR_MEM_OBJS];
188};
189
190/*
191 * We don't want allocation failures within the mmu code, so we preallocate
192 * enough memory for a single page fault in a cache.
193 */
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194struct kvm_guest_debug {
195 int enabled;
196 unsigned long bp[4];
197 int singlestep;
198};
199
200enum {
201 VCPU_REGS_RAX = 0,
202 VCPU_REGS_RCX = 1,
203 VCPU_REGS_RDX = 2,
204 VCPU_REGS_RBX = 3,
205 VCPU_REGS_RSP = 4,
206 VCPU_REGS_RBP = 5,
207 VCPU_REGS_RSI = 6,
208 VCPU_REGS_RDI = 7,
05b3e0c2 209#ifdef CONFIG_X86_64
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210 VCPU_REGS_R8 = 8,
211 VCPU_REGS_R9 = 9,
212 VCPU_REGS_R10 = 10,
213 VCPU_REGS_R11 = 11,
214 VCPU_REGS_R12 = 12,
215 VCPU_REGS_R13 = 13,
216 VCPU_REGS_R14 = 14,
217 VCPU_REGS_R15 = 15,
218#endif
219 NR_VCPU_REGS
220};
221
222enum {
223 VCPU_SREG_CS,
224 VCPU_SREG_DS,
225 VCPU_SREG_ES,
226 VCPU_SREG_FS,
227 VCPU_SREG_GS,
228 VCPU_SREG_SS,
229 VCPU_SREG_TR,
230 VCPU_SREG_LDTR,
231};
232
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233struct kvm_pio_request {
234 unsigned long count;
235 int cur_count;
236 struct page *guest_pages[2];
237 unsigned guest_page_offset;
238 int in;
239 int size;
240 int string;
241 int down;
242 int rep;
243};
244
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245struct kvm_stat {
246 u32 pf_fixed;
247 u32 pf_guest;
248 u32 tlb_flush;
249 u32 invlpg;
250
251 u32 exits;
252 u32 io_exits;
253 u32 mmio_exits;
254 u32 signal_exits;
255 u32 irq_window_exits;
256 u32 halt_exits;
257 u32 request_irq_exits;
258 u32 irq_exits;
e6adf283 259 u32 light_exits;
2cc51560 260 u32 efer_reload;
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261};
262
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263struct kvm_vcpu {
264 struct kvm *kvm;
265 union {
266 struct vmcs *vmcs;
267 struct vcpu_svm *svm;
268 };
269 struct mutex mutex;
270 int cpu;
271 int launched;
0cc5064d 272 u64 host_tsc;
9a2bb7f4 273 struct kvm_run *run;
c1150d8c 274 int interrupt_window_open;
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275 unsigned long irq_summary; /* bit vector: 1 per word in irq_pending */
276#define NR_IRQ_WORDS KVM_IRQ_BITMAP_SIZE(unsigned long)
277 unsigned long irq_pending[NR_IRQ_WORDS];
278 unsigned long regs[NR_VCPU_REGS]; /* for rsp: vcpu_load_rsp_rip() */
279 unsigned long rip; /* needs vcpu_load_rsp_rip() */
280
281 unsigned long cr0;
282 unsigned long cr2;
283 unsigned long cr3;
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284 gpa_t para_state_gpa;
285 struct page *para_state_page;
286 gpa_t hypercall_gpa;
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287 unsigned long cr4;
288 unsigned long cr8;
1342d353 289 u64 pdptrs[4]; /* pae */
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290 u64 shadow_efer;
291 u64 apic_base;
6f00e68f 292 u64 ia32_misc_enable_msr;
6aa8b732 293 int nmsrs;
a75beee6 294 int save_nmsrs;
2cc51560 295 int msr_offset_efer;
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296#ifdef CONFIG_X86_64
297 int msr_offset_kernel_gs_base;
298#endif
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299 struct vmx_msr_entry *guest_msrs;
300 struct vmx_msr_entry *host_msrs;
301
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302 struct kvm_mmu mmu;
303
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304 struct kvm_mmu_memory_cache mmu_pte_chain_cache;
305 struct kvm_mmu_memory_cache mmu_rmap_desc_cache;
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306 struct kvm_mmu_memory_cache mmu_page_cache;
307 struct kvm_mmu_memory_cache mmu_page_header_cache;
714b93da 308
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309 gfn_t last_pt_write_gfn;
310 int last_pt_write_count;
311
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312 struct kvm_guest_debug guest_debug;
313
314 char fx_buf[FX_BUF_SIZE];
315 char *host_fx_image;
316 char *guest_fx_image;
7807fa6c 317 int fpu_active;
7702fd1f 318 int guest_fpu_loaded;
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319 struct vmx_host_state {
320 int loaded;
321 u16 fs_sel, gs_sel, ldt_sel;
322 int fs_gs_ldt_reload_needed;
323 } vmx_host_state;
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324
325 int mmio_needed;
326 int mmio_read_completed;
327 int mmio_is_write;
328 int mmio_size;
329 unsigned char mmio_data[8];
330 gpa_t mmio_phys_addr;
e7df56e4 331 gva_t mmio_fault_cr2;
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332 struct kvm_pio_request pio;
333 void *pio_data;
6aa8b732 334
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335 int sigset_active;
336 sigset_t sigset;
337
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338 struct kvm_stat stat;
339
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340 struct {
341 int active;
342 u8 save_iopl;
343 struct kvm_save_segment {
344 u16 selector;
345 unsigned long base;
346 u32 limit;
347 u32 ar;
348 } tr, es, ds, fs, gs;
349 } rmode;
72d6e5a0 350 int halt_request; /* real mode on Intel only */
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351
352 int cpuid_nent;
353 struct kvm_cpuid_entry cpuid_entries[KVM_MAX_CPUID_ENTRIES];
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354};
355
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356struct kvm_mem_alias {
357 gfn_t base_gfn;
358 unsigned long npages;
359 gfn_t target_gfn;
360};
361
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362struct kvm_memory_slot {
363 gfn_t base_gfn;
364 unsigned long npages;
365 unsigned long flags;
366 struct page **phys_mem;
367 unsigned long *dirty_bitmap;
368};
369
370struct kvm {
371 spinlock_t lock; /* protects everything except vcpus */
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372 int naliases;
373 struct kvm_mem_alias aliases[KVM_ALIAS_SLOTS];
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374 int nmemslots;
375 struct kvm_memory_slot memslots[KVM_MEMORY_SLOTS];
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376 /*
377 * Hash table of struct kvm_mmu_page.
378 */
6aa8b732 379 struct list_head active_mmu_pages;
ebeace86 380 int n_free_mmu_pages;
cea0f0e7 381 struct hlist_head mmu_page_hash[KVM_NUM_MMU_PAGES];
39c3b86e 382 int nvcpus;
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383 struct kvm_vcpu vcpus[KVM_MAX_VCPUS];
384 int memory_config_version;
385 int busy;
cd4a4e53 386 unsigned long rmap_overflow;
133de902 387 struct list_head vm_list;
bccf2150 388 struct file *filp;
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389};
390
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391struct descriptor_table {
392 u16 limit;
393 unsigned long base;
394} __attribute__((packed));
395
396struct kvm_arch_ops {
397 int (*cpu_has_kvm_support)(void); /* __init */
398 int (*disabled_by_bios)(void); /* __init */
399 void (*hardware_enable)(void *dummy); /* __init */
400 void (*hardware_disable)(void *dummy);
401 int (*hardware_setup)(void); /* __init */
402 void (*hardware_unsetup)(void); /* __exit */
403
404 int (*vcpu_create)(struct kvm_vcpu *vcpu);
405 void (*vcpu_free)(struct kvm_vcpu *vcpu);
406
bccf2150 407 void (*vcpu_load)(struct kvm_vcpu *vcpu);
6aa8b732 408 void (*vcpu_put)(struct kvm_vcpu *vcpu);
774c47f1 409 void (*vcpu_decache)(struct kvm_vcpu *vcpu);
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410
411 int (*set_guest_debug)(struct kvm_vcpu *vcpu,
412 struct kvm_debug_guest *dbg);
413 int (*get_msr)(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata);
414 int (*set_msr)(struct kvm_vcpu *vcpu, u32 msr_index, u64 data);
415 u64 (*get_segment_base)(struct kvm_vcpu *vcpu, int seg);
416 void (*get_segment)(struct kvm_vcpu *vcpu,
417 struct kvm_segment *var, int seg);
418 void (*set_segment)(struct kvm_vcpu *vcpu,
419 struct kvm_segment *var, int seg);
6aa8b732 420 void (*get_cs_db_l_bits)(struct kvm_vcpu *vcpu, int *db, int *l);
25c4c276 421 void (*decache_cr4_guest_bits)(struct kvm_vcpu *vcpu);
6aa8b732 422 void (*set_cr0)(struct kvm_vcpu *vcpu, unsigned long cr0);
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423 void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3);
424 void (*set_cr4)(struct kvm_vcpu *vcpu, unsigned long cr4);
425 void (*set_efer)(struct kvm_vcpu *vcpu, u64 efer);
426 void (*get_idt)(struct kvm_vcpu *vcpu, struct descriptor_table *dt);
427 void (*set_idt)(struct kvm_vcpu *vcpu, struct descriptor_table *dt);
428 void (*get_gdt)(struct kvm_vcpu *vcpu, struct descriptor_table *dt);
429 void (*set_gdt)(struct kvm_vcpu *vcpu, struct descriptor_table *dt);
430 unsigned long (*get_dr)(struct kvm_vcpu *vcpu, int dr);
431 void (*set_dr)(struct kvm_vcpu *vcpu, int dr, unsigned long value,
432 int *exception);
433 void (*cache_regs)(struct kvm_vcpu *vcpu);
434 void (*decache_regs)(struct kvm_vcpu *vcpu);
435 unsigned long (*get_rflags)(struct kvm_vcpu *vcpu);
436 void (*set_rflags)(struct kvm_vcpu *vcpu, unsigned long rflags);
437
438 void (*invlpg)(struct kvm_vcpu *vcpu, gva_t addr);
439 void (*tlb_flush)(struct kvm_vcpu *vcpu);
440 void (*inject_page_fault)(struct kvm_vcpu *vcpu,
441 unsigned long addr, u32 err_code);
442
443 void (*inject_gp)(struct kvm_vcpu *vcpu, unsigned err_code);
444
445 int (*run)(struct kvm_vcpu *vcpu, struct kvm_run *run);
446 int (*vcpu_setup)(struct kvm_vcpu *vcpu);
447 void (*skip_emulated_instruction)(struct kvm_vcpu *vcpu);
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448 void (*patch_hypercall)(struct kvm_vcpu *vcpu,
449 unsigned char *hypercall_addr);
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450};
451
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452extern struct kvm_arch_ops *kvm_arch_ops;
453
454#define kvm_printf(kvm, fmt ...) printk(KERN_DEBUG fmt)
455#define vcpu_printf(vcpu, fmt...) kvm_printf(vcpu->kvm, fmt)
456
457int kvm_init_arch(struct kvm_arch_ops *ops, struct module *module);
458void kvm_exit_arch(void);
459
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460int kvm_mmu_module_init(void);
461void kvm_mmu_module_exit(void);
462
6aa8b732 463void kvm_mmu_destroy(struct kvm_vcpu *vcpu);
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464int kvm_mmu_create(struct kvm_vcpu *vcpu);
465int kvm_mmu_setup(struct kvm_vcpu *vcpu);
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466
467int kvm_mmu_reset_context(struct kvm_vcpu *vcpu);
714b93da 468void kvm_mmu_slot_remove_write_access(struct kvm_vcpu *vcpu, int slot);
e0fa826f 469void kvm_mmu_zap_all(struct kvm_vcpu *vcpu);
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470
471hpa_t gpa_to_hpa(struct kvm_vcpu *vcpu, gpa_t gpa);
472#define HPA_MSB ((sizeof(hpa_t) * 8) - 1)
473#define HPA_ERR_MASK ((hpa_t)1 << HPA_MSB)
474static inline int is_error_hpa(hpa_t hpa) { return hpa >> HPA_MSB; }
475hpa_t gva_to_hpa(struct kvm_vcpu *vcpu, gva_t gva);
039576c0 476struct page *gva_to_page(struct kvm_vcpu *vcpu, gva_t gva);
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477
478void kvm_emulator_want_group7_invlpg(void);
479
480extern hpa_t bad_page_address;
481
954bbbc2 482struct page *gfn_to_page(struct kvm *kvm, gfn_t gfn);
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483struct kvm_memory_slot *gfn_to_memslot(struct kvm *kvm, gfn_t gfn);
484void mark_page_dirty(struct kvm *kvm, gfn_t gfn);
485
486enum emulation_result {
487 EMULATE_DONE, /* no further processing */
488 EMULATE_DO_MMIO, /* kvm_run filled with mmio request */
489 EMULATE_FAIL, /* can't emulate this instruction */
490};
491
492int emulate_instruction(struct kvm_vcpu *vcpu, struct kvm_run *run,
493 unsigned long cr2, u16 error_code);
494void realmode_lgdt(struct kvm_vcpu *vcpu, u16 size, unsigned long address);
495void realmode_lidt(struct kvm_vcpu *vcpu, u16 size, unsigned long address);
496void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
497 unsigned long *rflags);
498
499unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr);
500void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long value,
501 unsigned long *rflags);
502
503struct x86_emulate_ctxt;
504
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505int kvm_setup_pio(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
506 int size, unsigned long count, int string, int down,
507 gva_t address, int rep, unsigned port);
06465c5a 508void kvm_emulate_cpuid(struct kvm_vcpu *vcpu);
d3bef15f 509int kvm_emulate_halt(struct kvm_vcpu *vcpu);
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510int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address);
511int emulate_clts(struct kvm_vcpu *vcpu);
512int emulator_get_dr(struct x86_emulate_ctxt* ctxt, int dr,
513 unsigned long *dest);
514int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
515 unsigned long value);
516
517void set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
518void set_cr3(struct kvm_vcpu *vcpu, unsigned long cr0);
519void set_cr4(struct kvm_vcpu *vcpu, unsigned long cr0);
520void set_cr8(struct kvm_vcpu *vcpu, unsigned long cr0);
521void lmsw(struct kvm_vcpu *vcpu, unsigned long msw);
522
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523int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata);
524int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data);
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525
526void fx_init(struct kvm_vcpu *vcpu);
527
528void load_msrs(struct vmx_msr_entry *e, int n);
529void save_msrs(struct vmx_msr_entry *e, int n);
530void kvm_resched(struct kvm_vcpu *vcpu);
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531void kvm_load_guest_fpu(struct kvm_vcpu *vcpu);
532void kvm_put_guest_fpu(struct kvm_vcpu *vcpu);
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533
534int kvm_read_guest(struct kvm_vcpu *vcpu,
535 gva_t addr,
536 unsigned long size,
537 void *dest);
538
539int kvm_write_guest(struct kvm_vcpu *vcpu,
540 gva_t addr,
541 unsigned long size,
542 void *data);
543
544unsigned long segment_base(u16 selector);
545
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546void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
547 const u8 *old, const u8 *new, int bytes);
a436036b 548int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva);
ebeace86 549void kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu);
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550int kvm_mmu_load(struct kvm_vcpu *vcpu);
551void kvm_mmu_unload(struct kvm_vcpu *vcpu);
ebeace86 552
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553int kvm_hypercall(struct kvm_vcpu *vcpu, struct kvm_run *run);
554
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555static inline int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
556 u32 error_code)
557{
558 if (unlikely(vcpu->kvm->n_free_mmu_pages < KVM_MIN_FREE_MMU_PAGES))
559 kvm_mmu_free_some_pages(vcpu);
560 return vcpu->mmu.page_fault(vcpu, gva, error_code);
561}
da4a00f0 562
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563static inline int kvm_mmu_reload(struct kvm_vcpu *vcpu)
564{
565 if (likely(vcpu->mmu.root_hpa != INVALID_PAGE))
566 return 0;
567
568 return kvm_mmu_load(vcpu);
569}
570
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571static inline int is_long_mode(struct kvm_vcpu *vcpu)
572{
573#ifdef CONFIG_X86_64
574 return vcpu->shadow_efer & EFER_LME;
575#else
576 return 0;
577#endif
578}
579
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580static inline int is_pae(struct kvm_vcpu *vcpu)
581{
582 return vcpu->cr4 & CR4_PAE_MASK;
583}
584
585static inline int is_pse(struct kvm_vcpu *vcpu)
586{
587 return vcpu->cr4 & CR4_PSE_MASK;
588}
589
590static inline int is_paging(struct kvm_vcpu *vcpu)
591{
592 return vcpu->cr0 & CR0_PG_MASK;
593}
594
595static inline int memslot_id(struct kvm *kvm, struct kvm_memory_slot *slot)
596{
597 return slot - kvm->memslots;
598}
599
600static inline struct kvm_mmu_page *page_header(hpa_t shadow_page)
601{
602 struct page *page = pfn_to_page(shadow_page >> PAGE_SHIFT);
603
5972e953 604 return (struct kvm_mmu_page *)page_private(page);
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605}
606
607static inline u16 read_fs(void)
608{
609 u16 seg;
610 asm ("mov %%fs, %0" : "=g"(seg));
611 return seg;
612}
613
614static inline u16 read_gs(void)
615{
616 u16 seg;
617 asm ("mov %%gs, %0" : "=g"(seg));
618 return seg;
619}
620
621static inline u16 read_ldt(void)
622{
623 u16 ldt;
624 asm ("sldt %0" : "=g"(ldt));
625 return ldt;
626}
627
628static inline void load_fs(u16 sel)
629{
630 asm ("mov %0, %%fs" : : "rm"(sel));
631}
632
633static inline void load_gs(u16 sel)
634{
635 asm ("mov %0, %%gs" : : "rm"(sel));
636}
637
638#ifndef load_ldt
639static inline void load_ldt(u16 sel)
640{
a0610ddf 641 asm ("lldt %0" : : "rm"(sel));
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642}
643#endif
644
645static inline void get_idt(struct descriptor_table *table)
646{
647 asm ("sidt %0" : "=m"(*table));
648}
649
650static inline void get_gdt(struct descriptor_table *table)
651{
652 asm ("sgdt %0" : "=m"(*table));
653}
654
655static inline unsigned long read_tr_base(void)
656{
657 u16 tr;
658 asm ("str %0" : "=g"(tr));
659 return segment_base(tr);
660}
661
05b3e0c2 662#ifdef CONFIG_X86_64
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663static inline unsigned long read_msr(unsigned long msr)
664{
665 u64 value;
666
667 rdmsrl(msr, value);
668 return value;
669}
670#endif
671
672static inline void fx_save(void *image)
673{
674 asm ("fxsave (%0)":: "r" (image));
675}
676
677static inline void fx_restore(void *image)
678{
679 asm ("fxrstor (%0)":: "r" (image));
680}
681
682static inline void fpu_init(void)
683{
684 asm ("finit");
685}
686
687static inline u32 get_rdx_init_val(void)
688{
689 return 0x600; /* P6 family */
690}
691
692#define ASM_VMX_VMCLEAR_RAX ".byte 0x66, 0x0f, 0xc7, 0x30"
693#define ASM_VMX_VMLAUNCH ".byte 0x0f, 0x01, 0xc2"
694#define ASM_VMX_VMRESUME ".byte 0x0f, 0x01, 0xc3"
695#define ASM_VMX_VMPTRLD_RAX ".byte 0x0f, 0xc7, 0x30"
696#define ASM_VMX_VMREAD_RDX_RAX ".byte 0x0f, 0x78, 0xd0"
697#define ASM_VMX_VMWRITE_RAX_RDX ".byte 0x0f, 0x79, 0xd0"
698#define ASM_VMX_VMWRITE_RSP_RDX ".byte 0x0f, 0x79, 0xd4"
699#define ASM_VMX_VMXOFF ".byte 0x0f, 0x01, 0xc4"
700#define ASM_VMX_VMXON_RAX ".byte 0xf3, 0x0f, 0xc7, 0x30"
701
702#define MSR_IA32_TIME_STAMP_COUNTER 0x010
703
704#define TSS_IOPB_BASE_OFFSET 0x66
705#define TSS_BASE_SIZE 0x68
706#define TSS_IOPB_SIZE (65536 / 8)
707#define TSS_REDIRECTION_SIZE (256 / 8)
708#define RMODE_TSS_SIZE (TSS_BASE_SIZE + TSS_REDIRECTION_SIZE + TSS_IOPB_SIZE + 1)
709
6aa8b732 710#endif