projects / GitHub / LineageOS / android_kernel_motorola_exynos9610.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | /* $Id: jade.h,v 1.5.2.3 2004/01/14 16:04:48 keil Exp $ |
| 2 | * | |
| 3 | * JADE specific defines | |
| 4 | * | |
| 5 | * Author Roland Klabunde | |
| 6 | * Copyright by Roland Klabunde <R.Klabunde@Berkom.de> | |
| 475be4d8 | 7 | * |
| 1da177e4 LT |
8 | * This software may be used and distributed according to the terms |
| 9 | * of the GNU General Public License, incorporated herein by reference. | |
| 10 | * | |
| 11 | */ | |
| 12 | ||
| 13 | /* All Registers original Siemens Spec */ | |
| 14 | #ifndef __JADE_H__ | |
| 15 | #define __JADE_H__ | |
| 16 | ||
| 17 | /* Special registers for access to indirect accessible JADE regs */ | |
| 18 | #define DIRECT_IO_JADE 0x0000 /* Jade direct io access area */ | |
| 475be4d8 | 19 | #define COMM_JADE 0x0040 /* Jade communication area */ |
| 1da177e4 LT |
20 | |
| 21 | /********************************************************************/ | |
| 475be4d8 | 22 | /* JADE-HDLC registers */ |
| 1da177e4 | 23 | /********************************************************************/ |
| 475be4d8 JP |
24 | #define jade_HDLC_RFIFO 0x00 /* R */ |
| 25 | #define jade_HDLC_XFIFO 0x00 /* W */ | |
| 26 | ||
| 27 | #define jade_HDLC_STAR 0x20 /* R */ | |
| 28 | #define jadeSTAR_XDOV 0x80 | |
| 29 | #define jadeSTAR_XFW 0x40 /* Does not work*/ | |
| 30 | #define jadeSTAR_XCEC 0x20 | |
| 31 | #define jadeSTAR_RCEC 0x10 | |
| 32 | #define jadeSTAR_BSY 0x08 | |
| 33 | #define jadeSTAR_RNA 0x04 | |
| 34 | #define jadeSTAR_STR 0x02 | |
| 35 | #define jadeSTAR_STX 0x01 | |
| 36 | ||
| 37 | #define jade_HDLC_XCMD 0x20 /* W */ | |
| 38 | #define jadeXCMD_XF 0x80 | |
| 39 | #define jadeXCMD_XME 0x40 | |
| 40 | #define jadeXCMD_XRES 0x20 | |
| 41 | #define jadeXCMD_STX 0x01 | |
| 42 | ||
| 43 | #define jade_HDLC_RSTA 0x21 /* R */ | |
| 44 | #define jadeRSTA_VFR 0x80 | |
| 45 | #define jadeRSTA_RDO 0x40 | |
| 46 | #define jadeRSTA_CRC 0x20 | |
| 47 | #define jadeRSTA_RAB 0x10 | |
| 48 | #define jadeRSTA_MASK 0xF0 | |
| 1da177e4 LT |
49 | |
| 50 | #define jade_HDLC_MODE 0x22 /* RW*/ | |
| 475be4d8 JP |
51 | #define jadeMODE_TMO 0x80 |
| 52 | #define jadeMODE_RAC 0x40 | |
| 53 | #define jadeMODE_XAC 0x20 | |
| 54 | #define jadeMODE_TLP 0x10 | |
| 55 | #define jadeMODE_ERFS 0x02 | |
| 56 | #define jadeMODE_ETFS 0x01 | |
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57 | |
| 58 | #define jade_HDLC_RBCH 0x24 /* R */ | |
| 59 | ||
| 475be4d8 JP |
60 | #define jade_HDLC_RBCL 0x25 /* R */ |
| 61 | #define jade_HDLC_RCMD 0x25 /* W */ | |
| 62 | #define jadeRCMD_RMC 0x80 | |
| 63 | #define jadeRCMD_RRES 0x40 | |
| 64 | #define jadeRCMD_RMD 0x20 | |
| 65 | #define jadeRCMD_STR 0x02 | |
| 1da177e4 LT |
66 | |
| 67 | #define jade_HDLC_CCR0 0x26 /* RW*/ | |
| 475be4d8 JP |
68 | #define jadeCCR0_PU 0x80 |
| 69 | #define jadeCCR0_ITF 0x40 | |
| 70 | #define jadeCCR0_C32 0x20 | |
| 71 | #define jadeCCR0_CRL 0x10 | |
| 72 | #define jadeCCR0_RCRC 0x08 | |
| 73 | #define jadeCCR0_XCRC 0x04 | |
| 74 | #define jadeCCR0_RMSB 0x02 | |
| 75 | #define jadeCCR0_XMSB 0x01 | |
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76 | |
| 77 | #define jade_HDLC_CCR1 0x27 /* RW*/ | |
| 475be4d8 JP |
78 | #define jadeCCR1_RCS0 0x80 |
| 79 | #define jadeCCR1_RCONT 0x40 | |
| 80 | #define jadeCCR1_RFDIS 0x20 | |
| 81 | #define jadeCCR1_XCS0 0x10 | |
| 82 | #define jadeCCR1_XCONT 0x08 | |
| 83 | #define jadeCCR1_XFDIS 0x04 | |
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84 | |
| 85 | #define jade_HDLC_TSAR 0x28 /* RW*/ | |
| 86 | #define jade_HDLC_TSAX 0x29 /* RW*/ | |
| 87 | #define jade_HDLC_RCCR 0x2A /* RW*/ | |
| 88 | #define jade_HDLC_XCCR 0x2B /* RW*/ | |
| 89 | ||
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90 | #define jade_HDLC_ISR 0x2C /* R */ |
| 91 | #define jade_HDLC_IMR 0x2C /* W */ | |
| 92 | #define jadeISR_RME 0x80 | |
| 93 | #define jadeISR_RPF 0x40 | |
| 94 | #define jadeISR_RFO 0x20 | |
| 95 | #define jadeISR_XPR 0x10 | |
| 96 | #define jadeISR_XDU 0x08 | |
| 97 | #define jadeISR_ALLS 0x04 | |
| 98 | ||
| 99 | #define jade_INT 0x75 | |
| 100 | #define jadeINT_HDLC1 0x02 | |
| 101 | #define jadeINT_HDLC2 0x01 | |
| 102 | #define jadeINT_DSP 0x04 | |
| 103 | #define jade_INTR 0x70 | |
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104 | |
| 105 | /********************************************************************/ | |
| 475be4d8 | 106 | /* Indirect accessible JADE registers of common interest */ |
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107 | /********************************************************************/ |
| 108 | #define jade_CHIPVERSIONNR 0x00 /* Does not work*/ | |
| 109 | ||
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110 | #define jade_HDLCCNTRACCESS 0x10 |
| 111 | #define jadeINDIRECT_HAH1 0x02 | |
| 112 | #define jadeINDIRECT_HAH2 0x01 | |
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113 | |
| 114 | #define jade_HDLC1SERRXPATH 0x1D | |
| 115 | #define jade_HDLC1SERTXPATH 0x1E | |
| 116 | #define jade_HDLC2SERRXPATH 0x1F | |
| 117 | #define jade_HDLC2SERTXPATH 0x20 | |
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118 | #define jadeINDIRECT_SLIN1 0x10 |
| 119 | #define jadeINDIRECT_SLIN0 0x08 | |
| 120 | #define jadeINDIRECT_LMOD1 0x04 | |
| 121 | #define jadeINDIRECT_LMOD0 0x02 | |
| 122 | #define jadeINDIRECT_HHR 0x01 | |
| 123 | #define jadeINDIRECT_HHX 0x01 | |
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124 | |
| 125 | #define jade_RXAUDIOCH1CFG 0x11 | |
| 126 | #define jade_RXAUDIOCH2CFG 0x14 | |
| 127 | #define jade_TXAUDIOCH1CFG 0x17 | |
| 128 | #define jade_TXAUDIOCH2CFG 0x1A | |
| 129 | ||
| 130 | extern int JadeVersion(struct IsdnCardState *cs, char *s); | |
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131 | extern void clear_pending_jade_ints(struct IsdnCardState *cs); |
| 132 | extern void initjade(struct IsdnCardState *cs); | |
| 133 | ||
| 134 | #endif /* __JADE_H__ */ |