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genirq: procfs: Make smp_affinity values go+r
[GitHub/moto-9609/android_kernel_motorola_exynos9610.git] / drivers / irqchip / irq-sun4i.c
CommitLineData
d7fbc6ca
MR		 1/*
2 * Allwinner A1X SoCs IRQ chip driver.
3 *
4 * Copyright (C) 2012 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * Based on code from
9 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
10 * Benn Huang <benn@allwinnertech.com>
11 *
12 * This file is licensed under the terms of the GNU General Public
13 * License version 2. This program is licensed "as is" without any
14 * warranty of any kind, whether express or implied.
15 */
16
17#include <linux/io.h>
18#include <linux/irq.h>
19#include <linux/of.h>
20#include <linux/of_address.h>
21#include <linux/of_irq.h>
22
23#include <asm/exception.h>
24#include <asm/mach/irq.h>
25
26#include "irqchip.h"
27
28#define SUN4I_IRQ_VECTOR_REG 0x00
29#define SUN4I_IRQ_PROTECTION_REG 0x08
30#define SUN4I_IRQ_NMI_CTRL_REG 0x0c
31#define SUN4I_IRQ_PENDING_REG(x) (0x10 + 0x4 * x)
32#define SUN4I_IRQ_FIQ_PENDING_REG(x) (0x20 + 0x4 * x)
33#define SUN4I_IRQ_ENABLE_REG(x) (0x40 + 0x4 * x)
34#define SUN4I_IRQ_MASK_REG(x) (0x50 + 0x4 * x)
35
36static void __iomem *sun4i_irq_base;
37static struct irq_domain *sun4i_irq_domain;
38
8783dd3a 39static void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs);
d7fbc6ca 40
baaecfa7 41static void sun4i_irq_ack(struct irq_data *irqd)
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MR		 42{
43 unsigned int irq = irqd_to_hwirq(irqd);
44 unsigned int irq_off = irq % 32;
45 int reg = irq / 32;
46 u32 val;
47
48 val = readl(sun4i_irq_base + SUN4I_IRQ_PENDING_REG(reg));
49 writel(val | (1 << irq_off),
50 sun4i_irq_base + SUN4I_IRQ_PENDING_REG(reg));
51}
52
53static void sun4i_irq_mask(struct irq_data *irqd)
54{
55 unsigned int irq = irqd_to_hwirq(irqd);
56 unsigned int irq_off = irq % 32;
57 int reg = irq / 32;
58 u32 val;
59
60 val = readl(sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
61 writel(val & ~(1 << irq_off),
62 sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
63}
64
65static void sun4i_irq_unmask(struct irq_data *irqd)
66{
67 unsigned int irq = irqd_to_hwirq(irqd);
68 unsigned int irq_off = irq % 32;
69 int reg = irq / 32;
70 u32 val;
71
72 val = readl(sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
73 writel(val | (1 << irq_off),
74 sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
75}
76
77static struct irq_chip sun4i_irq_chip = {
78 .name = "sun4i_irq",
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MR		 79 .irq_mask = sun4i_irq_mask,
80 .irq_unmask = sun4i_irq_unmask,
81};
82
e9df9e22
HG		 83/* IRQ 0 / the ENMI needs a late eoi call */
84static struct irq_chip sun4i_irq_chip_enmi = {
85 .name = "sun4i_irq",
86 .irq_eoi = sun4i_irq_ack,
87 .irq_mask = sun4i_irq_mask,
88 .irq_unmask = sun4i_irq_unmask,
89 .flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED,
90};
91
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MR		 92static int sun4i_irq_map(struct irq_domain *d, unsigned int virq,
93 irq_hw_number_t hw)
94{
e9df9e22
HG		 95 if (hw == 0)
96 irq_set_chip_and_handler(virq, &sun4i_irq_chip_enmi,
97 handle_fasteoi_irq);
98 else
99 irq_set_chip_and_handler(virq, &sun4i_irq_chip,
100 handle_level_irq);
101
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MR		 102 set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
103
104 return 0;
105}
106
107static struct irq_domain_ops sun4i_irq_ops = {
108 .map = sun4i_irq_map,
109 .xlate = irq_domain_xlate_onecell,
110};
111
112static int __init sun4i_of_init(struct device_node *node,
113 struct device_node *parent)
114{
115 sun4i_irq_base = of_iomap(node, 0);
116 if (!sun4i_irq_base)
117 panic("%s: unable to map IC registers\n",
118 node->full_name);
119
120 /* Disable all interrupts */
121 writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(0));
122 writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(1));
123 writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(2));
124
649ff46e 125 /* Unmask all the interrupts, ENABLE_REG(x) is used for masking */
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MR		 126 writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(0));
127 writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(1));
128 writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(2));
129
130 /* Clear all the pending interrupts */
131 writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0));
132 writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(1));
133 writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(2));
134
135 /* Enable protection mode */
136 writel(0x01, sun4i_irq_base + SUN4I_IRQ_PROTECTION_REG);
137
138 /* Configure the external interrupt source type */
139 writel(0x00, sun4i_irq_base + SUN4I_IRQ_NMI_CTRL_REG);
140
141 sun4i_irq_domain = irq_domain_add_linear(node, 3 * 32,
142 &sun4i_irq_ops, NULL);
143 if (!sun4i_irq_domain)
144 panic("%s: unable to create IRQ domain\n", node->full_name);
145
146 set_handle_irq(sun4i_handle_irq);
147
148 return 0;
149}
a7e8b4b5 150IRQCHIP_DECLARE(allwinner_sun4i_ic, "allwinner,sun4i-a10-ic", sun4i_of_init);
d7fbc6ca 151
8783dd3a 152static void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs)
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MR		 153{
154 u32 irq, hwirq;
155
56af0416
HG		 156 /*
157 * hwirq == 0 can mean one of 3 things:
158 * 1) no more irqs pending
159 * 2) irq 0 pending
160 * 3) spurious irq
161 * So if we immediately get a reading of 0, check the irq-pending reg
162 * to differentiate between 2 and 3. We only do this once to avoid
163 * the extra check in the common case of 1 hapening after having
164 * read the vector-reg once.
165 */
d7fbc6ca 166 hwirq = readl(sun4i_irq_base + SUN4I_IRQ_VECTOR_REG) >> 2;
56af0416
HG		 167 if (hwirq == 0 &&
168 !(readl(sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0)) & BIT(0)))
169 return;
170
171 do {
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MR		 172 irq = irq_find_mapping(sun4i_irq_domain, hwirq);
173 handle_IRQ(irq, regs);
174 hwirq = readl(sun4i_irq_base + SUN4I_IRQ_VECTOR_REG) >> 2;
56af0416 175 } while (hwirq != 0);
d7fbc6ca 176}