Commit | Line | Data |
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2299c49d SH |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org) | |
7 | * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. | |
8 | */ | |
39b8d525 | 9 | #include <linux/bitmap.h> |
fb8f7be1 | 10 | #include <linux/clocksource.h> |
39b8d525 | 11 | #include <linux/init.h> |
18743d27 | 12 | #include <linux/interrupt.h> |
fb8f7be1 | 13 | #include <linux/irq.h> |
4060bbe9 | 14 | #include <linux/irqchip/mips-gic.h> |
18743d27 | 15 | #include <linux/sched.h> |
631330f5 | 16 | #include <linux/smp.h> |
39b8d525 | 17 | |
98b67c37 SH |
18 | #include <asm/setup.h> |
19 | #include <asm/traps.h> | |
39b8d525 | 20 | |
28ea2151 | 21 | unsigned int gic_frequency; |
ff86714f | 22 | unsigned int gic_present; |
98b67c37 | 23 | |
822350bc | 24 | struct gic_pcpu_mask { |
fbd55241 | 25 | DECLARE_BITMAP(pcpu_mask, GIC_MAX_INTRS); |
822350bc JD |
26 | }; |
27 | ||
28 | struct gic_pending_regs { | |
fbd55241 | 29 | DECLARE_BITMAP(pending, GIC_MAX_INTRS); |
822350bc JD |
30 | }; |
31 | ||
32 | struct gic_intrmask_regs { | |
fbd55241 | 33 | DECLARE_BITMAP(intrmask, GIC_MAX_INTRS); |
822350bc JD |
34 | }; |
35 | ||
5f68fea0 | 36 | static void __iomem *gic_base; |
0b271f56 | 37 | static struct gic_pcpu_mask pcpu_masks[NR_CPUS]; |
39b8d525 RB |
38 | static struct gic_pending_regs pending_regs[NR_CPUS]; |
39 | static struct gic_intrmask_regs intrmask_regs[NR_CPUS]; | |
95150ae8 | 40 | static DEFINE_SPINLOCK(gic_lock); |
c49581a4 | 41 | static struct irq_domain *gic_irq_domain; |
fbd55241 | 42 | static int gic_shared_intrs; |
e9de688d | 43 | static int gic_vpes; |
3263d085 | 44 | static unsigned int gic_cpu_pin; |
4a6a3ea3 | 45 | static struct irq_chip gic_level_irq_controller, gic_edge_irq_controller; |
39b8d525 | 46 | |
18743d27 AB |
47 | static void __gic_irq_dispatch(void); |
48 | ||
5f68fea0 AB |
49 | static inline unsigned int gic_read(unsigned int reg) |
50 | { | |
51 | return __raw_readl(gic_base + reg); | |
52 | } | |
53 | ||
54 | static inline void gic_write(unsigned int reg, unsigned int val) | |
55 | { | |
56 | __raw_writel(val, gic_base + reg); | |
57 | } | |
58 | ||
59 | static inline void gic_update_bits(unsigned int reg, unsigned int mask, | |
60 | unsigned int val) | |
61 | { | |
62 | unsigned int regval; | |
63 | ||
64 | regval = gic_read(reg); | |
65 | regval &= ~mask; | |
66 | regval |= val; | |
67 | gic_write(reg, regval); | |
68 | } | |
69 | ||
70 | static inline void gic_reset_mask(unsigned int intr) | |
71 | { | |
72 | gic_write(GIC_REG(SHARED, GIC_SH_RMASK) + GIC_INTR_OFS(intr), | |
73 | 1 << GIC_INTR_BIT(intr)); | |
74 | } | |
75 | ||
76 | static inline void gic_set_mask(unsigned int intr) | |
77 | { | |
78 | gic_write(GIC_REG(SHARED, GIC_SH_SMASK) + GIC_INTR_OFS(intr), | |
79 | 1 << GIC_INTR_BIT(intr)); | |
80 | } | |
81 | ||
82 | static inline void gic_set_polarity(unsigned int intr, unsigned int pol) | |
83 | { | |
84 | gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_POLARITY) + | |
85 | GIC_INTR_OFS(intr), 1 << GIC_INTR_BIT(intr), | |
86 | pol << GIC_INTR_BIT(intr)); | |
87 | } | |
88 | ||
89 | static inline void gic_set_trigger(unsigned int intr, unsigned int trig) | |
90 | { | |
91 | gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_TRIGGER) + | |
92 | GIC_INTR_OFS(intr), 1 << GIC_INTR_BIT(intr), | |
93 | trig << GIC_INTR_BIT(intr)); | |
94 | } | |
95 | ||
96 | static inline void gic_set_dual_edge(unsigned int intr, unsigned int dual) | |
97 | { | |
98 | gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_DUAL) + GIC_INTR_OFS(intr), | |
99 | 1 << GIC_INTR_BIT(intr), | |
100 | dual << GIC_INTR_BIT(intr)); | |
101 | } | |
102 | ||
103 | static inline void gic_map_to_pin(unsigned int intr, unsigned int pin) | |
104 | { | |
105 | gic_write(GIC_REG(SHARED, GIC_SH_INTR_MAP_TO_PIN_BASE) + | |
106 | GIC_SH_MAP_TO_PIN(intr), GIC_MAP_TO_PIN_MSK | pin); | |
107 | } | |
108 | ||
109 | static inline void gic_map_to_vpe(unsigned int intr, unsigned int vpe) | |
110 | { | |
111 | gic_write(GIC_REG(SHARED, GIC_SH_INTR_MAP_TO_VPE_BASE) + | |
112 | GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe), | |
113 | GIC_SH_MAP_TO_VPE_REG_BIT(vpe)); | |
114 | } | |
115 | ||
0ab2b7d0 | 116 | #if defined(CONFIG_CSRC_GIC) || defined(CONFIG_CEVT_GIC) |
dfa762e1 SH |
117 | cycle_t gic_read_count(void) |
118 | { | |
119 | unsigned int hi, hi2, lo; | |
120 | ||
121 | do { | |
5f68fea0 AB |
122 | hi = gic_read(GIC_REG(SHARED, GIC_SH_COUNTER_63_32)); |
123 | lo = gic_read(GIC_REG(SHARED, GIC_SH_COUNTER_31_00)); | |
124 | hi2 = gic_read(GIC_REG(SHARED, GIC_SH_COUNTER_63_32)); | |
dfa762e1 SH |
125 | } while (hi2 != hi); |
126 | ||
127 | return (((cycle_t) hi) << 32) + lo; | |
128 | } | |
0ab2b7d0 | 129 | |
387904ff AB |
130 | unsigned int gic_get_count_width(void) |
131 | { | |
132 | unsigned int bits, config; | |
133 | ||
5f68fea0 | 134 | config = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG)); |
387904ff AB |
135 | bits = 32 + 4 * ((config & GIC_SH_CONFIG_COUNTBITS_MSK) >> |
136 | GIC_SH_CONFIG_COUNTBITS_SHF); | |
137 | ||
138 | return bits; | |
139 | } | |
140 | ||
0ab2b7d0 RG |
141 | void gic_write_compare(cycle_t cnt) |
142 | { | |
5f68fea0 | 143 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI), |
0ab2b7d0 | 144 | (int)(cnt >> 32)); |
5f68fea0 | 145 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO), |
0ab2b7d0 RG |
146 | (int)(cnt & 0xffffffff)); |
147 | } | |
148 | ||
414408d0 PB |
149 | void gic_write_cpu_compare(cycle_t cnt, int cpu) |
150 | { | |
151 | unsigned long flags; | |
152 | ||
153 | local_irq_save(flags); | |
154 | ||
5f68fea0 AB |
155 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), cpu); |
156 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_HI), | |
414408d0 | 157 | (int)(cnt >> 32)); |
5f68fea0 | 158 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_LO), |
414408d0 PB |
159 | (int)(cnt & 0xffffffff)); |
160 | ||
161 | local_irq_restore(flags); | |
162 | } | |
163 | ||
0ab2b7d0 RG |
164 | cycle_t gic_read_compare(void) |
165 | { | |
166 | unsigned int hi, lo; | |
167 | ||
5f68fea0 AB |
168 | hi = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI)); |
169 | lo = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO)); | |
0ab2b7d0 RG |
170 | |
171 | return (((cycle_t) hi) << 32) + lo; | |
172 | } | |
dfa762e1 SH |
173 | #endif |
174 | ||
e9de688d AB |
175 | static bool gic_local_irq_is_routable(int intr) |
176 | { | |
177 | u32 vpe_ctl; | |
178 | ||
179 | /* All local interrupts are routable in EIC mode. */ | |
180 | if (cpu_has_veic) | |
181 | return true; | |
182 | ||
5f68fea0 | 183 | vpe_ctl = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_CTL)); |
e9de688d AB |
184 | switch (intr) { |
185 | case GIC_LOCAL_INT_TIMER: | |
186 | return vpe_ctl & GIC_VPE_CTL_TIMER_RTBL_MSK; | |
187 | case GIC_LOCAL_INT_PERFCTR: | |
188 | return vpe_ctl & GIC_VPE_CTL_PERFCNT_RTBL_MSK; | |
189 | case GIC_LOCAL_INT_FDC: | |
190 | return vpe_ctl & GIC_VPE_CTL_FDC_RTBL_MSK; | |
191 | case GIC_LOCAL_INT_SWINT0: | |
192 | case GIC_LOCAL_INT_SWINT1: | |
193 | return vpe_ctl & GIC_VPE_CTL_SWINT_RTBL_MSK; | |
194 | default: | |
195 | return true; | |
196 | } | |
197 | } | |
198 | ||
98b67c37 SH |
199 | unsigned int gic_get_timer_pending(void) |
200 | { | |
201 | unsigned int vpe_pending; | |
202 | ||
5f68fea0 | 203 | vpe_pending = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_PEND)); |
635c9907 | 204 | return vpe_pending & GIC_VPE_PEND_TIMER_MSK; |
98b67c37 SH |
205 | } |
206 | ||
3263d085 | 207 | static void gic_bind_eic_interrupt(int irq, int set) |
98b67c37 SH |
208 | { |
209 | /* Convert irq vector # to hw int # */ | |
210 | irq -= GIC_PIN_TO_VEC_OFFSET; | |
211 | ||
212 | /* Set irq to use shadow set */ | |
5f68fea0 AB |
213 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_EIC_SHADOW_SET_BASE) + |
214 | GIC_VPE_EIC_SS(irq), set); | |
98b67c37 SH |
215 | } |
216 | ||
39b8d525 RB |
217 | void gic_send_ipi(unsigned int intr) |
218 | { | |
5f68fea0 | 219 | gic_write(GIC_REG(SHARED, GIC_SH_WEDGE), 0x80000000 | intr); |
39b8d525 RB |
220 | } |
221 | ||
e9de688d AB |
222 | int gic_get_c0_compare_int(void) |
223 | { | |
224 | if (!gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER)) | |
225 | return MIPS_CPU_IRQ_BASE + cp0_compare_irq; | |
226 | return irq_create_mapping(gic_irq_domain, | |
227 | GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_TIMER)); | |
228 | } | |
229 | ||
230 | int gic_get_c0_perfcount_int(void) | |
231 | { | |
232 | if (!gic_local_irq_is_routable(GIC_LOCAL_INT_PERFCTR)) { | |
233 | /* Is the erformance counter shared with the timer? */ | |
234 | if (cp0_perfcount_irq < 0) | |
235 | return -1; | |
236 | return MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; | |
237 | } | |
238 | return irq_create_mapping(gic_irq_domain, | |
239 | GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_PERFCTR)); | |
240 | } | |
241 | ||
3263d085 | 242 | static unsigned int gic_get_int(void) |
39b8d525 RB |
243 | { |
244 | unsigned int i; | |
245 | unsigned long *pending, *intrmask, *pcpu_mask; | |
5f68fea0 | 246 | unsigned long pending_reg, intrmask_reg; |
39b8d525 RB |
247 | |
248 | /* Get per-cpu bitmaps */ | |
249 | pending = pending_regs[smp_processor_id()].pending; | |
250 | intrmask = intrmask_regs[smp_processor_id()].intrmask; | |
251 | pcpu_mask = pcpu_masks[smp_processor_id()].pcpu_mask; | |
252 | ||
824f3f7f AB |
253 | pending_reg = GIC_REG(SHARED, GIC_SH_PEND); |
254 | intrmask_reg = GIC_REG(SHARED, GIC_SH_MASK); | |
39b8d525 | 255 | |
fbd55241 | 256 | for (i = 0; i < BITS_TO_LONGS(gic_shared_intrs); i++) { |
5f68fea0 AB |
257 | pending[i] = gic_read(pending_reg); |
258 | intrmask[i] = gic_read(intrmask_reg); | |
259 | pending_reg += 0x4; | |
260 | intrmask_reg += 0x4; | |
39b8d525 RB |
261 | } |
262 | ||
fbd55241 AB |
263 | bitmap_and(pending, pending, intrmask, gic_shared_intrs); |
264 | bitmap_and(pending, pending, pcpu_mask, gic_shared_intrs); | |
39b8d525 | 265 | |
3263d085 | 266 | return find_first_bit(pending, gic_shared_intrs); |
39b8d525 RB |
267 | } |
268 | ||
161d049e | 269 | static void gic_mask_irq(struct irq_data *d) |
39b8d525 | 270 | { |
5f68fea0 | 271 | gic_reset_mask(GIC_HWIRQ_TO_SHARED(d->hwirq)); |
39b8d525 RB |
272 | } |
273 | ||
161d049e | 274 | static void gic_unmask_irq(struct irq_data *d) |
39b8d525 | 275 | { |
5f68fea0 | 276 | gic_set_mask(GIC_HWIRQ_TO_SHARED(d->hwirq)); |
39b8d525 RB |
277 | } |
278 | ||
5561c9e4 AB |
279 | static void gic_ack_irq(struct irq_data *d) |
280 | { | |
e9de688d | 281 | unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq); |
c49581a4 | 282 | |
5f68fea0 | 283 | gic_write(GIC_REG(SHARED, GIC_SH_WEDGE), irq); |
5561c9e4 AB |
284 | } |
285 | ||
95150ae8 AB |
286 | static int gic_set_type(struct irq_data *d, unsigned int type) |
287 | { | |
e9de688d | 288 | unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq); |
95150ae8 AB |
289 | unsigned long flags; |
290 | bool is_edge; | |
291 | ||
292 | spin_lock_irqsave(&gic_lock, flags); | |
293 | switch (type & IRQ_TYPE_SENSE_MASK) { | |
294 | case IRQ_TYPE_EDGE_FALLING: | |
5f68fea0 AB |
295 | gic_set_polarity(irq, GIC_POL_NEG); |
296 | gic_set_trigger(irq, GIC_TRIG_EDGE); | |
297 | gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE); | |
95150ae8 AB |
298 | is_edge = true; |
299 | break; | |
300 | case IRQ_TYPE_EDGE_RISING: | |
5f68fea0 AB |
301 | gic_set_polarity(irq, GIC_POL_POS); |
302 | gic_set_trigger(irq, GIC_TRIG_EDGE); | |
303 | gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE); | |
95150ae8 AB |
304 | is_edge = true; |
305 | break; | |
306 | case IRQ_TYPE_EDGE_BOTH: | |
307 | /* polarity is irrelevant in this case */ | |
5f68fea0 AB |
308 | gic_set_trigger(irq, GIC_TRIG_EDGE); |
309 | gic_set_dual_edge(irq, GIC_TRIG_DUAL_ENABLE); | |
95150ae8 AB |
310 | is_edge = true; |
311 | break; | |
312 | case IRQ_TYPE_LEVEL_LOW: | |
5f68fea0 AB |
313 | gic_set_polarity(irq, GIC_POL_NEG); |
314 | gic_set_trigger(irq, GIC_TRIG_LEVEL); | |
315 | gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE); | |
95150ae8 AB |
316 | is_edge = false; |
317 | break; | |
318 | case IRQ_TYPE_LEVEL_HIGH: | |
319 | default: | |
5f68fea0 AB |
320 | gic_set_polarity(irq, GIC_POL_POS); |
321 | gic_set_trigger(irq, GIC_TRIG_LEVEL); | |
322 | gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE); | |
95150ae8 AB |
323 | is_edge = false; |
324 | break; | |
325 | } | |
326 | ||
327 | if (is_edge) { | |
4a6a3ea3 AB |
328 | __irq_set_chip_handler_name_locked(d->irq, |
329 | &gic_edge_irq_controller, | |
330 | handle_edge_irq, NULL); | |
95150ae8 | 331 | } else { |
4a6a3ea3 AB |
332 | __irq_set_chip_handler_name_locked(d->irq, |
333 | &gic_level_irq_controller, | |
334 | handle_level_irq, NULL); | |
95150ae8 AB |
335 | } |
336 | spin_unlock_irqrestore(&gic_lock, flags); | |
39b8d525 | 337 | |
95150ae8 AB |
338 | return 0; |
339 | } | |
340 | ||
341 | #ifdef CONFIG_SMP | |
161d049e TG |
342 | static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask, |
343 | bool force) | |
39b8d525 | 344 | { |
e9de688d | 345 | unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq); |
39b8d525 RB |
346 | cpumask_t tmp = CPU_MASK_NONE; |
347 | unsigned long flags; | |
348 | int i; | |
349 | ||
0de26520 | 350 | cpumask_and(&tmp, cpumask, cpu_online_mask); |
39b8d525 | 351 | if (cpus_empty(tmp)) |
14d160ab | 352 | return -EINVAL; |
39b8d525 RB |
353 | |
354 | /* Assumption : cpumask refers to a single CPU */ | |
355 | spin_lock_irqsave(&gic_lock, flags); | |
39b8d525 | 356 | |
c214c035 | 357 | /* Re-route this IRQ */ |
5f68fea0 | 358 | gic_map_to_vpe(irq, first_cpu(tmp)); |
c214c035 TW |
359 | |
360 | /* Update the pcpu_masks */ | |
361 | for (i = 0; i < NR_CPUS; i++) | |
362 | clear_bit(irq, pcpu_masks[i].pcpu_mask); | |
363 | set_bit(irq, pcpu_masks[first_cpu(tmp)].pcpu_mask); | |
39b8d525 | 364 | |
161d049e | 365 | cpumask_copy(d->affinity, cpumask); |
39b8d525 RB |
366 | spin_unlock_irqrestore(&gic_lock, flags); |
367 | ||
161d049e | 368 | return IRQ_SET_MASK_OK_NOCOPY; |
39b8d525 RB |
369 | } |
370 | #endif | |
371 | ||
4a6a3ea3 AB |
372 | static struct irq_chip gic_level_irq_controller = { |
373 | .name = "MIPS GIC", | |
374 | .irq_mask = gic_mask_irq, | |
375 | .irq_unmask = gic_unmask_irq, | |
376 | .irq_set_type = gic_set_type, | |
377 | #ifdef CONFIG_SMP | |
378 | .irq_set_affinity = gic_set_affinity, | |
379 | #endif | |
380 | }; | |
381 | ||
382 | static struct irq_chip gic_edge_irq_controller = { | |
161d049e | 383 | .name = "MIPS GIC", |
5561c9e4 | 384 | .irq_ack = gic_ack_irq, |
161d049e | 385 | .irq_mask = gic_mask_irq, |
161d049e | 386 | .irq_unmask = gic_unmask_irq, |
95150ae8 | 387 | .irq_set_type = gic_set_type, |
39b8d525 | 388 | #ifdef CONFIG_SMP |
161d049e | 389 | .irq_set_affinity = gic_set_affinity, |
39b8d525 RB |
390 | #endif |
391 | }; | |
392 | ||
e9de688d AB |
393 | static unsigned int gic_get_local_int(void) |
394 | { | |
395 | unsigned long pending, masked; | |
396 | ||
5f68fea0 AB |
397 | pending = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_PEND)); |
398 | masked = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_MASK)); | |
e9de688d AB |
399 | |
400 | bitmap_and(&pending, &pending, &masked, GIC_NUM_LOCAL_INTRS); | |
401 | ||
402 | return find_first_bit(&pending, GIC_NUM_LOCAL_INTRS); | |
403 | } | |
404 | ||
405 | static void gic_mask_local_irq(struct irq_data *d) | |
406 | { | |
407 | int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); | |
408 | ||
5f68fea0 | 409 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_RMASK), 1 << intr); |
e9de688d AB |
410 | } |
411 | ||
412 | static void gic_unmask_local_irq(struct irq_data *d) | |
413 | { | |
414 | int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); | |
415 | ||
5f68fea0 | 416 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_SMASK), 1 << intr); |
e9de688d AB |
417 | } |
418 | ||
419 | static struct irq_chip gic_local_irq_controller = { | |
420 | .name = "MIPS GIC Local", | |
421 | .irq_mask = gic_mask_local_irq, | |
422 | .irq_unmask = gic_unmask_local_irq, | |
423 | }; | |
424 | ||
425 | static void gic_mask_local_irq_all_vpes(struct irq_data *d) | |
426 | { | |
427 | int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); | |
428 | int i; | |
429 | unsigned long flags; | |
430 | ||
431 | spin_lock_irqsave(&gic_lock, flags); | |
432 | for (i = 0; i < gic_vpes; i++) { | |
5f68fea0 AB |
433 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i); |
434 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_RMASK), 1 << intr); | |
e9de688d AB |
435 | } |
436 | spin_unlock_irqrestore(&gic_lock, flags); | |
437 | } | |
438 | ||
439 | static void gic_unmask_local_irq_all_vpes(struct irq_data *d) | |
440 | { | |
441 | int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); | |
442 | int i; | |
443 | unsigned long flags; | |
444 | ||
445 | spin_lock_irqsave(&gic_lock, flags); | |
446 | for (i = 0; i < gic_vpes; i++) { | |
5f68fea0 AB |
447 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i); |
448 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_SMASK), 1 << intr); | |
e9de688d AB |
449 | } |
450 | spin_unlock_irqrestore(&gic_lock, flags); | |
451 | } | |
452 | ||
453 | static struct irq_chip gic_all_vpes_local_irq_controller = { | |
454 | .name = "MIPS GIC Local", | |
455 | .irq_mask = gic_mask_local_irq_all_vpes, | |
456 | .irq_unmask = gic_unmask_local_irq_all_vpes, | |
457 | }; | |
458 | ||
18743d27 | 459 | static void __gic_irq_dispatch(void) |
39b8d525 | 460 | { |
18743d27 | 461 | unsigned int intr, virq; |
6096e114 | 462 | |
e9de688d AB |
463 | while ((intr = gic_get_local_int()) != GIC_NUM_LOCAL_INTRS) { |
464 | virq = irq_linear_revmap(gic_irq_domain, | |
465 | GIC_LOCAL_TO_HWIRQ(intr)); | |
466 | do_IRQ(virq); | |
467 | } | |
468 | ||
fbd55241 | 469 | while ((intr = gic_get_int()) != gic_shared_intrs) { |
e9de688d AB |
470 | virq = irq_linear_revmap(gic_irq_domain, |
471 | GIC_SHARED_TO_HWIRQ(intr)); | |
18743d27 | 472 | do_IRQ(virq); |
39b8d525 | 473 | } |
18743d27 | 474 | } |
39b8d525 | 475 | |
18743d27 AB |
476 | static void gic_irq_dispatch(unsigned int irq, struct irq_desc *desc) |
477 | { | |
478 | __gic_irq_dispatch(); | |
479 | } | |
480 | ||
481 | #ifdef CONFIG_MIPS_GIC_IPI | |
482 | static int gic_resched_int_base; | |
483 | static int gic_call_int_base; | |
484 | ||
485 | unsigned int plat_ipi_resched_int_xlate(unsigned int cpu) | |
486 | { | |
487 | return gic_resched_int_base + cpu; | |
488 | } | |
39b8d525 | 489 | |
18743d27 AB |
490 | unsigned int plat_ipi_call_int_xlate(unsigned int cpu) |
491 | { | |
492 | return gic_call_int_base + cpu; | |
493 | } | |
39b8d525 | 494 | |
18743d27 AB |
495 | static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id) |
496 | { | |
497 | scheduler_ipi(); | |
498 | ||
499 | return IRQ_HANDLED; | |
500 | } | |
501 | ||
502 | static irqreturn_t ipi_call_interrupt(int irq, void *dev_id) | |
503 | { | |
504 | smp_call_function_interrupt(); | |
505 | ||
506 | return IRQ_HANDLED; | |
507 | } | |
b0a88ae5 | 508 | |
18743d27 AB |
509 | static struct irqaction irq_resched = { |
510 | .handler = ipi_resched_interrupt, | |
511 | .flags = IRQF_PERCPU, | |
512 | .name = "IPI resched" | |
513 | }; | |
514 | ||
515 | static struct irqaction irq_call = { | |
516 | .handler = ipi_call_interrupt, | |
517 | .flags = IRQF_PERCPU, | |
518 | .name = "IPI call" | |
519 | }; | |
520 | ||
521 | static __init void gic_ipi_init_one(unsigned int intr, int cpu, | |
522 | struct irqaction *action) | |
523 | { | |
e9de688d AB |
524 | int virq = irq_create_mapping(gic_irq_domain, |
525 | GIC_SHARED_TO_HWIRQ(intr)); | |
18743d27 AB |
526 | int i; |
527 | ||
5f68fea0 | 528 | gic_map_to_vpe(intr, cpu); |
c49581a4 AB |
529 | for (i = 0; i < NR_CPUS; i++) |
530 | clear_bit(intr, pcpu_masks[i].pcpu_mask); | |
b0a88ae5 JD |
531 | set_bit(intr, pcpu_masks[cpu].pcpu_mask); |
532 | ||
18743d27 AB |
533 | irq_set_irq_type(virq, IRQ_TYPE_EDGE_RISING); |
534 | ||
535 | irq_set_handler(virq, handle_percpu_irq); | |
536 | setup_irq(virq, action); | |
39b8d525 RB |
537 | } |
538 | ||
18743d27 | 539 | static __init void gic_ipi_init(void) |
39b8d525 | 540 | { |
18743d27 AB |
541 | int i; |
542 | ||
543 | /* Use last 2 * NR_CPUS interrupts as IPIs */ | |
fbd55241 | 544 | gic_resched_int_base = gic_shared_intrs - nr_cpu_ids; |
18743d27 AB |
545 | gic_call_int_base = gic_resched_int_base - nr_cpu_ids; |
546 | ||
547 | for (i = 0; i < nr_cpu_ids; i++) { | |
548 | gic_ipi_init_one(gic_call_int_base + i, i, &irq_call); | |
549 | gic_ipi_init_one(gic_resched_int_base + i, i, &irq_resched); | |
550 | } | |
551 | } | |
552 | #else | |
553 | static inline void gic_ipi_init(void) | |
554 | { | |
555 | } | |
556 | #endif | |
557 | ||
e9de688d | 558 | static void __init gic_basic_init(void) |
18743d27 AB |
559 | { |
560 | unsigned int i; | |
98b67c37 SH |
561 | |
562 | board_bind_eic_interrupt = &gic_bind_eic_interrupt; | |
39b8d525 RB |
563 | |
564 | /* Setup defaults */ | |
fbd55241 | 565 | for (i = 0; i < gic_shared_intrs; i++) { |
5f68fea0 AB |
566 | gic_set_polarity(i, GIC_POL_POS); |
567 | gic_set_trigger(i, GIC_TRIG_LEVEL); | |
568 | gic_reset_mask(i); | |
39b8d525 RB |
569 | } |
570 | ||
e9de688d AB |
571 | for (i = 0; i < gic_vpes; i++) { |
572 | unsigned int j; | |
573 | ||
5f68fea0 | 574 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i); |
e9de688d AB |
575 | for (j = 0; j < GIC_NUM_LOCAL_INTRS; j++) { |
576 | if (!gic_local_irq_is_routable(j)) | |
577 | continue; | |
5f68fea0 | 578 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_RMASK), 1 << j); |
e9de688d AB |
579 | } |
580 | } | |
39b8d525 RB |
581 | } |
582 | ||
e9de688d AB |
583 | static int gic_local_irq_domain_map(struct irq_domain *d, unsigned int virq, |
584 | irq_hw_number_t hw) | |
c49581a4 | 585 | { |
e9de688d AB |
586 | int intr = GIC_HWIRQ_TO_LOCAL(hw); |
587 | int ret = 0; | |
588 | int i; | |
589 | unsigned long flags; | |
590 | ||
591 | if (!gic_local_irq_is_routable(intr)) | |
592 | return -EPERM; | |
593 | ||
594 | /* | |
595 | * HACK: These are all really percpu interrupts, but the rest | |
596 | * of the MIPS kernel code does not use the percpu IRQ API for | |
597 | * the CP0 timer and performance counter interrupts. | |
598 | */ | |
599 | if (intr != GIC_LOCAL_INT_TIMER && intr != GIC_LOCAL_INT_PERFCTR) { | |
600 | irq_set_chip_and_handler(virq, | |
601 | &gic_local_irq_controller, | |
602 | handle_percpu_devid_irq); | |
603 | irq_set_percpu_devid(virq); | |
604 | } else { | |
605 | irq_set_chip_and_handler(virq, | |
606 | &gic_all_vpes_local_irq_controller, | |
607 | handle_percpu_irq); | |
608 | } | |
609 | ||
610 | spin_lock_irqsave(&gic_lock, flags); | |
611 | for (i = 0; i < gic_vpes; i++) { | |
612 | u32 val = GIC_MAP_TO_PIN_MSK | gic_cpu_pin; | |
613 | ||
5f68fea0 | 614 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i); |
e9de688d AB |
615 | |
616 | switch (intr) { | |
617 | case GIC_LOCAL_INT_WD: | |
5f68fea0 | 618 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_WD_MAP), val); |
e9de688d AB |
619 | break; |
620 | case GIC_LOCAL_INT_COMPARE: | |
5f68fea0 | 621 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_MAP), val); |
e9de688d AB |
622 | break; |
623 | case GIC_LOCAL_INT_TIMER: | |
5f68fea0 | 624 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP), val); |
e9de688d AB |
625 | break; |
626 | case GIC_LOCAL_INT_PERFCTR: | |
5f68fea0 | 627 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP), val); |
e9de688d AB |
628 | break; |
629 | case GIC_LOCAL_INT_SWINT0: | |
5f68fea0 | 630 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_SWINT0_MAP), val); |
e9de688d AB |
631 | break; |
632 | case GIC_LOCAL_INT_SWINT1: | |
5f68fea0 | 633 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_SWINT1_MAP), val); |
e9de688d AB |
634 | break; |
635 | case GIC_LOCAL_INT_FDC: | |
5f68fea0 | 636 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_FDC_MAP), val); |
e9de688d AB |
637 | break; |
638 | default: | |
639 | pr_err("Invalid local IRQ %d\n", intr); | |
640 | ret = -EINVAL; | |
641 | break; | |
642 | } | |
643 | } | |
644 | spin_unlock_irqrestore(&gic_lock, flags); | |
645 | ||
646 | return ret; | |
647 | } | |
648 | ||
649 | static int gic_shared_irq_domain_map(struct irq_domain *d, unsigned int virq, | |
650 | irq_hw_number_t hw) | |
651 | { | |
652 | int intr = GIC_HWIRQ_TO_SHARED(hw); | |
c49581a4 AB |
653 | unsigned long flags; |
654 | ||
4a6a3ea3 AB |
655 | irq_set_chip_and_handler(virq, &gic_level_irq_controller, |
656 | handle_level_irq); | |
c49581a4 AB |
657 | |
658 | spin_lock_irqsave(&gic_lock, flags); | |
5f68fea0 | 659 | gic_map_to_pin(intr, gic_cpu_pin); |
c49581a4 | 660 | /* Map to VPE 0 by default */ |
5f68fea0 | 661 | gic_map_to_vpe(intr, 0); |
e9de688d | 662 | set_bit(intr, pcpu_masks[0].pcpu_mask); |
c49581a4 AB |
663 | spin_unlock_irqrestore(&gic_lock, flags); |
664 | ||
665 | return 0; | |
666 | } | |
667 | ||
e9de688d AB |
668 | static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq, |
669 | irq_hw_number_t hw) | |
670 | { | |
671 | if (GIC_HWIRQ_TO_LOCAL(hw) < GIC_NUM_LOCAL_INTRS) | |
672 | return gic_local_irq_domain_map(d, virq, hw); | |
673 | return gic_shared_irq_domain_map(d, virq, hw); | |
674 | } | |
675 | ||
c49581a4 AB |
676 | static struct irq_domain_ops gic_irq_domain_ops = { |
677 | .map = gic_irq_domain_map, | |
678 | .xlate = irq_domain_xlate_twocell, | |
679 | }; | |
680 | ||
39b8d525 | 681 | void __init gic_init(unsigned long gic_base_addr, |
18743d27 | 682 | unsigned long gic_addrspace_size, unsigned int cpu_vec, |
39b8d525 RB |
683 | unsigned int irqbase) |
684 | { | |
685 | unsigned int gicconfig; | |
686 | ||
5f68fea0 | 687 | gic_base = ioremap_nocache(gic_base_addr, gic_addrspace_size); |
39b8d525 | 688 | |
5f68fea0 | 689 | gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG)); |
fbd55241 | 690 | gic_shared_intrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >> |
39b8d525 | 691 | GIC_SH_CONFIG_NUMINTRS_SHF; |
fbd55241 | 692 | gic_shared_intrs = ((gic_shared_intrs + 1) * 8); |
39b8d525 | 693 | |
e9de688d | 694 | gic_vpes = (gicconfig & GIC_SH_CONFIG_NUMVPES_MSK) >> |
39b8d525 | 695 | GIC_SH_CONFIG_NUMVPES_SHF; |
e9de688d | 696 | gic_vpes = gic_vpes + 1; |
39b8d525 | 697 | |
18743d27 AB |
698 | if (cpu_has_veic) { |
699 | /* Always use vector 1 in EIC mode */ | |
700 | gic_cpu_pin = 0; | |
701 | set_vi_handler(gic_cpu_pin + GIC_PIN_TO_VEC_OFFSET, | |
702 | __gic_irq_dispatch); | |
703 | } else { | |
704 | gic_cpu_pin = cpu_vec - GIC_CPU_PIN_OFFSET; | |
705 | irq_set_chained_handler(MIPS_CPU_IRQ_BASE + cpu_vec, | |
706 | gic_irq_dispatch); | |
707 | } | |
708 | ||
e9de688d AB |
709 | gic_irq_domain = irq_domain_add_simple(NULL, GIC_NUM_LOCAL_INTRS + |
710 | gic_shared_intrs, irqbase, | |
c49581a4 AB |
711 | &gic_irq_domain_ops, NULL); |
712 | if (!gic_irq_domain) | |
713 | panic("Failed to add GIC IRQ domain"); | |
0b271f56 | 714 | |
e9de688d | 715 | gic_basic_init(); |
18743d27 AB |
716 | |
717 | gic_ipi_init(); | |
39b8d525 | 718 | } |