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f27ecacc RK |
1 | /* |
2 | * linux/arch/arm/common/gic.c | |
3 | * | |
4 | * Copyright (C) 2002 ARM Limited, All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * Interrupt architecture for the GIC: | |
11 | * | |
12 | * o There is one Interrupt Distributor, which receives interrupts | |
13 | * from system devices and sends them to the Interrupt Controllers. | |
14 | * | |
15 | * o There is one CPU Interface per CPU, which sends interrupts sent | |
16 | * by the Distributor, and interrupts generated locally, to the | |
b3a1bde4 CM |
17 | * associated CPU. The base address of the CPU interface is usually |
18 | * aliased so that the same address points to different chips depending | |
19 | * on the CPU it is accessed from. | |
f27ecacc RK |
20 | * |
21 | * Note that IRQs 0-31 are special - they are local to each CPU. | |
22 | * As such, the enable set/clear, pending set/clear and active bit | |
23 | * registers are banked per-cpu for these sources. | |
24 | */ | |
25 | #include <linux/init.h> | |
26 | #include <linux/kernel.h> | |
f37a53cc | 27 | #include <linux/err.h> |
7e1efcf5 | 28 | #include <linux/module.h> |
f27ecacc RK |
29 | #include <linux/list.h> |
30 | #include <linux/smp.h> | |
c0114709 | 31 | #include <linux/cpu.h> |
254056f3 | 32 | #include <linux/cpu_pm.h> |
dcb86e8c | 33 | #include <linux/cpumask.h> |
fced80c7 | 34 | #include <linux/io.h> |
b3f7ed03 RH |
35 | #include <linux/of.h> |
36 | #include <linux/of_address.h> | |
37 | #include <linux/of_irq.h> | |
4294f8ba | 38 | #include <linux/irqdomain.h> |
292b293c MZ |
39 | #include <linux/interrupt.h> |
40 | #include <linux/percpu.h> | |
41 | #include <linux/slab.h> | |
de88cbb7 | 42 | #include <linux/irqchip/chained_irq.h> |
520f7bd7 | 43 | #include <linux/irqchip/arm-gic.h> |
f27ecacc RK |
44 | |
45 | #include <asm/irq.h> | |
562e0027 | 46 | #include <asm/exception.h> |
eb50439b | 47 | #include <asm/smp_plat.h> |
f27ecacc | 48 | |
81243e44 | 49 | #include "irqchip.h" |
f27ecacc | 50 | |
db0d4db2 MZ |
51 | union gic_base { |
52 | void __iomem *common_base; | |
53 | void __percpu __iomem **percpu_base; | |
54 | }; | |
55 | ||
56 | struct gic_chip_data { | |
db0d4db2 MZ |
57 | union gic_base dist_base; |
58 | union gic_base cpu_base; | |
59 | #ifdef CONFIG_CPU_PM | |
60 | u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)]; | |
61 | u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)]; | |
62 | u32 saved_spi_target[DIV_ROUND_UP(1020, 4)]; | |
63 | u32 __percpu *saved_ppi_enable; | |
64 | u32 __percpu *saved_ppi_conf; | |
65 | #endif | |
75294957 | 66 | struct irq_domain *domain; |
db0d4db2 MZ |
67 | unsigned int gic_irqs; |
68 | #ifdef CONFIG_GIC_NON_BANKED | |
69 | void __iomem *(*get_base)(union gic_base *); | |
70 | #endif | |
71 | }; | |
72 | ||
bd31b859 | 73 | static DEFINE_RAW_SPINLOCK(irq_controller_lock); |
f27ecacc | 74 | |
384a2902 NP |
75 | /* |
76 | * The GIC mapping of CPU interfaces does not necessarily match | |
77 | * the logical CPU numbering. Let's use a mapping as returned | |
78 | * by the GIC itself. | |
79 | */ | |
80 | #define NR_GIC_CPU_IF 8 | |
81 | static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly; | |
82 | ||
d7ed36a4 SS |
83 | /* |
84 | * Supported arch specific GIC irq extension. | |
85 | * Default make them NULL. | |
86 | */ | |
87 | struct irq_chip gic_arch_extn = { | |
1a01753e | 88 | .irq_eoi = NULL, |
d7ed36a4 SS |
89 | .irq_mask = NULL, |
90 | .irq_unmask = NULL, | |
91 | .irq_retrigger = NULL, | |
92 | .irq_set_type = NULL, | |
93 | .irq_set_wake = NULL, | |
94 | }; | |
95 | ||
b3a1bde4 CM |
96 | #ifndef MAX_GIC_NR |
97 | #define MAX_GIC_NR 1 | |
98 | #endif | |
99 | ||
bef8f9ee | 100 | static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly; |
b3a1bde4 | 101 | |
db0d4db2 MZ |
102 | #ifdef CONFIG_GIC_NON_BANKED |
103 | static void __iomem *gic_get_percpu_base(union gic_base *base) | |
104 | { | |
105 | return *__this_cpu_ptr(base->percpu_base); | |
106 | } | |
107 | ||
108 | static void __iomem *gic_get_common_base(union gic_base *base) | |
109 | { | |
110 | return base->common_base; | |
111 | } | |
112 | ||
113 | static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data) | |
114 | { | |
115 | return data->get_base(&data->dist_base); | |
116 | } | |
117 | ||
118 | static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data) | |
119 | { | |
120 | return data->get_base(&data->cpu_base); | |
121 | } | |
122 | ||
123 | static inline void gic_set_base_accessor(struct gic_chip_data *data, | |
124 | void __iomem *(*f)(union gic_base *)) | |
125 | { | |
126 | data->get_base = f; | |
127 | } | |
128 | #else | |
129 | #define gic_data_dist_base(d) ((d)->dist_base.common_base) | |
130 | #define gic_data_cpu_base(d) ((d)->cpu_base.common_base) | |
46f101df | 131 | #define gic_set_base_accessor(d, f) |
db0d4db2 MZ |
132 | #endif |
133 | ||
7d1f4288 | 134 | static inline void __iomem *gic_dist_base(struct irq_data *d) |
b3a1bde4 | 135 | { |
7d1f4288 | 136 | struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); |
db0d4db2 | 137 | return gic_data_dist_base(gic_data); |
b3a1bde4 CM |
138 | } |
139 | ||
7d1f4288 | 140 | static inline void __iomem *gic_cpu_base(struct irq_data *d) |
b3a1bde4 | 141 | { |
7d1f4288 | 142 | struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); |
db0d4db2 | 143 | return gic_data_cpu_base(gic_data); |
b3a1bde4 CM |
144 | } |
145 | ||
7d1f4288 | 146 | static inline unsigned int gic_irq(struct irq_data *d) |
b3a1bde4 | 147 | { |
4294f8ba | 148 | return d->hwirq; |
b3a1bde4 CM |
149 | } |
150 | ||
f27ecacc RK |
151 | /* |
152 | * Routines to acknowledge, disable and enable interrupts | |
f27ecacc | 153 | */ |
7d1f4288 | 154 | static void gic_mask_irq(struct irq_data *d) |
f27ecacc | 155 | { |
4294f8ba | 156 | u32 mask = 1 << (gic_irq(d) % 32); |
c4bfa28a | 157 | |
bd31b859 | 158 | raw_spin_lock(&irq_controller_lock); |
6ac77e46 | 159 | writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4); |
d7ed36a4 SS |
160 | if (gic_arch_extn.irq_mask) |
161 | gic_arch_extn.irq_mask(d); | |
bd31b859 | 162 | raw_spin_unlock(&irq_controller_lock); |
f27ecacc RK |
163 | } |
164 | ||
7d1f4288 | 165 | static void gic_unmask_irq(struct irq_data *d) |
f27ecacc | 166 | { |
4294f8ba | 167 | u32 mask = 1 << (gic_irq(d) % 32); |
c4bfa28a | 168 | |
bd31b859 | 169 | raw_spin_lock(&irq_controller_lock); |
d7ed36a4 SS |
170 | if (gic_arch_extn.irq_unmask) |
171 | gic_arch_extn.irq_unmask(d); | |
6ac77e46 | 172 | writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4); |
bd31b859 | 173 | raw_spin_unlock(&irq_controller_lock); |
f27ecacc RK |
174 | } |
175 | ||
1a01753e WD |
176 | static void gic_eoi_irq(struct irq_data *d) |
177 | { | |
178 | if (gic_arch_extn.irq_eoi) { | |
bd31b859 | 179 | raw_spin_lock(&irq_controller_lock); |
1a01753e | 180 | gic_arch_extn.irq_eoi(d); |
bd31b859 | 181 | raw_spin_unlock(&irq_controller_lock); |
1a01753e WD |
182 | } |
183 | ||
6ac77e46 | 184 | writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); |
1a01753e WD |
185 | } |
186 | ||
7d1f4288 | 187 | static int gic_set_type(struct irq_data *d, unsigned int type) |
5c0c1f08 | 188 | { |
7d1f4288 LB |
189 | void __iomem *base = gic_dist_base(d); |
190 | unsigned int gicirq = gic_irq(d); | |
5c0c1f08 RV |
191 | u32 enablemask = 1 << (gicirq % 32); |
192 | u32 enableoff = (gicirq / 32) * 4; | |
193 | u32 confmask = 0x2 << ((gicirq % 16) * 2); | |
194 | u32 confoff = (gicirq / 16) * 4; | |
195 | bool enabled = false; | |
196 | u32 val; | |
197 | ||
198 | /* Interrupt configuration for SGIs can't be changed */ | |
199 | if (gicirq < 16) | |
200 | return -EINVAL; | |
201 | ||
202 | if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING) | |
203 | return -EINVAL; | |
204 | ||
bd31b859 | 205 | raw_spin_lock(&irq_controller_lock); |
5c0c1f08 | 206 | |
d7ed36a4 SS |
207 | if (gic_arch_extn.irq_set_type) |
208 | gic_arch_extn.irq_set_type(d, type); | |
209 | ||
6ac77e46 | 210 | val = readl_relaxed(base + GIC_DIST_CONFIG + confoff); |
5c0c1f08 RV |
211 | if (type == IRQ_TYPE_LEVEL_HIGH) |
212 | val &= ~confmask; | |
213 | else if (type == IRQ_TYPE_EDGE_RISING) | |
214 | val |= confmask; | |
215 | ||
216 | /* | |
217 | * As recommended by the spec, disable the interrupt before changing | |
218 | * the configuration | |
219 | */ | |
6ac77e46 SS |
220 | if (readl_relaxed(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) { |
221 | writel_relaxed(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff); | |
5c0c1f08 RV |
222 | enabled = true; |
223 | } | |
224 | ||
6ac77e46 | 225 | writel_relaxed(val, base + GIC_DIST_CONFIG + confoff); |
5c0c1f08 RV |
226 | |
227 | if (enabled) | |
6ac77e46 | 228 | writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff); |
5c0c1f08 | 229 | |
bd31b859 | 230 | raw_spin_unlock(&irq_controller_lock); |
5c0c1f08 RV |
231 | |
232 | return 0; | |
233 | } | |
234 | ||
d7ed36a4 SS |
235 | static int gic_retrigger(struct irq_data *d) |
236 | { | |
237 | if (gic_arch_extn.irq_retrigger) | |
238 | return gic_arch_extn.irq_retrigger(d); | |
239 | ||
bad9a43a AD |
240 | /* the genirq layer expects 0 if we can't retrigger in hardware */ |
241 | return 0; | |
d7ed36a4 SS |
242 | } |
243 | ||
a06f5466 | 244 | #ifdef CONFIG_SMP |
c191789c RK |
245 | static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, |
246 | bool force) | |
f27ecacc | 247 | { |
7d1f4288 | 248 | void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3); |
4294f8ba | 249 | unsigned int shift = (gic_irq(d) % 4) * 8; |
5dfc54e0 | 250 | unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask); |
c191789c | 251 | u32 val, mask, bit; |
f27ecacc | 252 | |
384a2902 | 253 | if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids) |
87507500 | 254 | return -EINVAL; |
c191789c | 255 | |
1a6b69b6 | 256 | raw_spin_lock(&irq_controller_lock); |
c191789c | 257 | mask = 0xff << shift; |
384a2902 | 258 | bit = gic_cpu_map[cpu] << shift; |
6ac77e46 SS |
259 | val = readl_relaxed(reg) & ~mask; |
260 | writel_relaxed(val | bit, reg); | |
bd31b859 | 261 | raw_spin_unlock(&irq_controller_lock); |
d5dedd45 | 262 | |
5dfc54e0 | 263 | return IRQ_SET_MASK_OK; |
f27ecacc | 264 | } |
a06f5466 | 265 | #endif |
f27ecacc | 266 | |
d7ed36a4 SS |
267 | #ifdef CONFIG_PM |
268 | static int gic_set_wake(struct irq_data *d, unsigned int on) | |
269 | { | |
270 | int ret = -ENXIO; | |
271 | ||
272 | if (gic_arch_extn.irq_set_wake) | |
273 | ret = gic_arch_extn.irq_set_wake(d, on); | |
274 | ||
275 | return ret; | |
276 | } | |
277 | ||
278 | #else | |
279 | #define gic_set_wake NULL | |
280 | #endif | |
281 | ||
1d5cc604 | 282 | static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) |
562e0027 MZ |
283 | { |
284 | u32 irqstat, irqnr; | |
285 | struct gic_chip_data *gic = &gic_data[0]; | |
286 | void __iomem *cpu_base = gic_data_cpu_base(gic); | |
287 | ||
288 | do { | |
289 | irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK); | |
290 | irqnr = irqstat & ~0x1c00; | |
291 | ||
292 | if (likely(irqnr > 15 && irqnr < 1021)) { | |
75294957 | 293 | irqnr = irq_find_mapping(gic->domain, irqnr); |
562e0027 MZ |
294 | handle_IRQ(irqnr, regs); |
295 | continue; | |
296 | } | |
297 | if (irqnr < 16) { | |
298 | writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); | |
299 | #ifdef CONFIG_SMP | |
300 | handle_IPI(irqnr, regs); | |
301 | #endif | |
302 | continue; | |
303 | } | |
304 | break; | |
305 | } while (1); | |
306 | } | |
307 | ||
0f347bb9 | 308 | static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) |
b3a1bde4 | 309 | { |
6845664a TG |
310 | struct gic_chip_data *chip_data = irq_get_handler_data(irq); |
311 | struct irq_chip *chip = irq_get_chip(irq); | |
0f347bb9 | 312 | unsigned int cascade_irq, gic_irq; |
b3a1bde4 CM |
313 | unsigned long status; |
314 | ||
1a01753e | 315 | chained_irq_enter(chip, desc); |
b3a1bde4 | 316 | |
bd31b859 | 317 | raw_spin_lock(&irq_controller_lock); |
db0d4db2 | 318 | status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK); |
bd31b859 | 319 | raw_spin_unlock(&irq_controller_lock); |
b3a1bde4 | 320 | |
0f347bb9 RK |
321 | gic_irq = (status & 0x3ff); |
322 | if (gic_irq == 1023) | |
b3a1bde4 | 323 | goto out; |
b3a1bde4 | 324 | |
75294957 GL |
325 | cascade_irq = irq_find_mapping(chip_data->domain, gic_irq); |
326 | if (unlikely(gic_irq < 32 || gic_irq > 1020)) | |
aec00956 | 327 | handle_bad_irq(cascade_irq, desc); |
0f347bb9 RK |
328 | else |
329 | generic_handle_irq(cascade_irq); | |
b3a1bde4 CM |
330 | |
331 | out: | |
1a01753e | 332 | chained_irq_exit(chip, desc); |
b3a1bde4 CM |
333 | } |
334 | ||
38c677cb | 335 | static struct irq_chip gic_chip = { |
7d1f4288 | 336 | .name = "GIC", |
7d1f4288 LB |
337 | .irq_mask = gic_mask_irq, |
338 | .irq_unmask = gic_unmask_irq, | |
1a01753e | 339 | .irq_eoi = gic_eoi_irq, |
7d1f4288 | 340 | .irq_set_type = gic_set_type, |
d7ed36a4 | 341 | .irq_retrigger = gic_retrigger, |
f27ecacc | 342 | #ifdef CONFIG_SMP |
c191789c | 343 | .irq_set_affinity = gic_set_affinity, |
f27ecacc | 344 | #endif |
d7ed36a4 | 345 | .irq_set_wake = gic_set_wake, |
f27ecacc RK |
346 | }; |
347 | ||
b3a1bde4 CM |
348 | void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) |
349 | { | |
350 | if (gic_nr >= MAX_GIC_NR) | |
351 | BUG(); | |
6845664a | 352 | if (irq_set_handler_data(irq, &gic_data[gic_nr]) != 0) |
b3a1bde4 | 353 | BUG(); |
6845664a | 354 | irq_set_chained_handler(irq, gic_handle_cascade_irq); |
b3a1bde4 CM |
355 | } |
356 | ||
2bb31351 RK |
357 | static u8 gic_get_cpumask(struct gic_chip_data *gic) |
358 | { | |
359 | void __iomem *base = gic_data_dist_base(gic); | |
360 | u32 mask, i; | |
361 | ||
362 | for (i = mask = 0; i < 32; i += 4) { | |
363 | mask = readl_relaxed(base + GIC_DIST_TARGET + i); | |
364 | mask |= mask >> 16; | |
365 | mask |= mask >> 8; | |
366 | if (mask) | |
367 | break; | |
368 | } | |
369 | ||
370 | if (!mask) | |
371 | pr_crit("GIC CPU mask not found - kernel will fail to boot.\n"); | |
372 | ||
373 | return mask; | |
374 | } | |
375 | ||
4294f8ba | 376 | static void __init gic_dist_init(struct gic_chip_data *gic) |
f27ecacc | 377 | { |
75294957 | 378 | unsigned int i; |
267840f3 | 379 | u32 cpumask; |
4294f8ba | 380 | unsigned int gic_irqs = gic->gic_irqs; |
db0d4db2 | 381 | void __iomem *base = gic_data_dist_base(gic); |
f27ecacc | 382 | |
6ac77e46 | 383 | writel_relaxed(0, base + GIC_DIST_CTRL); |
f27ecacc | 384 | |
f27ecacc RK |
385 | /* |
386 | * Set all global interrupts to be level triggered, active low. | |
387 | */ | |
e6afec9b | 388 | for (i = 32; i < gic_irqs; i += 16) |
6ac77e46 | 389 | writel_relaxed(0, base + GIC_DIST_CONFIG + i * 4 / 16); |
f27ecacc RK |
390 | |
391 | /* | |
392 | * Set all global interrupts to this CPU only. | |
393 | */ | |
2bb31351 RK |
394 | cpumask = gic_get_cpumask(gic); |
395 | cpumask |= cpumask << 8; | |
396 | cpumask |= cpumask << 16; | |
e6afec9b | 397 | for (i = 32; i < gic_irqs; i += 4) |
6ac77e46 | 398 | writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); |
f27ecacc RK |
399 | |
400 | /* | |
9395f6ea | 401 | * Set priority on all global interrupts. |
f27ecacc | 402 | */ |
e6afec9b | 403 | for (i = 32; i < gic_irqs; i += 4) |
6ac77e46 | 404 | writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4); |
f27ecacc RK |
405 | |
406 | /* | |
9395f6ea RK |
407 | * Disable all interrupts. Leave the PPI and SGIs alone |
408 | * as these enables are banked registers. | |
f27ecacc | 409 | */ |
e6afec9b | 410 | for (i = 32; i < gic_irqs; i += 32) |
6ac77e46 | 411 | writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32); |
f27ecacc | 412 | |
6ac77e46 | 413 | writel_relaxed(1, base + GIC_DIST_CTRL); |
f27ecacc RK |
414 | } |
415 | ||
8c37bb3a | 416 | static void gic_cpu_init(struct gic_chip_data *gic) |
f27ecacc | 417 | { |
db0d4db2 MZ |
418 | void __iomem *dist_base = gic_data_dist_base(gic); |
419 | void __iomem *base = gic_data_cpu_base(gic); | |
384a2902 | 420 | unsigned int cpu_mask, cpu = smp_processor_id(); |
9395f6ea RK |
421 | int i; |
422 | ||
384a2902 NP |
423 | /* |
424 | * Get what the GIC says our CPU mask is. | |
425 | */ | |
426 | BUG_ON(cpu >= NR_GIC_CPU_IF); | |
2bb31351 | 427 | cpu_mask = gic_get_cpumask(gic); |
384a2902 NP |
428 | gic_cpu_map[cpu] = cpu_mask; |
429 | ||
430 | /* | |
431 | * Clear our mask from the other map entries in case they're | |
432 | * still undefined. | |
433 | */ | |
434 | for (i = 0; i < NR_GIC_CPU_IF; i++) | |
435 | if (i != cpu) | |
436 | gic_cpu_map[i] &= ~cpu_mask; | |
437 | ||
9395f6ea RK |
438 | /* |
439 | * Deal with the banked PPI and SGI interrupts - disable all | |
440 | * PPI interrupts, ensure all SGI interrupts are enabled. | |
441 | */ | |
6ac77e46 SS |
442 | writel_relaxed(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR); |
443 | writel_relaxed(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET); | |
9395f6ea RK |
444 | |
445 | /* | |
446 | * Set priority on PPI and SGI interrupts | |
447 | */ | |
448 | for (i = 0; i < 32; i += 4) | |
6ac77e46 | 449 | writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4); |
9395f6ea | 450 | |
6ac77e46 SS |
451 | writel_relaxed(0xf0, base + GIC_CPU_PRIMASK); |
452 | writel_relaxed(1, base + GIC_CPU_CTRL); | |
f27ecacc RK |
453 | } |
454 | ||
10d9eb8a NP |
455 | void gic_cpu_if_down(void) |
456 | { | |
457 | void __iomem *cpu_base = gic_data_cpu_base(&gic_data[0]); | |
458 | writel_relaxed(0, cpu_base + GIC_CPU_CTRL); | |
459 | } | |
460 | ||
254056f3 CC |
461 | #ifdef CONFIG_CPU_PM |
462 | /* | |
463 | * Saves the GIC distributor registers during suspend or idle. Must be called | |
464 | * with interrupts disabled but before powering down the GIC. After calling | |
465 | * this function, no interrupts will be delivered by the GIC, and another | |
466 | * platform-specific wakeup source must be enabled. | |
467 | */ | |
468 | static void gic_dist_save(unsigned int gic_nr) | |
469 | { | |
470 | unsigned int gic_irqs; | |
471 | void __iomem *dist_base; | |
472 | int i; | |
473 | ||
474 | if (gic_nr >= MAX_GIC_NR) | |
475 | BUG(); | |
476 | ||
477 | gic_irqs = gic_data[gic_nr].gic_irqs; | |
db0d4db2 | 478 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); |
254056f3 CC |
479 | |
480 | if (!dist_base) | |
481 | return; | |
482 | ||
483 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) | |
484 | gic_data[gic_nr].saved_spi_conf[i] = | |
485 | readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); | |
486 | ||
487 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) | |
488 | gic_data[gic_nr].saved_spi_target[i] = | |
489 | readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); | |
490 | ||
491 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) | |
492 | gic_data[gic_nr].saved_spi_enable[i] = | |
493 | readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); | |
494 | } | |
495 | ||
496 | /* | |
497 | * Restores the GIC distributor registers during resume or when coming out of | |
498 | * idle. Must be called before enabling interrupts. If a level interrupt | |
499 | * that occured while the GIC was suspended is still present, it will be | |
500 | * handled normally, but any edge interrupts that occured will not be seen by | |
501 | * the GIC and need to be handled by the platform-specific wakeup source. | |
502 | */ | |
503 | static void gic_dist_restore(unsigned int gic_nr) | |
504 | { | |
505 | unsigned int gic_irqs; | |
506 | unsigned int i; | |
507 | void __iomem *dist_base; | |
508 | ||
509 | if (gic_nr >= MAX_GIC_NR) | |
510 | BUG(); | |
511 | ||
512 | gic_irqs = gic_data[gic_nr].gic_irqs; | |
db0d4db2 | 513 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); |
254056f3 CC |
514 | |
515 | if (!dist_base) | |
516 | return; | |
517 | ||
518 | writel_relaxed(0, dist_base + GIC_DIST_CTRL); | |
519 | ||
520 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) | |
521 | writel_relaxed(gic_data[gic_nr].saved_spi_conf[i], | |
522 | dist_base + GIC_DIST_CONFIG + i * 4); | |
523 | ||
524 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) | |
525 | writel_relaxed(0xa0a0a0a0, | |
526 | dist_base + GIC_DIST_PRI + i * 4); | |
527 | ||
528 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) | |
529 | writel_relaxed(gic_data[gic_nr].saved_spi_target[i], | |
530 | dist_base + GIC_DIST_TARGET + i * 4); | |
531 | ||
532 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) | |
533 | writel_relaxed(gic_data[gic_nr].saved_spi_enable[i], | |
534 | dist_base + GIC_DIST_ENABLE_SET + i * 4); | |
535 | ||
536 | writel_relaxed(1, dist_base + GIC_DIST_CTRL); | |
537 | } | |
538 | ||
539 | static void gic_cpu_save(unsigned int gic_nr) | |
540 | { | |
541 | int i; | |
542 | u32 *ptr; | |
543 | void __iomem *dist_base; | |
544 | void __iomem *cpu_base; | |
545 | ||
546 | if (gic_nr >= MAX_GIC_NR) | |
547 | BUG(); | |
548 | ||
db0d4db2 MZ |
549 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); |
550 | cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); | |
254056f3 CC |
551 | |
552 | if (!dist_base || !cpu_base) | |
553 | return; | |
554 | ||
555 | ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_enable); | |
556 | for (i = 0; i < DIV_ROUND_UP(32, 32); i++) | |
557 | ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); | |
558 | ||
559 | ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_conf); | |
560 | for (i = 0; i < DIV_ROUND_UP(32, 16); i++) | |
561 | ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); | |
562 | ||
563 | } | |
564 | ||
565 | static void gic_cpu_restore(unsigned int gic_nr) | |
566 | { | |
567 | int i; | |
568 | u32 *ptr; | |
569 | void __iomem *dist_base; | |
570 | void __iomem *cpu_base; | |
571 | ||
572 | if (gic_nr >= MAX_GIC_NR) | |
573 | BUG(); | |
574 | ||
db0d4db2 MZ |
575 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); |
576 | cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); | |
254056f3 CC |
577 | |
578 | if (!dist_base || !cpu_base) | |
579 | return; | |
580 | ||
581 | ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_enable); | |
582 | for (i = 0; i < DIV_ROUND_UP(32, 32); i++) | |
583 | writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4); | |
584 | ||
585 | ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_conf); | |
586 | for (i = 0; i < DIV_ROUND_UP(32, 16); i++) | |
587 | writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4); | |
588 | ||
589 | for (i = 0; i < DIV_ROUND_UP(32, 4); i++) | |
590 | writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4); | |
591 | ||
592 | writel_relaxed(0xf0, cpu_base + GIC_CPU_PRIMASK); | |
593 | writel_relaxed(1, cpu_base + GIC_CPU_CTRL); | |
594 | } | |
595 | ||
596 | static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v) | |
597 | { | |
598 | int i; | |
599 | ||
600 | for (i = 0; i < MAX_GIC_NR; i++) { | |
db0d4db2 MZ |
601 | #ifdef CONFIG_GIC_NON_BANKED |
602 | /* Skip over unused GICs */ | |
603 | if (!gic_data[i].get_base) | |
604 | continue; | |
605 | #endif | |
254056f3 CC |
606 | switch (cmd) { |
607 | case CPU_PM_ENTER: | |
608 | gic_cpu_save(i); | |
609 | break; | |
610 | case CPU_PM_ENTER_FAILED: | |
611 | case CPU_PM_EXIT: | |
612 | gic_cpu_restore(i); | |
613 | break; | |
614 | case CPU_CLUSTER_PM_ENTER: | |
615 | gic_dist_save(i); | |
616 | break; | |
617 | case CPU_CLUSTER_PM_ENTER_FAILED: | |
618 | case CPU_CLUSTER_PM_EXIT: | |
619 | gic_dist_restore(i); | |
620 | break; | |
621 | } | |
622 | } | |
623 | ||
624 | return NOTIFY_OK; | |
625 | } | |
626 | ||
627 | static struct notifier_block gic_notifier_block = { | |
628 | .notifier_call = gic_notifier, | |
629 | }; | |
630 | ||
631 | static void __init gic_pm_init(struct gic_chip_data *gic) | |
632 | { | |
633 | gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, | |
634 | sizeof(u32)); | |
635 | BUG_ON(!gic->saved_ppi_enable); | |
636 | ||
637 | gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4, | |
638 | sizeof(u32)); | |
639 | BUG_ON(!gic->saved_ppi_conf); | |
640 | ||
abdd7b91 MZ |
641 | if (gic == &gic_data[0]) |
642 | cpu_pm_register_notifier(&gic_notifier_block); | |
254056f3 CC |
643 | } |
644 | #else | |
645 | static void __init gic_pm_init(struct gic_chip_data *gic) | |
646 | { | |
647 | } | |
648 | #endif | |
649 | ||
b1cffebf RH |
650 | #ifdef CONFIG_SMP |
651 | void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) | |
652 | { | |
653 | int cpu; | |
1a6b69b6 NP |
654 | unsigned long flags, map = 0; |
655 | ||
656 | raw_spin_lock_irqsave(&irq_controller_lock, flags); | |
b1cffebf RH |
657 | |
658 | /* Convert our logical CPU mask into a physical one. */ | |
659 | for_each_cpu(cpu, mask) | |
91bdf0d0 | 660 | map |= gic_cpu_map[cpu]; |
b1cffebf RH |
661 | |
662 | /* | |
663 | * Ensure that stores to Normal memory are visible to the | |
664 | * other CPUs before issuing the IPI. | |
665 | */ | |
666 | dsb(); | |
667 | ||
668 | /* this always happens on GIC0 */ | |
669 | writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); | |
1a6b69b6 NP |
670 | |
671 | raw_spin_unlock_irqrestore(&irq_controller_lock, flags); | |
672 | } | |
673 | #endif | |
674 | ||
675 | #ifdef CONFIG_BL_SWITCHER | |
14d2ca61 NP |
676 | /* |
677 | * gic_send_sgi - send a SGI directly to given CPU interface number | |
678 | * | |
679 | * cpu_id: the ID for the destination CPU interface | |
680 | * irq: the IPI number to send a SGI for | |
681 | */ | |
682 | void gic_send_sgi(unsigned int cpu_id, unsigned int irq) | |
683 | { | |
684 | BUG_ON(cpu_id >= NR_GIC_CPU_IF); | |
685 | cpu_id = 1 << cpu_id; | |
686 | /* this always happens on GIC0 */ | |
687 | writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); | |
688 | } | |
689 | ||
ed96762e NP |
690 | /* |
691 | * gic_get_cpu_id - get the CPU interface ID for the specified CPU | |
692 | * | |
693 | * @cpu: the logical CPU number to get the GIC ID for. | |
694 | * | |
695 | * Return the CPU interface ID for the given logical CPU number, | |
696 | * or -1 if the CPU number is too large or the interface ID is | |
697 | * unknown (more than one bit set). | |
698 | */ | |
699 | int gic_get_cpu_id(unsigned int cpu) | |
700 | { | |
701 | unsigned int cpu_bit; | |
702 | ||
703 | if (cpu >= NR_GIC_CPU_IF) | |
704 | return -1; | |
705 | cpu_bit = gic_cpu_map[cpu]; | |
706 | if (cpu_bit & (cpu_bit - 1)) | |
707 | return -1; | |
708 | return __ffs(cpu_bit); | |
709 | } | |
710 | ||
1a6b69b6 NP |
711 | /* |
712 | * gic_migrate_target - migrate IRQs to another CPU interface | |
713 | * | |
714 | * @new_cpu_id: the CPU target ID to migrate IRQs to | |
715 | * | |
716 | * Migrate all peripheral interrupts with a target matching the current CPU | |
717 | * to the interface corresponding to @new_cpu_id. The CPU interface mapping | |
718 | * is also updated. Targets to other CPU interfaces are unchanged. | |
719 | * This must be called with IRQs locally disabled. | |
720 | */ | |
721 | void gic_migrate_target(unsigned int new_cpu_id) | |
722 | { | |
723 | unsigned int cur_cpu_id, gic_irqs, gic_nr = 0; | |
724 | void __iomem *dist_base; | |
725 | int i, ror_val, cpu = smp_processor_id(); | |
726 | u32 val, cur_target_mask, active_mask; | |
727 | ||
728 | if (gic_nr >= MAX_GIC_NR) | |
729 | BUG(); | |
730 | ||
731 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); | |
732 | if (!dist_base) | |
733 | return; | |
734 | gic_irqs = gic_data[gic_nr].gic_irqs; | |
735 | ||
736 | cur_cpu_id = __ffs(gic_cpu_map[cpu]); | |
737 | cur_target_mask = 0x01010101 << cur_cpu_id; | |
738 | ror_val = (cur_cpu_id - new_cpu_id) & 31; | |
739 | ||
740 | raw_spin_lock(&irq_controller_lock); | |
741 | ||
742 | /* Update the target interface for this logical CPU */ | |
743 | gic_cpu_map[cpu] = 1 << new_cpu_id; | |
744 | ||
745 | /* | |
746 | * Find all the peripheral interrupts targetting the current | |
747 | * CPU interface and migrate them to the new CPU interface. | |
748 | * We skip DIST_TARGET 0 to 7 as they are read-only. | |
749 | */ | |
750 | for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) { | |
751 | val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); | |
752 | active_mask = val & cur_target_mask; | |
753 | if (active_mask) { | |
754 | val &= ~active_mask; | |
755 | val |= ror32(active_mask, ror_val); | |
756 | writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4); | |
757 | } | |
758 | } | |
759 | ||
760 | raw_spin_unlock(&irq_controller_lock); | |
761 | ||
762 | /* | |
763 | * Now let's migrate and clear any potential SGIs that might be | |
764 | * pending for us (cur_cpu_id). Since GIC_DIST_SGI_PENDING_SET | |
765 | * is a banked register, we can only forward the SGI using | |
766 | * GIC_DIST_SOFTINT. The original SGI source is lost but Linux | |
767 | * doesn't use that information anyway. | |
768 | * | |
769 | * For the same reason we do not adjust SGI source information | |
770 | * for previously sent SGIs by us to other CPUs either. | |
771 | */ | |
772 | for (i = 0; i < 16; i += 4) { | |
773 | int j; | |
774 | val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i); | |
775 | if (!val) | |
776 | continue; | |
777 | writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i); | |
778 | for (j = i; j < i + 4; j++) { | |
779 | if (val & 0xff) | |
780 | writel_relaxed((1 << (new_cpu_id + 16)) | j, | |
781 | dist_base + GIC_DIST_SOFTINT); | |
782 | val >>= 8; | |
783 | } | |
784 | } | |
b1cffebf | 785 | } |
eeb44658 NP |
786 | |
787 | /* | |
788 | * gic_get_sgir_physaddr - get the physical address for the SGI register | |
789 | * | |
790 | * REturn the physical address of the SGI register to be used | |
791 | * by some early assembly code when the kernel is not yet available. | |
792 | */ | |
793 | static unsigned long gic_dist_physaddr; | |
794 | ||
795 | unsigned long gic_get_sgir_physaddr(void) | |
796 | { | |
797 | if (!gic_dist_physaddr) | |
798 | return 0; | |
799 | return gic_dist_physaddr + GIC_DIST_SOFTINT; | |
800 | } | |
801 | ||
802 | void __init gic_init_physaddr(struct device_node *node) | |
803 | { | |
804 | struct resource res; | |
805 | if (of_address_to_resource(node, 0, &res) == 0) { | |
806 | gic_dist_physaddr = res.start; | |
807 | pr_info("GIC physical location is %#lx\n", gic_dist_physaddr); | |
808 | } | |
809 | } | |
810 | ||
811 | #else | |
812 | #define gic_init_physaddr(node) do { } while (0) | |
b1cffebf RH |
813 | #endif |
814 | ||
75294957 GL |
815 | static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, |
816 | irq_hw_number_t hw) | |
817 | { | |
818 | if (hw < 32) { | |
819 | irq_set_percpu_devid(irq); | |
820 | irq_set_chip_and_handler(irq, &gic_chip, | |
821 | handle_percpu_devid_irq); | |
822 | set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN); | |
823 | } else { | |
824 | irq_set_chip_and_handler(irq, &gic_chip, | |
825 | handle_fasteoi_irq); | |
826 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | |
827 | } | |
828 | irq_set_chip_data(irq, d->host_data); | |
829 | return 0; | |
830 | } | |
831 | ||
7bb69bad GL |
832 | static int gic_irq_domain_xlate(struct irq_domain *d, |
833 | struct device_node *controller, | |
834 | const u32 *intspec, unsigned int intsize, | |
835 | unsigned long *out_hwirq, unsigned int *out_type) | |
b3f7ed03 RH |
836 | { |
837 | if (d->of_node != controller) | |
838 | return -EINVAL; | |
839 | if (intsize < 3) | |
840 | return -EINVAL; | |
841 | ||
842 | /* Get the interrupt number and add 16 to skip over SGIs */ | |
843 | *out_hwirq = intspec[1] + 16; | |
844 | ||
845 | /* For SPIs, we need to add 16 more to get the GIC irq ID number */ | |
846 | if (!intspec[0]) | |
847 | *out_hwirq += 16; | |
848 | ||
849 | *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; | |
850 | return 0; | |
851 | } | |
b3f7ed03 | 852 | |
c0114709 | 853 | #ifdef CONFIG_SMP |
8c37bb3a PG |
854 | static int gic_secondary_init(struct notifier_block *nfb, unsigned long action, |
855 | void *hcpu) | |
c0114709 | 856 | { |
8b6fd652 | 857 | if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) |
c0114709 CM |
858 | gic_cpu_init(&gic_data[0]); |
859 | return NOTIFY_OK; | |
860 | } | |
861 | ||
862 | /* | |
863 | * Notifier for enabling the GIC CPU interface. Set an arbitrarily high | |
864 | * priority because the GIC needs to be up before the ARM generic timers. | |
865 | */ | |
8c37bb3a | 866 | static struct notifier_block gic_cpu_notifier = { |
c0114709 CM |
867 | .notifier_call = gic_secondary_init, |
868 | .priority = 100, | |
869 | }; | |
870 | #endif | |
871 | ||
15a25980 | 872 | const struct irq_domain_ops gic_irq_domain_ops = { |
75294957 | 873 | .map = gic_irq_domain_map, |
7bb69bad | 874 | .xlate = gic_irq_domain_xlate, |
4294f8ba RH |
875 | }; |
876 | ||
db0d4db2 MZ |
877 | void __init gic_init_bases(unsigned int gic_nr, int irq_start, |
878 | void __iomem *dist_base, void __iomem *cpu_base, | |
75294957 | 879 | u32 percpu_offset, struct device_node *node) |
b580b899 | 880 | { |
75294957 | 881 | irq_hw_number_t hwirq_base; |
bef8f9ee | 882 | struct gic_chip_data *gic; |
384a2902 | 883 | int gic_irqs, irq_base, i; |
bef8f9ee RK |
884 | |
885 | BUG_ON(gic_nr >= MAX_GIC_NR); | |
886 | ||
887 | gic = &gic_data[gic_nr]; | |
db0d4db2 MZ |
888 | #ifdef CONFIG_GIC_NON_BANKED |
889 | if (percpu_offset) { /* Frankein-GIC without banked registers... */ | |
890 | unsigned int cpu; | |
891 | ||
892 | gic->dist_base.percpu_base = alloc_percpu(void __iomem *); | |
893 | gic->cpu_base.percpu_base = alloc_percpu(void __iomem *); | |
894 | if (WARN_ON(!gic->dist_base.percpu_base || | |
895 | !gic->cpu_base.percpu_base)) { | |
896 | free_percpu(gic->dist_base.percpu_base); | |
897 | free_percpu(gic->cpu_base.percpu_base); | |
898 | return; | |
899 | } | |
900 | ||
901 | for_each_possible_cpu(cpu) { | |
902 | unsigned long offset = percpu_offset * cpu_logical_map(cpu); | |
903 | *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = dist_base + offset; | |
904 | *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset; | |
905 | } | |
906 | ||
907 | gic_set_base_accessor(gic, gic_get_percpu_base); | |
908 | } else | |
909 | #endif | |
910 | { /* Normal, sane GIC... */ | |
911 | WARN(percpu_offset, | |
912 | "GIC_NON_BANKED not enabled, ignoring %08x offset!", | |
913 | percpu_offset); | |
914 | gic->dist_base.common_base = dist_base; | |
915 | gic->cpu_base.common_base = cpu_base; | |
916 | gic_set_base_accessor(gic, gic_get_common_base); | |
917 | } | |
bef8f9ee | 918 | |
384a2902 NP |
919 | /* |
920 | * Initialize the CPU interface map to all CPUs. | |
921 | * It will be refined as each CPU probes its ID. | |
922 | */ | |
923 | for (i = 0; i < NR_GIC_CPU_IF; i++) | |
924 | gic_cpu_map[i] = 0xff; | |
925 | ||
4294f8ba RH |
926 | /* |
927 | * For primary GICs, skip over SGIs. | |
928 | * For secondary GICs, skip over PPIs, too. | |
929 | */ | |
e0b823e9 | 930 | if (gic_nr == 0 && (irq_start & 31) > 0) { |
12679a2d | 931 | hwirq_base = 16; |
e0b823e9 WD |
932 | if (irq_start != -1) |
933 | irq_start = (irq_start & ~31) + 16; | |
934 | } else { | |
12679a2d | 935 | hwirq_base = 32; |
fe41db7b | 936 | } |
4294f8ba RH |
937 | |
938 | /* | |
939 | * Find out how many interrupts are supported. | |
940 | * The GIC only supports up to 1020 interrupt sources. | |
941 | */ | |
db0d4db2 | 942 | gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f; |
4294f8ba RH |
943 | gic_irqs = (gic_irqs + 1) * 32; |
944 | if (gic_irqs > 1020) | |
945 | gic_irqs = 1020; | |
946 | gic->gic_irqs = gic_irqs; | |
947 | ||
75294957 GL |
948 | gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */ |
949 | irq_base = irq_alloc_descs(irq_start, 16, gic_irqs, numa_node_id()); | |
950 | if (IS_ERR_VALUE(irq_base)) { | |
f37a53cc RH |
951 | WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n", |
952 | irq_start); | |
75294957 | 953 | irq_base = irq_start; |
f37a53cc | 954 | } |
75294957 GL |
955 | gic->domain = irq_domain_add_legacy(node, gic_irqs, irq_base, |
956 | hwirq_base, &gic_irq_domain_ops, gic); | |
957 | if (WARN_ON(!gic->domain)) | |
958 | return; | |
bef8f9ee | 959 | |
b1cffebf RH |
960 | #ifdef CONFIG_SMP |
961 | set_smp_cross_call(gic_raise_softirq); | |
c0114709 | 962 | register_cpu_notifier(&gic_cpu_notifier); |
b1cffebf | 963 | #endif |
cfed7d60 RH |
964 | |
965 | set_handle_irq(gic_handle_irq); | |
966 | ||
9c12845e | 967 | gic_chip.flags |= gic_arch_extn.flags; |
4294f8ba | 968 | gic_dist_init(gic); |
bef8f9ee | 969 | gic_cpu_init(gic); |
254056f3 | 970 | gic_pm_init(gic); |
b580b899 RK |
971 | } |
972 | ||
b3f7ed03 | 973 | #ifdef CONFIG_OF |
46f101df | 974 | static int gic_cnt __initdata; |
b3f7ed03 RH |
975 | |
976 | int __init gic_of_init(struct device_node *node, struct device_node *parent) | |
977 | { | |
978 | void __iomem *cpu_base; | |
979 | void __iomem *dist_base; | |
db0d4db2 | 980 | u32 percpu_offset; |
b3f7ed03 | 981 | int irq; |
b3f7ed03 RH |
982 | |
983 | if (WARN_ON(!node)) | |
984 | return -ENODEV; | |
985 | ||
986 | dist_base = of_iomap(node, 0); | |
987 | WARN(!dist_base, "unable to map gic dist registers\n"); | |
988 | ||
989 | cpu_base = of_iomap(node, 1); | |
990 | WARN(!cpu_base, "unable to map gic cpu registers\n"); | |
991 | ||
db0d4db2 MZ |
992 | if (of_property_read_u32(node, "cpu-offset", &percpu_offset)) |
993 | percpu_offset = 0; | |
994 | ||
75294957 | 995 | gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, node); |
eeb44658 NP |
996 | if (!gic_cnt) |
997 | gic_init_physaddr(node); | |
b3f7ed03 RH |
998 | |
999 | if (parent) { | |
1000 | irq = irq_of_parse_and_map(node, 0); | |
1001 | gic_cascade_irq(gic_cnt, irq); | |
1002 | } | |
1003 | gic_cnt++; | |
1004 | return 0; | |
1005 | } | |
81243e44 RH |
1006 | IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init); |
1007 | IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init); | |
1008 | IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); | |
1009 | IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init); | |
1010 | ||
b3f7ed03 | 1011 | #endif |