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Merge branch 'timer/cleanup' into late/mvebu2
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / iommu / tegra-smmu.c
CommitLineData
7a31f6f4
HD		 1/*
2 * IOMMU API for SMMU in Tegra30
3 *
4 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 */
19
20#define pr_fmt(fmt) "%s(): " fmt, __func__
21
22#include <linux/module.h>
23#include <linux/platform_device.h>
24#include <linux/spinlock.h>
25#include <linux/slab.h>
26#include <linux/vmalloc.h>
27#include <linux/mm.h>
28#include <linux/pagemap.h>
29#include <linux/device.h>
30#include <linux/sched.h>
31#include <linux/iommu.h>
32#include <linux/io.h>
0760e8fa
HD		 33#include <linux/of.h>
34#include <linux/of_iommu.h>
39abf8aa
HD		 35#include <linux/debugfs.h>
36#include <linux/seq_file.h>
cc95e347 37#include <linux/tegra-ahb.h>
7a31f6f4
HD		 38
39#include <asm/page.h>
40#include <asm/cacheflush.h>
41
e6bc5933
SW		 42enum smmu_hwgrp {
43 HWGRP_AFI,
44 HWGRP_AVPC,
45 HWGRP_DC,
46 HWGRP_DCB,
47 HWGRP_EPP,
48 HWGRP_G2,
49 HWGRP_HC,
50 HWGRP_HDA,
51 HWGRP_ISP,
52 HWGRP_MPE,
53 HWGRP_NV,
54 HWGRP_NV2,
55 HWGRP_PPCS,
56 HWGRP_SATA,
57 HWGRP_VDE,
58 HWGRP_VI,
59
60 HWGRP_COUNT,
61
62 HWGRP_END = ~0,
63};
64
65#define HWG_AFI (1 << HWGRP_AFI)
66#define HWG_AVPC (1 << HWGRP_AVPC)
67#define HWG_DC (1 << HWGRP_DC)
68#define HWG_DCB (1 << HWGRP_DCB)
69#define HWG_EPP (1 << HWGRP_EPP)
70#define HWG_G2 (1 << HWGRP_G2)
71#define HWG_HC (1 << HWGRP_HC)
72#define HWG_HDA (1 << HWGRP_HDA)
73#define HWG_ISP (1 << HWGRP_ISP)
74#define HWG_MPE (1 << HWGRP_MPE)
75#define HWG_NV (1 << HWGRP_NV)
76#define HWG_NV2 (1 << HWGRP_NV2)
77#define HWG_PPCS (1 << HWGRP_PPCS)
78#define HWG_SATA (1 << HWGRP_SATA)
79#define HWG_VDE (1 << HWGRP_VDE)
80#define HWG_VI (1 << HWGRP_VI)
81
7a31f6f4
HD		 82/* bitmap of the page sizes currently supported */
83#define SMMU_IOMMU_PGSIZES (SZ_4K)
84
85#define SMMU_CONFIG 0x10
86#define SMMU_CONFIG_DISABLE 0
87#define SMMU_CONFIG_ENABLE 1
88
39abf8aa
HD		 89/* REVISIT: To support multiple MCs */
90enum {
91 _MC = 0,
92};
93
94enum {
95 _TLB = 0,
96 _PTC,
97};
98
99#define SMMU_CACHE_CONFIG_BASE 0x14
100#define __SMMU_CACHE_CONFIG(mc, cache) (SMMU_CACHE_CONFIG_BASE + 4 * cache)
101#define SMMU_CACHE_CONFIG(cache) __SMMU_CACHE_CONFIG(_MC, cache)
102
103#define SMMU_CACHE_CONFIG_STATS_SHIFT 31
104#define SMMU_CACHE_CONFIG_STATS_ENABLE (1 << SMMU_CACHE_CONFIG_STATS_SHIFT)
105#define SMMU_CACHE_CONFIG_STATS_TEST_SHIFT 30
106#define SMMU_CACHE_CONFIG_STATS_TEST (1 << SMMU_CACHE_CONFIG_STATS_TEST_SHIFT)
107
7a31f6f4
HD		 108#define SMMU_TLB_CONFIG_HIT_UNDER_MISS__ENABLE (1 << 29)
109#define SMMU_TLB_CONFIG_ACTIVE_LINES__VALUE 0x10
110#define SMMU_TLB_CONFIG_RESET_VAL 0x20000010
111
7a31f6f4
HD		 112#define SMMU_PTC_CONFIG_CACHE__ENABLE (1 << 29)
113#define SMMU_PTC_CONFIG_INDEX_MAP__PATTERN 0x3f
114#define SMMU_PTC_CONFIG_RESET_VAL 0x2000003f
115
116#define SMMU_PTB_ASID 0x1c
117#define SMMU_PTB_ASID_CURRENT_SHIFT 0
118
119#define SMMU_PTB_DATA 0x20
120#define SMMU_PTB_DATA_RESET_VAL 0
121#define SMMU_PTB_DATA_ASID_NONSECURE_SHIFT 29
122#define SMMU_PTB_DATA_ASID_WRITABLE_SHIFT 30
123#define SMMU_PTB_DATA_ASID_READABLE_SHIFT 31
124
125#define SMMU_TLB_FLUSH 0x30
126#define SMMU_TLB_FLUSH_VA_MATCH_ALL 0
127#define SMMU_TLB_FLUSH_VA_MATCH_SECTION 2
128#define SMMU_TLB_FLUSH_VA_MATCH_GROUP 3
129#define SMMU_TLB_FLUSH_ASID_SHIFT 29
130#define SMMU_TLB_FLUSH_ASID_MATCH_DISABLE 0
131#define SMMU_TLB_FLUSH_ASID_MATCH_ENABLE 1
132#define SMMU_TLB_FLUSH_ASID_MATCH_SHIFT 31
133
134#define SMMU_PTC_FLUSH 0x34
135#define SMMU_PTC_FLUSH_TYPE_ALL 0
136#define SMMU_PTC_FLUSH_TYPE_ADR 1
137#define SMMU_PTC_FLUSH_ADR_SHIFT 4
138
139#define SMMU_ASID_SECURITY 0x38
140
39abf8aa
HD		 141#define SMMU_STATS_CACHE_COUNT_BASE 0x1f0
142
143#define SMMU_STATS_CACHE_COUNT(mc, cache, hitmiss) \
144 (SMMU_STATS_CACHE_COUNT_BASE + 8 * cache + 4 * hitmiss)
7a31f6f4
HD		 145
146#define SMMU_TRANSLATION_ENABLE_0 0x228
147#define SMMU_TRANSLATION_ENABLE_1 0x22c
148#define SMMU_TRANSLATION_ENABLE_2 0x230
149
150#define SMMU_AFI_ASID 0x238 /* PCIE */
151#define SMMU_AVPC_ASID 0x23c /* AVP */
152#define SMMU_DC_ASID 0x240 /* Display controller */
153#define SMMU_DCB_ASID 0x244 /* Display controller B */
154#define SMMU_EPP_ASID 0x248 /* Encoder pre-processor */
155#define SMMU_G2_ASID 0x24c /* 2D engine */
156#define SMMU_HC_ASID 0x250 /* Host1x */
157#define SMMU_HDA_ASID 0x254 /* High-def audio */
158#define SMMU_ISP_ASID 0x258 /* Image signal processor */
159#define SMMU_MPE_ASID 0x264 /* MPEG encoder */
160#define SMMU_NV_ASID 0x268 /* (3D) */
161#define SMMU_NV2_ASID 0x26c /* (3D) */
162#define SMMU_PPCS_ASID 0x270 /* AHB */
163#define SMMU_SATA_ASID 0x278 /* SATA */
164#define SMMU_VDE_ASID 0x27c /* Video decoder */
165#define SMMU_VI_ASID 0x280 /* Video input */
166
167#define SMMU_PDE_NEXT_SHIFT 28
168
7a31f6f4
HD		 169#define SMMU_TLB_FLUSH_VA_SECTION__MASK 0xffc00000
170#define SMMU_TLB_FLUSH_VA_SECTION__SHIFT 12 /* right shift */
171#define SMMU_TLB_FLUSH_VA_GROUP__MASK 0xffffc000
172#define SMMU_TLB_FLUSH_VA_GROUP__SHIFT 12 /* right shift */
173#define SMMU_TLB_FLUSH_VA(iova, which) \
174 ((((iova) & SMMU_TLB_FLUSH_VA_##which##__MASK) >> \
175 SMMU_TLB_FLUSH_VA_##which##__SHIFT) | \
176 SMMU_TLB_FLUSH_VA_MATCH_##which)
177#define SMMU_PTB_ASID_CUR(n) \
178 ((n) << SMMU_PTB_ASID_CURRENT_SHIFT)
179#define SMMU_TLB_FLUSH_ASID_MATCH_disable \
180 (SMMU_TLB_FLUSH_ASID_MATCH_DISABLE << \
181 SMMU_TLB_FLUSH_ASID_MATCH_SHIFT)
182#define SMMU_TLB_FLUSH_ASID_MATCH__ENABLE \
183 (SMMU_TLB_FLUSH_ASID_MATCH_ENABLE << \
184 SMMU_TLB_FLUSH_ASID_MATCH_SHIFT)
185
186#define SMMU_PAGE_SHIFT 12
187#define SMMU_PAGE_SIZE (1 << SMMU_PAGE_SHIFT)
0760e8fa 188#define SMMU_PAGE_MASK ((1 << SMMU_PAGE_SHIFT) - 1)
7a31f6f4
HD		 189
190#define SMMU_PDIR_COUNT 1024
191#define SMMU_PDIR_SIZE (sizeof(unsigned long) * SMMU_PDIR_COUNT)
192#define SMMU_PTBL_COUNT 1024
193#define SMMU_PTBL_SIZE (sizeof(unsigned long) * SMMU_PTBL_COUNT)
194#define SMMU_PDIR_SHIFT 12
195#define SMMU_PDE_SHIFT 12
196#define SMMU_PTE_SHIFT 12
197#define SMMU_PFN_MASK 0x000fffff
198
199#define SMMU_ADDR_TO_PFN(addr) ((addr) >> 12)
200#define SMMU_ADDR_TO_PDN(addr) ((addr) >> 22)
d0078e72 201#define SMMU_PDN_TO_ADDR(pdn) ((pdn) << 22)
7a31f6f4
HD		 202
203#define _READABLE (1 << SMMU_PTB_DATA_ASID_READABLE_SHIFT)
204#define _WRITABLE (1 << SMMU_PTB_DATA_ASID_WRITABLE_SHIFT)
205#define _NONSECURE (1 << SMMU_PTB_DATA_ASID_NONSECURE_SHIFT)
206#define _PDE_NEXT (1 << SMMU_PDE_NEXT_SHIFT)
207#define _MASK_ATTR (_READABLE | _WRITABLE | _NONSECURE)
208
209#define _PDIR_ATTR (_READABLE | _WRITABLE | _NONSECURE)
210
211#define _PDE_ATTR (_READABLE | _WRITABLE | _NONSECURE)
212#define _PDE_ATTR_N (_PDE_ATTR | _PDE_NEXT)
213#define _PDE_VACANT(pdn) (((pdn) << 10) | _PDE_ATTR)
214
215#define _PTE_ATTR (_READABLE | _WRITABLE | _NONSECURE)
216#define _PTE_VACANT(addr) (((addr) >> SMMU_PAGE_SHIFT) | _PTE_ATTR)
217
218#define SMMU_MK_PDIR(page, attr) \
219 ((page_to_phys(page) >> SMMU_PDIR_SHIFT) | (attr))
220#define SMMU_MK_PDE(page, attr) \
221 (unsigned long)((page_to_phys(page) >> SMMU_PDE_SHIFT) | (attr))
222#define SMMU_EX_PTBL_PAGE(pde) \
223 pfn_to_page((unsigned long)(pde) & SMMU_PFN_MASK)
224#define SMMU_PFN_TO_PTE(pfn, attr) (unsigned long)((pfn) | (attr))
225
226#define SMMU_ASID_ENABLE(asid) ((asid) | (1 << 31))
227#define SMMU_ASID_DISABLE 0
228#define SMMU_ASID_ASID(n) ((n) & ~SMMU_ASID_ENABLE(0))
229
0760e8fa
HD		 230#define NUM_SMMU_REG_BANKS 3
231
7a31f6f4
HD		 232#define smmu_client_enable_hwgrp(c, m) smmu_client_set_hwgrp(c, m, 1)
233#define smmu_client_disable_hwgrp(c) smmu_client_set_hwgrp(c, 0, 0)
234#define __smmu_client_enable_hwgrp(c, m) __smmu_client_set_hwgrp(c, m, 1)
235#define __smmu_client_disable_hwgrp(c) __smmu_client_set_hwgrp(c, 0, 0)
236
237#define HWGRP_INIT(client) [HWGRP_##client] = SMMU_##client##_ASID
238
239static const u32 smmu_hwgrp_asid_reg[] = {
240 HWGRP_INIT(AFI),
241 HWGRP_INIT(AVPC),
242 HWGRP_INIT(DC),
243 HWGRP_INIT(DCB),
244 HWGRP_INIT(EPP),
245 HWGRP_INIT(G2),
246 HWGRP_INIT(HC),
247 HWGRP_INIT(HDA),
248 HWGRP_INIT(ISP),
249 HWGRP_INIT(MPE),
250 HWGRP_INIT(NV),
251 HWGRP_INIT(NV2),
252 HWGRP_INIT(PPCS),
253 HWGRP_INIT(SATA),
254 HWGRP_INIT(VDE),
255 HWGRP_INIT(VI),
256};
257#define HWGRP_ASID_REG(x) (smmu_hwgrp_asid_reg[x])
258
259/*
260 * Per client for address space
261 */
262struct smmu_client {
263 struct device *dev;
264 struct list_head list;
265 struct smmu_as *as;
266 u32 hwgrp;
267};
268
269/*
270 * Per address space
271 */
272struct smmu_as {
273 struct smmu_device *smmu; /* back pointer to container */
274 unsigned int asid;
275 spinlock_t lock; /* for pagetable */
276 struct page *pdir_page;
277 unsigned long pdir_attr;
278 unsigned long pde_attr;
279 unsigned long pte_attr;
280 unsigned int *pte_count;
281
282 struct list_head client;
283 spinlock_t client_lock; /* for client list */
284};
285
5a2c937a
HD		 286struct smmu_debugfs_info {
287 struct smmu_device *smmu;
288 int mc;
289 int cache;
290};
291
7a31f6f4
HD		 292/*
293 * Per SMMU device - IOMMU device
294 */
295struct smmu_device {
0760e8fa 296 void __iomem *regs[NUM_SMMU_REG_BANKS];
7a31f6f4
HD		 297 unsigned long iovmm_base; /* remappable base address */
298 unsigned long page_count; /* total remappable size */
299 spinlock_t lock;
300 char *name;
301 struct device *dev;
7a31f6f4
HD		 302 struct page *avp_vector_page; /* dummy page shared by all AS's */
303
304 /*
305 * Register image savers for suspend/resume
306 */
307 unsigned long translation_enable_0;
308 unsigned long translation_enable_1;
309 unsigned long translation_enable_2;
310 unsigned long asid_security;
0760e8fa 311
39abf8aa 312 struct dentry *debugfs_root;
5a2c937a 313 struct smmu_debugfs_info *debugfs_info;
39abf8aa 314
0760e8fa 315 struct device_node *ahb;
a3b24915
HD		 316
317 int num_as;
318 struct smmu_as as[0]; /* Run-time allocated array */
7a31f6f4
HD		 319};
320
321static struct smmu_device *smmu_handle; /* unique for a system */
322
323/*
0760e8fa 324 * SMMU register accessors
7a31f6f4
HD		 325 */
326static inline u32 smmu_read(struct smmu_device *smmu, size_t offs)
327{
0760e8fa
HD		 328 BUG_ON(offs < 0x10);
329 if (offs < 0x3c)
330 return readl(smmu->regs[0] + offs - 0x10);
331 BUG_ON(offs < 0x1f0);
332 if (offs < 0x200)
333 return readl(smmu->regs[1] + offs - 0x1f0);
334 BUG_ON(offs < 0x228);
335 if (offs < 0x284)
336 return readl(smmu->regs[2] + offs - 0x228);
337 BUG();
7a31f6f4
HD		 338}
339
0760e8fa 340static inline void smmu_write(struct smmu_device *smmu, u32 val, size_t offs)
7a31f6f4 341{
0760e8fa
HD		 342 BUG_ON(offs < 0x10);
343 if (offs < 0x3c) {
344 writel(val, smmu->regs[0] + offs - 0x10);
345 return;
346 }
347 BUG_ON(offs < 0x1f0);
348 if (offs < 0x200) {
349 writel(val, smmu->regs[1] + offs - 0x1f0);
350 return;
351 }
352 BUG_ON(offs < 0x228);
353 if (offs < 0x284) {
354 writel(val, smmu->regs[2] + offs - 0x228);
355 return;
356 }
357 BUG();
7a31f6f4
HD		 358}
359
360#define VA_PAGE_TO_PA(va, page) \
361 (page_to_phys(page) + ((unsigned long)(va) & ~PAGE_MASK))
362
363#define FLUSH_CPU_DCACHE(va, page, size) \
364 do { \
365 unsigned long _pa_ = VA_PAGE_TO_PA(va, page); \
366 __cpuc_flush_dcache_area((void *)(va), (size_t)(size)); \
367 outer_flush_range(_pa_, _pa_+(size_t)(size)); \
368 } while (0)
369
370/*
371 * Any interaction between any block on PPSB and a block on APB or AHB
372 * must have these read-back barriers to ensure the APB/AHB bus
373 * transaction is complete before initiating activity on the PPSB
374 * block.
375 */
376#define FLUSH_SMMU_REGS(smmu) smmu_read(smmu, SMMU_CONFIG)
377
378#define smmu_client_hwgrp(c) (u32)((c)->dev->platform_data)
379
380static int __smmu_client_set_hwgrp(struct smmu_client *c,
381 unsigned long map, int on)
382{
383 int i;
384 struct smmu_as *as = c->as;
385 u32 val, offs, mask = SMMU_ASID_ENABLE(as->asid);
386 struct smmu_device *smmu = as->smmu;
387
388 WARN_ON(!on && map);
389 if (on && !map)
390 return -EINVAL;
391 if (!on)
392 map = smmu_client_hwgrp(c);
393
394 for_each_set_bit(i, &map, HWGRP_COUNT) {
395 offs = HWGRP_ASID_REG(i);
396 val = smmu_read(smmu, offs);
397 if (on) {
398 if (WARN_ON(val & mask))
399 goto err_hw_busy;
400 val |= mask;
401 } else {
402 WARN_ON((val & mask) == mask);
403 val &= ~mask;
404 }
405 smmu_write(smmu, val, offs);
406 }
407 FLUSH_SMMU_REGS(smmu);
408 c->hwgrp = map;
409 return 0;
410
411err_hw_busy:
412 for_each_set_bit(i, &map, HWGRP_COUNT) {
413 offs = HWGRP_ASID_REG(i);
414 val = smmu_read(smmu, offs);
415 val &= ~mask;
416 smmu_write(smmu, val, offs);
417 }
418 return -EBUSY;
419}
420
421static int smmu_client_set_hwgrp(struct smmu_client *c, u32 map, int on)
422{
423 u32 val;
424 unsigned long flags;
425 struct smmu_as *as = c->as;
426 struct smmu_device *smmu = as->smmu;
427
428 spin_lock_irqsave(&smmu->lock, flags);
429 val = __smmu_client_set_hwgrp(c, map, on);
430 spin_unlock_irqrestore(&smmu->lock, flags);
431 return val;
432}
433
434/*
435 * Flush all TLB entries and all PTC entries
436 * Caller must lock smmu
437 */
438static void smmu_flush_regs(struct smmu_device *smmu, int enable)
439{
440 u32 val;
441
442 smmu_write(smmu, SMMU_PTC_FLUSH_TYPE_ALL, SMMU_PTC_FLUSH);
443 FLUSH_SMMU_REGS(smmu);
444 val = SMMU_TLB_FLUSH_VA_MATCH_ALL |
445 SMMU_TLB_FLUSH_ASID_MATCH_disable;
446 smmu_write(smmu, val, SMMU_TLB_FLUSH);
447
448 if (enable)
449 smmu_write(smmu, SMMU_CONFIG_ENABLE, SMMU_CONFIG);
450 FLUSH_SMMU_REGS(smmu);
451}
452
0760e8fa 453static int smmu_setup_regs(struct smmu_device *smmu)
7a31f6f4
HD		 454{
455 int i;
456 u32 val;
457
458 for (i = 0; i < smmu->num_as; i++) {
459 struct smmu_as *as = &smmu->as[i];
460 struct smmu_client *c;
461
462 smmu_write(smmu, SMMU_PTB_ASID_CUR(as->asid), SMMU_PTB_ASID);
463 val = as->pdir_page ?
464 SMMU_MK_PDIR(as->pdir_page, as->pdir_attr) :
465 SMMU_PTB_DATA_RESET_VAL;
466 smmu_write(smmu, val, SMMU_PTB_DATA);
467
468 list_for_each_entry(c, &as->client, list)
469 __smmu_client_set_hwgrp(c, c->hwgrp, 1);
470 }
471
472 smmu_write(smmu, smmu->translation_enable_0, SMMU_TRANSLATION_ENABLE_0);
473 smmu_write(smmu, smmu->translation_enable_1, SMMU_TRANSLATION_ENABLE_1);
474 smmu_write(smmu, smmu->translation_enable_2, SMMU_TRANSLATION_ENABLE_2);
475 smmu_write(smmu, smmu->asid_security, SMMU_ASID_SECURITY);
39abf8aa
HD		 476 smmu_write(smmu, SMMU_TLB_CONFIG_RESET_VAL, SMMU_CACHE_CONFIG(_TLB));
477 smmu_write(smmu, SMMU_PTC_CONFIG_RESET_VAL, SMMU_CACHE_CONFIG(_PTC));
7a31f6f4
HD		 478
479 smmu_flush_regs(smmu, 1);
480
0760e8fa 481 return tegra_ahb_enable_smmu(smmu->ahb);
7a31f6f4
HD		 482}
483
484static void flush_ptc_and_tlb(struct smmu_device *smmu,
485 struct smmu_as *as, dma_addr_t iova,
486 unsigned long *pte, struct page *page, int is_pde)
487{
488 u32 val;
489 unsigned long tlb_flush_va = is_pde
490 ? SMMU_TLB_FLUSH_VA(iova, SECTION)
491 : SMMU_TLB_FLUSH_VA(iova, GROUP);
492
493 val = SMMU_PTC_FLUSH_TYPE_ADR | VA_PAGE_TO_PA(pte, page);
494 smmu_write(smmu, val, SMMU_PTC_FLUSH);
495 FLUSH_SMMU_REGS(smmu);
496 val = tlb_flush_va |
497 SMMU_TLB_FLUSH_ASID_MATCH__ENABLE |
498 (as->asid << SMMU_TLB_FLUSH_ASID_SHIFT);
499 smmu_write(smmu, val, SMMU_TLB_FLUSH);
500 FLUSH_SMMU_REGS(smmu);
501}
502
503static void free_ptbl(struct smmu_as *as, dma_addr_t iova)
504{
505 unsigned long pdn = SMMU_ADDR_TO_PDN(iova);
506 unsigned long *pdir = (unsigned long *)page_address(as->pdir_page);
507
508 if (pdir[pdn] != _PDE_VACANT(pdn)) {
509 dev_dbg(as->smmu->dev, "pdn: %lx\n", pdn);
510
511 ClearPageReserved(SMMU_EX_PTBL_PAGE(pdir[pdn]));
512 __free_page(SMMU_EX_PTBL_PAGE(pdir[pdn]));
513 pdir[pdn] = _PDE_VACANT(pdn);
514 FLUSH_CPU_DCACHE(&pdir[pdn], as->pdir_page, sizeof pdir[pdn]);
515 flush_ptc_and_tlb(as->smmu, as, iova, &pdir[pdn],
516 as->pdir_page, 1);
517 }
518}
519
520static void free_pdir(struct smmu_as *as)
521{
522 unsigned addr;
523 int count;
524 struct device *dev = as->smmu->dev;
525
526 if (!as->pdir_page)
527 return;
528
529 addr = as->smmu->iovmm_base;
530 count = as->smmu->page_count;
531 while (count-- > 0) {
532 free_ptbl(as, addr);
533 addr += SMMU_PAGE_SIZE * SMMU_PTBL_COUNT;
534 }
535 ClearPageReserved(as->pdir_page);
536 __free_page(as->pdir_page);
537 as->pdir_page = NULL;
538 devm_kfree(dev, as->pte_count);
539 as->pte_count = NULL;
540}
541
542/*
543 * Maps PTBL for given iova and returns the PTE address
544 * Caller must unmap the mapped PTBL returned in *ptbl_page_p
545 */
546static unsigned long *locate_pte(struct smmu_as *as,
547 dma_addr_t iova, bool allocate,
548 struct page **ptbl_page_p,
549 unsigned int **count)
550{
551 unsigned long ptn = SMMU_ADDR_TO_PFN(iova);
552 unsigned long pdn = SMMU_ADDR_TO_PDN(iova);
553 unsigned long *pdir = page_address(as->pdir_page);
554 unsigned long *ptbl;
555
556 if (pdir[pdn] != _PDE_VACANT(pdn)) {
557 /* Mapped entry table already exists */
558 *ptbl_page_p = SMMU_EX_PTBL_PAGE(pdir[pdn]);
559 ptbl = page_address(*ptbl_page_p);
560 } else if (!allocate) {
561 return NULL;
562 } else {
563 int pn;
564 unsigned long addr = SMMU_PDN_TO_ADDR(pdn);
565
566 /* Vacant - allocate a new page table */
567 dev_dbg(as->smmu->dev, "New PTBL pdn: %lx\n", pdn);
568
569 *ptbl_page_p = alloc_page(GFP_ATOMIC);
570 if (!*ptbl_page_p) {
571 dev_err(as->smmu->dev,
572 "failed to allocate smmu_device page table\n");
573 return NULL;
574 }
575 SetPageReserved(*ptbl_page_p);
576 ptbl = (unsigned long *)page_address(*ptbl_page_p);
577 for (pn = 0; pn < SMMU_PTBL_COUNT;
578 pn++, addr += SMMU_PAGE_SIZE) {
579 ptbl[pn] = _PTE_VACANT(addr);
580 }
581 FLUSH_CPU_DCACHE(ptbl, *ptbl_page_p, SMMU_PTBL_SIZE);
582 pdir[pdn] = SMMU_MK_PDE(*ptbl_page_p,
583 as->pde_attr | _PDE_NEXT);
584 FLUSH_CPU_DCACHE(&pdir[pdn], as->pdir_page, sizeof pdir[pdn]);
585 flush_ptc_and_tlb(as->smmu, as, iova, &pdir[pdn],
586 as->pdir_page, 1);
587 }
588 *count = &as->pte_count[pdn];
589
590 return &ptbl[ptn % SMMU_PTBL_COUNT];
591}
592
593#ifdef CONFIG_SMMU_SIG_DEBUG
594static void put_signature(struct smmu_as *as,
595 dma_addr_t iova, unsigned long pfn)
596{
597 struct page *page;
598 unsigned long *vaddr;
599
600 page = pfn_to_page(pfn);
601 vaddr = page_address(page);
602 if (!vaddr)
603 return;
604
605 vaddr[0] = iova;
606 vaddr[1] = pfn << PAGE_SHIFT;
607 FLUSH_CPU_DCACHE(vaddr, page, sizeof(vaddr[0]) * 2);
608}
609#else
610static inline void put_signature(struct smmu_as *as,
611 unsigned long addr, unsigned long pfn)
612{
613}
614#endif
615
616/*
f9a4f063 617 * Caller must not hold as->lock
7a31f6f4
HD		 618 */
619static int alloc_pdir(struct smmu_as *as)
620{
f9a4f063 621 unsigned long *pdir, flags;
9e971a03 622 int pdn, err = 0;
7a31f6f4
HD		 623 u32 val;
624 struct smmu_device *smmu = as->smmu;
9e971a03
HD		 625 struct page *page;
626 unsigned int *cnt;
7a31f6f4 627
9e971a03 628 /*
f9a4f063 629 * do the allocation, then grab as->lock
9e971a03 630 */
9e971a03 631 cnt = devm_kzalloc(smmu->dev,
f9a4f063
JR		 632 sizeof(cnt[0]) * SMMU_PDIR_COUNT,
633 GFP_KERNEL);
9e971a03 634 page = alloc_page(GFP_KERNEL | __GFP_DMA);
7a31f6f4 635
f9a4f063 636 spin_lock_irqsave(&as->lock, flags);
7a31f6f4 637
9e971a03
HD		 638 if (as->pdir_page) {
639 /* We raced, free the redundant */
640 err = -EAGAIN;
641 goto err_out;
7a31f6f4 642 }
9e971a03
HD		 643
644 if (!page || !cnt) {
645 dev_err(smmu->dev, "failed to allocate at %s\n", __func__);
646 err = -ENOMEM;
647 goto err_out;
7a31f6f4 648 }
9e971a03
HD		 649
650 as->pdir_page = page;
651 as->pte_count = cnt;
652
7a31f6f4
HD		 653 SetPageReserved(as->pdir_page);
654 pdir = page_address(as->pdir_page);
655
656 for (pdn = 0; pdn < SMMU_PDIR_COUNT; pdn++)
657 pdir[pdn] = _PDE_VACANT(pdn);
658 FLUSH_CPU_DCACHE(pdir, as->pdir_page, SMMU_PDIR_SIZE);
659 val = SMMU_PTC_FLUSH_TYPE_ADR | VA_PAGE_TO_PA(pdir, as->pdir_page);
660 smmu_write(smmu, val, SMMU_PTC_FLUSH);
661 FLUSH_SMMU_REGS(as->smmu);
662 val = SMMU_TLB_FLUSH_VA_MATCH_ALL |
663 SMMU_TLB_FLUSH_ASID_MATCH__ENABLE |
664 (as->asid << SMMU_TLB_FLUSH_ASID_SHIFT);
665 smmu_write(smmu, val, SMMU_TLB_FLUSH);
666 FLUSH_SMMU_REGS(as->smmu);
667
f9a4f063
JR		 668 spin_unlock_irqrestore(&as->lock, flags);
669
7a31f6f4 670 return 0;
9e971a03
HD		 671
672err_out:
f9a4f063
JR		 673 spin_unlock_irqrestore(&as->lock, flags);
674
9e971a03
HD		 675 devm_kfree(smmu->dev, cnt);
676 if (page)
677 __free_page(page);
678 return err;
7a31f6f4
HD		 679}
680
681static void __smmu_iommu_unmap(struct smmu_as *as, dma_addr_t iova)
682{
683 unsigned long *pte;
684 struct page *page;
685 unsigned int *count;
686
687 pte = locate_pte(as, iova, false, &page, &count);
688 if (WARN_ON(!pte))
689 return;
690
691 if (WARN_ON(*pte == _PTE_VACANT(iova)))
692 return;
693
694 *pte = _PTE_VACANT(iova);
695 FLUSH_CPU_DCACHE(pte, page, sizeof(*pte));
696 flush_ptc_and_tlb(as->smmu, as, iova, pte, page, 0);
37683e45 697 if (!--(*count))
7a31f6f4 698 free_ptbl(as, iova);
7a31f6f4
HD		 699}
700
701static void __smmu_iommu_map_pfn(struct smmu_as *as, dma_addr_t iova,
702 unsigned long pfn)
703{
704 struct smmu_device *smmu = as->smmu;
705 unsigned long *pte;
706 unsigned int *count;
707 struct page *page;
708
709 pte = locate_pte(as, iova, true, &page, &count);
710 if (WARN_ON(!pte))
711 return;
712
713 if (*pte == _PTE_VACANT(iova))
714 (*count)++;
715 *pte = SMMU_PFN_TO_PTE(pfn, as->pte_attr);
716 if (unlikely((*pte == _PTE_VACANT(iova))))
717 (*count)--;
718 FLUSH_CPU_DCACHE(pte, page, sizeof(*pte));
719 flush_ptc_and_tlb(smmu, as, iova, pte, page, 0);
720 put_signature(as, iova, pfn);
721}
722
723static int smmu_iommu_map(struct iommu_domain *domain, unsigned long iova,
724 phys_addr_t pa, size_t bytes, int prot)
725{
726 struct smmu_as *as = domain->priv;
727 unsigned long pfn = __phys_to_pfn(pa);
728 unsigned long flags;
729
730 dev_dbg(as->smmu->dev, "[%d] %08lx:%08x\n", as->asid, iova, pa);
731
732 if (!pfn_valid(pfn))
733 return -ENOMEM;
734
735 spin_lock_irqsave(&as->lock, flags);
736 __smmu_iommu_map_pfn(as, iova, pfn);
737 spin_unlock_irqrestore(&as->lock, flags);
738 return 0;
739}
740
741static size_t smmu_iommu_unmap(struct iommu_domain *domain, unsigned long iova,
742 size_t bytes)
743{
744 struct smmu_as *as = domain->priv;
745 unsigned long flags;
746
747 dev_dbg(as->smmu->dev, "[%d] %08lx\n", as->asid, iova);
748
749 spin_lock_irqsave(&as->lock, flags);
750 __smmu_iommu_unmap(as, iova);
751 spin_unlock_irqrestore(&as->lock, flags);
752 return SMMU_PAGE_SIZE;
753}
754
755static phys_addr_t smmu_iommu_iova_to_phys(struct iommu_domain *domain,
756 unsigned long iova)
757{
758 struct smmu_as *as = domain->priv;
759 unsigned long *pte;
760 unsigned int *count;
761 struct page *page;
762 unsigned long pfn;
763 unsigned long flags;
764
765 spin_lock_irqsave(&as->lock, flags);
766
767 pte = locate_pte(as, iova, true, &page, &count);
768 pfn = *pte & SMMU_PFN_MASK;
769 WARN_ON(!pfn_valid(pfn));
770 dev_dbg(as->smmu->dev,
771 "iova:%08lx pfn:%08lx asid:%d\n", iova, pfn, as->asid);
772
773 spin_unlock_irqrestore(&as->lock, flags);
774 return PFN_PHYS(pfn);
775}
776
777static int smmu_iommu_domain_has_cap(struct iommu_domain *domain,
778 unsigned long cap)
779{
780 return 0;
781}
782
783static int smmu_iommu_attach_dev(struct iommu_domain *domain,
784 struct device *dev)
785{
786 struct smmu_as *as = domain->priv;
787 struct smmu_device *smmu = as->smmu;
788 struct smmu_client *client, *c;
789 u32 map;
790 int err;
791
792 client = devm_kzalloc(smmu->dev, sizeof(*c), GFP_KERNEL);
793 if (!client)
794 return -ENOMEM;
795 client->dev = dev;
796 client->as = as;
797 map = (unsigned long)dev->platform_data;
798 if (!map)
799 return -EINVAL;
800
801 err = smmu_client_enable_hwgrp(client, map);
802 if (err)
803 goto err_hwgrp;
804
805 spin_lock(&as->client_lock);
806 list_for_each_entry(c, &as->client, list) {
807 if (c->dev == dev) {
808 dev_err(smmu->dev,
809 "%s is already attached\n", dev_name(c->dev));
810 err = -EINVAL;
811 goto err_client;
812 }
813 }
814 list_add(&client->list, &as->client);
815 spin_unlock(&as->client_lock);
816
817 /*
818 * Reserve "page zero" for AVP vectors using a common dummy
819 * page.
820 */
821 if (map & HWG_AVPC) {
822 struct page *page;
823
824 page = as->smmu->avp_vector_page;
825 __smmu_iommu_map_pfn(as, 0, page_to_pfn(page));
826
827 pr_info("Reserve \"page zero\" for AVP vectors using a common dummy\n");
828 }
829
90730917 830 dev_dbg(smmu->dev, "%s is attached\n", dev_name(dev));
7a31f6f4
HD		 831 return 0;
832
833err_client:
834 smmu_client_disable_hwgrp(client);
835 spin_unlock(&as->client_lock);
836err_hwgrp:
837 devm_kfree(smmu->dev, client);
838 return err;
839}
840
841static void smmu_iommu_detach_dev(struct iommu_domain *domain,
842 struct device *dev)
843{
844 struct smmu_as *as = domain->priv;
845 struct smmu_device *smmu = as->smmu;
846 struct smmu_client *c;
847
848 spin_lock(&as->client_lock);
849
850 list_for_each_entry(c, &as->client, list) {
851 if (c->dev == dev) {
852 smmu_client_disable_hwgrp(c);
853 list_del(&c->list);
854 devm_kfree(smmu->dev, c);
855 c->as = NULL;
856 dev_dbg(smmu->dev,
857 "%s is detached\n", dev_name(c->dev));
858 goto out;
859 }
860 }
9579a974 861 dev_err(smmu->dev, "Couldn't find %s\n", dev_name(dev));
7a31f6f4
HD		 862out:
863 spin_unlock(&as->client_lock);
864}
865
866static int smmu_iommu_domain_init(struct iommu_domain *domain)
867{
d1d076f1 868 int i, err = -EAGAIN;
7a31f6f4
HD		 869 unsigned long flags;
870 struct smmu_as *as;
871 struct smmu_device *smmu = smmu_handle;
872
873 /* Look for a free AS with lock held */
874 for (i = 0; i < smmu->num_as; i++) {
9e971a03 875 as = &smmu->as[i];
d2453b2c
HD		 876
877 if (as->pdir_page)
878 continue;
879
880 err = alloc_pdir(as);
881 if (!err)
882 goto found;
883
9e971a03
HD		 884 if (err != -EAGAIN)
885 break;
7a31f6f4 886 }
9e971a03
HD		 887 if (i == smmu->num_as)
888 dev_err(smmu->dev, "no free AS\n");
889 return err;
7a31f6f4
HD		 890
891found:
f9a4f063 892 spin_lock_irqsave(&smmu->lock, flags);
7a31f6f4
HD		 893
894 /* Update PDIR register */
895 smmu_write(smmu, SMMU_PTB_ASID_CUR(as->asid), SMMU_PTB_ASID);
896 smmu_write(smmu,
897 SMMU_MK_PDIR(as->pdir_page, as->pdir_attr), SMMU_PTB_DATA);
898 FLUSH_SMMU_REGS(smmu);
899
f9a4f063 900 spin_unlock_irqrestore(&smmu->lock, flags);
7a31f6f4 901
7a31f6f4
HD		 902 domain->priv = as;
903
23349902
HD		 904 domain->geometry.aperture_start = smmu->iovmm_base;
905 domain->geometry.aperture_end = smmu->iovmm_base +
906 smmu->page_count * SMMU_PAGE_SIZE - 1;
907 domain->geometry.force_aperture = true;
908
7a31f6f4 909 dev_dbg(smmu->dev, "smmu_as@%p\n", as);
7a31f6f4 910
7a31f6f4 911 return 0;
7a31f6f4
HD		 912}
913
914static void smmu_iommu_domain_destroy(struct iommu_domain *domain)
915{
916 struct smmu_as *as = domain->priv;
917 struct smmu_device *smmu = as->smmu;
918 unsigned long flags;
919
920 spin_lock_irqsave(&as->lock, flags);
921
922 if (as->pdir_page) {
923 spin_lock(&smmu->lock);
924 smmu_write(smmu, SMMU_PTB_ASID_CUR(as->asid), SMMU_PTB_ASID);
925 smmu_write(smmu, SMMU_PTB_DATA_RESET_VAL, SMMU_PTB_DATA);
926 FLUSH_SMMU_REGS(smmu);
927 spin_unlock(&smmu->lock);
928
929 free_pdir(as);
930 }
931
932 if (!list_empty(&as->client)) {
933 struct smmu_client *c;
934
935 list_for_each_entry(c, &as->client, list)
936 smmu_iommu_detach_dev(domain, c->dev);
937 }
938
939 spin_unlock_irqrestore(&as->lock, flags);
940
941 domain->priv = NULL;
942 dev_dbg(smmu->dev, "smmu_as@%p\n", as);
943}
944
945static struct iommu_ops smmu_iommu_ops = {
946 .domain_init = smmu_iommu_domain_init,
947 .domain_destroy = smmu_iommu_domain_destroy,
948 .attach_dev = smmu_iommu_attach_dev,
949 .detach_dev = smmu_iommu_detach_dev,
950 .map = smmu_iommu_map,
951 .unmap = smmu_iommu_unmap,
952 .iova_to_phys = smmu_iommu_iova_to_phys,
953 .domain_has_cap = smmu_iommu_domain_has_cap,
954 .pgsize_bitmap = SMMU_IOMMU_PGSIZES,
955};
956
39abf8aa
HD		 957/* Should be in the order of enum */
958static const char * const smmu_debugfs_mc[] = { "mc", };
959static const char * const smmu_debugfs_cache[] = { "tlb", "ptc", };
960
961static ssize_t smmu_debugfs_stats_write(struct file *file,
962 const char __user *buffer,
963 size_t count, loff_t *pos)
964{
5a2c937a 965 struct smmu_debugfs_info *info;
39abf8aa
HD		 966 struct smmu_device *smmu;
967 struct dentry *dent;
5a2c937a 968 int i;
39abf8aa
HD		 969 enum {
970 _OFF = 0,
971 _ON,
972 _RESET,
973 };
974 const char * const command[] = {
975 [_OFF] = "off",
976 [_ON] = "on",
977 [_RESET] = "reset",
978 };
979 char str[] = "reset";
980 u32 val;
981 size_t offs;
982
983 count = min_t(size_t, count, sizeof(str));
984 if (copy_from_user(str, buffer, count))
985 return -EINVAL;
986
987 for (i = 0; i < ARRAY_SIZE(command); i++)
988 if (strncmp(str, command[i],
989 strlen(command[i])) == 0)
990 break;
991
992 if (i == ARRAY_SIZE(command))
993 return -EINVAL;
994
995 dent = file->f_dentry;
5a2c937a
HD		 996 info = dent->d_inode->i_private;
997 smmu = info->smmu;
39abf8aa 998
5a2c937a 999 offs = SMMU_CACHE_CONFIG(info->cache);
39abf8aa
HD		 1000 val = smmu_read(smmu, offs);
1001 switch (i) {
1002 case _OFF:
1003 val &= ~SMMU_CACHE_CONFIG_STATS_ENABLE;
1004 val &= ~SMMU_CACHE_CONFIG_STATS_TEST;
1005 smmu_write(smmu, val, offs);
1006 break;
1007 case _ON:
1008 val |= SMMU_CACHE_CONFIG_STATS_ENABLE;
1009 val &= ~SMMU_CACHE_CONFIG_STATS_TEST;
1010 smmu_write(smmu, val, offs);
1011 break;
1012 case _RESET:
1013 val |= SMMU_CACHE_CONFIG_STATS_TEST;
1014 smmu_write(smmu, val, offs);
1015 val &= ~SMMU_CACHE_CONFIG_STATS_TEST;
1016 smmu_write(smmu, val, offs);
1017 break;
1018 default:
1019 BUG();
1020 break;
1021 }
1022
1023 dev_dbg(smmu->dev, "%s() %08x, %08x @%08x\n", __func__,
1024 val, smmu_read(smmu, offs), offs);
1025
1026 return count;
1027}
1028
1029static int smmu_debugfs_stats_show(struct seq_file *s, void *v)
1030{
5a2c937a 1031 struct smmu_debugfs_info *info;
39abf8aa
HD		 1032 struct smmu_device *smmu;
1033 struct dentry *dent;
5a2c937a 1034 int i;
39abf8aa
HD		 1035 const char * const stats[] = { "hit", "miss", };
1036
1037 dent = d_find_alias(s->private);
5a2c937a
HD		 1038 info = dent->d_inode->i_private;
1039 smmu = info->smmu;
39abf8aa
HD		 1040
1041 for (i = 0; i < ARRAY_SIZE(stats); i++) {
1042 u32 val;
1043 size_t offs;
1044
5a2c937a 1045 offs = SMMU_STATS_CACHE_COUNT(info->mc, info->cache, i);
39abf8aa
HD		 1046 val = smmu_read(smmu, offs);
1047 seq_printf(s, "%s:%08x ", stats[i], val);
1048
1049 dev_dbg(smmu->dev, "%s() %s %08x @%08x\n", __func__,
1050 stats[i], val, offs);
1051 }
1052 seq_printf(s, "\n");
b334b648 1053 dput(dent);
39abf8aa
HD		 1054
1055 return 0;
1056}
1057
1058static int smmu_debugfs_stats_open(struct inode *inode, struct file *file)
1059{
1060 return single_open(file, smmu_debugfs_stats_show, inode);
1061}
1062
1063static const struct file_operations smmu_debugfs_stats_fops = {
1064 .open = smmu_debugfs_stats_open,
1065 .read = seq_read,
1066 .llseek = seq_lseek,
1067 .release = single_release,
1068 .write = smmu_debugfs_stats_write,
1069};
1070
1071static void smmu_debugfs_delete(struct smmu_device *smmu)
1072{
1073 debugfs_remove_recursive(smmu->debugfs_root);
5a2c937a 1074 kfree(smmu->debugfs_info);
39abf8aa
HD		 1075}
1076
1077static void smmu_debugfs_create(struct smmu_device *smmu)
1078{
1079 int i;
5a2c937a 1080 size_t bytes;
39abf8aa
HD		 1081 struct dentry *root;
1082
5a2c937a
HD		 1083 bytes = ARRAY_SIZE(smmu_debugfs_mc) * ARRAY_SIZE(smmu_debugfs_cache) *
1084 sizeof(*smmu->debugfs_info);
1085 smmu->debugfs_info = kmalloc(bytes, GFP_KERNEL);
1086 if (!smmu->debugfs_info)
1087 return;
1088
1089 root = debugfs_create_dir(dev_name(smmu->dev), NULL);
39abf8aa
HD		 1090 if (!root)
1091 goto err_out;
1092 smmu->debugfs_root = root;
1093
1094 for (i = 0; i < ARRAY_SIZE(smmu_debugfs_mc); i++) {
1095 int j;
1096 struct dentry *mc;
1097
5a2c937a 1098 mc = debugfs_create_dir(smmu_debugfs_mc[i], root);
39abf8aa
HD		 1099 if (!mc)
1100 goto err_out;
1101
1102 for (j = 0; j < ARRAY_SIZE(smmu_debugfs_cache); j++) {
1103 struct dentry *cache;
5a2c937a
HD		 1104 struct smmu_debugfs_info *info;
1105
1106 info = smmu->debugfs_info;
1107 info += i * ARRAY_SIZE(smmu_debugfs_mc) + j;
1108 info->smmu = smmu;
1109 info->mc = i;
1110 info->cache = j;
39abf8aa
HD		 1111
1112 cache = debugfs_create_file(smmu_debugfs_cache[j],
1113 S_IWUGO | S_IRUGO, mc,
5a2c937a 1114 (void *)info,
39abf8aa
HD		 1115 &smmu_debugfs_stats_fops);
1116 if (!cache)
1117 goto err_out;
1118 }
1119 }
1120
1121 return;
1122
1123err_out:
1124 smmu_debugfs_delete(smmu);
1125}
1126
7a31f6f4
HD		 1127static int tegra_smmu_suspend(struct device *dev)
1128{
1129 struct smmu_device *smmu = dev_get_drvdata(dev);
1130
1131 smmu->translation_enable_0 = smmu_read(smmu, SMMU_TRANSLATION_ENABLE_0);
1132 smmu->translation_enable_1 = smmu_read(smmu, SMMU_TRANSLATION_ENABLE_1);
1133 smmu->translation_enable_2 = smmu_read(smmu, SMMU_TRANSLATION_ENABLE_2);
1134 smmu->asid_security = smmu_read(smmu, SMMU_ASID_SECURITY);
1135 return 0;
1136}
1137
1138static int tegra_smmu_resume(struct device *dev)
1139{
1140 struct smmu_device *smmu = dev_get_drvdata(dev);
1141 unsigned long flags;
0760e8fa 1142 int err;
7a31f6f4
HD		 1143
1144 spin_lock_irqsave(&smmu->lock, flags);
0760e8fa 1145 err = smmu_setup_regs(smmu);
7a31f6f4 1146 spin_unlock_irqrestore(&smmu->lock, flags);
0760e8fa 1147 return err;
7a31f6f4
HD		 1148}
1149
1150static int tegra_smmu_probe(struct platform_device *pdev)
1151{
1152 struct smmu_device *smmu;
7a31f6f4 1153 struct device *dev = &pdev->dev;
0760e8fa 1154 int i, asids, err = 0;
ff763629
HD		 1155 dma_addr_t uninitialized_var(base);
1156 size_t bytes, uninitialized_var(size);
7a31f6f4
HD		 1157
1158 if (smmu_handle)
1159 return -EIO;
1160
1161 BUILD_BUG_ON(PAGE_SHIFT != SMMU_PAGE_SHIFT);
1162
a3b24915 1163 if (of_property_read_u32(dev->of_node, "nvidia,#asids", &asids))
7a31f6f4 1164 return -ENODEV;
7a31f6f4 1165
a3b24915
HD		 1166 bytes = sizeof(*smmu) + asids * sizeof(*smmu->as);
1167 smmu = devm_kzalloc(dev, bytes, GFP_KERNEL);
7a31f6f4
HD		 1168 if (!smmu) {
1169 dev_err(dev, "failed to allocate smmu_device\n");
1170 return -ENOMEM;
1171 }
1172
0760e8fa
HD		 1173 for (i = 0; i < ARRAY_SIZE(smmu->regs); i++) {
1174 struct resource *res;
1175
1176 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
1177 if (!res)
1178 return -ENODEV;
1179 smmu->regs[i] = devm_request_and_ioremap(&pdev->dev, res);
1180 if (!smmu->regs[i])
1181 return -EBUSY;
7a31f6f4
HD		 1182 }
1183
0760e8fa
HD		 1184 err = of_get_dma_window(dev->of_node, NULL, 0, NULL, &base, &size);
1185 if (err)
1186 return -ENODEV;
1187
1188 if (size & SMMU_PAGE_MASK)
1189 return -EINVAL;
1190
1191 size >>= SMMU_PAGE_SHIFT;
1192 if (!size)
1193 return -EINVAL;
1194
0760e8fa
HD		 1195 smmu->ahb = of_parse_phandle(dev->of_node, "nvidia,ahb", 0);
1196 if (!smmu->ahb)
1197 return -ENODEV;
1198
1199 smmu->dev = dev;
1200 smmu->num_as = asids;
1201 smmu->iovmm_base = base;
1202 smmu->page_count = size;
1203
7a31f6f4
HD		 1204 smmu->translation_enable_0 = ~0;
1205 smmu->translation_enable_1 = ~0;
1206 smmu->translation_enable_2 = ~0;
1207 smmu->asid_security = 0;
1208
7a31f6f4
HD		 1209 for (i = 0; i < smmu->num_as; i++) {
1210 struct smmu_as *as = &smmu->as[i];
1211
1212 as->smmu = smmu;
1213 as->asid = i;
1214 as->pdir_attr = _PDIR_ATTR;
1215 as->pde_attr = _PDE_ATTR;
1216 as->pte_attr = _PTE_ATTR;
1217
1218 spin_lock_init(&as->lock);
1219 INIT_LIST_HEAD(&as->client);
1220 }
1221 spin_lock_init(&smmu->lock);
0760e8fa
HD		 1222 err = smmu_setup_regs(smmu);
1223 if (err)
0547c2f5 1224 return err;
7a31f6f4
HD		 1225 platform_set_drvdata(pdev, smmu);
1226
1227 smmu->avp_vector_page = alloc_page(GFP_KERNEL);
1228 if (!smmu->avp_vector_page)
0547c2f5 1229 return -ENOMEM;
7a31f6f4 1230
39abf8aa 1231 smmu_debugfs_create(smmu);
7a31f6f4 1232 smmu_handle = smmu;
f1bda29c 1233 bus_set_iommu(&platform_bus_type, &smmu_iommu_ops);
7a31f6f4 1234 return 0;
7a31f6f4
HD		 1235}
1236
1237static int tegra_smmu_remove(struct platform_device *pdev)
1238{
1239 struct smmu_device *smmu = platform_get_drvdata(pdev);
0547c2f5 1240 int i;
7a31f6f4 1241
39abf8aa
HD		 1242 smmu_debugfs_delete(smmu);
1243
7a31f6f4 1244 smmu_write(smmu, SMMU_CONFIG_DISABLE, SMMU_CONFIG);
0547c2f5
HD		 1245 for (i = 0; i < smmu->num_as; i++)
1246 free_pdir(&smmu->as[i]);
1247 __free_page(smmu->avp_vector_page);
7a31f6f4
HD		 1248 smmu_handle = NULL;
1249 return 0;
1250}
1251
1252const struct dev_pm_ops tegra_smmu_pm_ops = {
1253 .suspend = tegra_smmu_suspend,
1254 .resume = tegra_smmu_resume,
1255};
1256
0760e8fa 1257#ifdef CONFIG_OF
d34d6517 1258static struct of_device_id tegra_smmu_of_match[] = {
0760e8fa
HD		 1259 { .compatible = "nvidia,tegra30-smmu", },
1260 { },
1261};
1262MODULE_DEVICE_TABLE(of, tegra_smmu_of_match);
1263#endif
1264
7a31f6f4
HD		 1265static struct platform_driver tegra_smmu_driver = {
1266 .probe = tegra_smmu_probe,
1267 .remove = tegra_smmu_remove,
1268 .driver = {
1269 .owner = THIS_MODULE,
1270 .name = "tegra-smmu",
1271 .pm = &tegra_smmu_pm_ops,
0760e8fa 1272 .of_match_table = of_match_ptr(tegra_smmu_of_match),
7a31f6f4
HD		 1273 },
1274};
1275
d34d6517 1276static int tegra_smmu_init(void)
7a31f6f4 1277{
7a31f6f4
HD		 1278 return platform_driver_register(&tegra_smmu_driver);
1279}
1280
1281static void __exit tegra_smmu_exit(void)
1282{
1283 platform_driver_unregister(&tegra_smmu_driver);
1284}
1285
1286subsys_initcall(tegra_smmu_init);
1287module_exit(tegra_smmu_exit);
1288
1289MODULE_DESCRIPTION("IOMMU API for SMMU in Tegra30");
1290MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>");
0760e8fa 1291MODULE_ALIAS("platform:tegra-smmu");
7a31f6f4 1292MODULE_LICENSE("GPL v2");
kernel source for telekom puls (alcatel/mediatek)