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iommu/tegra: smmu: debugfs for TLB/PTC statistics
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / iommu / tegra-smmu.c
CommitLineData
7a31f6f4
HD		 1/*
2 * IOMMU API for SMMU in Tegra30
3 *
4 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 */
19
20#define pr_fmt(fmt) "%s(): " fmt, __func__
21
22#include <linux/module.h>
23#include <linux/platform_device.h>
24#include <linux/spinlock.h>
25#include <linux/slab.h>
26#include <linux/vmalloc.h>
27#include <linux/mm.h>
28#include <linux/pagemap.h>
29#include <linux/device.h>
30#include <linux/sched.h>
31#include <linux/iommu.h>
32#include <linux/io.h>
0760e8fa
HD		 33#include <linux/of.h>
34#include <linux/of_iommu.h>
39abf8aa
HD		 35#include <linux/debugfs.h>
36#include <linux/seq_file.h>
7a31f6f4
HD		 37
38#include <asm/page.h>
39#include <asm/cacheflush.h>
40
41#include <mach/iomap.h>
42#include <mach/smmu.h>
0760e8fa 43#include <mach/tegra-ahb.h>
7a31f6f4
HD		 44
45/* bitmap of the page sizes currently supported */
46#define SMMU_IOMMU_PGSIZES (SZ_4K)
47
48#define SMMU_CONFIG 0x10
49#define SMMU_CONFIG_DISABLE 0
50#define SMMU_CONFIG_ENABLE 1
51
39abf8aa
HD		 52/* REVISIT: To support multiple MCs */
53enum {
54 _MC = 0,
55};
56
57enum {
58 _TLB = 0,
59 _PTC,
60};
61
62#define SMMU_CACHE_CONFIG_BASE 0x14
63#define __SMMU_CACHE_CONFIG(mc, cache) (SMMU_CACHE_CONFIG_BASE + 4 * cache)
64#define SMMU_CACHE_CONFIG(cache) __SMMU_CACHE_CONFIG(_MC, cache)
65
66#define SMMU_CACHE_CONFIG_STATS_SHIFT 31
67#define SMMU_CACHE_CONFIG_STATS_ENABLE (1 << SMMU_CACHE_CONFIG_STATS_SHIFT)
68#define SMMU_CACHE_CONFIG_STATS_TEST_SHIFT 30
69#define SMMU_CACHE_CONFIG_STATS_TEST (1 << SMMU_CACHE_CONFIG_STATS_TEST_SHIFT)
70
7a31f6f4
HD		 71#define SMMU_TLB_CONFIG_HIT_UNDER_MISS__ENABLE (1 << 29)
72#define SMMU_TLB_CONFIG_ACTIVE_LINES__VALUE 0x10
73#define SMMU_TLB_CONFIG_RESET_VAL 0x20000010
74
7a31f6f4
HD		 75#define SMMU_PTC_CONFIG_CACHE__ENABLE (1 << 29)
76#define SMMU_PTC_CONFIG_INDEX_MAP__PATTERN 0x3f
77#define SMMU_PTC_CONFIG_RESET_VAL 0x2000003f
78
79#define SMMU_PTB_ASID 0x1c
80#define SMMU_PTB_ASID_CURRENT_SHIFT 0
81
82#define SMMU_PTB_DATA 0x20
83#define SMMU_PTB_DATA_RESET_VAL 0
84#define SMMU_PTB_DATA_ASID_NONSECURE_SHIFT 29
85#define SMMU_PTB_DATA_ASID_WRITABLE_SHIFT 30
86#define SMMU_PTB_DATA_ASID_READABLE_SHIFT 31
87
88#define SMMU_TLB_FLUSH 0x30
89#define SMMU_TLB_FLUSH_VA_MATCH_ALL 0
90#define SMMU_TLB_FLUSH_VA_MATCH_SECTION 2
91#define SMMU_TLB_FLUSH_VA_MATCH_GROUP 3
92#define SMMU_TLB_FLUSH_ASID_SHIFT 29
93#define SMMU_TLB_FLUSH_ASID_MATCH_DISABLE 0
94#define SMMU_TLB_FLUSH_ASID_MATCH_ENABLE 1
95#define SMMU_TLB_FLUSH_ASID_MATCH_SHIFT 31
96
97#define SMMU_PTC_FLUSH 0x34
98#define SMMU_PTC_FLUSH_TYPE_ALL 0
99#define SMMU_PTC_FLUSH_TYPE_ADR 1
100#define SMMU_PTC_FLUSH_ADR_SHIFT 4
101
102#define SMMU_ASID_SECURITY 0x38
103
39abf8aa
HD		 104#define SMMU_STATS_CACHE_COUNT_BASE 0x1f0
105
106#define SMMU_STATS_CACHE_COUNT(mc, cache, hitmiss) \
107 (SMMU_STATS_CACHE_COUNT_BASE + 8 * cache + 4 * hitmiss)
7a31f6f4
HD		 108
109#define SMMU_TRANSLATION_ENABLE_0 0x228
110#define SMMU_TRANSLATION_ENABLE_1 0x22c
111#define SMMU_TRANSLATION_ENABLE_2 0x230
112
113#define SMMU_AFI_ASID 0x238 /* PCIE */
114#define SMMU_AVPC_ASID 0x23c /* AVP */
115#define SMMU_DC_ASID 0x240 /* Display controller */
116#define SMMU_DCB_ASID 0x244 /* Display controller B */
117#define SMMU_EPP_ASID 0x248 /* Encoder pre-processor */
118#define SMMU_G2_ASID 0x24c /* 2D engine */
119#define SMMU_HC_ASID 0x250 /* Host1x */
120#define SMMU_HDA_ASID 0x254 /* High-def audio */
121#define SMMU_ISP_ASID 0x258 /* Image signal processor */
122#define SMMU_MPE_ASID 0x264 /* MPEG encoder */
123#define SMMU_NV_ASID 0x268 /* (3D) */
124#define SMMU_NV2_ASID 0x26c /* (3D) */
125#define SMMU_PPCS_ASID 0x270 /* AHB */
126#define SMMU_SATA_ASID 0x278 /* SATA */
127#define SMMU_VDE_ASID 0x27c /* Video decoder */
128#define SMMU_VI_ASID 0x280 /* Video input */
129
130#define SMMU_PDE_NEXT_SHIFT 28
131
7a31f6f4
HD		 132#define SMMU_TLB_FLUSH_VA_SECTION__MASK 0xffc00000
133#define SMMU_TLB_FLUSH_VA_SECTION__SHIFT 12 /* right shift */
134#define SMMU_TLB_FLUSH_VA_GROUP__MASK 0xffffc000
135#define SMMU_TLB_FLUSH_VA_GROUP__SHIFT 12 /* right shift */
136#define SMMU_TLB_FLUSH_VA(iova, which) \
137 ((((iova) & SMMU_TLB_FLUSH_VA_##which##__MASK) >> \
138 SMMU_TLB_FLUSH_VA_##which##__SHIFT) | \
139 SMMU_TLB_FLUSH_VA_MATCH_##which)
140#define SMMU_PTB_ASID_CUR(n) \
141 ((n) << SMMU_PTB_ASID_CURRENT_SHIFT)
142#define SMMU_TLB_FLUSH_ASID_MATCH_disable \
143 (SMMU_TLB_FLUSH_ASID_MATCH_DISABLE << \
144 SMMU_TLB_FLUSH_ASID_MATCH_SHIFT)
145#define SMMU_TLB_FLUSH_ASID_MATCH__ENABLE \
146 (SMMU_TLB_FLUSH_ASID_MATCH_ENABLE << \
147 SMMU_TLB_FLUSH_ASID_MATCH_SHIFT)
148
149#define SMMU_PAGE_SHIFT 12
150#define SMMU_PAGE_SIZE (1 << SMMU_PAGE_SHIFT)
0760e8fa 151#define SMMU_PAGE_MASK ((1 << SMMU_PAGE_SHIFT) - 1)
7a31f6f4
HD		 152
153#define SMMU_PDIR_COUNT 1024
154#define SMMU_PDIR_SIZE (sizeof(unsigned long) * SMMU_PDIR_COUNT)
155#define SMMU_PTBL_COUNT 1024
156#define SMMU_PTBL_SIZE (sizeof(unsigned long) * SMMU_PTBL_COUNT)
157#define SMMU_PDIR_SHIFT 12
158#define SMMU_PDE_SHIFT 12
159#define SMMU_PTE_SHIFT 12
160#define SMMU_PFN_MASK 0x000fffff
161
162#define SMMU_ADDR_TO_PFN(addr) ((addr) >> 12)
163#define SMMU_ADDR_TO_PDN(addr) ((addr) >> 22)
164#define SMMU_PDN_TO_ADDR(addr) ((pdn) << 22)
165
166#define _READABLE (1 << SMMU_PTB_DATA_ASID_READABLE_SHIFT)
167#define _WRITABLE (1 << SMMU_PTB_DATA_ASID_WRITABLE_SHIFT)
168#define _NONSECURE (1 << SMMU_PTB_DATA_ASID_NONSECURE_SHIFT)
169#define _PDE_NEXT (1 << SMMU_PDE_NEXT_SHIFT)
170#define _MASK_ATTR (_READABLE | _WRITABLE | _NONSECURE)
171
172#define _PDIR_ATTR (_READABLE | _WRITABLE | _NONSECURE)
173
174#define _PDE_ATTR (_READABLE | _WRITABLE | _NONSECURE)
175#define _PDE_ATTR_N (_PDE_ATTR | _PDE_NEXT)
176#define _PDE_VACANT(pdn) (((pdn) << 10) | _PDE_ATTR)
177
178#define _PTE_ATTR (_READABLE | _WRITABLE | _NONSECURE)
179#define _PTE_VACANT(addr) (((addr) >> SMMU_PAGE_SHIFT) | _PTE_ATTR)
180
181#define SMMU_MK_PDIR(page, attr) \
182 ((page_to_phys(page) >> SMMU_PDIR_SHIFT) | (attr))
183#define SMMU_MK_PDE(page, attr) \
184 (unsigned long)((page_to_phys(page) >> SMMU_PDE_SHIFT) | (attr))
185#define SMMU_EX_PTBL_PAGE(pde) \
186 pfn_to_page((unsigned long)(pde) & SMMU_PFN_MASK)
187#define SMMU_PFN_TO_PTE(pfn, attr) (unsigned long)((pfn) | (attr))
188
189#define SMMU_ASID_ENABLE(asid) ((asid) | (1 << 31))
190#define SMMU_ASID_DISABLE 0
191#define SMMU_ASID_ASID(n) ((n) & ~SMMU_ASID_ENABLE(0))
192
0760e8fa
HD		 193#define NUM_SMMU_REG_BANKS 3
194
7a31f6f4
HD		 195#define smmu_client_enable_hwgrp(c, m) smmu_client_set_hwgrp(c, m, 1)
196#define smmu_client_disable_hwgrp(c) smmu_client_set_hwgrp(c, 0, 0)
197#define __smmu_client_enable_hwgrp(c, m) __smmu_client_set_hwgrp(c, m, 1)
198#define __smmu_client_disable_hwgrp(c) __smmu_client_set_hwgrp(c, 0, 0)
199
200#define HWGRP_INIT(client) [HWGRP_##client] = SMMU_##client##_ASID
201
202static const u32 smmu_hwgrp_asid_reg[] = {
203 HWGRP_INIT(AFI),
204 HWGRP_INIT(AVPC),
205 HWGRP_INIT(DC),
206 HWGRP_INIT(DCB),
207 HWGRP_INIT(EPP),
208 HWGRP_INIT(G2),
209 HWGRP_INIT(HC),
210 HWGRP_INIT(HDA),
211 HWGRP_INIT(ISP),
212 HWGRP_INIT(MPE),
213 HWGRP_INIT(NV),
214 HWGRP_INIT(NV2),
215 HWGRP_INIT(PPCS),
216 HWGRP_INIT(SATA),
217 HWGRP_INIT(VDE),
218 HWGRP_INIT(VI),
219};
220#define HWGRP_ASID_REG(x) (smmu_hwgrp_asid_reg[x])
221
222/*
223 * Per client for address space
224 */
225struct smmu_client {
226 struct device *dev;
227 struct list_head list;
228 struct smmu_as *as;
229 u32 hwgrp;
230};
231
232/*
233 * Per address space
234 */
235struct smmu_as {
236 struct smmu_device *smmu; /* back pointer to container */
237 unsigned int asid;
238 spinlock_t lock; /* for pagetable */
239 struct page *pdir_page;
240 unsigned long pdir_attr;
241 unsigned long pde_attr;
242 unsigned long pte_attr;
243 unsigned int *pte_count;
244
245 struct list_head client;
246 spinlock_t client_lock; /* for client list */
247};
248
249/*
250 * Per SMMU device - IOMMU device
251 */
252struct smmu_device {
0760e8fa 253 void __iomem *regs[NUM_SMMU_REG_BANKS];
7a31f6f4
HD		 254 unsigned long iovmm_base; /* remappable base address */
255 unsigned long page_count; /* total remappable size */
256 spinlock_t lock;
257 char *name;
258 struct device *dev;
7a31f6f4
HD		 259 struct page *avp_vector_page; /* dummy page shared by all AS's */
260
261 /*
262 * Register image savers for suspend/resume
263 */
264 unsigned long translation_enable_0;
265 unsigned long translation_enable_1;
266 unsigned long translation_enable_2;
267 unsigned long asid_security;
0760e8fa 268
39abf8aa
HD		 269 struct dentry *debugfs_root;
270
0760e8fa 271 struct device_node *ahb;
a3b24915
HD		 272
273 int num_as;
274 struct smmu_as as[0]; /* Run-time allocated array */
7a31f6f4
HD		 275};
276
277static struct smmu_device *smmu_handle; /* unique for a system */
278
279/*
0760e8fa 280 * SMMU register accessors
7a31f6f4
HD		 281 */
282static inline u32 smmu_read(struct smmu_device *smmu, size_t offs)
283{
0760e8fa
HD		 284 BUG_ON(offs < 0x10);
285 if (offs < 0x3c)
286 return readl(smmu->regs[0] + offs - 0x10);
287 BUG_ON(offs < 0x1f0);
288 if (offs < 0x200)
289 return readl(smmu->regs[1] + offs - 0x1f0);
290 BUG_ON(offs < 0x228);
291 if (offs < 0x284)
292 return readl(smmu->regs[2] + offs - 0x228);
293 BUG();
7a31f6f4
HD		 294}
295
0760e8fa 296static inline void smmu_write(struct smmu_device *smmu, u32 val, size_t offs)
7a31f6f4 297{
0760e8fa
HD		 298 BUG_ON(offs < 0x10);
299 if (offs < 0x3c) {
300 writel(val, smmu->regs[0] + offs - 0x10);
301 return;
302 }
303 BUG_ON(offs < 0x1f0);
304 if (offs < 0x200) {
305 writel(val, smmu->regs[1] + offs - 0x1f0);
306 return;
307 }
308 BUG_ON(offs < 0x228);
309 if (offs < 0x284) {
310 writel(val, smmu->regs[2] + offs - 0x228);
311 return;
312 }
313 BUG();
7a31f6f4
HD		 314}
315
316#define VA_PAGE_TO_PA(va, page) \
317 (page_to_phys(page) + ((unsigned long)(va) & ~PAGE_MASK))
318
319#define FLUSH_CPU_DCACHE(va, page, size) \
320 do { \
321 unsigned long _pa_ = VA_PAGE_TO_PA(va, page); \
322 __cpuc_flush_dcache_area((void *)(va), (size_t)(size)); \
323 outer_flush_range(_pa_, _pa_+(size_t)(size)); \
324 } while (0)
325
326/*
327 * Any interaction between any block on PPSB and a block on APB or AHB
328 * must have these read-back barriers to ensure the APB/AHB bus
329 * transaction is complete before initiating activity on the PPSB
330 * block.
331 */
332#define FLUSH_SMMU_REGS(smmu) smmu_read(smmu, SMMU_CONFIG)
333
334#define smmu_client_hwgrp(c) (u32)((c)->dev->platform_data)
335
336static int __smmu_client_set_hwgrp(struct smmu_client *c,
337 unsigned long map, int on)
338{
339 int i;
340 struct smmu_as *as = c->as;
341 u32 val, offs, mask = SMMU_ASID_ENABLE(as->asid);
342 struct smmu_device *smmu = as->smmu;
343
344 WARN_ON(!on && map);
345 if (on && !map)
346 return -EINVAL;
347 if (!on)
348 map = smmu_client_hwgrp(c);
349
350 for_each_set_bit(i, &map, HWGRP_COUNT) {
351 offs = HWGRP_ASID_REG(i);
352 val = smmu_read(smmu, offs);
353 if (on) {
354 if (WARN_ON(val & mask))
355 goto err_hw_busy;
356 val |= mask;
357 } else {
358 WARN_ON((val & mask) == mask);
359 val &= ~mask;
360 }
361 smmu_write(smmu, val, offs);
362 }
363 FLUSH_SMMU_REGS(smmu);
364 c->hwgrp = map;
365 return 0;
366
367err_hw_busy:
368 for_each_set_bit(i, &map, HWGRP_COUNT) {
369 offs = HWGRP_ASID_REG(i);
370 val = smmu_read(smmu, offs);
371 val &= ~mask;
372 smmu_write(smmu, val, offs);
373 }
374 return -EBUSY;
375}
376
377static int smmu_client_set_hwgrp(struct smmu_client *c, u32 map, int on)
378{
379 u32 val;
380 unsigned long flags;
381 struct smmu_as *as = c->as;
382 struct smmu_device *smmu = as->smmu;
383
384 spin_lock_irqsave(&smmu->lock, flags);
385 val = __smmu_client_set_hwgrp(c, map, on);
386 spin_unlock_irqrestore(&smmu->lock, flags);
387 return val;
388}
389
390/*
391 * Flush all TLB entries and all PTC entries
392 * Caller must lock smmu
393 */
394static void smmu_flush_regs(struct smmu_device *smmu, int enable)
395{
396 u32 val;
397
398 smmu_write(smmu, SMMU_PTC_FLUSH_TYPE_ALL, SMMU_PTC_FLUSH);
399 FLUSH_SMMU_REGS(smmu);
400 val = SMMU_TLB_FLUSH_VA_MATCH_ALL |
401 SMMU_TLB_FLUSH_ASID_MATCH_disable;
402 smmu_write(smmu, val, SMMU_TLB_FLUSH);
403
404 if (enable)
405 smmu_write(smmu, SMMU_CONFIG_ENABLE, SMMU_CONFIG);
406 FLUSH_SMMU_REGS(smmu);
407}
408
0760e8fa 409static int smmu_setup_regs(struct smmu_device *smmu)
7a31f6f4
HD		 410{
411 int i;
412 u32 val;
413
414 for (i = 0; i < smmu->num_as; i++) {
415 struct smmu_as *as = &smmu->as[i];
416 struct smmu_client *c;
417
418 smmu_write(smmu, SMMU_PTB_ASID_CUR(as->asid), SMMU_PTB_ASID);
419 val = as->pdir_page ?
420 SMMU_MK_PDIR(as->pdir_page, as->pdir_attr) :
421 SMMU_PTB_DATA_RESET_VAL;
422 smmu_write(smmu, val, SMMU_PTB_DATA);
423
424 list_for_each_entry(c, &as->client, list)
425 __smmu_client_set_hwgrp(c, c->hwgrp, 1);
426 }
427
428 smmu_write(smmu, smmu->translation_enable_0, SMMU_TRANSLATION_ENABLE_0);
429 smmu_write(smmu, smmu->translation_enable_1, SMMU_TRANSLATION_ENABLE_1);
430 smmu_write(smmu, smmu->translation_enable_2, SMMU_TRANSLATION_ENABLE_2);
431 smmu_write(smmu, smmu->asid_security, SMMU_ASID_SECURITY);
39abf8aa
HD		 432 smmu_write(smmu, SMMU_TLB_CONFIG_RESET_VAL, SMMU_CACHE_CONFIG(_TLB));
433 smmu_write(smmu, SMMU_PTC_CONFIG_RESET_VAL, SMMU_CACHE_CONFIG(_PTC));
7a31f6f4
HD		 434
435 smmu_flush_regs(smmu, 1);
436
0760e8fa 437 return tegra_ahb_enable_smmu(smmu->ahb);
7a31f6f4
HD		 438}
439
440static void flush_ptc_and_tlb(struct smmu_device *smmu,
441 struct smmu_as *as, dma_addr_t iova,
442 unsigned long *pte, struct page *page, int is_pde)
443{
444 u32 val;
445 unsigned long tlb_flush_va = is_pde
446 ? SMMU_TLB_FLUSH_VA(iova, SECTION)
447 : SMMU_TLB_FLUSH_VA(iova, GROUP);
448
449 val = SMMU_PTC_FLUSH_TYPE_ADR | VA_PAGE_TO_PA(pte, page);
450 smmu_write(smmu, val, SMMU_PTC_FLUSH);
451 FLUSH_SMMU_REGS(smmu);
452 val = tlb_flush_va |
453 SMMU_TLB_FLUSH_ASID_MATCH__ENABLE |
454 (as->asid << SMMU_TLB_FLUSH_ASID_SHIFT);
455 smmu_write(smmu, val, SMMU_TLB_FLUSH);
456 FLUSH_SMMU_REGS(smmu);
457}
458
459static void free_ptbl(struct smmu_as *as, dma_addr_t iova)
460{
461 unsigned long pdn = SMMU_ADDR_TO_PDN(iova);
462 unsigned long *pdir = (unsigned long *)page_address(as->pdir_page);
463
464 if (pdir[pdn] != _PDE_VACANT(pdn)) {
465 dev_dbg(as->smmu->dev, "pdn: %lx\n", pdn);
466
467 ClearPageReserved(SMMU_EX_PTBL_PAGE(pdir[pdn]));
468 __free_page(SMMU_EX_PTBL_PAGE(pdir[pdn]));
469 pdir[pdn] = _PDE_VACANT(pdn);
470 FLUSH_CPU_DCACHE(&pdir[pdn], as->pdir_page, sizeof pdir[pdn]);
471 flush_ptc_and_tlb(as->smmu, as, iova, &pdir[pdn],
472 as->pdir_page, 1);
473 }
474}
475
476static void free_pdir(struct smmu_as *as)
477{
478 unsigned addr;
479 int count;
480 struct device *dev = as->smmu->dev;
481
482 if (!as->pdir_page)
483 return;
484
485 addr = as->smmu->iovmm_base;
486 count = as->smmu->page_count;
487 while (count-- > 0) {
488 free_ptbl(as, addr);
489 addr += SMMU_PAGE_SIZE * SMMU_PTBL_COUNT;
490 }
491 ClearPageReserved(as->pdir_page);
492 __free_page(as->pdir_page);
493 as->pdir_page = NULL;
494 devm_kfree(dev, as->pte_count);
495 as->pte_count = NULL;
496}
497
498/*
499 * Maps PTBL for given iova and returns the PTE address
500 * Caller must unmap the mapped PTBL returned in *ptbl_page_p
501 */
502static unsigned long *locate_pte(struct smmu_as *as,
503 dma_addr_t iova, bool allocate,
504 struct page **ptbl_page_p,
505 unsigned int **count)
506{
507 unsigned long ptn = SMMU_ADDR_TO_PFN(iova);
508 unsigned long pdn = SMMU_ADDR_TO_PDN(iova);
509 unsigned long *pdir = page_address(as->pdir_page);
510 unsigned long *ptbl;
511
512 if (pdir[pdn] != _PDE_VACANT(pdn)) {
513 /* Mapped entry table already exists */
514 *ptbl_page_p = SMMU_EX_PTBL_PAGE(pdir[pdn]);
515 ptbl = page_address(*ptbl_page_p);
516 } else if (!allocate) {
517 return NULL;
518 } else {
519 int pn;
520 unsigned long addr = SMMU_PDN_TO_ADDR(pdn);
521
522 /* Vacant - allocate a new page table */
523 dev_dbg(as->smmu->dev, "New PTBL pdn: %lx\n", pdn);
524
525 *ptbl_page_p = alloc_page(GFP_ATOMIC);
526 if (!*ptbl_page_p) {
527 dev_err(as->smmu->dev,
528 "failed to allocate smmu_device page table\n");
529 return NULL;
530 }
531 SetPageReserved(*ptbl_page_p);
532 ptbl = (unsigned long *)page_address(*ptbl_page_p);
533 for (pn = 0; pn < SMMU_PTBL_COUNT;
534 pn++, addr += SMMU_PAGE_SIZE) {
535 ptbl[pn] = _PTE_VACANT(addr);
536 }
537 FLUSH_CPU_DCACHE(ptbl, *ptbl_page_p, SMMU_PTBL_SIZE);
538 pdir[pdn] = SMMU_MK_PDE(*ptbl_page_p,
539 as->pde_attr | _PDE_NEXT);
540 FLUSH_CPU_DCACHE(&pdir[pdn], as->pdir_page, sizeof pdir[pdn]);
541 flush_ptc_and_tlb(as->smmu, as, iova, &pdir[pdn],
542 as->pdir_page, 1);
543 }
544 *count = &as->pte_count[pdn];
545
546 return &ptbl[ptn % SMMU_PTBL_COUNT];
547}
548
549#ifdef CONFIG_SMMU_SIG_DEBUG
550static void put_signature(struct smmu_as *as,
551 dma_addr_t iova, unsigned long pfn)
552{
553 struct page *page;
554 unsigned long *vaddr;
555
556 page = pfn_to_page(pfn);
557 vaddr = page_address(page);
558 if (!vaddr)
559 return;
560
561 vaddr[0] = iova;
562 vaddr[1] = pfn << PAGE_SHIFT;
563 FLUSH_CPU_DCACHE(vaddr, page, sizeof(vaddr[0]) * 2);
564}
565#else
566static inline void put_signature(struct smmu_as *as,
567 unsigned long addr, unsigned long pfn)
568{
569}
570#endif
571
572/*
f9a4f063 573 * Caller must not hold as->lock
7a31f6f4
HD		 574 */
575static int alloc_pdir(struct smmu_as *as)
576{
f9a4f063 577 unsigned long *pdir, flags;
9e971a03 578 int pdn, err = 0;
7a31f6f4
HD		 579 u32 val;
580 struct smmu_device *smmu = as->smmu;
9e971a03
HD		 581 struct page *page;
582 unsigned int *cnt;
7a31f6f4 583
9e971a03 584 /*
f9a4f063 585 * do the allocation, then grab as->lock
9e971a03 586 */
9e971a03 587 cnt = devm_kzalloc(smmu->dev,
f9a4f063
JR		 588 sizeof(cnt[0]) * SMMU_PDIR_COUNT,
589 GFP_KERNEL);
9e971a03 590 page = alloc_page(GFP_KERNEL | __GFP_DMA);
7a31f6f4 591
f9a4f063 592 spin_lock_irqsave(&as->lock, flags);
7a31f6f4 593
9e971a03
HD		 594 if (as->pdir_page) {
595 /* We raced, free the redundant */
596 err = -EAGAIN;
597 goto err_out;
7a31f6f4 598 }
9e971a03
HD		 599
600 if (!page || !cnt) {
601 dev_err(smmu->dev, "failed to allocate at %s\n", __func__);
602 err = -ENOMEM;
603 goto err_out;
7a31f6f4 604 }
9e971a03
HD		 605
606 as->pdir_page = page;
607 as->pte_count = cnt;
608
7a31f6f4
HD		 609 SetPageReserved(as->pdir_page);
610 pdir = page_address(as->pdir_page);
611
612 for (pdn = 0; pdn < SMMU_PDIR_COUNT; pdn++)
613 pdir[pdn] = _PDE_VACANT(pdn);
614 FLUSH_CPU_DCACHE(pdir, as->pdir_page, SMMU_PDIR_SIZE);
615 val = SMMU_PTC_FLUSH_TYPE_ADR | VA_PAGE_TO_PA(pdir, as->pdir_page);
616 smmu_write(smmu, val, SMMU_PTC_FLUSH);
617 FLUSH_SMMU_REGS(as->smmu);
618 val = SMMU_TLB_FLUSH_VA_MATCH_ALL |
619 SMMU_TLB_FLUSH_ASID_MATCH__ENABLE |
620 (as->asid << SMMU_TLB_FLUSH_ASID_SHIFT);
621 smmu_write(smmu, val, SMMU_TLB_FLUSH);
622 FLUSH_SMMU_REGS(as->smmu);
623
f9a4f063
JR		 624 spin_unlock_irqrestore(&as->lock, flags);
625
7a31f6f4 626 return 0;
9e971a03
HD		 627
628err_out:
f9a4f063
JR		 629 spin_unlock_irqrestore(&as->lock, flags);
630
9e971a03
HD		 631 devm_kfree(smmu->dev, cnt);
632 if (page)
633 __free_page(page);
634 return err;
7a31f6f4
HD		 635}
636
637static void __smmu_iommu_unmap(struct smmu_as *as, dma_addr_t iova)
638{
639 unsigned long *pte;
640 struct page *page;
641 unsigned int *count;
642
643 pte = locate_pte(as, iova, false, &page, &count);
644 if (WARN_ON(!pte))
645 return;
646
647 if (WARN_ON(*pte == _PTE_VACANT(iova)))
648 return;
649
650 *pte = _PTE_VACANT(iova);
651 FLUSH_CPU_DCACHE(pte, page, sizeof(*pte));
652 flush_ptc_and_tlb(as->smmu, as, iova, pte, page, 0);
653 if (!--(*count)) {
654 free_ptbl(as, iova);
655 smmu_flush_regs(as->smmu, 0);
656 }
657}
658
659static void __smmu_iommu_map_pfn(struct smmu_as *as, dma_addr_t iova,
660 unsigned long pfn)
661{
662 struct smmu_device *smmu = as->smmu;
663 unsigned long *pte;
664 unsigned int *count;
665 struct page *page;
666
667 pte = locate_pte(as, iova, true, &page, &count);
668 if (WARN_ON(!pte))
669 return;
670
671 if (*pte == _PTE_VACANT(iova))
672 (*count)++;
673 *pte = SMMU_PFN_TO_PTE(pfn, as->pte_attr);
674 if (unlikely((*pte == _PTE_VACANT(iova))))
675 (*count)--;
676 FLUSH_CPU_DCACHE(pte, page, sizeof(*pte));
677 flush_ptc_and_tlb(smmu, as, iova, pte, page, 0);
678 put_signature(as, iova, pfn);
679}
680
681static int smmu_iommu_map(struct iommu_domain *domain, unsigned long iova,
682 phys_addr_t pa, size_t bytes, int prot)
683{
684 struct smmu_as *as = domain->priv;
685 unsigned long pfn = __phys_to_pfn(pa);
686 unsigned long flags;
687
688 dev_dbg(as->smmu->dev, "[%d] %08lx:%08x\n", as->asid, iova, pa);
689
690 if (!pfn_valid(pfn))
691 return -ENOMEM;
692
693 spin_lock_irqsave(&as->lock, flags);
694 __smmu_iommu_map_pfn(as, iova, pfn);
695 spin_unlock_irqrestore(&as->lock, flags);
696 return 0;
697}
698
699static size_t smmu_iommu_unmap(struct iommu_domain *domain, unsigned long iova,
700 size_t bytes)
701{
702 struct smmu_as *as = domain->priv;
703 unsigned long flags;
704
705 dev_dbg(as->smmu->dev, "[%d] %08lx\n", as->asid, iova);
706
707 spin_lock_irqsave(&as->lock, flags);
708 __smmu_iommu_unmap(as, iova);
709 spin_unlock_irqrestore(&as->lock, flags);
710 return SMMU_PAGE_SIZE;
711}
712
713static phys_addr_t smmu_iommu_iova_to_phys(struct iommu_domain *domain,
714 unsigned long iova)
715{
716 struct smmu_as *as = domain->priv;
717 unsigned long *pte;
718 unsigned int *count;
719 struct page *page;
720 unsigned long pfn;
721 unsigned long flags;
722
723 spin_lock_irqsave(&as->lock, flags);
724
725 pte = locate_pte(as, iova, true, &page, &count);
726 pfn = *pte & SMMU_PFN_MASK;
727 WARN_ON(!pfn_valid(pfn));
728 dev_dbg(as->smmu->dev,
729 "iova:%08lx pfn:%08lx asid:%d\n", iova, pfn, as->asid);
730
731 spin_unlock_irqrestore(&as->lock, flags);
732 return PFN_PHYS(pfn);
733}
734
735static int smmu_iommu_domain_has_cap(struct iommu_domain *domain,
736 unsigned long cap)
737{
738 return 0;
739}
740
741static int smmu_iommu_attach_dev(struct iommu_domain *domain,
742 struct device *dev)
743{
744 struct smmu_as *as = domain->priv;
745 struct smmu_device *smmu = as->smmu;
746 struct smmu_client *client, *c;
747 u32 map;
748 int err;
749
750 client = devm_kzalloc(smmu->dev, sizeof(*c), GFP_KERNEL);
751 if (!client)
752 return -ENOMEM;
753 client->dev = dev;
754 client->as = as;
755 map = (unsigned long)dev->platform_data;
756 if (!map)
757 return -EINVAL;
758
759 err = smmu_client_enable_hwgrp(client, map);
760 if (err)
761 goto err_hwgrp;
762
763 spin_lock(&as->client_lock);
764 list_for_each_entry(c, &as->client, list) {
765 if (c->dev == dev) {
766 dev_err(smmu->dev,
767 "%s is already attached\n", dev_name(c->dev));
768 err = -EINVAL;
769 goto err_client;
770 }
771 }
772 list_add(&client->list, &as->client);
773 spin_unlock(&as->client_lock);
774
775 /*
776 * Reserve "page zero" for AVP vectors using a common dummy
777 * page.
778 */
779 if (map & HWG_AVPC) {
780 struct page *page;
781
782 page = as->smmu->avp_vector_page;
783 __smmu_iommu_map_pfn(as, 0, page_to_pfn(page));
784
785 pr_info("Reserve \"page zero\" for AVP vectors using a common dummy\n");
786 }
787
90730917 788 dev_dbg(smmu->dev, "%s is attached\n", dev_name(dev));
7a31f6f4
HD		 789 return 0;
790
791err_client:
792 smmu_client_disable_hwgrp(client);
793 spin_unlock(&as->client_lock);
794err_hwgrp:
795 devm_kfree(smmu->dev, client);
796 return err;
797}
798
799static void smmu_iommu_detach_dev(struct iommu_domain *domain,
800 struct device *dev)
801{
802 struct smmu_as *as = domain->priv;
803 struct smmu_device *smmu = as->smmu;
804 struct smmu_client *c;
805
806 spin_lock(&as->client_lock);
807
808 list_for_each_entry(c, &as->client, list) {
809 if (c->dev == dev) {
810 smmu_client_disable_hwgrp(c);
811 list_del(&c->list);
812 devm_kfree(smmu->dev, c);
813 c->as = NULL;
814 dev_dbg(smmu->dev,
815 "%s is detached\n", dev_name(c->dev));
816 goto out;
817 }
818 }
819 dev_err(smmu->dev, "Couldn't find %s\n", dev_name(c->dev));
820out:
821 spin_unlock(&as->client_lock);
822}
823
824static int smmu_iommu_domain_init(struct iommu_domain *domain)
825{
9e971a03 826 int i, err = -ENODEV;
7a31f6f4
HD		 827 unsigned long flags;
828 struct smmu_as *as;
829 struct smmu_device *smmu = smmu_handle;
830
831 /* Look for a free AS with lock held */
832 for (i = 0; i < smmu->num_as; i++) {
9e971a03 833 as = &smmu->as[i];
9e971a03 834 if (!as->pdir_page) {
f9a4f063 835 err = alloc_pdir(as);
9e971a03
HD		 836 if (!err)
837 goto found;
7a31f6f4 838 }
9e971a03
HD		 839 if (err != -EAGAIN)
840 break;
7a31f6f4 841 }
9e971a03
HD		 842 if (i == smmu->num_as)
843 dev_err(smmu->dev, "no free AS\n");
844 return err;
7a31f6f4
HD		 845
846found:
f9a4f063 847 spin_lock_irqsave(&smmu->lock, flags);
7a31f6f4
HD		 848
849 /* Update PDIR register */
850 smmu_write(smmu, SMMU_PTB_ASID_CUR(as->asid), SMMU_PTB_ASID);
851 smmu_write(smmu,
852 SMMU_MK_PDIR(as->pdir_page, as->pdir_attr), SMMU_PTB_DATA);
853 FLUSH_SMMU_REGS(smmu);
854
f9a4f063 855 spin_unlock_irqrestore(&smmu->lock, flags);
7a31f6f4 856
7a31f6f4
HD		 857 domain->priv = as;
858
23349902
HD		 859 domain->geometry.aperture_start = smmu->iovmm_base;
860 domain->geometry.aperture_end = smmu->iovmm_base +
861 smmu->page_count * SMMU_PAGE_SIZE - 1;
862 domain->geometry.force_aperture = true;
863
7a31f6f4 864 dev_dbg(smmu->dev, "smmu_as@%p\n", as);
7a31f6f4 865
7a31f6f4 866 return 0;
7a31f6f4
HD		 867}
868
869static void smmu_iommu_domain_destroy(struct iommu_domain *domain)
870{
871 struct smmu_as *as = domain->priv;
872 struct smmu_device *smmu = as->smmu;
873 unsigned long flags;
874
875 spin_lock_irqsave(&as->lock, flags);
876
877 if (as->pdir_page) {
878 spin_lock(&smmu->lock);
879 smmu_write(smmu, SMMU_PTB_ASID_CUR(as->asid), SMMU_PTB_ASID);
880 smmu_write(smmu, SMMU_PTB_DATA_RESET_VAL, SMMU_PTB_DATA);
881 FLUSH_SMMU_REGS(smmu);
882 spin_unlock(&smmu->lock);
883
884 free_pdir(as);
885 }
886
887 if (!list_empty(&as->client)) {
888 struct smmu_client *c;
889
890 list_for_each_entry(c, &as->client, list)
891 smmu_iommu_detach_dev(domain, c->dev);
892 }
893
894 spin_unlock_irqrestore(&as->lock, flags);
895
896 domain->priv = NULL;
897 dev_dbg(smmu->dev, "smmu_as@%p\n", as);
898}
899
900static struct iommu_ops smmu_iommu_ops = {
901 .domain_init = smmu_iommu_domain_init,
902 .domain_destroy = smmu_iommu_domain_destroy,
903 .attach_dev = smmu_iommu_attach_dev,
904 .detach_dev = smmu_iommu_detach_dev,
905 .map = smmu_iommu_map,
906 .unmap = smmu_iommu_unmap,
907 .iova_to_phys = smmu_iommu_iova_to_phys,
908 .domain_has_cap = smmu_iommu_domain_has_cap,
909 .pgsize_bitmap = SMMU_IOMMU_PGSIZES,
910};
911
39abf8aa
HD		 912/* Should be in the order of enum */
913static const char * const smmu_debugfs_mc[] = { "mc", };
914static const char * const smmu_debugfs_cache[] = { "tlb", "ptc", };
915
916static ssize_t smmu_debugfs_stats_write(struct file *file,
917 const char __user *buffer,
918 size_t count, loff_t *pos)
919{
920 struct smmu_device *smmu;
921 struct dentry *dent;
922 int i, cache, mc;
923 enum {
924 _OFF = 0,
925 _ON,
926 _RESET,
927 };
928 const char * const command[] = {
929 [_OFF] = "off",
930 [_ON] = "on",
931 [_RESET] = "reset",
932 };
933 char str[] = "reset";
934 u32 val;
935 size_t offs;
936
937 count = min_t(size_t, count, sizeof(str));
938 if (copy_from_user(str, buffer, count))
939 return -EINVAL;
940
941 for (i = 0; i < ARRAY_SIZE(command); i++)
942 if (strncmp(str, command[i],
943 strlen(command[i])) == 0)
944 break;
945
946 if (i == ARRAY_SIZE(command))
947 return -EINVAL;
948
949 dent = file->f_dentry;
950 cache = (int)dent->d_inode->i_private;
951 mc = (int)dent->d_parent->d_inode->i_private;
952 smmu = dent->d_parent->d_parent->d_inode->i_private;
953
954 offs = SMMU_CACHE_CONFIG(cache);
955 val = smmu_read(smmu, offs);
956 switch (i) {
957 case _OFF:
958 val &= ~SMMU_CACHE_CONFIG_STATS_ENABLE;
959 val &= ~SMMU_CACHE_CONFIG_STATS_TEST;
960 smmu_write(smmu, val, offs);
961 break;
962 case _ON:
963 val |= SMMU_CACHE_CONFIG_STATS_ENABLE;
964 val &= ~SMMU_CACHE_CONFIG_STATS_TEST;
965 smmu_write(smmu, val, offs);
966 break;
967 case _RESET:
968 val |= SMMU_CACHE_CONFIG_STATS_TEST;
969 smmu_write(smmu, val, offs);
970 val &= ~SMMU_CACHE_CONFIG_STATS_TEST;
971 smmu_write(smmu, val, offs);
972 break;
973 default:
974 BUG();
975 break;
976 }
977
978 dev_dbg(smmu->dev, "%s() %08x, %08x @%08x\n", __func__,
979 val, smmu_read(smmu, offs), offs);
980
981 return count;
982}
983
984static int smmu_debugfs_stats_show(struct seq_file *s, void *v)
985{
986 struct smmu_device *smmu;
987 struct dentry *dent;
988 int i, cache, mc;
989 const char * const stats[] = { "hit", "miss", };
990
991 dent = d_find_alias(s->private);
992 cache = (int)dent->d_inode->i_private;
993 mc = (int)dent->d_parent->d_inode->i_private;
994 smmu = dent->d_parent->d_parent->d_inode->i_private;
995
996 for (i = 0; i < ARRAY_SIZE(stats); i++) {
997 u32 val;
998 size_t offs;
999
1000 offs = SMMU_STATS_CACHE_COUNT(mc, cache, i);
1001 val = smmu_read(smmu, offs);
1002 seq_printf(s, "%s:%08x ", stats[i], val);
1003
1004 dev_dbg(smmu->dev, "%s() %s %08x @%08x\n", __func__,
1005 stats[i], val, offs);
1006 }
1007 seq_printf(s, "\n");
1008
1009 return 0;
1010}
1011
1012static int smmu_debugfs_stats_open(struct inode *inode, struct file *file)
1013{
1014 return single_open(file, smmu_debugfs_stats_show, inode);
1015}
1016
1017static const struct file_operations smmu_debugfs_stats_fops = {
1018 .open = smmu_debugfs_stats_open,
1019 .read = seq_read,
1020 .llseek = seq_lseek,
1021 .release = single_release,
1022 .write = smmu_debugfs_stats_write,
1023};
1024
1025static void smmu_debugfs_delete(struct smmu_device *smmu)
1026{
1027 debugfs_remove_recursive(smmu->debugfs_root);
1028}
1029
1030static void smmu_debugfs_create(struct smmu_device *smmu)
1031{
1032 int i;
1033 struct dentry *root;
1034
1035 root = debugfs_create_file(dev_name(smmu->dev),
1036 S_IFDIR | S_IRWXU | S_IRUGO | S_IXUGO,
1037 NULL, smmu, NULL);
1038 if (!root)
1039 goto err_out;
1040 smmu->debugfs_root = root;
1041
1042 for (i = 0; i < ARRAY_SIZE(smmu_debugfs_mc); i++) {
1043 int j;
1044 struct dentry *mc;
1045
1046 mc = debugfs_create_file(smmu_debugfs_mc[i],
1047 S_IFDIR | S_IRWXU | S_IRUGO | S_IXUGO,
1048 root, (void *)i, NULL);
1049 if (!mc)
1050 goto err_out;
1051
1052 for (j = 0; j < ARRAY_SIZE(smmu_debugfs_cache); j++) {
1053 struct dentry *cache;
1054
1055 cache = debugfs_create_file(smmu_debugfs_cache[j],
1056 S_IWUGO | S_IRUGO, mc,
1057 (void *)j,
1058 &smmu_debugfs_stats_fops);
1059 if (!cache)
1060 goto err_out;
1061 }
1062 }
1063
1064 return;
1065
1066err_out:
1067 smmu_debugfs_delete(smmu);
1068}
1069
7a31f6f4
HD		 1070static int tegra_smmu_suspend(struct device *dev)
1071{
1072 struct smmu_device *smmu = dev_get_drvdata(dev);
1073
1074 smmu->translation_enable_0 = smmu_read(smmu, SMMU_TRANSLATION_ENABLE_0);
1075 smmu->translation_enable_1 = smmu_read(smmu, SMMU_TRANSLATION_ENABLE_1);
1076 smmu->translation_enable_2 = smmu_read(smmu, SMMU_TRANSLATION_ENABLE_2);
1077 smmu->asid_security = smmu_read(smmu, SMMU_ASID_SECURITY);
1078 return 0;
1079}
1080
1081static int tegra_smmu_resume(struct device *dev)
1082{
1083 struct smmu_device *smmu = dev_get_drvdata(dev);
1084 unsigned long flags;
0760e8fa 1085 int err;
7a31f6f4
HD		 1086
1087 spin_lock_irqsave(&smmu->lock, flags);
0760e8fa 1088 err = smmu_setup_regs(smmu);
7a31f6f4 1089 spin_unlock_irqrestore(&smmu->lock, flags);
0760e8fa 1090 return err;
7a31f6f4
HD		 1091}
1092
1093static int tegra_smmu_probe(struct platform_device *pdev)
1094{
1095 struct smmu_device *smmu;
7a31f6f4 1096 struct device *dev = &pdev->dev;
0760e8fa 1097 int i, asids, err = 0;
ff763629
HD		 1098 dma_addr_t uninitialized_var(base);
1099 size_t bytes, uninitialized_var(size);
7a31f6f4
HD		 1100
1101 if (smmu_handle)
1102 return -EIO;
1103
1104 BUILD_BUG_ON(PAGE_SHIFT != SMMU_PAGE_SHIFT);
1105
a3b24915 1106 if (of_property_read_u32(dev->of_node, "nvidia,#asids", &asids))
7a31f6f4 1107 return -ENODEV;
7a31f6f4 1108
a3b24915
HD		 1109 bytes = sizeof(*smmu) + asids * sizeof(*smmu->as);
1110 smmu = devm_kzalloc(dev, bytes, GFP_KERNEL);
7a31f6f4
HD		 1111 if (!smmu) {
1112 dev_err(dev, "failed to allocate smmu_device\n");
1113 return -ENOMEM;
1114 }
1115
0760e8fa
HD		 1116 for (i = 0; i < ARRAY_SIZE(smmu->regs); i++) {
1117 struct resource *res;
1118
1119 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
1120 if (!res)
1121 return -ENODEV;
1122 smmu->regs[i] = devm_request_and_ioremap(&pdev->dev, res);
1123 if (!smmu->regs[i])
1124 return -EBUSY;
7a31f6f4
HD		 1125 }
1126
0760e8fa
HD		 1127 err = of_get_dma_window(dev->of_node, NULL, 0, NULL, &base, &size);
1128 if (err)
1129 return -ENODEV;
1130
1131 if (size & SMMU_PAGE_MASK)
1132 return -EINVAL;
1133
1134 size >>= SMMU_PAGE_SHIFT;
1135 if (!size)
1136 return -EINVAL;
1137
0760e8fa
HD		 1138 smmu->ahb = of_parse_phandle(dev->of_node, "nvidia,ahb", 0);
1139 if (!smmu->ahb)
1140 return -ENODEV;
1141
1142 smmu->dev = dev;
1143 smmu->num_as = asids;
1144 smmu->iovmm_base = base;
1145 smmu->page_count = size;
1146
7a31f6f4
HD		 1147 smmu->translation_enable_0 = ~0;
1148 smmu->translation_enable_1 = ~0;
1149 smmu->translation_enable_2 = ~0;
1150 smmu->asid_security = 0;
1151
7a31f6f4
HD		 1152 for (i = 0; i < smmu->num_as; i++) {
1153 struct smmu_as *as = &smmu->as[i];
1154
1155 as->smmu = smmu;
1156 as->asid = i;
1157 as->pdir_attr = _PDIR_ATTR;
1158 as->pde_attr = _PDE_ATTR;
1159 as->pte_attr = _PTE_ATTR;
1160
1161 spin_lock_init(&as->lock);
1162 INIT_LIST_HEAD(&as->client);
1163 }
1164 spin_lock_init(&smmu->lock);
0760e8fa
HD		 1165 err = smmu_setup_regs(smmu);
1166 if (err)
0547c2f5 1167 return err;
7a31f6f4
HD		 1168 platform_set_drvdata(pdev, smmu);
1169
1170 smmu->avp_vector_page = alloc_page(GFP_KERNEL);
1171 if (!smmu->avp_vector_page)
0547c2f5 1172 return -ENOMEM;
7a31f6f4 1173
39abf8aa 1174 smmu_debugfs_create(smmu);
7a31f6f4
HD		 1175 smmu_handle = smmu;
1176 return 0;
7a31f6f4
HD		 1177}
1178
1179static int tegra_smmu_remove(struct platform_device *pdev)
1180{
1181 struct smmu_device *smmu = platform_get_drvdata(pdev);
0547c2f5 1182 int i;
7a31f6f4 1183
39abf8aa
HD		 1184 smmu_debugfs_delete(smmu);
1185
7a31f6f4 1186 smmu_write(smmu, SMMU_CONFIG_DISABLE, SMMU_CONFIG);
0547c2f5
HD		 1187 for (i = 0; i < smmu->num_as; i++)
1188 free_pdir(&smmu->as[i]);
1189 __free_page(smmu->avp_vector_page);
7a31f6f4
HD		 1190 smmu_handle = NULL;
1191 return 0;
1192}
1193
1194const struct dev_pm_ops tegra_smmu_pm_ops = {
1195 .suspend = tegra_smmu_suspend,
1196 .resume = tegra_smmu_resume,
1197};
1198
0760e8fa
HD		 1199#ifdef CONFIG_OF
1200static struct of_device_id tegra_smmu_of_match[] __devinitdata = {
1201 { .compatible = "nvidia,tegra30-smmu", },
1202 { },
1203};
1204MODULE_DEVICE_TABLE(of, tegra_smmu_of_match);
1205#endif
1206
7a31f6f4
HD		 1207static struct platform_driver tegra_smmu_driver = {
1208 .probe = tegra_smmu_probe,
1209 .remove = tegra_smmu_remove,
1210 .driver = {
1211 .owner = THIS_MODULE,
1212 .name = "tegra-smmu",
1213 .pm = &tegra_smmu_pm_ops,
0760e8fa 1214 .of_match_table = of_match_ptr(tegra_smmu_of_match),
7a31f6f4
HD		 1215 },
1216};
1217
1218static int __devinit tegra_smmu_init(void)
1219{
1220 bus_set_iommu(&platform_bus_type, &smmu_iommu_ops);
1221 return platform_driver_register(&tegra_smmu_driver);
1222}
1223
1224static void __exit tegra_smmu_exit(void)
1225{
1226 platform_driver_unregister(&tegra_smmu_driver);
1227}
1228
1229subsys_initcall(tegra_smmu_init);
1230module_exit(tegra_smmu_exit);
1231
1232MODULE_DESCRIPTION("IOMMU API for SMMU in Tegra30");
1233MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>");
0760e8fa 1234MODULE_ALIAS("platform:tegra-smmu");
7a31f6f4 1235MODULE_LICENSE("GPL v2");
kernel source for telekom puls (alcatel/mediatek)