projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'master' into next
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / infiniband / hw / qib / qib_iba6120.c
CommitLineData
f931551b
RC		 1/*
2 * Copyright (c) 2006, 2007, 2008, 2009, 2010 QLogic Corporation.
3 * All rights reserved.
4 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34/*
35 * This file contains all of the code that is specific to the
36 * QLogic_IB 6120 PCIe chip.
37 */
38
39#include <linux/interrupt.h>
40#include <linux/pci.h>
41#include <linux/delay.h>
42#include <rdma/ib_verbs.h>
43
44#include "qib.h"
45#include "qib_6120_regs.h"
46
47static void qib_6120_setup_setextled(struct qib_pportdata *, u32);
48static void sendctrl_6120_mod(struct qib_pportdata *ppd, u32 op);
49static u8 qib_6120_phys_portstate(u64);
50static u32 qib_6120_iblink_state(u64);
51
52/*
53 * This file contains all the chip-specific register information and
54 * access functions for the QLogic QLogic_IB PCI-Express chip.
55 *
56 */
57
58/* KREG_IDX uses machine-generated #defines */
59#define KREG_IDX(regname) (QIB_6120_##regname##_OFFS / sizeof(u64))
60
61/* Use defines to tie machine-generated names to lower-case names */
62#define kr_extctrl KREG_IDX(EXTCtrl)
63#define kr_extstatus KREG_IDX(EXTStatus)
64#define kr_gpio_clear KREG_IDX(GPIOClear)
65#define kr_gpio_mask KREG_IDX(GPIOMask)
66#define kr_gpio_out KREG_IDX(GPIOOut)
67#define kr_gpio_status KREG_IDX(GPIOStatus)
68#define kr_rcvctrl KREG_IDX(RcvCtrl)
69#define kr_sendctrl KREG_IDX(SendCtrl)
70#define kr_partitionkey KREG_IDX(RcvPartitionKey)
71#define kr_hwdiagctrl KREG_IDX(HwDiagCtrl)
72#define kr_ibcstatus KREG_IDX(IBCStatus)
73#define kr_ibcctrl KREG_IDX(IBCCtrl)
74#define kr_sendbuffererror KREG_IDX(SendBufErr0)
75#define kr_rcvbthqp KREG_IDX(RcvBTHQP)
76#define kr_counterregbase KREG_IDX(CntrRegBase)
77#define kr_palign KREG_IDX(PageAlign)
78#define kr_rcvegrbase KREG_IDX(RcvEgrBase)
79#define kr_rcvegrcnt KREG_IDX(RcvEgrCnt)
80#define kr_rcvhdrcnt KREG_IDX(RcvHdrCnt)
81#define kr_rcvhdrentsize KREG_IDX(RcvHdrEntSize)
82#define kr_rcvhdrsize KREG_IDX(RcvHdrSize)
83#define kr_rcvtidbase KREG_IDX(RcvTIDBase)
84#define kr_rcvtidcnt KREG_IDX(RcvTIDCnt)
85#define kr_scratch KREG_IDX(Scratch)
86#define kr_sendctrl KREG_IDX(SendCtrl)
87#define kr_sendpioavailaddr KREG_IDX(SendPIOAvailAddr)
88#define kr_sendpiobufbase KREG_IDX(SendPIOBufBase)
89#define kr_sendpiobufcnt KREG_IDX(SendPIOBufCnt)
90#define kr_sendpiosize KREG_IDX(SendPIOSize)
91#define kr_sendregbase KREG_IDX(SendRegBase)
92#define kr_userregbase KREG_IDX(UserRegBase)
93#define kr_control KREG_IDX(Control)
94#define kr_intclear KREG_IDX(IntClear)
95#define kr_intmask KREG_IDX(IntMask)
96#define kr_intstatus KREG_IDX(IntStatus)
97#define kr_errclear KREG_IDX(ErrClear)
98#define kr_errmask KREG_IDX(ErrMask)
99#define kr_errstatus KREG_IDX(ErrStatus)
100#define kr_hwerrclear KREG_IDX(HwErrClear)
101#define kr_hwerrmask KREG_IDX(HwErrMask)
102#define kr_hwerrstatus KREG_IDX(HwErrStatus)
103#define kr_revision KREG_IDX(Revision)
104#define kr_portcnt KREG_IDX(PortCnt)
105#define kr_serdes_cfg0 KREG_IDX(SerdesCfg0)
106#define kr_serdes_cfg1 (kr_serdes_cfg0 + 1)
107#define kr_serdes_stat KREG_IDX(SerdesStat)
108#define kr_xgxs_cfg KREG_IDX(XGXSCfg)
109
110/* These must only be written via qib_write_kreg_ctxt() */
111#define kr_rcvhdraddr KREG_IDX(RcvHdrAddr0)
112#define kr_rcvhdrtailaddr KREG_IDX(RcvHdrTailAddr0)
113
114#define CREG_IDX(regname) ((QIB_6120_##regname##_OFFS - \
115 QIB_6120_LBIntCnt_OFFS) / sizeof(u64))
116
117#define cr_badformat CREG_IDX(RxBadFormatCnt)
118#define cr_erricrc CREG_IDX(RxICRCErrCnt)
119#define cr_errlink CREG_IDX(RxLinkProblemCnt)
120#define cr_errlpcrc CREG_IDX(RxLPCRCErrCnt)
121#define cr_errpkey CREG_IDX(RxPKeyMismatchCnt)
122#define cr_rcvflowctrl_err CREG_IDX(RxFlowCtrlErrCnt)
123#define cr_err_rlen CREG_IDX(RxLenErrCnt)
124#define cr_errslen CREG_IDX(TxLenErrCnt)
125#define cr_errtidfull CREG_IDX(RxTIDFullErrCnt)
126#define cr_errtidvalid CREG_IDX(RxTIDValidErrCnt)
127#define cr_errvcrc CREG_IDX(RxVCRCErrCnt)
128#define cr_ibstatuschange CREG_IDX(IBStatusChangeCnt)
129#define cr_lbint CREG_IDX(LBIntCnt)
130#define cr_invalidrlen CREG_IDX(RxMaxMinLenErrCnt)
131#define cr_invalidslen CREG_IDX(TxMaxMinLenErrCnt)
132#define cr_lbflowstall CREG_IDX(LBFlowStallCnt)
133#define cr_pktrcv CREG_IDX(RxDataPktCnt)
134#define cr_pktrcvflowctrl CREG_IDX(RxFlowPktCnt)
135#define cr_pktsend CREG_IDX(TxDataPktCnt)
136#define cr_pktsendflow CREG_IDX(TxFlowPktCnt)
137#define cr_portovfl CREG_IDX(RxP0HdrEgrOvflCnt)
138#define cr_rcvebp CREG_IDX(RxEBPCnt)
139#define cr_rcvovfl CREG_IDX(RxBufOvflCnt)
140#define cr_senddropped CREG_IDX(TxDroppedPktCnt)
141#define cr_sendstall CREG_IDX(TxFlowStallCnt)
142#define cr_sendunderrun CREG_IDX(TxUnderrunCnt)
143#define cr_wordrcv CREG_IDX(RxDwordCnt)
144#define cr_wordsend CREG_IDX(TxDwordCnt)
145#define cr_txunsupvl CREG_IDX(TxUnsupVLErrCnt)
146#define cr_rxdroppkt CREG_IDX(RxDroppedPktCnt)
147#define cr_iblinkerrrecov CREG_IDX(IBLinkErrRecoveryCnt)
148#define cr_iblinkdown CREG_IDX(IBLinkDownedCnt)
149#define cr_ibsymbolerr CREG_IDX(IBSymbolErrCnt)
150
151#define SYM_RMASK(regname, fldname) ((u64) \
152 QIB_6120_##regname##_##fldname##_RMASK)
153#define SYM_MASK(regname, fldname) ((u64) \
154 QIB_6120_##regname##_##fldname##_RMASK << \
155 QIB_6120_##regname##_##fldname##_LSB)
156#define SYM_LSB(regname, fldname) (QIB_6120_##regname##_##fldname##_LSB)
157
158#define SYM_FIELD(value, regname, fldname) ((u64) \
159 (((value) >> SYM_LSB(regname, fldname)) & \
160 SYM_RMASK(regname, fldname)))
161#define ERR_MASK(fldname) SYM_MASK(ErrMask, fldname##Mask)
162#define HWE_MASK(fldname) SYM_MASK(HwErrMask, fldname##Mask)
163
164/* link training states, from IBC */
165#define IB_6120_LT_STATE_DISABLED 0x00
166#define IB_6120_LT_STATE_LINKUP 0x01
167#define IB_6120_LT_STATE_POLLACTIVE 0x02
168#define IB_6120_LT_STATE_POLLQUIET 0x03
169#define IB_6120_LT_STATE_SLEEPDELAY 0x04
170#define IB_6120_LT_STATE_SLEEPQUIET 0x05
171#define IB_6120_LT_STATE_CFGDEBOUNCE 0x08
172#define IB_6120_LT_STATE_CFGRCVFCFG 0x09
173#define IB_6120_LT_STATE_CFGWAITRMT 0x0a
174#define IB_6120_LT_STATE_CFGIDLE 0x0b
175#define IB_6120_LT_STATE_RECOVERRETRAIN 0x0c
176#define IB_6120_LT_STATE_RECOVERWAITRMT 0x0e
177#define IB_6120_LT_STATE_RECOVERIDLE 0x0f
178
179/* link state machine states from IBC */
180#define IB_6120_L_STATE_DOWN 0x0
181#define IB_6120_L_STATE_INIT 0x1
182#define IB_6120_L_STATE_ARM 0x2
183#define IB_6120_L_STATE_ACTIVE 0x3
184#define IB_6120_L_STATE_ACT_DEFER 0x4
185
186static const u8 qib_6120_physportstate[0x20] = {
187 [IB_6120_LT_STATE_DISABLED] = IB_PHYSPORTSTATE_DISABLED,
188 [IB_6120_LT_STATE_LINKUP] = IB_PHYSPORTSTATE_LINKUP,
189 [IB_6120_LT_STATE_POLLACTIVE] = IB_PHYSPORTSTATE_POLL,
190 [IB_6120_LT_STATE_POLLQUIET] = IB_PHYSPORTSTATE_POLL,
191 [IB_6120_LT_STATE_SLEEPDELAY] = IB_PHYSPORTSTATE_SLEEP,
192 [IB_6120_LT_STATE_SLEEPQUIET] = IB_PHYSPORTSTATE_SLEEP,
193 [IB_6120_LT_STATE_CFGDEBOUNCE] =
194 IB_PHYSPORTSTATE_CFG_TRAIN,
195 [IB_6120_LT_STATE_CFGRCVFCFG] =
196 IB_PHYSPORTSTATE_CFG_TRAIN,
197 [IB_6120_LT_STATE_CFGWAITRMT] =
198 IB_PHYSPORTSTATE_CFG_TRAIN,
199 [IB_6120_LT_STATE_CFGIDLE] = IB_PHYSPORTSTATE_CFG_TRAIN,
200 [IB_6120_LT_STATE_RECOVERRETRAIN] =
201 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
202 [IB_6120_LT_STATE_RECOVERWAITRMT] =
203 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
204 [IB_6120_LT_STATE_RECOVERIDLE] =
205 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
206 [0x10] = IB_PHYSPORTSTATE_CFG_TRAIN,
207 [0x11] = IB_PHYSPORTSTATE_CFG_TRAIN,
208 [0x12] = IB_PHYSPORTSTATE_CFG_TRAIN,
209 [0x13] = IB_PHYSPORTSTATE_CFG_TRAIN,
210 [0x14] = IB_PHYSPORTSTATE_CFG_TRAIN,
211 [0x15] = IB_PHYSPORTSTATE_CFG_TRAIN,
212 [0x16] = IB_PHYSPORTSTATE_CFG_TRAIN,
213 [0x17] = IB_PHYSPORTSTATE_CFG_TRAIN
214};
215
216
217struct qib_chip_specific {
218 u64 __iomem *cregbase;
219 u64 *cntrs;
220 u64 *portcntrs;
221 void *dummy_hdrq; /* used after ctxt close */
222 dma_addr_t dummy_hdrq_phys;
223 spinlock_t kernel_tid_lock; /* no back to back kernel TID writes */
224 spinlock_t user_tid_lock; /* no back to back user TID writes */
225 spinlock_t rcvmod_lock; /* protect rcvctrl shadow changes */
226 spinlock_t gpio_lock; /* RMW of shadows/regs for ExtCtrl and GPIO */
227 u64 hwerrmask;
228 u64 errormask;
229 u64 gpio_out; /* shadow of kr_gpio_out, for rmw ops */
230 u64 gpio_mask; /* shadow the gpio mask register */
231 u64 extctrl; /* shadow the gpio output enable, etc... */
232 /*
233 * these 5 fields are used to establish deltas for IB symbol
234 * errors and linkrecovery errors. They can be reported on
235 * some chips during link negotiation prior to INIT, and with
236 * DDR when faking DDR negotiations with non-IBTA switches.
237 * The chip counters are adjusted at driver unload if there is
238 * a non-zero delta.
239 */
240 u64 ibdeltainprog;
241 u64 ibsymdelta;
242 u64 ibsymsnap;
243 u64 iblnkerrdelta;
244 u64 iblnkerrsnap;
245 u64 ibcctrl; /* shadow for kr_ibcctrl */
246 u32 lastlinkrecov; /* link recovery issue */
247 int irq;
248 u32 cntrnamelen;
249 u32 portcntrnamelen;
250 u32 ncntrs;
251 u32 nportcntrs;
252 /* used with gpio interrupts to implement IB counters */
253 u32 rxfc_unsupvl_errs;
254 u32 overrun_thresh_errs;
255 /*
256 * these count only cases where _successive_ LocalLinkIntegrity
257 * errors were seen in the receive headers of IB standard packets
258 */
259 u32 lli_errs;
260 u32 lli_counter;
261 u64 lli_thresh;
262 u64 sword; /* total dwords sent (sample result) */
263 u64 rword; /* total dwords received (sample result) */
264 u64 spkts; /* total packets sent (sample result) */
265 u64 rpkts; /* total packets received (sample result) */
266 u64 xmit_wait; /* # of ticks no data sent (sample result) */
267 struct timer_list pma_timer;
268 char emsgbuf[128];
269 char bitsmsgbuf[64];
270 u8 pma_sample_status;
271};
272
273/* ibcctrl bits */
274#define QLOGIC_IB_IBCC_LINKINITCMD_DISABLE 1
275/* cycle through TS1/TS2 till OK */
276#define QLOGIC_IB_IBCC_LINKINITCMD_POLL 2
277/* wait for TS1, then go on */
278#define QLOGIC_IB_IBCC_LINKINITCMD_SLEEP 3
279#define QLOGIC_IB_IBCC_LINKINITCMD_SHIFT 16
280
281#define QLOGIC_IB_IBCC_LINKCMD_DOWN 1 /* move to 0x11 */
282#define QLOGIC_IB_IBCC_LINKCMD_ARMED 2 /* move to 0x21 */
283#define QLOGIC_IB_IBCC_LINKCMD_ACTIVE 3 /* move to 0x31 */
284#define QLOGIC_IB_IBCC_LINKCMD_SHIFT 18
285
286/*
287 * We could have a single register get/put routine, that takes a group type,
288 * but this is somewhat clearer and cleaner. It also gives us some error
289 * checking. 64 bit register reads should always work, but are inefficient
290 * on opteron (the northbridge always generates 2 separate HT 32 bit reads),
291 * so we use kreg32 wherever possible. User register and counter register
292 * reads are always 32 bit reads, so only one form of those routines.
293 */
294
295/**
296 * qib_read_ureg32 - read 32-bit virtualized per-context register
297 * @dd: device
298 * @regno: register number
299 * @ctxt: context number
300 *
301 * Return the contents of a register that is virtualized to be per context.
302 * Returns -1 on errors (not distinguishable from valid contents at
303 * runtime; we may add a separate error variable at some point).
304 */
305static inline u32 qib_read_ureg32(const struct qib_devdata *dd,
306 enum qib_ureg regno, int ctxt)
307{
308 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
309 return 0;
310
311 if (dd->userbase)
312 return readl(regno + (u64 __iomem *)
313 ((char __iomem *)dd->userbase +
314 dd->ureg_align * ctxt));
315 else
316 return readl(regno + (u64 __iomem *)
317 (dd->uregbase +
318 (char __iomem *)dd->kregbase +
319 dd->ureg_align * ctxt));
320}
321
322/**
323 * qib_write_ureg - write 32-bit virtualized per-context register
324 * @dd: device
325 * @regno: register number
326 * @value: value
327 * @ctxt: context
328 *
329 * Write the contents of a register that is virtualized to be per context.
330 */
331static inline void qib_write_ureg(const struct qib_devdata *dd,
332 enum qib_ureg regno, u64 value, int ctxt)
333{
334 u64 __iomem *ubase;
335 if (dd->userbase)
336 ubase = (u64 __iomem *)
337 ((char __iomem *) dd->userbase +
338 dd->ureg_align * ctxt);
339 else
340 ubase = (u64 __iomem *)
341 (dd->uregbase +
342 (char __iomem *) dd->kregbase +
343 dd->ureg_align * ctxt);
344
345 if (dd->kregbase && (dd->flags & QIB_PRESENT))
346 writeq(value, &ubase[regno]);
347}
348
349static inline u32 qib_read_kreg32(const struct qib_devdata *dd,
350 const u16 regno)
351{
352 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
353 return -1;
354 return readl((u32 __iomem *)&dd->kregbase[regno]);
355}
356
357static inline u64 qib_read_kreg64(const struct qib_devdata *dd,
358 const u16 regno)
359{
360 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
361 return -1;
362
363 return readq(&dd->kregbase[regno]);
364}
365
366static inline void qib_write_kreg(const struct qib_devdata *dd,
367 const u16 regno, u64 value)
368{
369 if (dd->kregbase && (dd->flags & QIB_PRESENT))
370 writeq(value, &dd->kregbase[regno]);
371}
372
373/**
374 * qib_write_kreg_ctxt - write a device's per-ctxt 64-bit kernel register
375 * @dd: the qlogic_ib device
376 * @regno: the register number to write
377 * @ctxt: the context containing the register
378 * @value: the value to write
379 */
380static inline void qib_write_kreg_ctxt(const struct qib_devdata *dd,
381 const u16 regno, unsigned ctxt,
382 u64 value)
383{
384 qib_write_kreg(dd, regno + ctxt, value);
385}
386
387static inline void write_6120_creg(const struct qib_devdata *dd,
388 u16 regno, u64 value)
389{
390 if (dd->cspec->cregbase && (dd->flags & QIB_PRESENT))
391 writeq(value, &dd->cspec->cregbase[regno]);
392}
393
394static inline u64 read_6120_creg(const struct qib_devdata *dd, u16 regno)
395{
396 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
397 return 0;
398 return readq(&dd->cspec->cregbase[regno]);
399}
400
401static inline u32 read_6120_creg32(const struct qib_devdata *dd, u16 regno)
402{
403 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
404 return 0;
405 return readl(&dd->cspec->cregbase[regno]);
406}
407
408/* kr_control bits */
409#define QLOGIC_IB_C_RESET 1U
410
411/* kr_intstatus, kr_intclear, kr_intmask bits */
412#define QLOGIC_IB_I_RCVURG_MASK ((1U << 5) - 1)
413#define QLOGIC_IB_I_RCVURG_SHIFT 0
414#define QLOGIC_IB_I_RCVAVAIL_MASK ((1U << 5) - 1)
415#define QLOGIC_IB_I_RCVAVAIL_SHIFT 12
416
417#define QLOGIC_IB_C_FREEZEMODE 0x00000002
418#define QLOGIC_IB_C_LINKENABLE 0x00000004
419#define QLOGIC_IB_I_ERROR 0x0000000080000000ULL
420#define QLOGIC_IB_I_SPIOSENT 0x0000000040000000ULL
421#define QLOGIC_IB_I_SPIOBUFAVAIL 0x0000000020000000ULL
422#define QLOGIC_IB_I_GPIO 0x0000000010000000ULL
423#define QLOGIC_IB_I_BITSEXTANT \
424 ((QLOGIC_IB_I_RCVURG_MASK << QLOGIC_IB_I_RCVURG_SHIFT) | \
425 (QLOGIC_IB_I_RCVAVAIL_MASK << \
426 QLOGIC_IB_I_RCVAVAIL_SHIFT) | \
427 QLOGIC_IB_I_ERROR | QLOGIC_IB_I_SPIOSENT | \
428 QLOGIC_IB_I_SPIOBUFAVAIL | QLOGIC_IB_I_GPIO)
429
430/* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
431#define QLOGIC_IB_HWE_PCIEMEMPARITYERR_MASK 0x000000000000003fULL
432#define QLOGIC_IB_HWE_PCIEMEMPARITYERR_SHIFT 0
433#define QLOGIC_IB_HWE_PCIEPOISONEDTLP 0x0000000010000000ULL
434#define QLOGIC_IB_HWE_PCIECPLTIMEOUT 0x0000000020000000ULL
435#define QLOGIC_IB_HWE_PCIEBUSPARITYXTLH 0x0000000040000000ULL
436#define QLOGIC_IB_HWE_PCIEBUSPARITYXADM 0x0000000080000000ULL
437#define QLOGIC_IB_HWE_PCIEBUSPARITYRADM 0x0000000100000000ULL
438#define QLOGIC_IB_HWE_COREPLL_FBSLIP 0x0080000000000000ULL
439#define QLOGIC_IB_HWE_COREPLL_RFSLIP 0x0100000000000000ULL
440#define QLOGIC_IB_HWE_PCIE1PLLFAILED 0x0400000000000000ULL
441#define QLOGIC_IB_HWE_PCIE0PLLFAILED 0x0800000000000000ULL
442#define QLOGIC_IB_HWE_SERDESPLLFAILED 0x1000000000000000ULL
443
444
445/* kr_extstatus bits */
446#define QLOGIC_IB_EXTS_FREQSEL 0x2
447#define QLOGIC_IB_EXTS_SERDESSEL 0x4
448#define QLOGIC_IB_EXTS_MEMBIST_ENDTEST 0x0000000000004000
449#define QLOGIC_IB_EXTS_MEMBIST_FOUND 0x0000000000008000
450
451/* kr_xgxsconfig bits */
452#define QLOGIC_IB_XGXS_RESET 0x5ULL
453
454#define _QIB_GPIO_SDA_NUM 1
455#define _QIB_GPIO_SCL_NUM 0
456
457/* Bits in GPIO for the added IB link interrupts */
458#define GPIO_RXUVL_BIT 3
459#define GPIO_OVRUN_BIT 4
460#define GPIO_LLI_BIT 5
461#define GPIO_ERRINTR_MASK 0x38
462
463
464#define QLOGIC_IB_RT_BUFSIZE_MASK 0xe0000000ULL
465#define QLOGIC_IB_RT_BUFSIZE_SHIFTVAL(tid) \
466 ((((tid) & QLOGIC_IB_RT_BUFSIZE_MASK) >> 29) + 11 - 1)
467#define QLOGIC_IB_RT_BUFSIZE(tid) (1 << QLOGIC_IB_RT_BUFSIZE_SHIFTVAL(tid))
468#define QLOGIC_IB_RT_IS_VALID(tid) \
469 (((tid) & QLOGIC_IB_RT_BUFSIZE_MASK) && \
470 ((((tid) & QLOGIC_IB_RT_BUFSIZE_MASK) != QLOGIC_IB_RT_BUFSIZE_MASK)))
471#define QLOGIC_IB_RT_ADDR_MASK 0x1FFFFFFFULL /* 29 bits valid */
472#define QLOGIC_IB_RT_ADDR_SHIFT 10
473
474#define QLOGIC_IB_R_INTRAVAIL_SHIFT 16
475#define QLOGIC_IB_R_TAILUPD_SHIFT 31
476#define IBA6120_R_PKEY_DIS_SHIFT 30
477
478#define PBC_6120_VL15_SEND_CTRL (1ULL << 31) /* pbc; VL15; link_buf only */
479
480#define IBCBUSFRSPCPARITYERR HWE_MASK(IBCBusFromSPCParityErr)
481#define IBCBUSTOSPCPARITYERR HWE_MASK(IBCBusToSPCParityErr)
482
483#define SYM_MASK_BIT(regname, fldname, bit) ((u64) \
484 ((1ULL << (SYM_LSB(regname, fldname) + (bit)))))
485
486#define TXEMEMPARITYERR_PIOBUF \
487 SYM_MASK_BIT(HwErrMask, TXEMemParityErrMask, 0)
488#define TXEMEMPARITYERR_PIOPBC \
489 SYM_MASK_BIT(HwErrMask, TXEMemParityErrMask, 1)
490#define TXEMEMPARITYERR_PIOLAUNCHFIFO \
491 SYM_MASK_BIT(HwErrMask, TXEMemParityErrMask, 2)
492
493#define RXEMEMPARITYERR_RCVBUF \
494 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 0)
495#define RXEMEMPARITYERR_LOOKUPQ \
496 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 1)
497#define RXEMEMPARITYERR_EXPTID \
498 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 2)
499#define RXEMEMPARITYERR_EAGERTID \
500 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 3)
501#define RXEMEMPARITYERR_FLAGBUF \
502 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 4)
503#define RXEMEMPARITYERR_DATAINFO \
504 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 5)
505#define RXEMEMPARITYERR_HDRINFO \
506 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 6)
507
508/* 6120 specific hardware errors... */
509static const struct qib_hwerror_msgs qib_6120_hwerror_msgs[] = {
510 /* generic hardware errors */
511 QLOGIC_IB_HWE_MSG(IBCBUSFRSPCPARITYERR, "QIB2IB Parity"),
512 QLOGIC_IB_HWE_MSG(IBCBUSTOSPCPARITYERR, "IB2QIB Parity"),
513
514 QLOGIC_IB_HWE_MSG(TXEMEMPARITYERR_PIOBUF,
515 "TXE PIOBUF Memory Parity"),
516 QLOGIC_IB_HWE_MSG(TXEMEMPARITYERR_PIOPBC,
517 "TXE PIOPBC Memory Parity"),
518 QLOGIC_IB_HWE_MSG(TXEMEMPARITYERR_PIOLAUNCHFIFO,
519 "TXE PIOLAUNCHFIFO Memory Parity"),
520
521 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_RCVBUF,
522 "RXE RCVBUF Memory Parity"),
523 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_LOOKUPQ,
524 "RXE LOOKUPQ Memory Parity"),
525 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_EAGERTID,
526 "RXE EAGERTID Memory Parity"),
527 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_EXPTID,
528 "RXE EXPTID Memory Parity"),
529 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_FLAGBUF,
530 "RXE FLAGBUF Memory Parity"),
531 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_DATAINFO,
532 "RXE DATAINFO Memory Parity"),
533 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_HDRINFO,
534 "RXE HDRINFO Memory Parity"),
535
536 /* chip-specific hardware errors */
537 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIEPOISONEDTLP,
538 "PCIe Poisoned TLP"),
539 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIECPLTIMEOUT,
540 "PCIe completion timeout"),
541 /*
542 * In practice, it's unlikely wthat we'll see PCIe PLL, or bus
543 * parity or memory parity error failures, because most likely we
544 * won't be able to talk to the core of the chip. Nonetheless, we
545 * might see them, if they are in parts of the PCIe core that aren't
546 * essential.
547 */
548 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIE1PLLFAILED,
549 "PCIePLL1"),
550 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIE0PLLFAILED,
551 "PCIePLL0"),
552 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIEBUSPARITYXTLH,
553 "PCIe XTLH core parity"),
554 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIEBUSPARITYXADM,
555 "PCIe ADM TX core parity"),
556 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIEBUSPARITYRADM,
557 "PCIe ADM RX core parity"),
558 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_SERDESPLLFAILED,
559 "SerDes PLL"),
560};
561
562#define TXE_PIO_PARITY (TXEMEMPARITYERR_PIOBUF | TXEMEMPARITYERR_PIOPBC)
563#define _QIB_PLL_FAIL (QLOGIC_IB_HWE_COREPLL_FBSLIP | \
564 QLOGIC_IB_HWE_COREPLL_RFSLIP)
565
566 /* variables for sanity checking interrupt and errors */
567#define IB_HWE_BITSEXTANT \
568 (HWE_MASK(RXEMemParityErr) | \
569 HWE_MASK(TXEMemParityErr) | \
570 (QLOGIC_IB_HWE_PCIEMEMPARITYERR_MASK << \
571 QLOGIC_IB_HWE_PCIEMEMPARITYERR_SHIFT) | \
572 QLOGIC_IB_HWE_PCIE1PLLFAILED | \
573 QLOGIC_IB_HWE_PCIE0PLLFAILED | \
574 QLOGIC_IB_HWE_PCIEPOISONEDTLP | \
575 QLOGIC_IB_HWE_PCIECPLTIMEOUT | \
576 QLOGIC_IB_HWE_PCIEBUSPARITYXTLH | \
577 QLOGIC_IB_HWE_PCIEBUSPARITYXADM | \
578 QLOGIC_IB_HWE_PCIEBUSPARITYRADM | \
579 HWE_MASK(PowerOnBISTFailed) | \
580 QLOGIC_IB_HWE_COREPLL_FBSLIP | \
581 QLOGIC_IB_HWE_COREPLL_RFSLIP | \
582 QLOGIC_IB_HWE_SERDESPLLFAILED | \
583 HWE_MASK(IBCBusToSPCParityErr) | \
584 HWE_MASK(IBCBusFromSPCParityErr))
585
586#define IB_E_BITSEXTANT \
587 (ERR_MASK(RcvFormatErr) | ERR_MASK(RcvVCRCErr) | \
588 ERR_MASK(RcvICRCErr) | ERR_MASK(RcvMinPktLenErr) | \
589 ERR_MASK(RcvMaxPktLenErr) | ERR_MASK(RcvLongPktLenErr) | \
590 ERR_MASK(RcvShortPktLenErr) | ERR_MASK(RcvUnexpectedCharErr) | \
591 ERR_MASK(RcvUnsupportedVLErr) | ERR_MASK(RcvEBPErr) | \
592 ERR_MASK(RcvIBFlowErr) | ERR_MASK(RcvBadVersionErr) | \
593 ERR_MASK(RcvEgrFullErr) | ERR_MASK(RcvHdrFullErr) | \
594 ERR_MASK(RcvBadTidErr) | ERR_MASK(RcvHdrLenErr) | \
595 ERR_MASK(RcvHdrErr) | ERR_MASK(RcvIBLostLinkErr) | \
596 ERR_MASK(SendMinPktLenErr) | ERR_MASK(SendMaxPktLenErr) | \
597 ERR_MASK(SendUnderRunErr) | ERR_MASK(SendPktLenErr) | \
598 ERR_MASK(SendDroppedSmpPktErr) | \
599 ERR_MASK(SendDroppedDataPktErr) | \
600 ERR_MASK(SendPioArmLaunchErr) | \
601 ERR_MASK(SendUnexpectedPktNumErr) | \
602 ERR_MASK(SendUnsupportedVLErr) | ERR_MASK(IBStatusChanged) | \
603 ERR_MASK(InvalidAddrErr) | ERR_MASK(ResetNegated) | \
604 ERR_MASK(HardwareErr))
605
606#define QLOGIC_IB_E_PKTERRS ( \
607 ERR_MASK(SendPktLenErr) | \
608 ERR_MASK(SendDroppedDataPktErr) | \
609 ERR_MASK(RcvVCRCErr) | \
610 ERR_MASK(RcvICRCErr) | \
611 ERR_MASK(RcvShortPktLenErr) | \
612 ERR_MASK(RcvEBPErr))
613
614/* These are all rcv-related errors which we want to count for stats */
615#define E_SUM_PKTERRS \
616 (ERR_MASK(RcvHdrLenErr) | ERR_MASK(RcvBadTidErr) | \
617 ERR_MASK(RcvBadVersionErr) | ERR_MASK(RcvHdrErr) | \
618 ERR_MASK(RcvLongPktLenErr) | ERR_MASK(RcvShortPktLenErr) | \
619 ERR_MASK(RcvMaxPktLenErr) | ERR_MASK(RcvMinPktLenErr) | \
620 ERR_MASK(RcvFormatErr) | ERR_MASK(RcvUnsupportedVLErr) | \
621 ERR_MASK(RcvUnexpectedCharErr) | ERR_MASK(RcvEBPErr))
622
623/* These are all send-related errors which we want to count for stats */
624#define E_SUM_ERRS \
625 (ERR_MASK(SendPioArmLaunchErr) | \
626 ERR_MASK(SendUnexpectedPktNumErr) | \
627 ERR_MASK(SendDroppedDataPktErr) | \
628 ERR_MASK(SendDroppedSmpPktErr) | \
629 ERR_MASK(SendMaxPktLenErr) | ERR_MASK(SendUnsupportedVLErr) | \
630 ERR_MASK(SendMinPktLenErr) | ERR_MASK(SendPktLenErr) | \
631 ERR_MASK(InvalidAddrErr))
632
633/*
634 * this is similar to E_SUM_ERRS, but can't ignore armlaunch, don't ignore
635 * errors not related to freeze and cancelling buffers. Can't ignore
636 * armlaunch because could get more while still cleaning up, and need
637 * to cancel those as they happen.
638 */
639#define E_SPKT_ERRS_IGNORE \
640 (ERR_MASK(SendDroppedDataPktErr) | \
641 ERR_MASK(SendDroppedSmpPktErr) | \
642 ERR_MASK(SendMaxPktLenErr) | ERR_MASK(SendMinPktLenErr) | \
643 ERR_MASK(SendPktLenErr))
644
645/*
646 * these are errors that can occur when the link changes state while
647 * a packet is being sent or received. This doesn't cover things
648 * like EBP or VCRC that can be the result of a sending having the
649 * link change state, so we receive a "known bad" packet.
650 */
651#define E_SUM_LINK_PKTERRS \
652 (ERR_MASK(SendDroppedDataPktErr) | \
653 ERR_MASK(SendDroppedSmpPktErr) | \
654 ERR_MASK(SendMinPktLenErr) | ERR_MASK(SendPktLenErr) | \
655 ERR_MASK(RcvShortPktLenErr) | ERR_MASK(RcvMinPktLenErr) | \
656 ERR_MASK(RcvUnexpectedCharErr))
657
658static void qib_6120_put_tid_2(struct qib_devdata *, u64 __iomem *,
659 u32, unsigned long);
660
661/*
662 * On platforms using this chip, and not having ordered WC stores, we
663 * can get TXE parity errors due to speculative reads to the PIO buffers,
664 * and this, due to a chip issue can result in (many) false parity error
665 * reports. So it's a debug print on those, and an info print on systems
666 * where the speculative reads don't occur.
667 */
668static void qib_6120_txe_recover(struct qib_devdata *dd)
669{
670 if (!qib_unordered_wc())
671 qib_devinfo(dd->pcidev,
672 "Recovering from TXE PIO parity error\n");
673}
674
675/* enable/disable chip from delivering interrupts */
676static void qib_6120_set_intr_state(struct qib_devdata *dd, u32 enable)
677{
678 if (enable) {
679 if (dd->flags & QIB_BADINTR)
680 return;
681 qib_write_kreg(dd, kr_intmask, ~0ULL);
682 /* force re-interrupt of any pending interrupts. */
683 qib_write_kreg(dd, kr_intclear, 0ULL);
684 } else
685 qib_write_kreg(dd, kr_intmask, 0ULL);
686}
687
688/*
689 * Try to cleanup as much as possible for anything that might have gone
690 * wrong while in freeze mode, such as pio buffers being written by user
691 * processes (causing armlaunch), send errors due to going into freeze mode,
692 * etc., and try to avoid causing extra interrupts while doing so.
693 * Forcibly update the in-memory pioavail register copies after cleanup
694 * because the chip won't do it while in freeze mode (the register values
695 * themselves are kept correct).
696 * Make sure that we don't lose any important interrupts by using the chip
697 * feature that says that writing 0 to a bit in *clear that is set in
698 * *status will cause an interrupt to be generated again (if allowed by
699 * the *mask value).
700 * This is in chip-specific code because of all of the register accesses,
701 * even though the details are similar on most chips
702 */
703static void qib_6120_clear_freeze(struct qib_devdata *dd)
704{
705 /* disable error interrupts, to avoid confusion */
706 qib_write_kreg(dd, kr_errmask, 0ULL);
707
708 /* also disable interrupts; errormask is sometimes overwriten */
709 qib_6120_set_intr_state(dd, 0);
710
711 qib_cancel_sends(dd->pport);
712
713 /* clear the freeze, and be sure chip saw it */
714 qib_write_kreg(dd, kr_control, dd->control);
715 qib_read_kreg32(dd, kr_scratch);
716
717 /* force in-memory update now we are out of freeze */
718 qib_force_pio_avail_update(dd);
719
720 /*
721 * force new interrupt if any hwerr, error or interrupt bits are
722 * still set, and clear "safe" send packet errors related to freeze
723 * and cancelling sends. Re-enable error interrupts before possible
724 * force of re-interrupt on pending interrupts.
725 */
726 qib_write_kreg(dd, kr_hwerrclear, 0ULL);
727 qib_write_kreg(dd, kr_errclear, E_SPKT_ERRS_IGNORE);
728 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
729 qib_6120_set_intr_state(dd, 1);
730}
731
732/**
733 * qib_handle_6120_hwerrors - display hardware errors.
734 * @dd: the qlogic_ib device
735 * @msg: the output buffer
736 * @msgl: the size of the output buffer
737 *
738 * Use same msg buffer as regular errors to avoid excessive stack
739 * use. Most hardware errors are catastrophic, but for right now,
740 * we'll print them and continue. Reuse the same message buffer as
741 * handle_6120_errors() to avoid excessive stack usage.
742 */
743static void qib_handle_6120_hwerrors(struct qib_devdata *dd, char *msg,
744 size_t msgl)
745{
746 u64 hwerrs;
747 u32 bits, ctrl;
748 int isfatal = 0;
749 char *bitsmsg;
750 int log_idx;
751
752 hwerrs = qib_read_kreg64(dd, kr_hwerrstatus);
753 if (!hwerrs)
754 return;
755 if (hwerrs == ~0ULL) {
756 qib_dev_err(dd, "Read of hardware error status failed "
757 "(all bits set); ignoring\n");
758 return;
759 }
760 qib_stats.sps_hwerrs++;
761
762 /* Always clear the error status register, except MEMBISTFAIL,
763 * regardless of whether we continue or stop using the chip.
764 * We want that set so we know it failed, even across driver reload.
765 * We'll still ignore it in the hwerrmask. We do this partly for
766 * diagnostics, but also for support */
767 qib_write_kreg(dd, kr_hwerrclear,
768 hwerrs & ~HWE_MASK(PowerOnBISTFailed));
769
770 hwerrs &= dd->cspec->hwerrmask;
771
772 /* We log some errors to EEPROM, check if we have any of those. */
773 for (log_idx = 0; log_idx < QIB_EEP_LOG_CNT; ++log_idx)
774 if (hwerrs & dd->eep_st_masks[log_idx].hwerrs_to_log)
775 qib_inc_eeprom_err(dd, log_idx, 1);
776
777 /*
778 * Make sure we get this much out, unless told to be quiet,
779 * or it's occurred within the last 5 seconds.
780 */
781 if (hwerrs & ~(TXE_PIO_PARITY | RXEMEMPARITYERR_EAGERTID))
782 qib_devinfo(dd->pcidev, "Hardware error: hwerr=0x%llx "
783 "(cleared)\n", (unsigned long long) hwerrs);
784
785 if (hwerrs & ~IB_HWE_BITSEXTANT)
786 qib_dev_err(dd, "hwerror interrupt with unknown errors "
787 "%llx set\n", (unsigned long long)
788 (hwerrs & ~IB_HWE_BITSEXTANT));
789
790 ctrl = qib_read_kreg32(dd, kr_control);
791 if ((ctrl & QLOGIC_IB_C_FREEZEMODE) && !dd->diag_client) {
792 /*
793 * Parity errors in send memory are recoverable,
794 * just cancel the send (if indicated in * sendbuffererror),
795 * count the occurrence, unfreeze (if no other handled
796 * hardware error bits are set), and continue. They can
797 * occur if a processor speculative read is done to the PIO
798 * buffer while we are sending a packet, for example.
799 */
800 if (hwerrs & TXE_PIO_PARITY) {
801 qib_6120_txe_recover(dd);
802 hwerrs &= ~TXE_PIO_PARITY;
803 }
804
805 if (!hwerrs) {
806 static u32 freeze_cnt;
807
808 freeze_cnt++;
809 qib_6120_clear_freeze(dd);
810 } else
811 isfatal = 1;
812 }
813
814 *msg = '\0';
815
816 if (hwerrs & HWE_MASK(PowerOnBISTFailed)) {
817 isfatal = 1;
818 strlcat(msg, "[Memory BIST test failed, InfiniPath hardware"
819 " unusable]", msgl);
820 /* ignore from now on, so disable until driver reloaded */
821 dd->cspec->hwerrmask &= ~HWE_MASK(PowerOnBISTFailed);
822 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
823 }
824
825 qib_format_hwerrors(hwerrs, qib_6120_hwerror_msgs,
826 ARRAY_SIZE(qib_6120_hwerror_msgs), msg, msgl);
827
828 bitsmsg = dd->cspec->bitsmsgbuf;
829 if (hwerrs & (QLOGIC_IB_HWE_PCIEMEMPARITYERR_MASK <<
830 QLOGIC_IB_HWE_PCIEMEMPARITYERR_SHIFT)) {
831 bits = (u32) ((hwerrs >>
832 QLOGIC_IB_HWE_PCIEMEMPARITYERR_SHIFT) &
833 QLOGIC_IB_HWE_PCIEMEMPARITYERR_MASK);
834 snprintf(bitsmsg, sizeof dd->cspec->bitsmsgbuf,
835 "[PCIe Mem Parity Errs %x] ", bits);
836 strlcat(msg, bitsmsg, msgl);
837 }
838
839 if (hwerrs & _QIB_PLL_FAIL) {
840 isfatal = 1;
841 snprintf(bitsmsg, sizeof dd->cspec->bitsmsgbuf,
842 "[PLL failed (%llx), InfiniPath hardware unusable]",
843 (unsigned long long) hwerrs & _QIB_PLL_FAIL);
844 strlcat(msg, bitsmsg, msgl);
845 /* ignore from now on, so disable until driver reloaded */
846 dd->cspec->hwerrmask &= ~(hwerrs & _QIB_PLL_FAIL);
847 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
848 }
849
850 if (hwerrs & QLOGIC_IB_HWE_SERDESPLLFAILED) {
851 /*
852 * If it occurs, it is left masked since the external
853 * interface is unused
854 */
855 dd->cspec->hwerrmask &= ~QLOGIC_IB_HWE_SERDESPLLFAILED;
856 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
857 }
858
859 if (hwerrs)
860 /*
861 * if any set that we aren't ignoring; only
862 * make the complaint once, in case it's stuck
863 * or recurring, and we get here multiple
864 * times.
865 */
866 qib_dev_err(dd, "%s hardware error\n", msg);
867 else
868 *msg = 0; /* recovered from all of them */
869
870 if (isfatal && !dd->diag_client) {
871 qib_dev_err(dd, "Fatal Hardware Error, no longer"
872 " usable, SN %.16s\n", dd->serial);
873 /*
874 * for /sys status file and user programs to print; if no
875 * trailing brace is copied, we'll know it was truncated.
876 */
877 if (dd->freezemsg)
878 snprintf(dd->freezemsg, dd->freezelen,
879 "{%s}", msg);
880 qib_disable_after_error(dd);
881 }
882}
883
884/*
885 * Decode the error status into strings, deciding whether to always
886 * print * it or not depending on "normal packet errors" vs everything
887 * else. Return 1 if "real" errors, otherwise 0 if only packet
888 * errors, so caller can decide what to print with the string.
889 */
890static int qib_decode_6120_err(struct qib_devdata *dd, char *buf, size_t blen,
891 u64 err)
892{
893 int iserr = 1;
894
895 *buf = '\0';
896 if (err & QLOGIC_IB_E_PKTERRS) {
897 if (!(err & ~QLOGIC_IB_E_PKTERRS))
898 iserr = 0;
899 if ((err & ERR_MASK(RcvICRCErr)) &&
900 !(err&(ERR_MASK(RcvVCRCErr)|ERR_MASK(RcvEBPErr))))
901 strlcat(buf, "CRC ", blen);
902 if (!iserr)
903 goto done;
904 }
905 if (err & ERR_MASK(RcvHdrLenErr))
906 strlcat(buf, "rhdrlen ", blen);
907 if (err & ERR_MASK(RcvBadTidErr))
908 strlcat(buf, "rbadtid ", blen);
909 if (err & ERR_MASK(RcvBadVersionErr))
910 strlcat(buf, "rbadversion ", blen);
911 if (err & ERR_MASK(RcvHdrErr))
912 strlcat(buf, "rhdr ", blen);
913 if (err & ERR_MASK(RcvLongPktLenErr))
914 strlcat(buf, "rlongpktlen ", blen);
915 if (err & ERR_MASK(RcvMaxPktLenErr))
916 strlcat(buf, "rmaxpktlen ", blen);
917 if (err & ERR_MASK(RcvMinPktLenErr))
918 strlcat(buf, "rminpktlen ", blen);
919 if (err & ERR_MASK(SendMinPktLenErr))
920 strlcat(buf, "sminpktlen ", blen);
921 if (err & ERR_MASK(RcvFormatErr))
922 strlcat(buf, "rformaterr ", blen);
923 if (err & ERR_MASK(RcvUnsupportedVLErr))
924 strlcat(buf, "runsupvl ", blen);
925 if (err & ERR_MASK(RcvUnexpectedCharErr))
926 strlcat(buf, "runexpchar ", blen);
927 if (err & ERR_MASK(RcvIBFlowErr))
928 strlcat(buf, "ribflow ", blen);
929 if (err & ERR_MASK(SendUnderRunErr))
930 strlcat(buf, "sunderrun ", blen);
931 if (err & ERR_MASK(SendPioArmLaunchErr))
932 strlcat(buf, "spioarmlaunch ", blen);
933 if (err & ERR_MASK(SendUnexpectedPktNumErr))
934 strlcat(buf, "sunexperrpktnum ", blen);
935 if (err & ERR_MASK(SendDroppedSmpPktErr))
936 strlcat(buf, "sdroppedsmppkt ", blen);
937 if (err & ERR_MASK(SendMaxPktLenErr))
938 strlcat(buf, "smaxpktlen ", blen);
939 if (err & ERR_MASK(SendUnsupportedVLErr))
940 strlcat(buf, "sunsupVL ", blen);
941 if (err & ERR_MASK(InvalidAddrErr))
942 strlcat(buf, "invalidaddr ", blen);
943 if (err & ERR_MASK(RcvEgrFullErr))
944 strlcat(buf, "rcvegrfull ", blen);
945 if (err & ERR_MASK(RcvHdrFullErr))
946 strlcat(buf, "rcvhdrfull ", blen);
947 if (err & ERR_MASK(IBStatusChanged))
948 strlcat(buf, "ibcstatuschg ", blen);
949 if (err & ERR_MASK(RcvIBLostLinkErr))
950 strlcat(buf, "riblostlink ", blen);
951 if (err & ERR_MASK(HardwareErr))
952 strlcat(buf, "hardware ", blen);
953 if (err & ERR_MASK(ResetNegated))
954 strlcat(buf, "reset ", blen);
955done:
956 return iserr;
957}
958
959/*
960 * Called when we might have an error that is specific to a particular
961 * PIO buffer, and may need to cancel that buffer, so it can be re-used.
962 */
963static void qib_disarm_6120_senderrbufs(struct qib_pportdata *ppd)
964{
965 unsigned long sbuf[2];
966 struct qib_devdata *dd = ppd->dd;
967
968 /*
969 * It's possible that sendbuffererror could have bits set; might
970 * have already done this as a result of hardware error handling.
971 */
972 sbuf[0] = qib_read_kreg64(dd, kr_sendbuffererror);
973 sbuf[1] = qib_read_kreg64(dd, kr_sendbuffererror + 1);
974
975 if (sbuf[0] || sbuf[1])
976 qib_disarm_piobufs_set(dd, sbuf,
977 dd->piobcnt2k + dd->piobcnt4k);
978}
979
980static int chk_6120_linkrecovery(struct qib_devdata *dd, u64 ibcs)
981{
982 int ret = 1;
983 u32 ibstate = qib_6120_iblink_state(ibcs);
984 u32 linkrecov = read_6120_creg32(dd, cr_iblinkerrrecov);
985
986 if (linkrecov != dd->cspec->lastlinkrecov) {
987 /* and no more until active again */
988 dd->cspec->lastlinkrecov = 0;
989 qib_set_linkstate(dd->pport, QIB_IB_LINKDOWN);
990 ret = 0;
991 }
992 if (ibstate == IB_PORT_ACTIVE)
993 dd->cspec->lastlinkrecov =
994 read_6120_creg32(dd, cr_iblinkerrrecov);
995 return ret;
996}
997
998static void handle_6120_errors(struct qib_devdata *dd, u64 errs)
999{
1000 char *msg;
1001 u64 ignore_this_time = 0;
1002 u64 iserr = 0;
1003 int log_idx;
1004 struct qib_pportdata *ppd = dd->pport;
1005 u64 mask;
1006
1007 /* don't report errors that are masked */
1008 errs &= dd->cspec->errormask;
1009 msg = dd->cspec->emsgbuf;
1010
1011 /* do these first, they are most important */
1012 if (errs & ERR_MASK(HardwareErr))
1013 qib_handle_6120_hwerrors(dd, msg, sizeof dd->cspec->emsgbuf);
1014 else
1015 for (log_idx = 0; log_idx < QIB_EEP_LOG_CNT; ++log_idx)
1016 if (errs & dd->eep_st_masks[log_idx].errs_to_log)
1017 qib_inc_eeprom_err(dd, log_idx, 1);
1018
1019 if (errs & ~IB_E_BITSEXTANT)
1020 qib_dev_err(dd, "error interrupt with unknown errors "
1021 "%llx set\n",
1022 (unsigned long long) (errs & ~IB_E_BITSEXTANT));
1023
1024 if (errs & E_SUM_ERRS) {
1025 qib_disarm_6120_senderrbufs(ppd);
1026 if ((errs & E_SUM_LINK_PKTERRS) &&
1027 !(ppd->lflags & QIBL_LINKACTIVE)) {
1028 /*
1029 * This can happen when trying to bring the link
1030 * up, but the IB link changes state at the "wrong"
1031 * time. The IB logic then complains that the packet
1032 * isn't valid. We don't want to confuse people, so
1033 * we just don't print them, except at debug
1034 */
1035 ignore_this_time = errs & E_SUM_LINK_PKTERRS;
1036 }
1037 } else if ((errs & E_SUM_LINK_PKTERRS) &&
1038 !(ppd->lflags & QIBL_LINKACTIVE)) {
1039 /*
1040 * This can happen when SMA is trying to bring the link
1041 * up, but the IB link changes state at the "wrong" time.
1042 * The IB logic then complains that the packet isn't
1043 * valid. We don't want to confuse people, so we just
1044 * don't print them, except at debug
1045 */
1046 ignore_this_time = errs & E_SUM_LINK_PKTERRS;
1047 }
1048
1049 qib_write_kreg(dd, kr_errclear, errs);
1050
1051 errs &= ~ignore_this_time;
1052 if (!errs)
1053 goto done;
1054
1055 /*
1056 * The ones we mask off are handled specially below
1057 * or above.
1058 */
1059 mask = ERR_MASK(IBStatusChanged) | ERR_MASK(RcvEgrFullErr) |
1060 ERR_MASK(RcvHdrFullErr) | ERR_MASK(HardwareErr);
1061 qib_decode_6120_err(dd, msg, sizeof dd->cspec->emsgbuf, errs & ~mask);
1062
1063 if (errs & E_SUM_PKTERRS)
1064 qib_stats.sps_rcverrs++;
1065 if (errs & E_SUM_ERRS)
1066 qib_stats.sps_txerrs++;
1067
1068 iserr = errs & ~(E_SUM_PKTERRS | QLOGIC_IB_E_PKTERRS);
1069
1070 if (errs & ERR_MASK(IBStatusChanged)) {
1071 u64 ibcs = qib_read_kreg64(dd, kr_ibcstatus);
1072 u32 ibstate = qib_6120_iblink_state(ibcs);
1073 int handle = 1;
1074
1075 if (ibstate != IB_PORT_INIT && dd->cspec->lastlinkrecov)
1076 handle = chk_6120_linkrecovery(dd, ibcs);
1077 /*
1078 * Since going into a recovery state causes the link state
1079 * to go down and since recovery is transitory, it is better
1080 * if we "miss" ever seeing the link training state go into
1081 * recovery (i.e., ignore this transition for link state
1082 * special handling purposes) without updating lastibcstat.
1083 */
1084 if (handle && qib_6120_phys_portstate(ibcs) ==
1085 IB_PHYSPORTSTATE_LINK_ERR_RECOVER)
1086 handle = 0;
1087 if (handle)
1088 qib_handle_e_ibstatuschanged(ppd, ibcs);
1089 }
1090
1091 if (errs & ERR_MASK(ResetNegated)) {
1092 qib_dev_err(dd, "Got reset, requires re-init "
1093 "(unload and reload driver)\n");
1094 dd->flags &= ~QIB_INITTED; /* needs re-init */
1095 /* mark as having had error */
1096 *dd->devstatusp |= QIB_STATUS_HWERROR;
1097 *dd->pport->statusp &= ~QIB_STATUS_IB_CONF;
1098 }
1099
1100 if (*msg && iserr)
1101 qib_dev_porterr(dd, ppd->port, "%s error\n", msg);
1102
1103 if (ppd->state_wanted & ppd->lflags)
1104 wake_up_interruptible(&ppd->state_wait);
1105
1106 /*
1107 * If there were hdrq or egrfull errors, wake up any processes
1108 * waiting in poll. We used to try to check which contexts had
1109 * the overflow, but given the cost of that and the chip reads
1110 * to support it, it's better to just wake everybody up if we
1111 * get an overflow; waiters can poll again if it's not them.
1112 */
1113 if (errs & (ERR_MASK(RcvEgrFullErr) | ERR_MASK(RcvHdrFullErr))) {
1114 qib_handle_urcv(dd, ~0U);
1115 if (errs & ERR_MASK(RcvEgrFullErr))
1116 qib_stats.sps_buffull++;
1117 else
1118 qib_stats.sps_hdrfull++;
1119 }
1120done:
1121 return;
1122}
1123
1124/**
1125 * qib_6120_init_hwerrors - enable hardware errors
1126 * @dd: the qlogic_ib device
1127 *
1128 * now that we have finished initializing everything that might reasonably
1129 * cause a hardware error, and cleared those errors bits as they occur,
1130 * we can enable hardware errors in the mask (potentially enabling
1131 * freeze mode), and enable hardware errors as errors (along with
1132 * everything else) in errormask
1133 */
1134static void qib_6120_init_hwerrors(struct qib_devdata *dd)
1135{
1136 u64 val;
1137 u64 extsval;
1138
1139 extsval = qib_read_kreg64(dd, kr_extstatus);
1140
1141 if (!(extsval & QLOGIC_IB_EXTS_MEMBIST_ENDTEST))
1142 qib_dev_err(dd, "MemBIST did not complete!\n");
1143
1144 /* init so all hwerrors interrupt, and enter freeze, ajdust below */
1145 val = ~0ULL;
1146 if (dd->minrev < 2) {
1147 /*
1148 * Avoid problem with internal interface bus parity
1149 * checking. Fixed in Rev2.
1150 */
1151 val &= ~QLOGIC_IB_HWE_PCIEBUSPARITYRADM;
1152 }
1153 /* avoid some intel cpu's speculative read freeze mode issue */
1154 val &= ~TXEMEMPARITYERR_PIOBUF;
1155
1156 dd->cspec->hwerrmask = val;
1157
1158 qib_write_kreg(dd, kr_hwerrclear, ~HWE_MASK(PowerOnBISTFailed));
1159 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
1160
1161 /* clear all */
1162 qib_write_kreg(dd, kr_errclear, ~0ULL);
1163 /* enable errors that are masked, at least this first time. */
1164 qib_write_kreg(dd, kr_errmask, ~0ULL);
1165 dd->cspec->errormask = qib_read_kreg64(dd, kr_errmask);
1166 /* clear any interrupts up to this point (ints still not enabled) */
1167 qib_write_kreg(dd, kr_intclear, ~0ULL);
1168
1169 qib_write_kreg(dd, kr_rcvbthqp,
1170 dd->qpn_mask << (QIB_6120_RcvBTHQP_BTHQP_Mask_LSB - 1) |
1171 QIB_KD_QP);
1172}
1173
1174/*
1175 * Disable and enable the armlaunch error. Used for PIO bandwidth testing
1176 * on chips that are count-based, rather than trigger-based. There is no
1177 * reference counting, but that's also fine, given the intended use.
1178 * Only chip-specific because it's all register accesses
1179 */
1180static void qib_set_6120_armlaunch(struct qib_devdata *dd, u32 enable)
1181{
1182 if (enable) {
1183 qib_write_kreg(dd, kr_errclear,
1184 ERR_MASK(SendPioArmLaunchErr));
1185 dd->cspec->errormask |= ERR_MASK(SendPioArmLaunchErr);
1186 } else
1187 dd->cspec->errormask &= ~ERR_MASK(SendPioArmLaunchErr);
1188 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
1189}
1190
1191/*
1192 * Formerly took parameter <which> in pre-shifted,
1193 * pre-merged form with LinkCmd and LinkInitCmd
1194 * together, and assuming the zero was NOP.
1195 */
1196static void qib_set_ib_6120_lstate(struct qib_pportdata *ppd, u16 linkcmd,
1197 u16 linitcmd)
1198{
1199 u64 mod_wd;
1200 struct qib_devdata *dd = ppd->dd;
1201 unsigned long flags;
1202
1203 if (linitcmd == QLOGIC_IB_IBCC_LINKINITCMD_DISABLE) {
1204 /*
1205 * If we are told to disable, note that so link-recovery
1206 * code does not attempt to bring us back up.
1207 */
1208 spin_lock_irqsave(&ppd->lflags_lock, flags);
1209 ppd->lflags |= QIBL_IB_LINK_DISABLED;
1210 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
1211 } else if (linitcmd || linkcmd == QLOGIC_IB_IBCC_LINKCMD_DOWN) {
1212 /*
1213 * Any other linkinitcmd will lead to LINKDOWN and then
1214 * to INIT (if all is well), so clear flag to let
1215 * link-recovery code attempt to bring us back up.
1216 */
1217 spin_lock_irqsave(&ppd->lflags_lock, flags);
1218 ppd->lflags &= ~QIBL_IB_LINK_DISABLED;
1219 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
1220 }
1221
1222 mod_wd = (linkcmd << QLOGIC_IB_IBCC_LINKCMD_SHIFT) |
1223 (linitcmd << QLOGIC_IB_IBCC_LINKINITCMD_SHIFT);
1224
1225 qib_write_kreg(dd, kr_ibcctrl, dd->cspec->ibcctrl | mod_wd);
1226 /* write to chip to prevent back-to-back writes of control reg */
1227 qib_write_kreg(dd, kr_scratch, 0);
1228}
1229
1230/**
1231 * qib_6120_bringup_serdes - bring up the serdes
1232 * @dd: the qlogic_ib device
1233 */
1234static int qib_6120_bringup_serdes(struct qib_pportdata *ppd)
1235{
1236 struct qib_devdata *dd = ppd->dd;
1237 u64 val, config1, prev_val, hwstat, ibc;
1238
1239 /* Put IBC in reset, sends disabled */
1240 dd->control &= ~QLOGIC_IB_C_LINKENABLE;
1241 qib_write_kreg(dd, kr_control, 0ULL);
1242
1243 dd->cspec->ibdeltainprog = 1;
1244 dd->cspec->ibsymsnap = read_6120_creg32(dd, cr_ibsymbolerr);
1245 dd->cspec->iblnkerrsnap = read_6120_creg32(dd, cr_iblinkerrrecov);
1246
1247 /* flowcontrolwatermark is in units of KBytes */
1248 ibc = 0x5ULL << SYM_LSB(IBCCtrl, FlowCtrlWaterMark);
1249 /*
1250 * How often flowctrl sent. More or less in usecs; balance against
1251 * watermark value, so that in theory senders always get a flow
1252 * control update in time to not let the IB link go idle.
1253 */
1254 ibc |= 0x3ULL << SYM_LSB(IBCCtrl, FlowCtrlPeriod);
1255 /* max error tolerance */
1256 dd->cspec->lli_thresh = 0xf;
1257 ibc |= (u64) dd->cspec->lli_thresh << SYM_LSB(IBCCtrl, PhyerrThreshold);
1258 /* use "real" buffer space for */
1259 ibc |= 4ULL << SYM_LSB(IBCCtrl, CreditScale);
1260 /* IB credit flow control. */
1261 ibc |= 0xfULL << SYM_LSB(IBCCtrl, OverrunThreshold);
1262 /*
1263 * set initial max size pkt IBC will send, including ICRC; it's the
1264 * PIO buffer size in dwords, less 1; also see qib_set_mtu()
1265 */
1266 ibc |= ((u64)(ppd->ibmaxlen >> 2) + 1) << SYM_LSB(IBCCtrl, MaxPktLen);
1267 dd->cspec->ibcctrl = ibc; /* without linkcmd or linkinitcmd! */
1268
1269 /* initially come up waiting for TS1, without sending anything. */
1270 val = dd->cspec->ibcctrl | (QLOGIC_IB_IBCC_LINKINITCMD_DISABLE <<
1271 QLOGIC_IB_IBCC_LINKINITCMD_SHIFT);
1272 qib_write_kreg(dd, kr_ibcctrl, val);
1273
1274 val = qib_read_kreg64(dd, kr_serdes_cfg0);
1275 config1 = qib_read_kreg64(dd, kr_serdes_cfg1);
1276
1277 /*
1278 * Force reset on, also set rxdetect enable. Must do before reading
1279 * serdesstatus at least for simulation, or some of the bits in
1280 * serdes status will come back as undefined and cause simulation
1281 * failures
1282 */
1283 val |= SYM_MASK(SerdesCfg0, ResetPLL) |
1284 SYM_MASK(SerdesCfg0, RxDetEnX) |
1285 (SYM_MASK(SerdesCfg0, L1PwrDnA) |
1286 SYM_MASK(SerdesCfg0, L1PwrDnB) |
1287 SYM_MASK(SerdesCfg0, L1PwrDnC) |
1288 SYM_MASK(SerdesCfg0, L1PwrDnD));
1289 qib_write_kreg(dd, kr_serdes_cfg0, val);
1290 /* be sure chip saw it */
1291 qib_read_kreg64(dd, kr_scratch);
1292 udelay(5); /* need pll reset set at least for a bit */
1293 /*
1294 * after PLL is reset, set the per-lane Resets and TxIdle and
1295 * clear the PLL reset and rxdetect (to get falling edge).
1296 * Leave L1PWR bits set (permanently)
1297 */
1298 val &= ~(SYM_MASK(SerdesCfg0, RxDetEnX) |
1299 SYM_MASK(SerdesCfg0, ResetPLL) |
1300 (SYM_MASK(SerdesCfg0, L1PwrDnA) |
1301 SYM_MASK(SerdesCfg0, L1PwrDnB) |
1302 SYM_MASK(SerdesCfg0, L1PwrDnC) |
1303 SYM_MASK(SerdesCfg0, L1PwrDnD)));
1304 val |= (SYM_MASK(SerdesCfg0, ResetA) |
1305 SYM_MASK(SerdesCfg0, ResetB) |
1306 SYM_MASK(SerdesCfg0, ResetC) |
1307 SYM_MASK(SerdesCfg0, ResetD)) |
1308 SYM_MASK(SerdesCfg0, TxIdeEnX);
1309 qib_write_kreg(dd, kr_serdes_cfg0, val);
1310 /* be sure chip saw it */
1311 (void) qib_read_kreg64(dd, kr_scratch);
1312 /* need PLL reset clear for at least 11 usec before lane
1313 * resets cleared; give it a few more to be sure */
1314 udelay(15);
1315 val &= ~((SYM_MASK(SerdesCfg0, ResetA) |
1316 SYM_MASK(SerdesCfg0, ResetB) |
1317 SYM_MASK(SerdesCfg0, ResetC) |
1318 SYM_MASK(SerdesCfg0, ResetD)) |
1319 SYM_MASK(SerdesCfg0, TxIdeEnX));
1320
1321 qib_write_kreg(dd, kr_serdes_cfg0, val);
1322 /* be sure chip saw it */
1323 (void) qib_read_kreg64(dd, kr_scratch);
1324
1325 val = qib_read_kreg64(dd, kr_xgxs_cfg);
1326 prev_val = val;
1327 if (val & QLOGIC_IB_XGXS_RESET)
1328 val &= ~QLOGIC_IB_XGXS_RESET;
1329 if (SYM_FIELD(val, XGXSCfg, polarity_inv) != ppd->rx_pol_inv) {
1330 /* need to compensate for Tx inversion in partner */
1331 val &= ~SYM_MASK(XGXSCfg, polarity_inv);
1332 val |= (u64)ppd->rx_pol_inv << SYM_LSB(XGXSCfg, polarity_inv);
1333 }
1334 if (val != prev_val)
1335 qib_write_kreg(dd, kr_xgxs_cfg, val);
1336
1337 val = qib_read_kreg64(dd, kr_serdes_cfg0);
1338
1339 /* clear current and de-emphasis bits */
1340 config1 &= ~0x0ffffffff00ULL;
1341 /* set current to 20ma */
1342 config1 |= 0x00000000000ULL;
1343 /* set de-emphasis to -5.68dB */
1344 config1 |= 0x0cccc000000ULL;
1345 qib_write_kreg(dd, kr_serdes_cfg1, config1);
1346
1347 /* base and port guid same for single port */
1348 ppd->guid = dd->base_guid;
1349
1350 /*
1351 * the process of setting and un-resetting the serdes normally
1352 * causes a serdes PLL error, so check for that and clear it
1353 * here. Also clearr hwerr bit in errstatus, but not others.
1354 */
1355 hwstat = qib_read_kreg64(dd, kr_hwerrstatus);
1356 if (hwstat) {
1357 /* should just have PLL, clear all set, in an case */
2d757a7c 1358 qib_write_kreg(dd, kr_hwerrclear, hwstat);
f931551b
RC		 1359 qib_write_kreg(dd, kr_errclear, ERR_MASK(HardwareErr));
1360 }
1361
1362 dd->control |= QLOGIC_IB_C_LINKENABLE;
1363 dd->control &= ~QLOGIC_IB_C_FREEZEMODE;
1364 qib_write_kreg(dd, kr_control, dd->control);
1365
1366 return 0;
1367}
1368
1369/**
1370 * qib_6120_quiet_serdes - set serdes to txidle
1371 * @ppd: physical port of the qlogic_ib device
1372 * Called when driver is being unloaded
1373 */
1374static void qib_6120_quiet_serdes(struct qib_pportdata *ppd)
1375{
1376 struct qib_devdata *dd = ppd->dd;
1377 u64 val;
1378
1379 qib_set_ib_6120_lstate(ppd, 0, QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
1380
1381 /* disable IBC */
1382 dd->control &= ~QLOGIC_IB_C_LINKENABLE;
1383 qib_write_kreg(dd, kr_control,
1384 dd->control | QLOGIC_IB_C_FREEZEMODE);
1385
1386 if (dd->cspec->ibsymdelta || dd->cspec->iblnkerrdelta ||
1387 dd->cspec->ibdeltainprog) {
1388 u64 diagc;
1389
1390 /* enable counter writes */
1391 diagc = qib_read_kreg64(dd, kr_hwdiagctrl);
1392 qib_write_kreg(dd, kr_hwdiagctrl,
1393 diagc | SYM_MASK(HwDiagCtrl, CounterWrEnable));
1394
1395 if (dd->cspec->ibsymdelta || dd->cspec->ibdeltainprog) {
1396 val = read_6120_creg32(dd, cr_ibsymbolerr);
1397 if (dd->cspec->ibdeltainprog)
1398 val -= val - dd->cspec->ibsymsnap;
1399 val -= dd->cspec->ibsymdelta;
1400 write_6120_creg(dd, cr_ibsymbolerr, val);
1401 }
1402 if (dd->cspec->iblnkerrdelta || dd->cspec->ibdeltainprog) {
1403 val = read_6120_creg32(dd, cr_iblinkerrrecov);
1404 if (dd->cspec->ibdeltainprog)
1405 val -= val - dd->cspec->iblnkerrsnap;
1406 val -= dd->cspec->iblnkerrdelta;
1407 write_6120_creg(dd, cr_iblinkerrrecov, val);
1408 }
1409
1410 /* and disable counter writes */
1411 qib_write_kreg(dd, kr_hwdiagctrl, diagc);
1412 }
1413
1414 val = qib_read_kreg64(dd, kr_serdes_cfg0);
1415 val |= SYM_MASK(SerdesCfg0, TxIdeEnX);
1416 qib_write_kreg(dd, kr_serdes_cfg0, val);
1417}
1418
1419/**
1420 * qib_6120_setup_setextled - set the state of the two external LEDs
1421 * @dd: the qlogic_ib device
1422 * @on: whether the link is up or not
1423 *
1424 * The exact combo of LEDs if on is true is determined by looking
1425 * at the ibcstatus.
1426
1427 * These LEDs indicate the physical and logical state of IB link.
1428 * For this chip (at least with recommended board pinouts), LED1
1429 * is Yellow (logical state) and LED2 is Green (physical state),
1430 *
1431 * Note: We try to match the Mellanox HCA LED behavior as best
1432 * we can. Green indicates physical link state is OK (something is
1433 * plugged in, and we can train).
1434 * Amber indicates the link is logically up (ACTIVE).
1435 * Mellanox further blinks the amber LED to indicate data packet
1436 * activity, but we have no hardware support for that, so it would
1437 * require waking up every 10-20 msecs and checking the counters
1438 * on the chip, and then turning the LED off if appropriate. That's
1439 * visible overhead, so not something we will do.
1440 *
1441 */
1442static void qib_6120_setup_setextled(struct qib_pportdata *ppd, u32 on)
1443{
1444 u64 extctl, val, lst, ltst;
1445 unsigned long flags;
1446 struct qib_devdata *dd = ppd->dd;
1447
1448 /*
1449 * The diags use the LED to indicate diag info, so we leave
1450 * the external LED alone when the diags are running.
1451 */
1452 if (dd->diag_client)
1453 return;
1454
1455 /* Allow override of LED display for, e.g. Locating system in rack */
1456 if (ppd->led_override) {
1457 ltst = (ppd->led_override & QIB_LED_PHYS) ?
1458 IB_PHYSPORTSTATE_LINKUP : IB_PHYSPORTSTATE_DISABLED,
1459 lst = (ppd->led_override & QIB_LED_LOG) ?
1460 IB_PORT_ACTIVE : IB_PORT_DOWN;
1461 } else if (on) {
1462 val = qib_read_kreg64(dd, kr_ibcstatus);
1463 ltst = qib_6120_phys_portstate(val);
1464 lst = qib_6120_iblink_state(val);
1465 } else {
1466 ltst = 0;
1467 lst = 0;
1468 }
1469
1470 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
1471 extctl = dd->cspec->extctrl & ~(SYM_MASK(EXTCtrl, LEDPriPortGreenOn) |
1472 SYM_MASK(EXTCtrl, LEDPriPortYellowOn));
1473
1474 if (ltst == IB_PHYSPORTSTATE_LINKUP)
1475 extctl |= SYM_MASK(EXTCtrl, LEDPriPortYellowOn);
1476 if (lst == IB_PORT_ACTIVE)
1477 extctl |= SYM_MASK(EXTCtrl, LEDPriPortGreenOn);
1478 dd->cspec->extctrl = extctl;
1479 qib_write_kreg(dd, kr_extctrl, extctl);
1480 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
1481}
1482
1483static void qib_6120_free_irq(struct qib_devdata *dd)
1484{
1485 if (dd->cspec->irq) {
1486 free_irq(dd->cspec->irq, dd);
1487 dd->cspec->irq = 0;
1488 }
1489 qib_nomsi(dd);
1490}
1491
1492/**
1493 * qib_6120_setup_cleanup - clean up any per-chip chip-specific stuff
1494 * @dd: the qlogic_ib device
1495 *
1496 * This is called during driver unload.
1497*/
1498static void qib_6120_setup_cleanup(struct qib_devdata *dd)
1499{
1500 qib_6120_free_irq(dd);
1501 kfree(dd->cspec->cntrs);
1502 kfree(dd->cspec->portcntrs);
1503 if (dd->cspec->dummy_hdrq) {
1504 dma_free_coherent(&dd->pcidev->dev,
1505 ALIGN(dd->rcvhdrcnt *
1506 dd->rcvhdrentsize *
1507 sizeof(u32), PAGE_SIZE),
1508 dd->cspec->dummy_hdrq,
1509 dd->cspec->dummy_hdrq_phys);
1510 dd->cspec->dummy_hdrq = NULL;
1511 }
1512}
1513
1514static void qib_wantpiobuf_6120_intr(struct qib_devdata *dd, u32 needint)
1515{
1516 unsigned long flags;
1517
1518 spin_lock_irqsave(&dd->sendctrl_lock, flags);
1519 if (needint)
1520 dd->sendctrl |= SYM_MASK(SendCtrl, PIOIntBufAvail);
1521 else
1522 dd->sendctrl &= ~SYM_MASK(SendCtrl, PIOIntBufAvail);
1523 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
1524 qib_write_kreg(dd, kr_scratch, 0ULL);
1525 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
1526}
1527
1528/*
1529 * handle errors and unusual events first, separate function
1530 * to improve cache hits for fast path interrupt handling
1531 */
1532static noinline void unlikely_6120_intr(struct qib_devdata *dd, u64 istat)
1533{
1534 if (unlikely(istat & ~QLOGIC_IB_I_BITSEXTANT))
1535 qib_dev_err(dd, "interrupt with unknown interrupts %Lx set\n",
1536 istat & ~QLOGIC_IB_I_BITSEXTANT);
1537
1538 if (istat & QLOGIC_IB_I_ERROR) {
1539 u64 estat = 0;
1540
1541 qib_stats.sps_errints++;
1542 estat = qib_read_kreg64(dd, kr_errstatus);
1543 if (!estat)
1544 qib_devinfo(dd->pcidev, "error interrupt (%Lx), "
1545 "but no error bits set!\n", istat);
1546 handle_6120_errors(dd, estat);
1547 }
1548
1549 if (istat & QLOGIC_IB_I_GPIO) {
1550 u32 gpiostatus;
1551 u32 to_clear = 0;
1552
1553 /*
1554 * GPIO_3..5 on IBA6120 Rev2 chips indicate
1555 * errors that we need to count.
1556 */
1557 gpiostatus = qib_read_kreg32(dd, kr_gpio_status);
1558 /* First the error-counter case. */
1559 if (gpiostatus & GPIO_ERRINTR_MASK) {
1560 /* want to clear the bits we see asserted. */
1561 to_clear |= (gpiostatus & GPIO_ERRINTR_MASK);
1562
1563 /*
1564 * Count appropriately, clear bits out of our copy,
1565 * as they have been "handled".
1566 */
1567 if (gpiostatus & (1 << GPIO_RXUVL_BIT))
1568 dd->cspec->rxfc_unsupvl_errs++;
1569 if (gpiostatus & (1 << GPIO_OVRUN_BIT))
1570 dd->cspec->overrun_thresh_errs++;
1571 if (gpiostatus & (1 << GPIO_LLI_BIT))
1572 dd->cspec->lli_errs++;
1573 gpiostatus &= ~GPIO_ERRINTR_MASK;
1574 }
1575 if (gpiostatus) {
1576 /*
1577 * Some unexpected bits remain. If they could have
1578 * caused the interrupt, complain and clear.
1579 * To avoid repetition of this condition, also clear
1580 * the mask. It is almost certainly due to error.
1581 */
1582 const u32 mask = qib_read_kreg32(dd, kr_gpio_mask);
1583
1584 /*
1585 * Also check that the chip reflects our shadow,
1586 * and report issues, If they caused the interrupt.
1587 * we will suppress by refreshing from the shadow.
1588 */
1589 if (mask & gpiostatus) {
1590 to_clear |= (gpiostatus & mask);
1591 dd->cspec->gpio_mask &= ~(gpiostatus & mask);
1592 qib_write_kreg(dd, kr_gpio_mask,
1593 dd->cspec->gpio_mask);
1594 }
1595 }
1596 if (to_clear)
1597 qib_write_kreg(dd, kr_gpio_clear, (u64) to_clear);
1598 }
1599}
1600
1601static irqreturn_t qib_6120intr(int irq, void *data)
1602{
1603 struct qib_devdata *dd = data;
1604 irqreturn_t ret;
1605 u32 istat, ctxtrbits, rmask, crcs = 0;
1606 unsigned i;
1607
1608 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) {
1609 /*
1610 * This return value is not great, but we do not want the
1611 * interrupt core code to remove our interrupt handler
1612 * because we don't appear to be handling an interrupt
1613 * during a chip reset.
1614 */
1615 ret = IRQ_HANDLED;
1616 goto bail;
1617 }
1618
1619 istat = qib_read_kreg32(dd, kr_intstatus);
1620
1621 if (unlikely(!istat)) {
1622 ret = IRQ_NONE; /* not our interrupt, or already handled */
1623 goto bail;
1624 }
1625 if (unlikely(istat == -1)) {
1626 qib_bad_intrstatus(dd);
1627 /* don't know if it was our interrupt or not */
1628 ret = IRQ_NONE;
1629 goto bail;
1630 }
1631
1632 qib_stats.sps_ints++;
1633 if (dd->int_counter != (u32) -1)
1634 dd->int_counter++;
1635
1636 if (unlikely(istat & (~QLOGIC_IB_I_BITSEXTANT |
1637 QLOGIC_IB_I_GPIO | QLOGIC_IB_I_ERROR)))
1638 unlikely_6120_intr(dd, istat);
1639
1640 /*
1641 * Clear the interrupt bits we found set, relatively early, so we
1642 * "know" know the chip will have seen this by the time we process
1643 * the queue, and will re-interrupt if necessary. The processor
1644 * itself won't take the interrupt again until we return.
1645 */
1646 qib_write_kreg(dd, kr_intclear, istat);
1647
1648 /*
1649 * Handle kernel receive queues before checking for pio buffers
1650 * available since receives can overflow; piobuf waiters can afford
1651 * a few extra cycles, since they were waiting anyway.
1652 */
1653 ctxtrbits = istat &
1654 ((QLOGIC_IB_I_RCVAVAIL_MASK << QLOGIC_IB_I_RCVAVAIL_SHIFT) |
1655 (QLOGIC_IB_I_RCVURG_MASK << QLOGIC_IB_I_RCVURG_SHIFT));
1656 if (ctxtrbits) {
1657 rmask = (1U << QLOGIC_IB_I_RCVAVAIL_SHIFT) |
1658 (1U << QLOGIC_IB_I_RCVURG_SHIFT);
1659 for (i = 0; i < dd->first_user_ctxt; i++) {
1660 if (ctxtrbits & rmask) {
1661 ctxtrbits &= ~rmask;
1662 crcs += qib_kreceive(dd->rcd[i],
1663 &dd->cspec->lli_counter,
1664 NULL);
1665 }
1666 rmask <<= 1;
1667 }
1668 if (crcs) {
1669 u32 cntr = dd->cspec->lli_counter;
1670 cntr += crcs;
1671 if (cntr) {
1672 if (cntr > dd->cspec->lli_thresh) {
1673 dd->cspec->lli_counter = 0;
1674 dd->cspec->lli_errs++;
1675 } else
1676 dd->cspec->lli_counter += cntr;
1677 }
1678 }
1679
1680
1681 if (ctxtrbits) {
1682 ctxtrbits =
1683 (ctxtrbits >> QLOGIC_IB_I_RCVAVAIL_SHIFT) |
1684 (ctxtrbits >> QLOGIC_IB_I_RCVURG_SHIFT);
1685 qib_handle_urcv(dd, ctxtrbits);
1686 }
1687 }
1688
1689 if ((istat & QLOGIC_IB_I_SPIOBUFAVAIL) && (dd->flags & QIB_INITTED))
1690 qib_ib_piobufavail(dd);
1691
1692 ret = IRQ_HANDLED;
1693bail:
1694 return ret;
1695}
1696
1697/*
1698 * Set up our chip-specific interrupt handler
1699 * The interrupt type has already been setup, so
1700 * we just need to do the registration and error checking.
1701 */
1702static void qib_setup_6120_interrupt(struct qib_devdata *dd)
1703{
1704 /*
1705 * If the chip supports added error indication via GPIO pins,
1706 * enable interrupts on those bits so the interrupt routine
1707 * can count the events. Also set flag so interrupt routine
1708 * can know they are expected.
1709 */
1710 if (SYM_FIELD(dd->revision, Revision_R,
1711 ChipRevMinor) > 1) {
1712 /* Rev2+ reports extra errors via internal GPIO pins */
1713 dd->cspec->gpio_mask |= GPIO_ERRINTR_MASK;
1714 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
1715 }
1716
1717 if (!dd->cspec->irq)
1718 qib_dev_err(dd, "irq is 0, BIOS error? Interrupts won't "
1719 "work\n");
1720 else {
1721 int ret;
1722 ret = request_irq(dd->cspec->irq, qib_6120intr, 0,
1723 QIB_DRV_NAME, dd);
1724 if (ret)
1725 qib_dev_err(dd, "Couldn't setup interrupt "
1726 "(irq=%d): %d\n", dd->cspec->irq,
1727 ret);
1728 }
1729}
1730
1731/**
1732 * pe_boardname - fill in the board name
1733 * @dd: the qlogic_ib device
1734 *
1735 * info is based on the board revision register
1736 */
1737static void pe_boardname(struct qib_devdata *dd)
1738{
1739 char *n;
1740 u32 boardid, namelen;
1741
1742 boardid = SYM_FIELD(dd->revision, Revision,
1743 BoardID);
1744
1745 switch (boardid) {
1746 case 2:
1747 n = "InfiniPath_QLE7140";
1748 break;
1749 default:
1750 qib_dev_err(dd, "Unknown 6120 board with ID %u\n", boardid);
1751 n = "Unknown_InfiniPath_6120";
1752 break;
1753 }
1754 namelen = strlen(n) + 1;
1755 dd->boardname = kmalloc(namelen, GFP_KERNEL);
1756 if (!dd->boardname)
1757 qib_dev_err(dd, "Failed allocation for board name: %s\n", n);
1758 else
1759 snprintf(dd->boardname, namelen, "%s", n);
1760
1761 if (dd->majrev != 4 || !dd->minrev || dd->minrev > 2)
1762 qib_dev_err(dd, "Unsupported InfiniPath hardware revision "
1763 "%u.%u!\n", dd->majrev, dd->minrev);
1764
1765 snprintf(dd->boardversion, sizeof(dd->boardversion),
1766 "ChipABI %u.%u, %s, InfiniPath%u %u.%u, SW Compat %u\n",
1767 QIB_CHIP_VERS_MAJ, QIB_CHIP_VERS_MIN, dd->boardname,
1768 (unsigned)SYM_FIELD(dd->revision, Revision_R, Arch),
1769 dd->majrev, dd->minrev,
1770 (unsigned)SYM_FIELD(dd->revision, Revision_R, SW));
1771
1772}
1773
1774/*
1775 * This routine sleeps, so it can only be called from user context, not
1776 * from interrupt context. If we need interrupt context, we can split
1777 * it into two routines.
1778 */
1779static int qib_6120_setup_reset(struct qib_devdata *dd)
1780{
1781 u64 val;
1782 int i;
1783 int ret;
1784 u16 cmdval;
1785 u8 int_line, clinesz;
1786
1787 qib_pcie_getcmd(dd, &cmdval, &int_line, &clinesz);
1788
1789 /* Use ERROR so it shows up in logs, etc. */
1790 qib_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->unit);
1791
1792 /* no interrupts till re-initted */
1793 qib_6120_set_intr_state(dd, 0);
1794
1795 dd->cspec->ibdeltainprog = 0;
1796 dd->cspec->ibsymdelta = 0;
1797 dd->cspec->iblnkerrdelta = 0;
1798
1799 /*
1800 * Keep chip from being accessed until we are ready. Use
1801 * writeq() directly, to allow the write even though QIB_PRESENT
e9c54999 1802 * isn't set.
f931551b
RC		 1803 */
1804 dd->flags &= ~(QIB_INITTED | QIB_PRESENT);
1805 dd->int_counter = 0; /* so we check interrupts work again */
1806 val = dd->control | QLOGIC_IB_C_RESET;
1807 writeq(val, &dd->kregbase[kr_control]);
1808 mb(); /* prevent compiler re-ordering around actual reset */
1809
1810 for (i = 1; i <= 5; i++) {
1811 /*
1812 * Allow MBIST, etc. to complete; longer on each retry.
1813 * We sometimes get machine checks from bus timeout if no
1814 * response, so for now, make it *really* long.
1815 */
1816 msleep(1000 + (1 + i) * 2000);
1817
1818 qib_pcie_reenable(dd, cmdval, int_line, clinesz);
1819
1820 /*
1821 * Use readq directly, so we don't need to mark it as PRESENT
1822 * until we get a successful indication that all is well.
1823 */
1824 val = readq(&dd->kregbase[kr_revision]);
1825 if (val == dd->revision) {
1826 dd->flags |= QIB_PRESENT; /* it's back */
1827 ret = qib_reinit_intr(dd);
1828 goto bail;
1829 }
1830 }
1831 ret = 0; /* failed */
1832
1833bail:
1834 if (ret) {
1835 if (qib_pcie_params(dd, dd->lbus_width, NULL, NULL))
1836 qib_dev_err(dd, "Reset failed to setup PCIe or "
1837 "interrupts; continuing anyway\n");
1838 /* clear the reset error, init error/hwerror mask */
1839 qib_6120_init_hwerrors(dd);
1840 /* for Rev2 error interrupts; nop for rev 1 */
1841 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
1842 /* clear the reset error, init error/hwerror mask */
1843 qib_6120_init_hwerrors(dd);
1844 }
1845 return ret;
1846}
1847
1848/**
1849 * qib_6120_put_tid - write a TID in chip
1850 * @dd: the qlogic_ib device
1851 * @tidptr: pointer to the expected TID (in chip) to update
1852 * @tidtype: RCVHQ_RCV_TYPE_EAGER (1) for eager, RCVHQ_RCV_TYPE_EXPECTED (0)
1853 * for expected
1854 * @pa: physical address of in memory buffer; tidinvalid if freeing
1855 *
1856 * This exists as a separate routine to allow for special locking etc.
1857 * It's used for both the full cleanup on exit, as well as the normal
1858 * setup and teardown.
1859 */
1860static void qib_6120_put_tid(struct qib_devdata *dd, u64 __iomem *tidptr,
1861 u32 type, unsigned long pa)
1862{
1863 u32 __iomem *tidp32 = (u32 __iomem *)tidptr;
1864 unsigned long flags;
1865 int tidx;
1866 spinlock_t *tidlockp; /* select appropriate spinlock */
1867
1868 if (!dd->kregbase)
1869 return;
1870
1871 if (pa != dd->tidinvalid) {
1872 if (pa & ((1U << 11) - 1)) {
1873 qib_dev_err(dd, "Physaddr %lx not 2KB aligned!\n",
1874 pa);
1875 return;
1876 }
1877 pa >>= 11;
1878 if (pa & ~QLOGIC_IB_RT_ADDR_MASK) {
1879 qib_dev_err(dd, "Physical page address 0x%lx "
1880 "larger than supported\n", pa);
1881 return;
1882 }
1883
1884 if (type == RCVHQ_RCV_TYPE_EAGER)
1885 pa |= dd->tidtemplate;
1886 else /* for now, always full 4KB page */
1887 pa |= 2 << 29;
1888 }
1889
1890 /*
1891 * Avoid chip issue by writing the scratch register
1892 * before and after the TID, and with an io write barrier.
1893 * We use a spinlock around the writes, so they can't intermix
1894 * with other TID (eager or expected) writes (the chip problem
1895 * is triggered by back to back TID writes). Unfortunately, this
1896 * call can be done from interrupt level for the ctxt 0 eager TIDs,
1897 * so we have to use irqsave locks.
1898 */
1899 /*
1900 * Assumes tidptr always > egrtidbase
1901 * if type == RCVHQ_RCV_TYPE_EAGER.
1902 */
1903 tidx = tidptr - dd->egrtidbase;
1904
1905 tidlockp = (type == RCVHQ_RCV_TYPE_EAGER && tidx < dd->rcvhdrcnt)
1906 ? &dd->cspec->kernel_tid_lock : &dd->cspec->user_tid_lock;
1907 spin_lock_irqsave(tidlockp, flags);
1908 qib_write_kreg(dd, kr_scratch, 0xfeeddeaf);
1909 writel(pa, tidp32);
1910 qib_write_kreg(dd, kr_scratch, 0xdeadbeef);
1911 mmiowb();
1912 spin_unlock_irqrestore(tidlockp, flags);
1913}
1914
1915/**
1916 * qib_6120_put_tid_2 - write a TID in chip, Revision 2 or higher
1917 * @dd: the qlogic_ib device
1918 * @tidptr: pointer to the expected TID (in chip) to update
1919 * @tidtype: RCVHQ_RCV_TYPE_EAGER (1) for eager, RCVHQ_RCV_TYPE_EXPECTED (0)
1920 * for expected
1921 * @pa: physical address of in memory buffer; tidinvalid if freeing
1922 *
1923 * This exists as a separate routine to allow for selection of the
1924 * appropriate "flavor". The static calls in cleanup just use the
1925 * revision-agnostic form, as they are not performance critical.
1926 */
1927static void qib_6120_put_tid_2(struct qib_devdata *dd, u64 __iomem *tidptr,
1928 u32 type, unsigned long pa)
1929{
1930 u32 __iomem *tidp32 = (u32 __iomem *)tidptr;
1931 u32 tidx;
1932
1933 if (!dd->kregbase)
1934 return;
1935
1936 if (pa != dd->tidinvalid) {
1937 if (pa & ((1U << 11) - 1)) {
1938 qib_dev_err(dd, "Physaddr %lx not 2KB aligned!\n",
1939 pa);
1940 return;
1941 }
1942 pa >>= 11;
1943 if (pa & ~QLOGIC_IB_RT_ADDR_MASK) {
1944 qib_dev_err(dd, "Physical page address 0x%lx "
1945 "larger than supported\n", pa);
1946 return;
1947 }
1948
1949 if (type == RCVHQ_RCV_TYPE_EAGER)
1950 pa |= dd->tidtemplate;
1951 else /* for now, always full 4KB page */
1952 pa |= 2 << 29;
1953 }
1954 tidx = tidptr - dd->egrtidbase;
1955 writel(pa, tidp32);
1956 mmiowb();
1957}
1958
1959
1960/**
1961 * qib_6120_clear_tids - clear all TID entries for a context, expected and eager
1962 * @dd: the qlogic_ib device
1963 * @ctxt: the context
1964 *
1965 * clear all TID entries for a context, expected and eager.
1966 * Used from qib_close(). On this chip, TIDs are only 32 bits,
1967 * not 64, but they are still on 64 bit boundaries, so tidbase
1968 * is declared as u64 * for the pointer math, even though we write 32 bits
1969 */
1970static void qib_6120_clear_tids(struct qib_devdata *dd,
1971 struct qib_ctxtdata *rcd)
1972{
1973 u64 __iomem *tidbase;
1974 unsigned long tidinv;
1975 u32 ctxt;
1976 int i;
1977
1978 if (!dd->kregbase || !rcd)
1979 return;
1980
1981 ctxt = rcd->ctxt;
1982
1983 tidinv = dd->tidinvalid;
1984 tidbase = (u64 __iomem *)
1985 ((char __iomem *)(dd->kregbase) +
1986 dd->rcvtidbase +
1987 ctxt * dd->rcvtidcnt * sizeof(*tidbase));
1988
1989 for (i = 0; i < dd->rcvtidcnt; i++)
1990 /* use func pointer because could be one of two funcs */
1991 dd->f_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED,
1992 tidinv);
1993
1994 tidbase = (u64 __iomem *)
1995 ((char __iomem *)(dd->kregbase) +
1996 dd->rcvegrbase +
1997 rcd->rcvegr_tid_base * sizeof(*tidbase));
1998
1999 for (i = 0; i < rcd->rcvegrcnt; i++)
2000 /* use func pointer because could be one of two funcs */
2001 dd->f_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER,
2002 tidinv);
2003}
2004
2005/**
2006 * qib_6120_tidtemplate - setup constants for TID updates
2007 * @dd: the qlogic_ib device
2008 *
2009 * We setup stuff that we use a lot, to avoid calculating each time
2010 */
2011static void qib_6120_tidtemplate(struct qib_devdata *dd)
2012{
2013 u32 egrsize = dd->rcvegrbufsize;
2014
2015 /*
2016 * For now, we always allocate 4KB buffers (at init) so we can
2017 * receive max size packets. We may want a module parameter to
2018 * specify 2KB or 4KB and/or make be per ctxt instead of per device
2019 * for those who want to reduce memory footprint. Note that the
2020 * rcvhdrentsize size must be large enough to hold the largest
2021 * IB header (currently 96 bytes) that we expect to handle (plus of
2022 * course the 2 dwords of RHF).
2023 */
2024 if (egrsize == 2048)
2025 dd->tidtemplate = 1U << 29;
2026 else if (egrsize == 4096)
2027 dd->tidtemplate = 2U << 29;
2028 dd->tidinvalid = 0;
2029}
2030
2031int __attribute__((weak)) qib_unordered_wc(void)
2032{
2033 return 0;
2034}
2035
2036/**
2037 * qib_6120_get_base_info - set chip-specific flags for user code
2038 * @rcd: the qlogic_ib ctxt
2039 * @kbase: qib_base_info pointer
2040 *
2041 * We set the PCIE flag because the lower bandwidth on PCIe vs
2042 * HyperTransport can affect some user packet algorithms.
2043 */
2044static int qib_6120_get_base_info(struct qib_ctxtdata *rcd,
2045 struct qib_base_info *kinfo)
2046{
2047 if (qib_unordered_wc())
2048 kinfo->spi_runtime_flags |= QIB_RUNTIME_FORCE_WC_ORDER;
2049
2050 kinfo->spi_runtime_flags |= QIB_RUNTIME_PCIE |
2051 QIB_RUNTIME_FORCE_PIOAVAIL | QIB_RUNTIME_PIO_REGSWAPPED;
2052 return 0;
2053}
2054
2055
2056static struct qib_message_header *
2057qib_6120_get_msgheader(struct qib_devdata *dd, __le32 *rhf_addr)
2058{
2059 return (struct qib_message_header *)
2060 &rhf_addr[sizeof(u64) / sizeof(u32)];
2061}
2062
2063static void qib_6120_config_ctxts(struct qib_devdata *dd)
2064{
2065 dd->ctxtcnt = qib_read_kreg32(dd, kr_portcnt);
2066 if (qib_n_krcv_queues > 1) {
2067 dd->first_user_ctxt = qib_n_krcv_queues * dd->num_pports;
2068 if (dd->first_user_ctxt > dd->ctxtcnt)
2069 dd->first_user_ctxt = dd->ctxtcnt;
2070 dd->qpn_mask = dd->first_user_ctxt <= 2 ? 2 : 6;
2071 } else
2072 dd->first_user_ctxt = dd->num_pports;
2073 dd->n_krcv_queues = dd->first_user_ctxt;
2074}
2075
2076static void qib_update_6120_usrhead(struct qib_ctxtdata *rcd, u64 hd,
19ede2e4 2077 u32 updegr, u32 egrhd, u32 npkts)
f931551b
RC		 2078{
2079 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);
2080 if (updegr)
2081 qib_write_ureg(rcd->dd, ur_rcvegrindexhead, egrhd, rcd->ctxt);
2082}
2083
2084static u32 qib_6120_hdrqempty(struct qib_ctxtdata *rcd)
2085{
2086 u32 head, tail;
2087
2088 head = qib_read_ureg32(rcd->dd, ur_rcvhdrhead, rcd->ctxt);
2089 if (rcd->rcvhdrtail_kvaddr)
2090 tail = qib_get_rcvhdrtail(rcd);
2091 else
2092 tail = qib_read_ureg32(rcd->dd, ur_rcvhdrtail, rcd->ctxt);
2093 return head == tail;
2094}
2095
2096/*
2097 * Used when we close any ctxt, for DMA already in flight
2098 * at close. Can't be done until we know hdrq size, so not
2099 * early in chip init.
2100 */
2101static void alloc_dummy_hdrq(struct qib_devdata *dd)
2102{
2103 dd->cspec->dummy_hdrq = dma_alloc_coherent(&dd->pcidev->dev,
2104 dd->rcd[0]->rcvhdrq_size,
2105 &dd->cspec->dummy_hdrq_phys,
2106 GFP_KERNEL | __GFP_COMP);
2107 if (!dd->cspec->dummy_hdrq) {
2108 qib_devinfo(dd->pcidev, "Couldn't allocate dummy hdrq\n");
2109 /* fallback to just 0'ing */
2110 dd->cspec->dummy_hdrq_phys = 0UL;
2111 }
2112}
2113
2114/*
2115 * Modify the RCVCTRL register in chip-specific way. This
2116 * is a function because bit positions and (future) register
2117 * location is chip-specific, but the needed operations are
2118 * generic. <op> is a bit-mask because we often want to
2119 * do multiple modifications.
2120 */
2121static void rcvctrl_6120_mod(struct qib_pportdata *ppd, unsigned int op,
2122 int ctxt)
2123{
2124 struct qib_devdata *dd = ppd->dd;
2125 u64 mask, val;
2126 unsigned long flags;
2127
2128 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
2129
2130 if (op & QIB_RCVCTRL_TAILUPD_ENB)
2131 dd->rcvctrl |= (1ULL << QLOGIC_IB_R_TAILUPD_SHIFT);
2132 if (op & QIB_RCVCTRL_TAILUPD_DIS)
2133 dd->rcvctrl &= ~(1ULL << QLOGIC_IB_R_TAILUPD_SHIFT);
2134 if (op & QIB_RCVCTRL_PKEY_ENB)
2135 dd->rcvctrl &= ~(1ULL << IBA6120_R_PKEY_DIS_SHIFT);
2136 if (op & QIB_RCVCTRL_PKEY_DIS)
2137 dd->rcvctrl |= (1ULL << IBA6120_R_PKEY_DIS_SHIFT);
2138 if (ctxt < 0)
2139 mask = (1ULL << dd->ctxtcnt) - 1;
2140 else
2141 mask = (1ULL << ctxt);
2142 if (op & QIB_RCVCTRL_CTXT_ENB) {
2143 /* always done for specific ctxt */
2144 dd->rcvctrl |= (mask << SYM_LSB(RcvCtrl, PortEnable));
2145 if (!(dd->flags & QIB_NODMA_RTAIL))
2146 dd->rcvctrl |= 1ULL << QLOGIC_IB_R_TAILUPD_SHIFT;
2147 /* Write these registers before the context is enabled. */
2148 qib_write_kreg_ctxt(dd, kr_rcvhdrtailaddr, ctxt,
2149 dd->rcd[ctxt]->rcvhdrqtailaddr_phys);
2150 qib_write_kreg_ctxt(dd, kr_rcvhdraddr, ctxt,
2151 dd->rcd[ctxt]->rcvhdrq_phys);
2152
2153 if (ctxt == 0 && !dd->cspec->dummy_hdrq)
2154 alloc_dummy_hdrq(dd);
2155 }
2156 if (op & QIB_RCVCTRL_CTXT_DIS)
2157 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, PortEnable));
2158 if (op & QIB_RCVCTRL_INTRAVAIL_ENB)
2159 dd->rcvctrl |= (mask << QLOGIC_IB_R_INTRAVAIL_SHIFT);
2160 if (op & QIB_RCVCTRL_INTRAVAIL_DIS)
2161 dd->rcvctrl &= ~(mask << QLOGIC_IB_R_INTRAVAIL_SHIFT);
2162 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl);
2163 if ((op & QIB_RCVCTRL_INTRAVAIL_ENB) && dd->rhdrhead_intr_off) {
2164 /* arm rcv interrupt */
2165 val = qib_read_ureg32(dd, ur_rcvhdrhead, ctxt) |
2166 dd->rhdrhead_intr_off;
2167 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);
2168 }
2169 if (op & QIB_RCVCTRL_CTXT_ENB) {
2170 /*
2171 * Init the context registers also; if we were
2172 * disabled, tail and head should both be zero
2173 * already from the enable, but since we don't
25985edc 2174 * know, we have to do it explicitly.
f931551b
RC		 2175 */
2176 val = qib_read_ureg32(dd, ur_rcvegrindextail, ctxt);
2177 qib_write_ureg(dd, ur_rcvegrindexhead, val, ctxt);
2178
2179 val = qib_read_ureg32(dd, ur_rcvhdrtail, ctxt);
2180 dd->rcd[ctxt]->head = val;
2181 /* If kctxt, interrupt on next receive. */
2182 if (ctxt < dd->first_user_ctxt)
2183 val |= dd->rhdrhead_intr_off;
2184 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);
2185 }
2186 if (op & QIB_RCVCTRL_CTXT_DIS) {
2187 /*
2188 * Be paranoid, and never write 0's to these, just use an
2189 * unused page. Of course,
2190 * rcvhdraddr points to a large chunk of memory, so this
2191 * could still trash things, but at least it won't trash
2192 * page 0, and by disabling the ctxt, it should stop "soon",
2193 * even if a packet or two is in already in flight after we
2194 * disabled the ctxt. Only 6120 has this issue.
2195 */
2196 if (ctxt >= 0) {
2197 qib_write_kreg_ctxt(dd, kr_rcvhdrtailaddr, ctxt,
2198 dd->cspec->dummy_hdrq_phys);
2199 qib_write_kreg_ctxt(dd, kr_rcvhdraddr, ctxt,
2200 dd->cspec->dummy_hdrq_phys);
2201 } else {
2202 unsigned i;
2203
2204 for (i = 0; i < dd->cfgctxts; i++) {
2205 qib_write_kreg_ctxt(dd, kr_rcvhdrtailaddr,
2206 i, dd->cspec->dummy_hdrq_phys);
2207 qib_write_kreg_ctxt(dd, kr_rcvhdraddr,
2208 i, dd->cspec->dummy_hdrq_phys);
2209 }
2210 }
2211 }
2212 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
2213}
2214
2215/*
2216 * Modify the SENDCTRL register in chip-specific way. This
2217 * is a function there may be multiple such registers with
2218 * slightly different layouts. Only operations actually used
2219 * are implemented yet.
2220 * Chip requires no back-back sendctrl writes, so write
2221 * scratch register after writing sendctrl
2222 */
2223static void sendctrl_6120_mod(struct qib_pportdata *ppd, u32 op)
2224{
2225 struct qib_devdata *dd = ppd->dd;
2226 u64 tmp_dd_sendctrl;
2227 unsigned long flags;
2228
2229 spin_lock_irqsave(&dd->sendctrl_lock, flags);
2230
2231 /* First the ones that are "sticky", saved in shadow */
2232 if (op & QIB_SENDCTRL_CLEAR)
2233 dd->sendctrl = 0;
2234 if (op & QIB_SENDCTRL_SEND_DIS)
2235 dd->sendctrl &= ~SYM_MASK(SendCtrl, PIOEnable);
2236 else if (op & QIB_SENDCTRL_SEND_ENB)
2237 dd->sendctrl |= SYM_MASK(SendCtrl, PIOEnable);
2238 if (op & QIB_SENDCTRL_AVAIL_DIS)
2239 dd->sendctrl &= ~SYM_MASK(SendCtrl, PIOBufAvailUpd);
2240 else if (op & QIB_SENDCTRL_AVAIL_ENB)
2241 dd->sendctrl |= SYM_MASK(SendCtrl, PIOBufAvailUpd);
2242
2243 if (op & QIB_SENDCTRL_DISARM_ALL) {
2244 u32 i, last;
2245
2246 tmp_dd_sendctrl = dd->sendctrl;
2247 /*
2248 * disarm any that are not yet launched, disabling sends
2249 * and updates until done.
2250 */
2251 last = dd->piobcnt2k + dd->piobcnt4k;
2252 tmp_dd_sendctrl &=
2253 ~(SYM_MASK(SendCtrl, PIOEnable) |
2254 SYM_MASK(SendCtrl, PIOBufAvailUpd));
2255 for (i = 0; i < last; i++) {
2256 qib_write_kreg(dd, kr_sendctrl, tmp_dd_sendctrl |
2257 SYM_MASK(SendCtrl, Disarm) | i);
2258 qib_write_kreg(dd, kr_scratch, 0);
2259 }
2260 }
2261
2262 tmp_dd_sendctrl = dd->sendctrl;
2263
2264 if (op & QIB_SENDCTRL_FLUSH)
2265 tmp_dd_sendctrl |= SYM_MASK(SendCtrl, Abort);
2266 if (op & QIB_SENDCTRL_DISARM)
2267 tmp_dd_sendctrl |= SYM_MASK(SendCtrl, Disarm) |
2268 ((op & QIB_6120_SendCtrl_DisarmPIOBuf_RMASK) <<
2269 SYM_LSB(SendCtrl, DisarmPIOBuf));
2270 if (op & QIB_SENDCTRL_AVAIL_BLIP)
2271 tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, PIOBufAvailUpd);
2272
2273 qib_write_kreg(dd, kr_sendctrl, tmp_dd_sendctrl);
2274 qib_write_kreg(dd, kr_scratch, 0);
2275
2276 if (op & QIB_SENDCTRL_AVAIL_BLIP) {
2277 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
2278 qib_write_kreg(dd, kr_scratch, 0);
2279 }
2280
2281 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
2282
2283 if (op & QIB_SENDCTRL_FLUSH) {
2284 u32 v;
2285 /*
2286 * ensure writes have hit chip, then do a few
2287 * more reads, to allow DMA of pioavail registers
2288 * to occur, so in-memory copy is in sync with
2289 * the chip. Not always safe to sleep.
2290 */
2291 v = qib_read_kreg32(dd, kr_scratch);
2292 qib_write_kreg(dd, kr_scratch, v);
2293 v = qib_read_kreg32(dd, kr_scratch);
2294 qib_write_kreg(dd, kr_scratch, v);
2295 qib_read_kreg32(dd, kr_scratch);
2296 }
2297}
2298
2299/**
2300 * qib_portcntr_6120 - read a per-port counter
2301 * @dd: the qlogic_ib device
2302 * @creg: the counter to snapshot
2303 */
2304static u64 qib_portcntr_6120(struct qib_pportdata *ppd, u32 reg)
2305{
2306 u64 ret = 0ULL;
2307 struct qib_devdata *dd = ppd->dd;
2308 u16 creg;
2309 /* 0xffff for unimplemented or synthesized counters */
2310 static const u16 xlator[] = {
2311 [QIBPORTCNTR_PKTSEND] = cr_pktsend,
2312 [QIBPORTCNTR_WORDSEND] = cr_wordsend,
2313 [QIBPORTCNTR_PSXMITDATA] = 0xffff,
2314 [QIBPORTCNTR_PSXMITPKTS] = 0xffff,
2315 [QIBPORTCNTR_PSXMITWAIT] = 0xffff,
2316 [QIBPORTCNTR_SENDSTALL] = cr_sendstall,
2317 [QIBPORTCNTR_PKTRCV] = cr_pktrcv,
2318 [QIBPORTCNTR_PSRCVDATA] = 0xffff,
2319 [QIBPORTCNTR_PSRCVPKTS] = 0xffff,
2320 [QIBPORTCNTR_RCVEBP] = cr_rcvebp,
2321 [QIBPORTCNTR_RCVOVFL] = cr_rcvovfl,
2322 [QIBPORTCNTR_WORDRCV] = cr_wordrcv,
2323 [QIBPORTCNTR_RXDROPPKT] = cr_rxdroppkt,
2324 [QIBPORTCNTR_RXLOCALPHYERR] = 0xffff,
2325 [QIBPORTCNTR_RXVLERR] = 0xffff,
2326 [QIBPORTCNTR_ERRICRC] = cr_erricrc,
2327 [QIBPORTCNTR_ERRVCRC] = cr_errvcrc,
2328 [QIBPORTCNTR_ERRLPCRC] = cr_errlpcrc,
2329 [QIBPORTCNTR_BADFORMAT] = cr_badformat,
2330 [QIBPORTCNTR_ERR_RLEN] = cr_err_rlen,
2331 [QIBPORTCNTR_IBSYMBOLERR] = cr_ibsymbolerr,
2332 [QIBPORTCNTR_INVALIDRLEN] = cr_invalidrlen,
2333 [QIBPORTCNTR_UNSUPVL] = cr_txunsupvl,
2334 [QIBPORTCNTR_EXCESSBUFOVFL] = 0xffff,
2335 [QIBPORTCNTR_ERRLINK] = cr_errlink,
2336 [QIBPORTCNTR_IBLINKDOWN] = cr_iblinkdown,
2337 [QIBPORTCNTR_IBLINKERRRECOV] = cr_iblinkerrrecov,
2338 [QIBPORTCNTR_LLI] = 0xffff,
2339 [QIBPORTCNTR_PSINTERVAL] = 0xffff,
2340 [QIBPORTCNTR_PSSTART] = 0xffff,
2341 [QIBPORTCNTR_PSSTAT] = 0xffff,
2342 [QIBPORTCNTR_VL15PKTDROP] = 0xffff,
2343 [QIBPORTCNTR_ERRPKEY] = cr_errpkey,
2344 [QIBPORTCNTR_KHDROVFL] = 0xffff,
2345 };
2346
2347 if (reg >= ARRAY_SIZE(xlator)) {
2348 qib_devinfo(ppd->dd->pcidev,
2349 "Unimplemented portcounter %u\n", reg);
2350 goto done;
2351 }
2352 creg = xlator[reg];
2353
2354 /* handle counters requests not implemented as chip counters */
2355 if (reg == QIBPORTCNTR_LLI)
2356 ret = dd->cspec->lli_errs;
2357 else if (reg == QIBPORTCNTR_EXCESSBUFOVFL)
2358 ret = dd->cspec->overrun_thresh_errs;
2359 else if (reg == QIBPORTCNTR_KHDROVFL) {
2360 int i;
2361
2362 /* sum over all kernel contexts */
2363 for (i = 0; i < dd->first_user_ctxt; i++)
2364 ret += read_6120_creg32(dd, cr_portovfl + i);
2365 } else if (reg == QIBPORTCNTR_PSSTAT)
2366 ret = dd->cspec->pma_sample_status;
2367 if (creg == 0xffff)
2368 goto done;
2369
2370 /*
2371 * only fast incrementing counters are 64bit; use 32 bit reads to
2372 * avoid two independent reads when on opteron
2373 */
2374 if (creg == cr_wordsend || creg == cr_wordrcv ||
2375 creg == cr_pktsend || creg == cr_pktrcv)
2376 ret = read_6120_creg(dd, creg);
2377 else
2378 ret = read_6120_creg32(dd, creg);
2379 if (creg == cr_ibsymbolerr) {
2380 if (dd->cspec->ibdeltainprog)
2381 ret -= ret - dd->cspec->ibsymsnap;
2382 ret -= dd->cspec->ibsymdelta;
2383 } else if (creg == cr_iblinkerrrecov) {
2384 if (dd->cspec->ibdeltainprog)
2385 ret -= ret - dd->cspec->iblnkerrsnap;
2386 ret -= dd->cspec->iblnkerrdelta;
2387 }
2388 if (reg == QIBPORTCNTR_RXDROPPKT) /* add special cased count */
2389 ret += dd->cspec->rxfc_unsupvl_errs;
2390
2391done:
2392 return ret;
2393}
2394
2395/*
2396 * Device counter names (not port-specific), one line per stat,
2397 * single string. Used by utilities like ipathstats to print the stats
2398 * in a way which works for different versions of drivers, without changing
2399 * the utility. Names need to be 12 chars or less (w/o newline), for proper
2400 * display by utility.
2401 * Non-error counters are first.
2402 * Start of "error" conters is indicated by a leading "E " on the first
2403 * "error" counter, and doesn't count in label length.
2404 * The EgrOvfl list needs to be last so we truncate them at the configured
2405 * context count for the device.
2406 * cntr6120indices contains the corresponding register indices.
2407 */
2408static const char cntr6120names[] =
2409 "Interrupts\n"
2410 "HostBusStall\n"
2411 "E RxTIDFull\n"
2412 "RxTIDInvalid\n"
2413 "Ctxt0EgrOvfl\n"
2414 "Ctxt1EgrOvfl\n"
2415 "Ctxt2EgrOvfl\n"
2416 "Ctxt3EgrOvfl\n"
2417 "Ctxt4EgrOvfl\n";
2418
2419static const size_t cntr6120indices[] = {
2420 cr_lbint,
2421 cr_lbflowstall,
2422 cr_errtidfull,
2423 cr_errtidvalid,
2424 cr_portovfl + 0,
2425 cr_portovfl + 1,
2426 cr_portovfl + 2,
2427 cr_portovfl + 3,
2428 cr_portovfl + 4,
2429};
2430
2431/*
2432 * same as cntr6120names and cntr6120indices, but for port-specific counters.
2433 * portcntr6120indices is somewhat complicated by some registers needing
2434 * adjustments of various kinds, and those are ORed with _PORT_VIRT_FLAG
2435 */
2436static const char portcntr6120names[] =
2437 "TxPkt\n"
2438 "TxFlowPkt\n"
2439 "TxWords\n"
2440 "RxPkt\n"
2441 "RxFlowPkt\n"
2442 "RxWords\n"
2443 "TxFlowStall\n"
2444 "E IBStatusChng\n"
2445 "IBLinkDown\n"
2446 "IBLnkRecov\n"
2447 "IBRxLinkErr\n"
2448 "IBSymbolErr\n"
2449 "RxLLIErr\n"
2450 "RxBadFormat\n"
2451 "RxBadLen\n"
2452 "RxBufOvrfl\n"
2453 "RxEBP\n"
2454 "RxFlowCtlErr\n"
2455 "RxICRCerr\n"
2456 "RxLPCRCerr\n"
2457 "RxVCRCerr\n"
2458 "RxInvalLen\n"
2459 "RxInvalPKey\n"
2460 "RxPktDropped\n"
2461 "TxBadLength\n"
2462 "TxDropped\n"
2463 "TxInvalLen\n"
2464 "TxUnderrun\n"
2465 "TxUnsupVL\n"
2466 ;
2467
2468#define _PORT_VIRT_FLAG 0x8000 /* "virtual", need adjustments */
2469static const size_t portcntr6120indices[] = {
2470 QIBPORTCNTR_PKTSEND | _PORT_VIRT_FLAG,
2471 cr_pktsendflow,
2472 QIBPORTCNTR_WORDSEND | _PORT_VIRT_FLAG,
2473 QIBPORTCNTR_PKTRCV | _PORT_VIRT_FLAG,
2474 cr_pktrcvflowctrl,
2475 QIBPORTCNTR_WORDRCV | _PORT_VIRT_FLAG,
2476 QIBPORTCNTR_SENDSTALL | _PORT_VIRT_FLAG,
2477 cr_ibstatuschange,
2478 QIBPORTCNTR_IBLINKDOWN | _PORT_VIRT_FLAG,
2479 QIBPORTCNTR_IBLINKERRRECOV | _PORT_VIRT_FLAG,
2480 QIBPORTCNTR_ERRLINK | _PORT_VIRT_FLAG,
2481 QIBPORTCNTR_IBSYMBOLERR | _PORT_VIRT_FLAG,
2482 QIBPORTCNTR_LLI | _PORT_VIRT_FLAG,
2483 QIBPORTCNTR_BADFORMAT | _PORT_VIRT_FLAG,
2484 QIBPORTCNTR_ERR_RLEN | _PORT_VIRT_FLAG,
2485 QIBPORTCNTR_RCVOVFL | _PORT_VIRT_FLAG,
2486 QIBPORTCNTR_RCVEBP | _PORT_VIRT_FLAG,
2487 cr_rcvflowctrl_err,
2488 QIBPORTCNTR_ERRICRC | _PORT_VIRT_FLAG,
2489 QIBPORTCNTR_ERRLPCRC | _PORT_VIRT_FLAG,
2490 QIBPORTCNTR_ERRVCRC | _PORT_VIRT_FLAG,
2491 QIBPORTCNTR_INVALIDRLEN | _PORT_VIRT_FLAG,
2492 QIBPORTCNTR_ERRPKEY | _PORT_VIRT_FLAG,
2493 QIBPORTCNTR_RXDROPPKT | _PORT_VIRT_FLAG,
2494 cr_invalidslen,
2495 cr_senddropped,
2496 cr_errslen,
2497 cr_sendunderrun,
2498 cr_txunsupvl,
2499};
2500
2501/* do all the setup to make the counter reads efficient later */
2502static void init_6120_cntrnames(struct qib_devdata *dd)
2503{
2504 int i, j = 0;
2505 char *s;
2506
2507 for (i = 0, s = (char *)cntr6120names; s && j <= dd->cfgctxts;
2508 i++) {
2509 /* we always have at least one counter before the egrovfl */
2510 if (!j && !strncmp("Ctxt0EgrOvfl", s + 1, 12))
2511 j = 1;
2512 s = strchr(s + 1, '\n');
2513 if (s && j)
2514 j++;
2515 }
2516 dd->cspec->ncntrs = i;
2517 if (!s)
2518 /* full list; size is without terminating null */
2519 dd->cspec->cntrnamelen = sizeof(cntr6120names) - 1;
2520 else
2521 dd->cspec->cntrnamelen = 1 + s - cntr6120names;
2522 dd->cspec->cntrs = kmalloc(dd->cspec->ncntrs
2523 * sizeof(u64), GFP_KERNEL);
2524 if (!dd->cspec->cntrs)
2525 qib_dev_err(dd, "Failed allocation for counters\n");
2526
2527 for (i = 0, s = (char *)portcntr6120names; s; i++)
2528 s = strchr(s + 1, '\n');
2529 dd->cspec->nportcntrs = i - 1;
2530 dd->cspec->portcntrnamelen = sizeof(portcntr6120names) - 1;
2531 dd->cspec->portcntrs = kmalloc(dd->cspec->nportcntrs
2532 * sizeof(u64), GFP_KERNEL);
2533 if (!dd->cspec->portcntrs)
2534 qib_dev_err(dd, "Failed allocation for portcounters\n");
2535}
2536
2537static u32 qib_read_6120cntrs(struct qib_devdata *dd, loff_t pos, char **namep,
2538 u64 **cntrp)
2539{
2540 u32 ret;
2541
2542 if (namep) {
2543 ret = dd->cspec->cntrnamelen;
2544 if (pos >= ret)
2545 ret = 0; /* final read after getting everything */
2546 else
2547 *namep = (char *)cntr6120names;
2548 } else {
2549 u64 *cntr = dd->cspec->cntrs;
2550 int i;
2551
2552 ret = dd->cspec->ncntrs * sizeof(u64);
2553 if (!cntr || pos >= ret) {
2554 /* everything read, or couldn't get memory */
2555 ret = 0;
2556 goto done;
2557 }
2558 if (pos >= ret) {
2559 ret = 0; /* final read after getting everything */
2560 goto done;
2561 }
2562 *cntrp = cntr;
2563 for (i = 0; i < dd->cspec->ncntrs; i++)
2564 *cntr++ = read_6120_creg32(dd, cntr6120indices[i]);
2565 }
2566done:
2567 return ret;
2568}
2569
2570static u32 qib_read_6120portcntrs(struct qib_devdata *dd, loff_t pos, u32 port,
2571 char **namep, u64 **cntrp)
2572{
2573 u32 ret;
2574
2575 if (namep) {
2576 ret = dd->cspec->portcntrnamelen;
2577 if (pos >= ret)
2578 ret = 0; /* final read after getting everything */
2579 else
2580 *namep = (char *)portcntr6120names;
2581 } else {
2582 u64 *cntr = dd->cspec->portcntrs;
2583 struct qib_pportdata *ppd = &dd->pport[port];
2584 int i;
2585
2586 ret = dd->cspec->nportcntrs * sizeof(u64);
2587 if (!cntr || pos >= ret) {
2588 /* everything read, or couldn't get memory */
2589 ret = 0;
2590 goto done;
2591 }
2592 *cntrp = cntr;
2593 for (i = 0; i < dd->cspec->nportcntrs; i++) {
2594 if (portcntr6120indices[i] & _PORT_VIRT_FLAG)
2595 *cntr++ = qib_portcntr_6120(ppd,
2596 portcntr6120indices[i] &
2597 ~_PORT_VIRT_FLAG);
2598 else
2599 *cntr++ = read_6120_creg32(dd,
2600 portcntr6120indices[i]);
2601 }
2602 }
2603done:
2604 return ret;
2605}
2606
2607static void qib_chk_6120_errormask(struct qib_devdata *dd)
2608{
2609 static u32 fixed;
2610 u32 ctrl;
2611 unsigned long errormask;
2612 unsigned long hwerrs;
2613
2614 if (!dd->cspec->errormask || !(dd->flags & QIB_INITTED))
2615 return;
2616
2617 errormask = qib_read_kreg64(dd, kr_errmask);
2618
2619 if (errormask == dd->cspec->errormask)
2620 return;
2621 fixed++;
2622
2623 hwerrs = qib_read_kreg64(dd, kr_hwerrstatus);
2624 ctrl = qib_read_kreg32(dd, kr_control);
2625
2626 qib_write_kreg(dd, kr_errmask,
2627 dd->cspec->errormask);
2628
2629 if ((hwerrs & dd->cspec->hwerrmask) ||
2630 (ctrl & QLOGIC_IB_C_FREEZEMODE)) {
2631 qib_write_kreg(dd, kr_hwerrclear, 0ULL);
2632 qib_write_kreg(dd, kr_errclear, 0ULL);
2633 /* force re-interrupt of pending events, just in case */
2634 qib_write_kreg(dd, kr_intclear, 0ULL);
2635 qib_devinfo(dd->pcidev,
2636 "errormask fixed(%u) %lx->%lx, ctrl %x hwerr %lx\n",
2637 fixed, errormask, (unsigned long)dd->cspec->errormask,
2638 ctrl, hwerrs);
2639 }
2640}
2641
2642/**
2643 * qib_get_faststats - get word counters from chip before they overflow
2644 * @opaque - contains a pointer to the qlogic_ib device qib_devdata
2645 *
2646 * This needs more work; in particular, decision on whether we really
2647 * need traffic_wds done the way it is
2648 * called from add_timer
2649 */
2650static void qib_get_6120_faststats(unsigned long opaque)
2651{
2652 struct qib_devdata *dd = (struct qib_devdata *) opaque;
2653 struct qib_pportdata *ppd = dd->pport;
2654 unsigned long flags;
2655 u64 traffic_wds;
2656
2657 /*
2658 * don't access the chip while running diags, or memory diags can
2659 * fail
2660 */
2661 if (!(dd->flags & QIB_INITTED) || dd->diag_client)
2662 /* but re-arm the timer, for diags case; won't hurt other */
2663 goto done;
2664
2665 /*
2666 * We now try to maintain an activity timer, based on traffic
2667 * exceeding a threshold, so we need to check the word-counts
2668 * even if they are 64-bit.
2669 */
2670 traffic_wds = qib_portcntr_6120(ppd, cr_wordsend) +
2671 qib_portcntr_6120(ppd, cr_wordrcv);
2672 spin_lock_irqsave(&dd->eep_st_lock, flags);
2673 traffic_wds -= dd->traffic_wds;
2674 dd->traffic_wds += traffic_wds;
2675 if (traffic_wds >= QIB_TRAFFIC_ACTIVE_THRESHOLD)
2676 atomic_add(5, &dd->active_time); /* S/B #define */
2677 spin_unlock_irqrestore(&dd->eep_st_lock, flags);
2678
2679 qib_chk_6120_errormask(dd);
2680done:
2681 mod_timer(&dd->stats_timer, jiffies + HZ * ACTIVITY_TIMER);
2682}
2683
2684/* no interrupt fallback for these chips */
2685static int qib_6120_nointr_fallback(struct qib_devdata *dd)
2686{
2687 return 0;
2688}
2689
2690/*
2691 * reset the XGXS (between serdes and IBC). Slightly less intrusive
2692 * than resetting the IBC or external link state, and useful in some
2693 * cases to cause some retraining. To do this right, we reset IBC
2694 * as well.
2695 */
2696static void qib_6120_xgxs_reset(struct qib_pportdata *ppd)
2697{
2698 u64 val, prev_val;
2699 struct qib_devdata *dd = ppd->dd;
2700
2701 prev_val = qib_read_kreg64(dd, kr_xgxs_cfg);
2702 val = prev_val | QLOGIC_IB_XGXS_RESET;
2703 prev_val &= ~QLOGIC_IB_XGXS_RESET; /* be sure */
2704 qib_write_kreg(dd, kr_control,
2705 dd->control & ~QLOGIC_IB_C_LINKENABLE);
2706 qib_write_kreg(dd, kr_xgxs_cfg, val);
2707 qib_read_kreg32(dd, kr_scratch);
2708 qib_write_kreg(dd, kr_xgxs_cfg, prev_val);
2709 qib_write_kreg(dd, kr_control, dd->control);
2710}
2711
2712static int qib_6120_get_ib_cfg(struct qib_pportdata *ppd, int which)
2713{
2714 int ret;
2715
2716 switch (which) {
2717 case QIB_IB_CFG_LWID:
2718 ret = ppd->link_width_active;
2719 break;
2720
2721 case QIB_IB_CFG_SPD:
2722 ret = ppd->link_speed_active;
2723 break;
2724
2725 case QIB_IB_CFG_LWID_ENB:
2726 ret = ppd->link_width_enabled;
2727 break;
2728
2729 case QIB_IB_CFG_SPD_ENB:
2730 ret = ppd->link_speed_enabled;
2731 break;
2732
2733 case QIB_IB_CFG_OP_VLS:
2734 ret = ppd->vls_operational;
2735 break;
2736
2737 case QIB_IB_CFG_VL_HIGH_CAP:
2738 ret = 0;
2739 break;
2740
2741 case QIB_IB_CFG_VL_LOW_CAP:
2742 ret = 0;
2743 break;
2744
2745 case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
2746 ret = SYM_FIELD(ppd->dd->cspec->ibcctrl, IBCCtrl,
2747 OverrunThreshold);
2748 break;
2749
2750 case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
2751 ret = SYM_FIELD(ppd->dd->cspec->ibcctrl, IBCCtrl,
2752 PhyerrThreshold);
2753 break;
2754
2755 case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
2756 /* will only take effect when the link state changes */
2757 ret = (ppd->dd->cspec->ibcctrl &
2758 SYM_MASK(IBCCtrl, LinkDownDefaultState)) ?
2759 IB_LINKINITCMD_SLEEP : IB_LINKINITCMD_POLL;
2760 break;
2761
2762 case QIB_IB_CFG_HRTBT: /* Get Heartbeat off/enable/auto */
2763 ret = 0; /* no heartbeat on this chip */
2764 break;
2765
2766 case QIB_IB_CFG_PMA_TICKS:
2767 ret = 250; /* 1 usec. */
2768 break;
2769
2770 default:
2771 ret = -EINVAL;
2772 break;
2773 }
2774 return ret;
2775}
2776
2777/*
2778 * We assume range checking is already done, if needed.
2779 */
2780static int qib_6120_set_ib_cfg(struct qib_pportdata *ppd, int which, u32 val)
2781{
2782 struct qib_devdata *dd = ppd->dd;
2783 int ret = 0;
2784 u64 val64;
2785 u16 lcmd, licmd;
2786
2787 switch (which) {
2788 case QIB_IB_CFG_LWID_ENB:
2789 ppd->link_width_enabled = val;
2790 break;
2791
2792 case QIB_IB_CFG_SPD_ENB:
2793 ppd->link_speed_enabled = val;
2794 break;
2795
2796 case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
2797 val64 = SYM_FIELD(dd->cspec->ibcctrl, IBCCtrl,
2798 OverrunThreshold);
2799 if (val64 != val) {
2800 dd->cspec->ibcctrl &=
2801 ~SYM_MASK(IBCCtrl, OverrunThreshold);
2802 dd->cspec->ibcctrl |= (u64) val <<
2803 SYM_LSB(IBCCtrl, OverrunThreshold);
2804 qib_write_kreg(dd, kr_ibcctrl, dd->cspec->ibcctrl);
2805 qib_write_kreg(dd, kr_scratch, 0);
2806 }
2807 break;
2808
2809 case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
2810 val64 = SYM_FIELD(dd->cspec->ibcctrl, IBCCtrl,
2811 PhyerrThreshold);
2812 if (val64 != val) {
2813 dd->cspec->ibcctrl &=
2814 ~SYM_MASK(IBCCtrl, PhyerrThreshold);
2815 dd->cspec->ibcctrl |= (u64) val <<
2816 SYM_LSB(IBCCtrl, PhyerrThreshold);
2817 qib_write_kreg(dd, kr_ibcctrl, dd->cspec->ibcctrl);
2818 qib_write_kreg(dd, kr_scratch, 0);
2819 }
2820 break;
2821
2822 case QIB_IB_CFG_PKEYS: /* update pkeys */
2823 val64 = (u64) ppd->pkeys[0] | ((u64) ppd->pkeys[1] << 16) |
2824 ((u64) ppd->pkeys[2] << 32) |
2825 ((u64) ppd->pkeys[3] << 48);
2826 qib_write_kreg(dd, kr_partitionkey, val64);
2827 break;
2828
2829 case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
2830 /* will only take effect when the link state changes */
2831 if (val == IB_LINKINITCMD_POLL)
2832 dd->cspec->ibcctrl &=
2833 ~SYM_MASK(IBCCtrl, LinkDownDefaultState);
2834 else /* SLEEP */
2835 dd->cspec->ibcctrl |=
2836 SYM_MASK(IBCCtrl, LinkDownDefaultState);
2837 qib_write_kreg(dd, kr_ibcctrl, dd->cspec->ibcctrl);
2838 qib_write_kreg(dd, kr_scratch, 0);
2839 break;
2840
2841 case QIB_IB_CFG_MTU: /* update the MTU in IBC */
2842 /*
2843 * Update our housekeeping variables, and set IBC max
2844 * size, same as init code; max IBC is max we allow in
2845 * buffer, less the qword pbc, plus 1 for ICRC, in dwords
2846 * Set even if it's unchanged, print debug message only
2847 * on changes.
2848 */
2849 val = (ppd->ibmaxlen >> 2) + 1;
2850 dd->cspec->ibcctrl &= ~SYM_MASK(IBCCtrl, MaxPktLen);
2851 dd->cspec->ibcctrl |= (u64)val <<
2852 SYM_LSB(IBCCtrl, MaxPktLen);
2853 qib_write_kreg(dd, kr_ibcctrl, dd->cspec->ibcctrl);
2854 qib_write_kreg(dd, kr_scratch, 0);
2855 break;
2856
2857 case QIB_IB_CFG_LSTATE: /* set the IB link state */
2858 switch (val & 0xffff0000) {
2859 case IB_LINKCMD_DOWN:
2860 lcmd = QLOGIC_IB_IBCC_LINKCMD_DOWN;
2861 if (!dd->cspec->ibdeltainprog) {
2862 dd->cspec->ibdeltainprog = 1;
2863 dd->cspec->ibsymsnap =
2864 read_6120_creg32(dd, cr_ibsymbolerr);
2865 dd->cspec->iblnkerrsnap =
2866 read_6120_creg32(dd, cr_iblinkerrrecov);
2867 }
2868 break;
2869
2870 case IB_LINKCMD_ARMED:
2871 lcmd = QLOGIC_IB_IBCC_LINKCMD_ARMED;
2872 break;
2873
2874 case IB_LINKCMD_ACTIVE:
2875 lcmd = QLOGIC_IB_IBCC_LINKCMD_ACTIVE;
2876 break;
2877
2878 default:
2879 ret = -EINVAL;
2880 qib_dev_err(dd, "bad linkcmd req 0x%x\n", val >> 16);
2881 goto bail;
2882 }
2883 switch (val & 0xffff) {
2884 case IB_LINKINITCMD_NOP:
2885 licmd = 0;
2886 break;
2887
2888 case IB_LINKINITCMD_POLL:
2889 licmd = QLOGIC_IB_IBCC_LINKINITCMD_POLL;
2890 break;
2891
2892 case IB_LINKINITCMD_SLEEP:
2893 licmd = QLOGIC_IB_IBCC_LINKINITCMD_SLEEP;
2894 break;
2895
2896 case IB_LINKINITCMD_DISABLE:
2897 licmd = QLOGIC_IB_IBCC_LINKINITCMD_DISABLE;
2898 break;
2899
2900 default:
2901 ret = -EINVAL;
2902 qib_dev_err(dd, "bad linkinitcmd req 0x%x\n",
2903 val & 0xffff);
2904 goto bail;
2905 }
2906 qib_set_ib_6120_lstate(ppd, lcmd, licmd);
2907 goto bail;
2908
2909 case QIB_IB_CFG_HRTBT:
2910 ret = -EINVAL;
2911 break;
2912
2913 default:
2914 ret = -EINVAL;
2915 }
2916bail:
2917 return ret;
2918}
2919
2920static int qib_6120_set_loopback(struct qib_pportdata *ppd, const char *what)
2921{
2922 int ret = 0;
2923 if (!strncmp(what, "ibc", 3)) {
2924 ppd->dd->cspec->ibcctrl |= SYM_MASK(IBCCtrl, Loopback);
2925 qib_devinfo(ppd->dd->pcidev, "Enabling IB%u:%u IBC loopback\n",
2926 ppd->dd->unit, ppd->port);
2927 } else if (!strncmp(what, "off", 3)) {
2928 ppd->dd->cspec->ibcctrl &= ~SYM_MASK(IBCCtrl, Loopback);
2929 qib_devinfo(ppd->dd->pcidev, "Disabling IB%u:%u IBC loopback "
2930 "(normal)\n", ppd->dd->unit, ppd->port);
2931 } else
2932 ret = -EINVAL;
2933 if (!ret) {
2934 qib_write_kreg(ppd->dd, kr_ibcctrl, ppd->dd->cspec->ibcctrl);
2935 qib_write_kreg(ppd->dd, kr_scratch, 0);
2936 }
2937 return ret;
2938}
2939
2940static void pma_6120_timer(unsigned long data)
2941{
2942 struct qib_pportdata *ppd = (struct qib_pportdata *)data;
2943 struct qib_chip_specific *cs = ppd->dd->cspec;
2944 struct qib_ibport *ibp = &ppd->ibport_data;
2945 unsigned long flags;
2946
2947 spin_lock_irqsave(&ibp->lock, flags);
2948 if (cs->pma_sample_status == IB_PMA_SAMPLE_STATUS_STARTED) {
2949 cs->pma_sample_status = IB_PMA_SAMPLE_STATUS_RUNNING;
2950 qib_snapshot_counters(ppd, &cs->sword, &cs->rword,
2951 &cs->spkts, &cs->rpkts, &cs->xmit_wait);
2952 mod_timer(&cs->pma_timer,
2953 jiffies + usecs_to_jiffies(ibp->pma_sample_interval));
2954 } else if (cs->pma_sample_status == IB_PMA_SAMPLE_STATUS_RUNNING) {
2955 u64 ta, tb, tc, td, te;
2956
2957 cs->pma_sample_status = IB_PMA_SAMPLE_STATUS_DONE;
2958 qib_snapshot_counters(ppd, &ta, &tb, &tc, &td, &te);
2959
2960 cs->sword = ta - cs->sword;
2961 cs->rword = tb - cs->rword;
2962 cs->spkts = tc - cs->spkts;
2963 cs->rpkts = td - cs->rpkts;
2964 cs->xmit_wait = te - cs->xmit_wait;
2965 }
2966 spin_unlock_irqrestore(&ibp->lock, flags);
2967}
2968
2969/*
2970 * Note that the caller has the ibp->lock held.
2971 */
2972static void qib_set_cntr_6120_sample(struct qib_pportdata *ppd, u32 intv,
2973 u32 start)
2974{
2975 struct qib_chip_specific *cs = ppd->dd->cspec;
2976
2977 if (start && intv) {
2978 cs->pma_sample_status = IB_PMA_SAMPLE_STATUS_STARTED;
2979 mod_timer(&cs->pma_timer, jiffies + usecs_to_jiffies(start));
2980 } else if (intv) {
2981 cs->pma_sample_status = IB_PMA_SAMPLE_STATUS_RUNNING;
2982 qib_snapshot_counters(ppd, &cs->sword, &cs->rword,
2983 &cs->spkts, &cs->rpkts, &cs->xmit_wait);
2984 mod_timer(&cs->pma_timer, jiffies + usecs_to_jiffies(intv));
2985 } else {
2986 cs->pma_sample_status = IB_PMA_SAMPLE_STATUS_DONE;
2987 cs->sword = 0;
2988 cs->rword = 0;
2989 cs->spkts = 0;
2990 cs->rpkts = 0;
2991 cs->xmit_wait = 0;
2992 }
2993}
2994
2995static u32 qib_6120_iblink_state(u64 ibcs)
2996{
2997 u32 state = (u32)SYM_FIELD(ibcs, IBCStatus, LinkState);
2998
2999 switch (state) {
3000 case IB_6120_L_STATE_INIT:
3001 state = IB_PORT_INIT;
3002 break;
3003 case IB_6120_L_STATE_ARM:
3004 state = IB_PORT_ARMED;
3005 break;
3006 case IB_6120_L_STATE_ACTIVE:
3007 /* fall through */
3008 case IB_6120_L_STATE_ACT_DEFER:
3009 state = IB_PORT_ACTIVE;
3010 break;
3011 default: /* fall through */
3012 case IB_6120_L_STATE_DOWN:
3013 state = IB_PORT_DOWN;
3014 break;
3015 }
3016 return state;
3017}
3018
3019/* returns the IBTA port state, rather than the IBC link training state */
3020static u8 qib_6120_phys_portstate(u64 ibcs)
3021{
3022 u8 state = (u8)SYM_FIELD(ibcs, IBCStatus, LinkTrainingState);
3023 return qib_6120_physportstate[state];
3024}
3025
3026static int qib_6120_ib_updown(struct qib_pportdata *ppd, int ibup, u64 ibcs)
3027{
3028 unsigned long flags;
3029
3030 spin_lock_irqsave(&ppd->lflags_lock, flags);
3031 ppd->lflags &= ~QIBL_IB_FORCE_NOTIFY;
3032 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
3033
3034 if (ibup) {
3035 if (ppd->dd->cspec->ibdeltainprog) {
3036 ppd->dd->cspec->ibdeltainprog = 0;
3037 ppd->dd->cspec->ibsymdelta +=
3038 read_6120_creg32(ppd->dd, cr_ibsymbolerr) -
3039 ppd->dd->cspec->ibsymsnap;
3040 ppd->dd->cspec->iblnkerrdelta +=
3041 read_6120_creg32(ppd->dd, cr_iblinkerrrecov) -
3042 ppd->dd->cspec->iblnkerrsnap;
3043 }
3044 qib_hol_init(ppd);
3045 } else {
3046 ppd->dd->cspec->lli_counter = 0;
3047 if (!ppd->dd->cspec->ibdeltainprog) {
3048 ppd->dd->cspec->ibdeltainprog = 1;
3049 ppd->dd->cspec->ibsymsnap =
3050 read_6120_creg32(ppd->dd, cr_ibsymbolerr);
3051 ppd->dd->cspec->iblnkerrsnap =
3052 read_6120_creg32(ppd->dd, cr_iblinkerrrecov);
3053 }
3054 qib_hol_down(ppd);
3055 }
3056
3057 qib_6120_setup_setextled(ppd, ibup);
3058
3059 return 0;
3060}
3061
3062/* Does read/modify/write to appropriate registers to
3063 * set output and direction bits selected by mask.
3064 * these are in their canonical postions (e.g. lsb of
3065 * dir will end up in D48 of extctrl on existing chips).
3066 * returns contents of GP Inputs.
3067 */
3068static int gpio_6120_mod(struct qib_devdata *dd, u32 out, u32 dir, u32 mask)
3069{
3070 u64 read_val, new_out;
3071 unsigned long flags;
3072
3073 if (mask) {
3074 /* some bits being written, lock access to GPIO */
3075 dir &= mask;
3076 out &= mask;
3077 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
3078 dd->cspec->extctrl &= ~((u64)mask << SYM_LSB(EXTCtrl, GPIOOe));
3079 dd->cspec->extctrl |= ((u64) dir << SYM_LSB(EXTCtrl, GPIOOe));
3080 new_out = (dd->cspec->gpio_out & ~mask) | out;
3081
3082 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
3083 qib_write_kreg(dd, kr_gpio_out, new_out);
3084 dd->cspec->gpio_out = new_out;
3085 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
3086 }
3087 /*
3088 * It is unlikely that a read at this time would get valid
3089 * data on a pin whose direction line was set in the same
3090 * call to this function. We include the read here because
3091 * that allows us to potentially combine a change on one pin with
3092 * a read on another, and because the old code did something like
3093 * this.
3094 */
3095 read_val = qib_read_kreg64(dd, kr_extstatus);
3096 return SYM_FIELD(read_val, EXTStatus, GPIOIn);
3097}
3098
3099/*
3100 * Read fundamental info we need to use the chip. These are
3101 * the registers that describe chip capabilities, and are
3102 * saved in shadow registers.
3103 */
3104static void get_6120_chip_params(struct qib_devdata *dd)
3105{
3106 u64 val;
3107 u32 piobufs;
3108 int mtu;
3109
3110 dd->uregbase = qib_read_kreg32(dd, kr_userregbase);
3111
3112 dd->rcvtidcnt = qib_read_kreg32(dd, kr_rcvtidcnt);
3113 dd->rcvtidbase = qib_read_kreg32(dd, kr_rcvtidbase);
3114 dd->rcvegrbase = qib_read_kreg32(dd, kr_rcvegrbase);
3115 dd->palign = qib_read_kreg32(dd, kr_palign);
3116 dd->piobufbase = qib_read_kreg64(dd, kr_sendpiobufbase);
3117 dd->pio2k_bufbase = dd->piobufbase & 0xffffffff;
3118
3119 dd->rcvhdrcnt = qib_read_kreg32(dd, kr_rcvegrcnt);
3120
3121 val = qib_read_kreg64(dd, kr_sendpiosize);
3122 dd->piosize2k = val & ~0U;
3123 dd->piosize4k = val >> 32;
3124
3125 mtu = ib_mtu_enum_to_int(qib_ibmtu);
3126 if (mtu == -1)
3127 mtu = QIB_DEFAULT_MTU;
3128 dd->pport->ibmtu = (u32)mtu;
3129
3130 val = qib_read_kreg64(dd, kr_sendpiobufcnt);
3131 dd->piobcnt2k = val & ~0U;
3132 dd->piobcnt4k = val >> 32;
3133 /* these may be adjusted in init_chip_wc_pat() */
3134 dd->pio2kbase = (u32 __iomem *)
3135 (((char __iomem *)dd->kregbase) + dd->pio2k_bufbase);
3136 if (dd->piobcnt4k) {
3137 dd->pio4kbase = (u32 __iomem *)
3138 (((char __iomem *) dd->kregbase) +
3139 (dd->piobufbase >> 32));
3140 /*
3141 * 4K buffers take 2 pages; we use roundup just to be
3142 * paranoid; we calculate it once here, rather than on
3143 * ever buf allocate
3144 */
3145 dd->align4k = ALIGN(dd->piosize4k, dd->palign);
3146 }
3147
3148 piobufs = dd->piobcnt4k + dd->piobcnt2k;
3149
3150 dd->pioavregs = ALIGN(piobufs, sizeof(u64) * BITS_PER_BYTE / 2) /
3151 (sizeof(u64) * BITS_PER_BYTE / 2);
3152}
3153
3154/*
3155 * The chip base addresses in cspec and cpspec have to be set
3156 * after possible init_chip_wc_pat(), rather than in
3157 * get_6120_chip_params(), so split out as separate function
3158 */
3159static void set_6120_baseaddrs(struct qib_devdata *dd)
3160{
3161 u32 cregbase;
3162 cregbase = qib_read_kreg32(dd, kr_counterregbase);
3163 dd->cspec->cregbase = (u64 __iomem *)
3164 ((char __iomem *) dd->kregbase + cregbase);
3165
3166 dd->egrtidbase = (u64 __iomem *)
3167 ((char __iomem *) dd->kregbase + dd->rcvegrbase);
3168}
3169
3170/*
3171 * Write the final few registers that depend on some of the
3172 * init setup. Done late in init, just before bringing up
3173 * the serdes.
3174 */
3175static int qib_late_6120_initreg(struct qib_devdata *dd)
3176{
3177 int ret = 0;
3178 u64 val;
3179
3180 qib_write_kreg(dd, kr_rcvhdrentsize, dd->rcvhdrentsize);
3181 qib_write_kreg(dd, kr_rcvhdrsize, dd->rcvhdrsize);
3182 qib_write_kreg(dd, kr_rcvhdrcnt, dd->rcvhdrcnt);
3183 qib_write_kreg(dd, kr_sendpioavailaddr, dd->pioavailregs_phys);
3184 val = qib_read_kreg64(dd, kr_sendpioavailaddr);
3185 if (val != dd->pioavailregs_phys) {
3186 qib_dev_err(dd, "Catastrophic software error, "
3187 "SendPIOAvailAddr written as %lx, "
3188 "read back as %llx\n",
3189 (unsigned long) dd->pioavailregs_phys,
3190 (unsigned long long) val);
3191 ret = -EINVAL;
3192 }
3193 return ret;
3194}
3195
3196static int init_6120_variables(struct qib_devdata *dd)
3197{
3198 int ret = 0;
3199 struct qib_pportdata *ppd;
3200 u32 sbufs;
3201
3202 ppd = (struct qib_pportdata *)(dd + 1);
3203 dd->pport = ppd;
3204 dd->num_pports = 1;
3205
3206 dd->cspec = (struct qib_chip_specific *)(ppd + dd->num_pports);
3207 ppd->cpspec = NULL; /* not used in this chip */
3208
3209 spin_lock_init(&dd->cspec->kernel_tid_lock);
3210 spin_lock_init(&dd->cspec->user_tid_lock);
3211 spin_lock_init(&dd->cspec->rcvmod_lock);
3212 spin_lock_init(&dd->cspec->gpio_lock);
3213
3214 /* we haven't yet set QIB_PRESENT, so use read directly */
3215 dd->revision = readq(&dd->kregbase[kr_revision]);
3216
3217 if ((dd->revision & 0xffffffffU) == 0xffffffffU) {
3218 qib_dev_err(dd, "Revision register read failure, "
3219 "giving up initialization\n");
3220 ret = -ENODEV;
3221 goto bail;
3222 }
3223 dd->flags |= QIB_PRESENT; /* now register routines work */
3224
3225 dd->majrev = (u8) SYM_FIELD(dd->revision, Revision_R,
3226 ChipRevMajor);
3227 dd->minrev = (u8) SYM_FIELD(dd->revision, Revision_R,
3228 ChipRevMinor);
3229
3230 get_6120_chip_params(dd);
3231 pe_boardname(dd); /* fill in boardname */
3232
3233 /*
3234 * GPIO bits for TWSI data and clock,
3235 * used for serial EEPROM.
3236 */
3237 dd->gpio_sda_num = _QIB_GPIO_SDA_NUM;
3238 dd->gpio_scl_num = _QIB_GPIO_SCL_NUM;
3239 dd->twsi_eeprom_dev = QIB_TWSI_NO_DEV;
3240
3241 if (qib_unordered_wc())
3242 dd->flags |= QIB_PIO_FLUSH_WC;
3243
3244 /*
3245 * EEPROM error log 0 is TXE Parity errors. 1 is RXE Parity.
3246 * 2 is Some Misc, 3 is reserved for future.
3247 */
3248 dd->eep_st_masks[0].hwerrs_to_log = HWE_MASK(TXEMemParityErr);
3249
3250 /* Ignore errors in PIO/PBC on systems with unordered write-combining */
3251 if (qib_unordered_wc())
3252 dd->eep_st_masks[0].hwerrs_to_log &= ~TXE_PIO_PARITY;
3253
3254 dd->eep_st_masks[1].hwerrs_to_log = HWE_MASK(RXEMemParityErr);
3255
3256 dd->eep_st_masks[2].errs_to_log = ERR_MASK(ResetNegated);
3257
3258 qib_init_pportdata(ppd, dd, 0, 1);
3259 ppd->link_width_supported = IB_WIDTH_1X | IB_WIDTH_4X;
3260 ppd->link_speed_supported = QIB_IB_SDR;
3261 ppd->link_width_enabled = IB_WIDTH_4X;
3262 ppd->link_speed_enabled = ppd->link_speed_supported;
3263 /* these can't change for this chip, so set once */
3264 ppd->link_width_active = ppd->link_width_enabled;
3265 ppd->link_speed_active = ppd->link_speed_enabled;
3266 ppd->vls_supported = IB_VL_VL0;
3267 ppd->vls_operational = ppd->vls_supported;
3268
3269 dd->rcvhdrentsize = QIB_RCVHDR_ENTSIZE;
3270 dd->rcvhdrsize = QIB_DFLT_RCVHDRSIZE;
3271 dd->rhf_offset = 0;
3272
3273 /* we always allocate at least 2048 bytes for eager buffers */
3274 ret = ib_mtu_enum_to_int(qib_ibmtu);
3275 dd->rcvegrbufsize = ret != -1 ? max(ret, 2048) : QIB_DEFAULT_MTU;
3276
3277 qib_6120_tidtemplate(dd);
3278
3279 /*
3280 * We can request a receive interrupt for 1 or
3281 * more packets from current offset. For now, we set this
3282 * up for a single packet.
3283 */
3284 dd->rhdrhead_intr_off = 1ULL << 32;
3285
3286 /* setup the stats timer; the add_timer is done at end of init */
3287 init_timer(&dd->stats_timer);
3288 dd->stats_timer.function = qib_get_6120_faststats;
3289 dd->stats_timer.data = (unsigned long) dd;
3290
3291 init_timer(&dd->cspec->pma_timer);
3292 dd->cspec->pma_timer.function = pma_6120_timer;
3293 dd->cspec->pma_timer.data = (unsigned long) ppd;
3294
3295 dd->ureg_align = qib_read_kreg32(dd, kr_palign);
3296
3297 dd->piosize2kmax_dwords = dd->piosize2k >> 2;
3298 qib_6120_config_ctxts(dd);
3299 qib_set_ctxtcnt(dd);
3300
3301 if (qib_wc_pat) {
3302 ret = init_chip_wc_pat(dd, 0);
3303 if (ret)
3304 goto bail;
3305 }
3306 set_6120_baseaddrs(dd); /* set chip access pointers now */
3307
3308 ret = 0;
3309 if (qib_mini_init)
3310 goto bail;
3311
3312 qib_num_cfg_vls = 1; /* if any 6120's, only one VL */
3313
3314 ret = qib_create_ctxts(dd);
3315 init_6120_cntrnames(dd);
3316
3317 /* use all of 4KB buffers for the kernel, otherwise 16 */
3318 sbufs = dd->piobcnt4k ? dd->piobcnt4k : 16;
3319
3320 dd->lastctxt_piobuf = dd->piobcnt2k + dd->piobcnt4k - sbufs;
3321 dd->pbufsctxt = dd->lastctxt_piobuf /
3322 (dd->cfgctxts - dd->first_user_ctxt);
3323
3324 if (ret)
3325 goto bail;
3326bail:
3327 return ret;
3328}
3329
3330/*
3331 * For this chip, we want to use the same buffer every time
3332 * when we are trying to bring the link up (they are always VL15
3333 * packets). At that link state the packet should always go out immediately
3334 * (or at least be discarded at the tx interface if the link is down).
3335 * If it doesn't, and the buffer isn't available, that means some other
3336 * sender has gotten ahead of us, and is preventing our packet from going
3337 * out. In that case, we flush all packets, and try again. If that still
3338 * fails, we fail the request, and hope things work the next time around.
3339 *
3340 * We don't need very complicated heuristics on whether the packet had
3341 * time to go out or not, since even at SDR 1X, it goes out in very short
3342 * time periods, covered by the chip reads done here and as part of the
3343 * flush.
3344 */
3345static u32 __iomem *get_6120_link_buf(struct qib_pportdata *ppd, u32 *bnum)
3346{
3347 u32 __iomem *buf;
3348 u32 lbuf = ppd->dd->piobcnt2k + ppd->dd->piobcnt4k - 1;
3349
3350 /*
3351 * always blip to get avail list updated, since it's almost
3352 * always needed, and is fairly cheap.
3353 */
3354 sendctrl_6120_mod(ppd->dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
3355 qib_read_kreg64(ppd->dd, kr_scratch); /* extra chip flush */
3356 buf = qib_getsendbuf_range(ppd->dd, bnum, lbuf, lbuf);
3357 if (buf)
3358 goto done;
3359
3360 sendctrl_6120_mod(ppd, QIB_SENDCTRL_DISARM_ALL | QIB_SENDCTRL_FLUSH |
3361 QIB_SENDCTRL_AVAIL_BLIP);
3362 ppd->dd->upd_pio_shadow = 1; /* update our idea of what's busy */
3363 qib_read_kreg64(ppd->dd, kr_scratch); /* extra chip flush */
3364 buf = qib_getsendbuf_range(ppd->dd, bnum, lbuf, lbuf);
3365done:
3366 return buf;
3367}
3368
3369static u32 __iomem *qib_6120_getsendbuf(struct qib_pportdata *ppd, u64 pbc,
3370 u32 *pbufnum)
3371{
3372 u32 first, last, plen = pbc & QIB_PBC_LENGTH_MASK;
3373 struct qib_devdata *dd = ppd->dd;
3374 u32 __iomem *buf;
3375
3376 if (((pbc >> 32) & PBC_6120_VL15_SEND_CTRL) &&
3377 !(ppd->lflags & (QIBL_IB_AUTONEG_INPROG | QIBL_LINKACTIVE)))
3378 buf = get_6120_link_buf(ppd, pbufnum);
3379 else {
3380
3381 if ((plen + 1) > dd->piosize2kmax_dwords)
3382 first = dd->piobcnt2k;
3383 else
3384 first = 0;
3385 /* try 4k if all 2k busy, so same last for both sizes */
3386 last = dd->piobcnt2k + dd->piobcnt4k - 1;
3387 buf = qib_getsendbuf_range(dd, pbufnum, first, last);
3388 }
3389 return buf;
3390}
3391
3392static int init_sdma_6120_regs(struct qib_pportdata *ppd)
3393{
3394 return -ENODEV;
3395}
3396
3397static u16 qib_sdma_6120_gethead(struct qib_pportdata *ppd)
3398{
3399 return 0;
3400}
3401
3402static int qib_sdma_6120_busy(struct qib_pportdata *ppd)
3403{
3404 return 0;
3405}
3406
3407static void qib_sdma_update_6120_tail(struct qib_pportdata *ppd, u16 tail)
3408{
3409}
3410
3411static void qib_6120_sdma_sendctrl(struct qib_pportdata *ppd, unsigned op)
3412{
3413}
3414
3415static void qib_sdma_set_6120_desc_cnt(struct qib_pportdata *ppd, unsigned cnt)
3416{
3417}
3418
3419/*
3420 * the pbc doesn't need a VL15 indicator, but we need it for link_buf.
3421 * The chip ignores the bit if set.
3422 */
3423static u32 qib_6120_setpbc_control(struct qib_pportdata *ppd, u32 plen,
3424 u8 srate, u8 vl)
3425{
3426 return vl == 15 ? PBC_6120_VL15_SEND_CTRL : 0;
3427}
3428
3429static void qib_6120_initvl15_bufs(struct qib_devdata *dd)
3430{
3431}
3432
3433static void qib_6120_init_ctxt(struct qib_ctxtdata *rcd)
3434{
3435 rcd->rcvegrcnt = rcd->dd->rcvhdrcnt;
3436 rcd->rcvegr_tid_base = rcd->ctxt * rcd->rcvegrcnt;
3437}
3438
3439static void qib_6120_txchk_change(struct qib_devdata *dd, u32 start,
3440 u32 len, u32 avail, struct qib_ctxtdata *rcd)
3441{
3442}
3443
3444static void writescratch(struct qib_devdata *dd, u32 val)
3445{
3446 (void) qib_write_kreg(dd, kr_scratch, val);
3447}
3448
3449static int qib_6120_tempsense_rd(struct qib_devdata *dd, int regnum)
3450{
3451 return -ENXIO;
3452}
3453
3454/* Dummy function, as 6120 boards never disable EEPROM Write */
3455static int qib_6120_eeprom_wen(struct qib_devdata *dd, int wen)
3456{
3457 return 1;
3458}
3459
3460/**
3461 * qib_init_iba6120_funcs - set up the chip-specific function pointers
3462 * @pdev: pci_dev of the qlogic_ib device
3463 * @ent: pci_device_id matching this chip
3464 *
3465 * This is global, and is called directly at init to set up the
3466 * chip-specific function pointers for later use.
3467 *
3468 * It also allocates/partially-inits the qib_devdata struct for
3469 * this device.
3470 */
3471struct qib_devdata *qib_init_iba6120_funcs(struct pci_dev *pdev,
3472 const struct pci_device_id *ent)
3473{
3474 struct qib_devdata *dd;
3475 int ret;
3476
f931551b
RC		 3477 dd = qib_alloc_devdata(pdev, sizeof(struct qib_pportdata) +
3478 sizeof(struct qib_chip_specific));
3479 if (IS_ERR(dd))
3480 goto bail;
3481
3482 dd->f_bringup_serdes = qib_6120_bringup_serdes;
3483 dd->f_cleanup = qib_6120_setup_cleanup;
3484 dd->f_clear_tids = qib_6120_clear_tids;
3485 dd->f_free_irq = qib_6120_free_irq;
3486 dd->f_get_base_info = qib_6120_get_base_info;
3487 dd->f_get_msgheader = qib_6120_get_msgheader;
3488 dd->f_getsendbuf = qib_6120_getsendbuf;
3489 dd->f_gpio_mod = gpio_6120_mod;
3490 dd->f_eeprom_wen = qib_6120_eeprom_wen;
3491 dd->f_hdrqempty = qib_6120_hdrqempty;
3492 dd->f_ib_updown = qib_6120_ib_updown;
3493 dd->f_init_ctxt = qib_6120_init_ctxt;
3494 dd->f_initvl15_bufs = qib_6120_initvl15_bufs;
3495 dd->f_intr_fallback = qib_6120_nointr_fallback;
3496 dd->f_late_initreg = qib_late_6120_initreg;
3497 dd->f_setpbc_control = qib_6120_setpbc_control;
3498 dd->f_portcntr = qib_portcntr_6120;
3499 dd->f_put_tid = (dd->minrev >= 2) ?
3500 qib_6120_put_tid_2 :
3501 qib_6120_put_tid;
3502 dd->f_quiet_serdes = qib_6120_quiet_serdes;
3503 dd->f_rcvctrl = rcvctrl_6120_mod;
3504 dd->f_read_cntrs = qib_read_6120cntrs;
3505 dd->f_read_portcntrs = qib_read_6120portcntrs;
3506 dd->f_reset = qib_6120_setup_reset;
3507 dd->f_init_sdma_regs = init_sdma_6120_regs;
3508 dd->f_sdma_busy = qib_sdma_6120_busy;
3509 dd->f_sdma_gethead = qib_sdma_6120_gethead;
3510 dd->f_sdma_sendctrl = qib_6120_sdma_sendctrl;
3511 dd->f_sdma_set_desc_cnt = qib_sdma_set_6120_desc_cnt;
3512 dd->f_sdma_update_tail = qib_sdma_update_6120_tail;
3513 dd->f_sendctrl = sendctrl_6120_mod;
3514 dd->f_set_armlaunch = qib_set_6120_armlaunch;
3515 dd->f_set_cntr_sample = qib_set_cntr_6120_sample;
3516 dd->f_iblink_state = qib_6120_iblink_state;
3517 dd->f_ibphys_portstate = qib_6120_phys_portstate;
3518 dd->f_get_ib_cfg = qib_6120_get_ib_cfg;
3519 dd->f_set_ib_cfg = qib_6120_set_ib_cfg;
3520 dd->f_set_ib_loopback = qib_6120_set_loopback;
3521 dd->f_set_intr_state = qib_6120_set_intr_state;
3522 dd->f_setextled = qib_6120_setup_setextled;
3523 dd->f_txchk_change = qib_6120_txchk_change;
3524 dd->f_update_usrhead = qib_update_6120_usrhead;
3525 dd->f_wantpiobuf_intr = qib_wantpiobuf_6120_intr;
3526 dd->f_xgxs_reset = qib_6120_xgxs_reset;
3527 dd->f_writescratch = writescratch;
3528 dd->f_tempsense_rd = qib_6120_tempsense_rd;
3529 /*
3530 * Do remaining pcie setup and save pcie values in dd.
3531 * Any error printing is already done by the init code.
3532 * On return, we have the chip mapped and accessible,
3533 * but chip registers are not set up until start of
3534 * init_6120_variables.
3535 */
3536 ret = qib_pcie_ddinit(dd, pdev, ent);
3537 if (ret < 0)
3538 goto bail_free;
3539
3540 /* initialize chip-specific variables */
3541 ret = init_6120_variables(dd);
3542 if (ret)
3543 goto bail_cleanup;
3544
3545 if (qib_mini_init)
3546 goto bail;
3547
f931551b
RC		 3548 if (qib_pcie_params(dd, 8, NULL, NULL))
3549 qib_dev_err(dd, "Failed to setup PCIe or interrupts; "
3550 "continuing anyway\n");
3551 dd->cspec->irq = pdev->irq; /* save IRQ */
3552
3553 /* clear diagctrl register, in case diags were running and crashed */
3554 qib_write_kreg(dd, kr_hwdiagctrl, 0);
3555
3556 if (qib_read_kreg64(dd, kr_hwerrstatus) &
3557 QLOGIC_IB_HWE_SERDESPLLFAILED)
3558 qib_write_kreg(dd, kr_hwerrclear,
3559 QLOGIC_IB_HWE_SERDESPLLFAILED);
3560
3561 /* setup interrupt handler (interrupt type handled above) */
3562 qib_setup_6120_interrupt(dd);
3563 /* Note that qpn_mask is set by qib_6120_config_ctxts() first */
3564 qib_6120_init_hwerrors(dd);
3565
3566 goto bail;
3567
3568bail_cleanup:
3569 qib_pcie_ddcleanup(dd);
3570bail_free:
3571 qib_free_devdata(dd);
3572 dd = ERR_PTR(ret);
3573bail:
3574 return dd;
3575}
kernel source for telekom puls (alcatel/mediatek)