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097709fe | 1 | /* |
87427da5 | 2 | * Copyright (c) 2006, 2007 QLogic Corporation. All rights reserved. |
097709fe BS |
3 | * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved. |
4 | * | |
5 | * This software is available to you under a choice of one of two | |
6 | * licenses. You may choose to be licensed under the terms of the GNU | |
7 | * General Public License (GPL) Version 2, available from the file | |
8 | * COPYING in the main directory of this source tree, or the | |
9 | * OpenIB.org BSD license below: | |
10 | * | |
11 | * Redistribution and use in source and binary forms, with or | |
12 | * without modification, are permitted provided that the following | |
13 | * conditions are met: | |
14 | * | |
15 | * - Redistributions of source code must retain the above | |
16 | * copyright notice, this list of conditions and the following | |
17 | * disclaimer. | |
18 | * | |
19 | * - Redistributions in binary form must reproduce the above | |
20 | * copyright notice, this list of conditions and the following | |
21 | * disclaimer in the documentation and/or other materials | |
22 | * provided with the distribution. | |
23 | * | |
24 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
25 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
26 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
27 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
28 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
29 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
30 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
31 | * SOFTWARE. | |
32 | */ | |
33 | ||
34 | #include <linux/pci.h> | |
35 | #include <linux/netdevice.h> | |
36 | #include <linux/vmalloc.h> | |
37 | ||
38 | #include "ipath_kernel.h" | |
27b678dd | 39 | #include "ipath_common.h" |
097709fe BS |
40 | |
41 | /* | |
42 | * min buffers we want to have per port, after driver | |
43 | */ | |
44 | #define IPATH_MIN_USER_PORT_BUFCNT 8 | |
45 | ||
46 | /* | |
47 | * Number of ports we are configured to use (to allow for more pio | |
48 | * buffers per port, etc.) Zero means use chip value. | |
49 | */ | |
50 | static ushort ipath_cfgports; | |
51 | ||
52 | module_param_named(cfgports, ipath_cfgports, ushort, S_IRUGO); | |
53 | MODULE_PARM_DESC(cfgports, "Set max number of ports to use"); | |
54 | ||
55 | /* | |
0fd41363 BS |
56 | * Number of buffers reserved for driver (verbs and layered drivers.) |
57 | * Reserved at end of buffer list. Initialized based on | |
52e7fad8 BS |
58 | * number of PIO buffers if not set via module interface. |
59 | * The problem with this is that it's global, but we'll use different | |
60 | * numbers for different chip types. So the default value is not | |
61 | * very useful. I've redefined it for the 1.3 release so that it's | |
62 | * zero unless set by the user to something else, in which case we | |
63 | * try to respect it. | |
097709fe | 64 | */ |
52e7fad8 | 65 | static ushort ipath_kpiobufs; |
097709fe BS |
66 | |
67 | static int ipath_set_kpiobufs(const char *val, struct kernel_param *kp); | |
68 | ||
52e7fad8 | 69 | module_param_call(kpiobufs, ipath_set_kpiobufs, param_get_ushort, |
097709fe BS |
70 | &ipath_kpiobufs, S_IWUSR | S_IRUGO); |
71 | MODULE_PARM_DESC(kpiobufs, "Set number of PIO buffers for driver"); | |
72 | ||
73 | /** | |
74 | * create_port0_egr - allocate the eager TID buffers | |
75 | * @dd: the infinipath device | |
76 | * | |
77 | * This code is now quite different for user and kernel, because | |
78 | * the kernel uses skb's, for the accelerated network performance. | |
79 | * This is the kernel (port0) version. | |
80 | * | |
81 | * Allocate the eager TID buffers and program them into infinipath. | |
82 | * We use the network layer alloc_skb() allocator to allocate the | |
0fd41363 | 83 | * memory, and either use the buffers as is for things like verbs |
097709fe BS |
84 | * packets, or pass the buffers up to the ipath layered driver and |
85 | * thence the network layer, replacing them as we do so (see | |
86 | * ipath_rcv_layer()). | |
87 | */ | |
88 | static int create_port0_egr(struct ipath_devdata *dd) | |
89 | { | |
90 | unsigned e, egrcnt; | |
1fd3b40f | 91 | struct ipath_skbinfo *skbinfo; |
097709fe BS |
92 | int ret; |
93 | ||
60948a41 | 94 | egrcnt = dd->ipath_p0_rcvegrcnt; |
097709fe | 95 | |
1fd3b40f BS |
96 | skbinfo = vmalloc(sizeof(*dd->ipath_port0_skbinfo) * egrcnt); |
97 | if (skbinfo == NULL) { | |
097709fe BS |
98 | ipath_dev_err(dd, "allocation error for eager TID " |
99 | "skb array\n"); | |
100 | ret = -ENOMEM; | |
101 | goto bail; | |
102 | } | |
103 | for (e = 0; e < egrcnt; e++) { | |
104 | /* | |
105 | * This is a bit tricky in that we allocate extra | |
106 | * space for 2 bytes of the 14 byte ethernet header. | |
107 | * These two bytes are passed in the ipath header so | |
108 | * the rest of the data is word aligned. We allocate | |
109 | * 4 bytes so that the data buffer stays word aligned. | |
110 | * See ipath_kreceive() for more details. | |
111 | */ | |
1fd3b40f BS |
112 | skbinfo[e].skb = ipath_alloc_skb(dd, GFP_KERNEL); |
113 | if (!skbinfo[e].skb) { | |
097709fe BS |
114 | ipath_dev_err(dd, "SKB allocation error for " |
115 | "eager TID %u\n", e); | |
116 | while (e != 0) | |
1fd3b40f BS |
117 | dev_kfree_skb(skbinfo[--e].skb); |
118 | vfree(skbinfo); | |
097709fe BS |
119 | ret = -ENOMEM; |
120 | goto bail; | |
121 | } | |
122 | } | |
123 | /* | |
124 | * After loop above, so we can test non-NULL to see if ready | |
125 | * to use at receive, etc. | |
126 | */ | |
1fd3b40f | 127 | dd->ipath_port0_skbinfo = skbinfo; |
097709fe BS |
128 | |
129 | for (e = 0; e < egrcnt; e++) { | |
1fd3b40f BS |
130 | dd->ipath_port0_skbinfo[e].phys = |
131 | ipath_map_single(dd->pcidev, | |
132 | dd->ipath_port0_skbinfo[e].skb->data, | |
133 | dd->ipath_ibmaxlen, PCI_DMA_FROMDEVICE); | |
097709fe BS |
134 | dd->ipath_f_put_tid(dd, e + (u64 __iomem *) |
135 | ((char __iomem *) dd->ipath_kregbase + | |
f716cdfe JE |
136 | dd->ipath_rcvegrbase), |
137 | RCVHQ_RCV_TYPE_EAGER, | |
1fd3b40f | 138 | dd->ipath_port0_skbinfo[e].phys); |
097709fe BS |
139 | } |
140 | ||
141 | ret = 0; | |
142 | ||
143 | bail: | |
144 | return ret; | |
145 | } | |
146 | ||
147 | static int bringup_link(struct ipath_devdata *dd) | |
148 | { | |
149 | u64 val, ibc; | |
150 | int ret = 0; | |
151 | ||
152 | /* hold IBC in reset */ | |
153 | dd->ipath_control &= ~INFINIPATH_C_LINKENABLE; | |
154 | ipath_write_kreg(dd, dd->ipath_kregs->kr_control, | |
155 | dd->ipath_control); | |
156 | ||
157 | /* | |
826d8010 DO |
158 | * set initial max size pkt IBC will send, including ICRC; it's the |
159 | * PIO buffer size in dwords, less 1; also see ipath_set_mtu() | |
097709fe | 160 | */ |
826d8010 DO |
161 | val = (dd->ipath_ibmaxlen >> 2) + 1; |
162 | ibc = val << dd->ibcc_mpl_shift; | |
097709fe | 163 | |
826d8010 | 164 | /* flowcontrolwatermark is in units of KBytes */ |
097709fe BS |
165 | ibc |= 0x5ULL << INFINIPATH_IBCC_FLOWCTRLWATERMARK_SHIFT; |
166 | /* | |
167 | * How often flowctrl sent. More or less in usecs; balance against | |
168 | * watermark value, so that in theory senders always get a flow | |
169 | * control update in time to not let the IB link go idle. | |
170 | */ | |
171 | ibc |= 0x3ULL << INFINIPATH_IBCC_FLOWCTRLPERIOD_SHIFT; | |
172 | /* max error tolerance */ | |
173 | ibc |= 0xfULL << INFINIPATH_IBCC_PHYERRTHRESHOLD_SHIFT; | |
174 | /* use "real" buffer space for */ | |
175 | ibc |= 4ULL << INFINIPATH_IBCC_CREDITSCALE_SHIFT; | |
176 | /* IB credit flow control. */ | |
177 | ibc |= 0xfULL << INFINIPATH_IBCC_OVERRUNTHRESHOLD_SHIFT; | |
178 | /* initially come up waiting for TS1, without sending anything. */ | |
179 | dd->ipath_ibcctrl = ibc; | |
180 | /* | |
181 | * Want to start out with both LINKCMD and LINKINITCMD in NOP | |
182 | * (0 and 0). Don't put linkinitcmd in ipath_ibcctrl, want that | |
4330e4da MA |
183 | * to stay a NOP. Flag that we are disabled, for the (unlikely) |
184 | * case that some recovery path is trying to bring the link up | |
185 | * before we are ready. | |
097709fe BS |
186 | */ |
187 | ibc |= INFINIPATH_IBCC_LINKINITCMD_DISABLE << | |
188 | INFINIPATH_IBCC_LINKINITCMD_SHIFT; | |
4330e4da | 189 | dd->ipath_flags |= IPATH_IB_LINK_DISABLED; |
097709fe BS |
190 | ipath_cdbg(VERBOSE, "Writing 0x%llx to ibcctrl\n", |
191 | (unsigned long long) ibc); | |
192 | ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl, ibc); | |
193 | ||
194 | // be sure chip saw it | |
195 | val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch); | |
196 | ||
197 | ret = dd->ipath_f_bringup_serdes(dd); | |
198 | ||
199 | if (ret) | |
200 | dev_info(&dd->pcidev->dev, "Could not initialize SerDes, " | |
201 | "not usable\n"); | |
202 | else { | |
203 | /* enable IBC */ | |
204 | dd->ipath_control |= INFINIPATH_C_LINKENABLE; | |
205 | ipath_write_kreg(dd, dd->ipath_kregs->kr_control, | |
206 | dd->ipath_control); | |
207 | } | |
208 | ||
209 | return ret; | |
210 | } | |
211 | ||
27b044a8 MA |
212 | static struct ipath_portdata *create_portdata0(struct ipath_devdata *dd) |
213 | { | |
214 | struct ipath_portdata *pd = NULL; | |
215 | ||
216 | pd = kzalloc(sizeof(*pd), GFP_KERNEL); | |
217 | if (pd) { | |
218 | pd->port_dd = dd; | |
219 | pd->port_cnt = 1; | |
220 | /* The port 0 pkey table is used by the layer interface. */ | |
221 | pd->port_pkeys[0] = IPATH_DEFAULT_P_KEY; | |
9355fb6a | 222 | pd->port_seq_cnt = 1; |
27b044a8 MA |
223 | } |
224 | return pd; | |
225 | } | |
226 | ||
9355fb6a | 227 | static int init_chip_first(struct ipath_devdata *dd) |
097709fe | 228 | { |
9355fb6a | 229 | struct ipath_portdata *pd; |
097709fe BS |
230 | int ret = 0; |
231 | u64 val; | |
232 | ||
233 | /* | |
234 | * skip cfgports stuff because we are not allocating memory, | |
235 | * and we don't want problems if the portcnt changed due to | |
236 | * cfgports. We do still check and report a difference, if | |
237 | * not same (should be impossible). | |
238 | */ | |
60948a41 | 239 | dd->ipath_f_config_ports(dd, ipath_cfgports); |
097709fe BS |
240 | if (!ipath_cfgports) |
241 | dd->ipath_cfgports = dd->ipath_portcnt; | |
242 | else if (ipath_cfgports <= dd->ipath_portcnt) { | |
243 | dd->ipath_cfgports = ipath_cfgports; | |
244 | ipath_dbg("Configured to use %u ports out of %u in chip\n", | |
9355fb6a RC |
245 | dd->ipath_cfgports, ipath_read_kreg32(dd, |
246 | dd->ipath_kregs->kr_portcnt)); | |
097709fe BS |
247 | } else { |
248 | dd->ipath_cfgports = dd->ipath_portcnt; | |
249 | ipath_dbg("Tried to configured to use %u ports; chip " | |
250 | "only supports %u\n", ipath_cfgports, | |
9355fb6a RC |
251 | ipath_read_kreg32(dd, |
252 | dd->ipath_kregs->kr_portcnt)); | |
097709fe | 253 | } |
8e280d94 BS |
254 | /* |
255 | * Allocate full portcnt array, rather than just cfgports, because | |
256 | * cleanup iterates across all possible ports. | |
257 | */ | |
258 | dd->ipath_pd = kzalloc(sizeof(*dd->ipath_pd) * dd->ipath_portcnt, | |
097709fe BS |
259 | GFP_KERNEL); |
260 | ||
261 | if (!dd->ipath_pd) { | |
262 | ipath_dev_err(dd, "Unable to allocate portdata array, " | |
263 | "failing\n"); | |
264 | ret = -ENOMEM; | |
265 | goto done; | |
266 | } | |
267 | ||
27b044a8 | 268 | pd = create_portdata0(dd); |
27b044a8 | 269 | if (!pd) { |
097709fe BS |
270 | ipath_dev_err(dd, "Unable to allocate portdata for port " |
271 | "0, failing\n"); | |
272 | ret = -ENOMEM; | |
273 | goto done; | |
274 | } | |
27b044a8 MA |
275 | dd->ipath_pd[0] = pd; |
276 | ||
097709fe BS |
277 | dd->ipath_rcvtidcnt = |
278 | ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidcnt); | |
279 | dd->ipath_rcvtidbase = | |
280 | ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidbase); | |
281 | dd->ipath_rcvegrcnt = | |
282 | ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt); | |
283 | dd->ipath_rcvegrbase = | |
284 | ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrbase); | |
285 | dd->ipath_palign = | |
286 | ipath_read_kreg32(dd, dd->ipath_kregs->kr_pagealign); | |
287 | dd->ipath_piobufbase = | |
288 | ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiobufbase); | |
289 | val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiosize); | |
290 | dd->ipath_piosize2k = val & ~0U; | |
291 | dd->ipath_piosize4k = val >> 32; | |
826d8010 DO |
292 | if (dd->ipath_piosize4k == 0 && ipath_mtu4096) |
293 | ipath_mtu4096 = 0; /* 4KB not supported by this chip */ | |
294 | dd->ipath_ibmtu = ipath_mtu4096 ? 4096 : 2048; | |
097709fe BS |
295 | val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiobufcnt); |
296 | dd->ipath_piobcnt2k = val & ~0U; | |
297 | dd->ipath_piobcnt4k = val >> 32; | |
298 | dd->ipath_pio2kbase = | |
299 | (u32 __iomem *) (((char __iomem *) dd->ipath_kregbase) + | |
300 | (dd->ipath_piobufbase & 0xffffffff)); | |
301 | if (dd->ipath_piobcnt4k) { | |
302 | dd->ipath_pio4kbase = (u32 __iomem *) | |
303 | (((char __iomem *) dd->ipath_kregbase) + | |
304 | (dd->ipath_piobufbase >> 32)); | |
305 | /* | |
306 | * 4K buffers take 2 pages; we use roundup just to be | |
307 | * paranoid; we calculate it once here, rather than on | |
308 | * ever buf allocate | |
309 | */ | |
310 | dd->ipath_4kalign = ALIGN(dd->ipath_piosize4k, | |
311 | dd->ipath_palign); | |
312 | ipath_dbg("%u 2k(%x) piobufs @ %p, %u 4k(%x) @ %p " | |
313 | "(%x aligned)\n", | |
314 | dd->ipath_piobcnt2k, dd->ipath_piosize2k, | |
315 | dd->ipath_pio2kbase, dd->ipath_piobcnt4k, | |
316 | dd->ipath_piosize4k, dd->ipath_pio4kbase, | |
317 | dd->ipath_4kalign); | |
318 | } | |
319 | else ipath_dbg("%u 2k piobufs @ %p\n", | |
320 | dd->ipath_piobcnt2k, dd->ipath_pio2kbase); | |
321 | ||
6bb68835 | 322 | spin_lock_init(&dd->ipath_user_tid_lock); |
e342c119 | 323 | spin_lock_init(&dd->ipath_sendctrl_lock); |
17b2eb9f | 324 | spin_lock_init(&dd->ipath_gpio_lock); |
aecd3b5a | 325 | spin_lock_init(&dd->ipath_eep_st_lock); |
2c45688f | 326 | mutex_init(&dd->ipath_eep_lock); |
17b2eb9f | 327 | |
097709fe | 328 | done: |
097709fe BS |
329 | return ret; |
330 | } | |
331 | ||
332 | /** | |
333 | * init_chip_reset - re-initialize after a reset, or enable | |
334 | * @dd: the infinipath device | |
097709fe BS |
335 | * |
336 | * sanity check at least some of the values after reset, and | |
337 | * ensure no receive or transmit (explictly, in case reset | |
338 | * failed | |
339 | */ | |
9355fb6a | 340 | static int init_chip_reset(struct ipath_devdata *dd) |
097709fe | 341 | { |
097709fe | 342 | u32 rtmp; |
9355fb6a | 343 | int i; |
1d7c2e52 | 344 | unsigned long flags; |
9355fb6a RC |
345 | |
346 | /* | |
347 | * ensure chip does no sends or receives, tail updates, or | |
348 | * pioavail updates while we re-initialize | |
349 | */ | |
350 | dd->ipath_rcvctrl &= ~(1ULL << dd->ipath_r_tailupd_shift); | |
351 | for (i = 0; i < dd->ipath_portcnt; i++) { | |
352 | clear_bit(dd->ipath_r_portenable_shift + i, | |
353 | &dd->ipath_rcvctrl); | |
354 | clear_bit(dd->ipath_r_intravail_shift + i, | |
355 | &dd->ipath_rcvctrl); | |
356 | } | |
357 | ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl, | |
358 | dd->ipath_rcvctrl); | |
097709fe | 359 | |
1d7c2e52 DO |
360 | spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags); |
361 | dd->ipath_sendctrl = 0U; /* no sdma, etc */ | |
e342c119 | 362 | ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl); |
1d7c2e52 DO |
363 | ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch); |
364 | spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags); | |
365 | ||
366 | ipath_write_kreg(dd, dd->ipath_kregs->kr_control, 0ULL); | |
097709fe | 367 | |
097709fe BS |
368 | rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidcnt); |
369 | if (rtmp != dd->ipath_rcvtidcnt) | |
370 | dev_info(&dd->pcidev->dev, "tidcnt was %u before " | |
371 | "reset, now %u, using original\n", | |
372 | dd->ipath_rcvtidcnt, rtmp); | |
373 | rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidbase); | |
374 | if (rtmp != dd->ipath_rcvtidbase) | |
375 | dev_info(&dd->pcidev->dev, "tidbase was %u before " | |
376 | "reset, now %u, using original\n", | |
377 | dd->ipath_rcvtidbase, rtmp); | |
378 | rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt); | |
379 | if (rtmp != dd->ipath_rcvegrcnt) | |
380 | dev_info(&dd->pcidev->dev, "egrcnt was %u before " | |
381 | "reset, now %u, using original\n", | |
382 | dd->ipath_rcvegrcnt, rtmp); | |
383 | rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrbase); | |
384 | if (rtmp != dd->ipath_rcvegrbase) | |
385 | dev_info(&dd->pcidev->dev, "egrbase was %u before " | |
386 | "reset, now %u, using original\n", | |
387 | dd->ipath_rcvegrbase, rtmp); | |
388 | ||
389 | return 0; | |
390 | } | |
391 | ||
392 | static int init_pioavailregs(struct ipath_devdata *dd) | |
393 | { | |
394 | int ret; | |
395 | ||
396 | dd->ipath_pioavailregs_dma = dma_alloc_coherent( | |
397 | &dd->pcidev->dev, PAGE_SIZE, &dd->ipath_pioavailregs_phys, | |
398 | GFP_KERNEL); | |
399 | if (!dd->ipath_pioavailregs_dma) { | |
400 | ipath_dev_err(dd, "failed to allocate PIOavail reg area " | |
401 | "in memory\n"); | |
402 | ret = -ENOMEM; | |
403 | goto done; | |
404 | } | |
405 | ||
406 | /* | |
407 | * we really want L2 cache aligned, but for current CPUs of | |
408 | * interest, they are the same. | |
409 | */ | |
410 | dd->ipath_statusp = (u64 *) | |
411 | ((char *)dd->ipath_pioavailregs_dma + | |
412 | ((2 * L1_CACHE_BYTES + | |
413 | dd->ipath_pioavregs * sizeof(u64)) & ~L1_CACHE_BYTES)); | |
414 | /* copy the current value now that it's really allocated */ | |
415 | *dd->ipath_statusp = dd->_ipath_status; | |
416 | /* | |
417 | * setup buffer to hold freeze msg, accessible to apps, | |
418 | * following statusp | |
419 | */ | |
420 | dd->ipath_freezemsg = (char *)&dd->ipath_statusp[1]; | |
421 | /* and its length */ | |
422 | dd->ipath_freezelen = L1_CACHE_BYTES - sizeof(dd->ipath_statusp[0]); | |
423 | ||
f37bda92 | 424 | ret = 0; |
097709fe | 425 | |
097709fe BS |
426 | done: |
427 | return ret; | |
428 | } | |
429 | ||
430 | /** | |
431 | * init_shadow_tids - allocate the shadow TID array | |
432 | * @dd: the infinipath device | |
433 | * | |
434 | * allocate the shadow TID array, so we can ipath_munlock previous | |
435 | * entries. It may make more sense to move the pageshadow to the | |
436 | * port data structure, so we only allocate memory for ports actually | |
437 | * in use, since we at 8k per port, now. | |
438 | */ | |
439 | static void init_shadow_tids(struct ipath_devdata *dd) | |
440 | { | |
1fd3b40f BS |
441 | struct page **pages; |
442 | dma_addr_t *addrs; | |
443 | ||
444 | pages = vmalloc(dd->ipath_cfgports * dd->ipath_rcvtidcnt * | |
097709fe | 445 | sizeof(struct page *)); |
1fd3b40f | 446 | if (!pages) { |
097709fe BS |
447 | ipath_dev_err(dd, "failed to allocate shadow page * " |
448 | "array, no expected sends!\n"); | |
1fd3b40f BS |
449 | dd->ipath_pageshadow = NULL; |
450 | return; | |
451 | } | |
452 | ||
453 | addrs = vmalloc(dd->ipath_cfgports * dd->ipath_rcvtidcnt * | |
454 | sizeof(dma_addr_t)); | |
455 | if (!addrs) { | |
456 | ipath_dev_err(dd, "failed to allocate shadow dma handle " | |
457 | "array, no expected sends!\n"); | |
458 | vfree(dd->ipath_pageshadow); | |
459 | dd->ipath_pageshadow = NULL; | |
460 | return; | |
461 | } | |
462 | ||
463 | memset(pages, 0, dd->ipath_cfgports * dd->ipath_rcvtidcnt * | |
464 | sizeof(struct page *)); | |
465 | ||
466 | dd->ipath_pageshadow = pages; | |
467 | dd->ipath_physshadow = addrs; | |
097709fe BS |
468 | } |
469 | ||
9355fb6a | 470 | static void enable_chip(struct ipath_devdata *dd, int reinit) |
097709fe BS |
471 | { |
472 | u32 val; | |
9355fb6a | 473 | u64 rcvmask; |
e342c119 | 474 | unsigned long flags; |
097709fe BS |
475 | int i; |
476 | ||
0fd41363 BS |
477 | if (!reinit) |
478 | init_waitqueue_head(&ipath_state_wait); | |
479 | ||
097709fe BS |
480 | ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl, |
481 | dd->ipath_rcvctrl); | |
482 | ||
e342c119 | 483 | spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags); |
097709fe BS |
484 | /* Enable PIO send, and update of PIOavail regs to memory. */ |
485 | dd->ipath_sendctrl = INFINIPATH_S_PIOENABLE | | |
486 | INFINIPATH_S_PIOBUFAVAILUPD; | |
1d7c2e52 DO |
487 | |
488 | /* | |
489 | * Set the PIO avail update threshold to host memory | |
490 | * on chips that support it. | |
491 | */ | |
492 | if (dd->ipath_pioupd_thresh) | |
493 | dd->ipath_sendctrl |= dd->ipath_pioupd_thresh | |
494 | << INFINIPATH_S_UPDTHRESH_SHIFT; | |
e342c119 JG |
495 | ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl); |
496 | ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch); | |
497 | spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags); | |
097709fe BS |
498 | |
499 | /* | |
9355fb6a RC |
500 | * Enable kernel ports' receive and receive interrupt. |
501 | * Other ports done as user opens and inits them. | |
097709fe | 502 | */ |
9355fb6a RC |
503 | rcvmask = 1ULL; |
504 | dd->ipath_rcvctrl |= (rcvmask << dd->ipath_r_portenable_shift) | | |
505 | (rcvmask << dd->ipath_r_intravail_shift); | |
506 | if (!(dd->ipath_flags & IPATH_NODMA_RTAIL)) | |
507 | dd->ipath_rcvctrl |= (1ULL << dd->ipath_r_tailupd_shift); | |
508 | ||
097709fe BS |
509 | ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl, |
510 | dd->ipath_rcvctrl); | |
511 | ||
512 | /* | |
513 | * now ready for use. this should be cleared whenever we | |
514 | * detect a reset, or initiate one. | |
515 | */ | |
516 | dd->ipath_flags |= IPATH_INITTED; | |
517 | ||
518 | /* | |
9355fb6a RC |
519 | * Init our shadow copies of head from tail values, |
520 | * and write head values to match. | |
097709fe BS |
521 | */ |
522 | val = ipath_read_ureg32(dd, ur_rcvegrindextail, 0); | |
8c641d4b | 523 | ipath_write_ureg(dd, ur_rcvegrindexhead, val, 0); |
097709fe BS |
524 | |
525 | /* Initialize so we interrupt on next packet received */ | |
8c641d4b RC |
526 | ipath_write_ureg(dd, ur_rcvhdrhead, |
527 | dd->ipath_rhdrhead_intr_off | | |
528 | dd->ipath_pd[0]->port_head, 0); | |
097709fe BS |
529 | |
530 | /* | |
531 | * by now pioavail updates to memory should have occurred, so | |
532 | * copy them into our working/shadow registers; this is in | |
533 | * case something went wrong with abort, but mostly to get the | |
534 | * initial values of the generation bit correct. | |
535 | */ | |
536 | for (i = 0; i < dd->ipath_pioavregs; i++) { | |
6358ae25 | 537 | __le64 pioavail; |
097709fe BS |
538 | |
539 | /* | |
540 | * Chip Errata bug 6641; even and odd qwords>3 are swapped. | |
541 | */ | |
4ea61b54 | 542 | if (i > 3 && (dd->ipath_flags & IPATH_SWAP_PIOBUFS)) |
6358ae25 | 543 | pioavail = dd->ipath_pioavailregs_dma[i ^ 1]; |
097709fe | 544 | else |
6358ae25 | 545 | pioavail = dd->ipath_pioavailregs_dma[i]; |
c4b4d16e RC |
546 | dd->ipath_pioavailshadow[i] = le64_to_cpu(pioavail) | |
547 | (~dd->ipath_pioavailkernel[i] << | |
548 | INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT); | |
097709fe BS |
549 | } |
550 | /* can get counters, stats, etc. */ | |
551 | dd->ipath_flags |= IPATH_PRESENT; | |
552 | } | |
553 | ||
9355fb6a | 554 | static int init_housekeeping(struct ipath_devdata *dd, int reinit) |
097709fe BS |
555 | { |
556 | char boardn[32]; | |
557 | int ret = 0; | |
558 | ||
559 | /* | |
560 | * have to clear shadow copies of registers at init that are | |
561 | * not otherwise set here, or all kinds of bizarre things | |
562 | * happen with driver on chip reset | |
563 | */ | |
564 | dd->ipath_rcvhdrsize = 0; | |
565 | ||
566 | /* | |
567 | * Don't clear ipath_flags as 8bit mode was set before | |
568 | * entering this func. However, we do set the linkstate to | |
569 | * unknown, so we can watch for a transition. | |
52e7fad8 BS |
570 | * PRESENT is set because we want register reads to work, |
571 | * and the kernel infrastructure saw it in config space; | |
572 | * We clear it if we have failures. | |
097709fe | 573 | */ |
52e7fad8 | 574 | dd->ipath_flags |= IPATH_LINKUNK | IPATH_PRESENT; |
097709fe BS |
575 | dd->ipath_flags &= ~(IPATH_LINKACTIVE | IPATH_LINKARMED | |
576 | IPATH_LINKDOWN | IPATH_LINKINIT); | |
577 | ||
578 | ipath_cdbg(VERBOSE, "Try to read spc chip revision\n"); | |
579 | dd->ipath_revision = | |
580 | ipath_read_kreg64(dd, dd->ipath_kregs->kr_revision); | |
581 | ||
582 | /* | |
583 | * set up fundamental info we need to use the chip; we assume | |
584 | * if the revision reg and these regs are OK, we don't need to | |
585 | * special case the rest | |
586 | */ | |
587 | dd->ipath_sregbase = | |
588 | ipath_read_kreg32(dd, dd->ipath_kregs->kr_sendregbase); | |
589 | dd->ipath_cregbase = | |
590 | ipath_read_kreg32(dd, dd->ipath_kregs->kr_counterregbase); | |
591 | dd->ipath_uregbase = | |
592 | ipath_read_kreg32(dd, dd->ipath_kregs->kr_userregbase); | |
593 | ipath_cdbg(VERBOSE, "ipath_kregbase %p, sendbase %x usrbase %x, " | |
594 | "cntrbase %x\n", dd->ipath_kregbase, dd->ipath_sregbase, | |
595 | dd->ipath_uregbase, dd->ipath_cregbase); | |
596 | if ((dd->ipath_revision & 0xffffffff) == 0xffffffff | |
597 | || (dd->ipath_sregbase & 0xffffffff) == 0xffffffff | |
598 | || (dd->ipath_cregbase & 0xffffffff) == 0xffffffff | |
599 | || (dd->ipath_uregbase & 0xffffffff) == 0xffffffff) { | |
600 | ipath_dev_err(dd, "Register read failures from chip, " | |
601 | "giving up initialization\n"); | |
52e7fad8 | 602 | dd->ipath_flags &= ~IPATH_PRESENT; |
097709fe BS |
603 | ret = -ENODEV; |
604 | goto done; | |
605 | } | |
606 | ||
9783ab40 BS |
607 | |
608 | /* clear diagctrl register, in case diags were running and crashed */ | |
609 | ipath_write_kreg (dd, dd->ipath_kregs->kr_hwdiagctrl, 0); | |
610 | ||
097709fe BS |
611 | /* clear the initial reset flag, in case first driver load */ |
612 | ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, | |
613 | INFINIPATH_E_RESET); | |
614 | ||
9355fb6a RC |
615 | ipath_cdbg(VERBOSE, "Revision %llx (PCI %x)\n", |
616 | (unsigned long long) dd->ipath_revision, | |
617 | dd->ipath_pcirev); | |
097709fe BS |
618 | |
619 | if (((dd->ipath_revision >> INFINIPATH_R_SOFTWARE_SHIFT) & | |
620 | INFINIPATH_R_SOFTWARE_MASK) != IPATH_CHIP_SWVERSION) { | |
621 | ipath_dev_err(dd, "Driver only handles version %d, " | |
622 | "chip swversion is %d (%llx), failng\n", | |
623 | IPATH_CHIP_SWVERSION, | |
624 | (int)(dd->ipath_revision >> | |
625 | INFINIPATH_R_SOFTWARE_SHIFT) & | |
626 | INFINIPATH_R_SOFTWARE_MASK, | |
627 | (unsigned long long) dd->ipath_revision); | |
628 | ret = -ENOSYS; | |
629 | goto done; | |
630 | } | |
631 | dd->ipath_majrev = (u8) ((dd->ipath_revision >> | |
632 | INFINIPATH_R_CHIPREVMAJOR_SHIFT) & | |
633 | INFINIPATH_R_CHIPREVMAJOR_MASK); | |
634 | dd->ipath_minrev = (u8) ((dd->ipath_revision >> | |
635 | INFINIPATH_R_CHIPREVMINOR_SHIFT) & | |
636 | INFINIPATH_R_CHIPREVMINOR_MASK); | |
637 | dd->ipath_boardrev = (u8) ((dd->ipath_revision >> | |
638 | INFINIPATH_R_BOARDID_SHIFT) & | |
639 | INFINIPATH_R_BOARDID_MASK); | |
640 | ||
641 | ret = dd->ipath_f_get_boardname(dd, boardn, sizeof boardn); | |
642 | ||
643 | snprintf(dd->ipath_boardversion, sizeof(dd->ipath_boardversion), | |
12f9a49e | 644 | "ChipABI %u.%u, %s, InfiniPath%u %u.%u, PCI %u, " |
097709fe BS |
645 | "SW Compat %u\n", |
646 | IPATH_CHIP_VERS_MAJ, IPATH_CHIP_VERS_MIN, boardn, | |
647 | (unsigned)(dd->ipath_revision >> INFINIPATH_R_ARCH_SHIFT) & | |
648 | INFINIPATH_R_ARCH_MASK, | |
649 | dd->ipath_majrev, dd->ipath_minrev, dd->ipath_pcirev, | |
650 | (unsigned)(dd->ipath_revision >> | |
651 | INFINIPATH_R_SOFTWARE_SHIFT) & | |
652 | INFINIPATH_R_SOFTWARE_MASK); | |
653 | ||
654 | ipath_dbg("%s", dd->ipath_boardversion); | |
655 | ||
9355fb6a RC |
656 | if (ret) |
657 | goto done; | |
658 | ||
659 | if (reinit) | |
660 | ret = init_chip_reset(dd); | |
661 | else | |
662 | ret = init_chip_first(dd); | |
663 | ||
097709fe BS |
664 | done: |
665 | return ret; | |
666 | } | |
667 | ||
9b436eb4 DO |
668 | static void verify_interrupt(unsigned long opaque) |
669 | { | |
670 | struct ipath_devdata *dd = (struct ipath_devdata *) opaque; | |
671 | ||
672 | if (!dd) | |
673 | return; /* being torn down */ | |
674 | ||
675 | /* | |
676 | * If we don't have any interrupts, let the user know and | |
677 | * don't bother checking again. | |
678 | */ | |
679 | if (dd->ipath_int_counter == 0) { | |
680 | if (!dd->ipath_f_intr_fallback(dd)) | |
681 | dev_err(&dd->pcidev->dev, "No interrupts detected, " | |
682 | "not usable.\n"); | |
683 | else /* re-arm the timer to see if fallback works */ | |
684 | mod_timer(&dd->ipath_intrchk_timer, jiffies + HZ/2); | |
685 | } else | |
686 | ipath_cdbg(VERBOSE, "%u interrupts at timer check\n", | |
687 | dd->ipath_int_counter); | |
688 | } | |
689 | ||
097709fe BS |
690 | /** |
691 | * ipath_init_chip - do the actual initialization sequence on the chip | |
692 | * @dd: the infinipath device | |
693 | * @reinit: reinitializing, so don't allocate new memory | |
694 | * | |
695 | * Do the actual initialization sequence on the chip. This is done | |
696 | * both from the init routine called from the PCI infrastructure, and | |
697 | * when we reset the chip, or detect that it was reset internally, | |
698 | * or it's administratively re-enabled. | |
699 | * | |
700 | * Memory allocation here and in called routines is only done in | |
701 | * the first case (reinit == 0). We have to be careful, because even | |
702 | * without memory allocation, we need to re-write all the chip registers | |
703 | * TIDs, etc. after the reset or enable has completed. | |
704 | */ | |
705 | int ipath_init_chip(struct ipath_devdata *dd, int reinit) | |
706 | { | |
c59a80ac | 707 | int ret = 0; |
097709fe | 708 | u32 val32, kpiobufs; |
0ed3c594 | 709 | u32 piobufs, uports; |
f37bda92 | 710 | u64 val; |
9355fb6a | 711 | struct ipath_portdata *pd; |
35783ec0 | 712 | gfp_t gfp_flags = GFP_USER | __GFP_COMP; |
e342c119 | 713 | unsigned long flags; |
097709fe | 714 | |
9355fb6a | 715 | ret = init_housekeeping(dd, reinit); |
097709fe BS |
716 | if (ret) |
717 | goto done; | |
718 | ||
719 | /* | |
720 | * we ignore most issues after reporting them, but have to specially | |
721 | * handle hardware-disabled chips. | |
722 | */ | |
723 | if (ret == 2) { | |
724 | /* unique error, known to ipath_init_one */ | |
725 | ret = -EPERM; | |
726 | goto done; | |
727 | } | |
728 | ||
729 | /* | |
730 | * We could bump this to allow for full rcvegrcnt + rcvtidcnt, | |
731 | * but then it no longer nicely fits power of two, and since | |
732 | * we now use routines that backend onto __get_free_pages, the | |
733 | * rest would be wasted. | |
734 | */ | |
9355fb6a | 735 | dd->ipath_rcvhdrcnt = max(dd->ipath_p0_rcvegrcnt, dd->ipath_rcvegrcnt); |
097709fe BS |
736 | ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrcnt, |
737 | dd->ipath_rcvhdrcnt); | |
738 | ||
739 | /* | |
740 | * Set up the shadow copies of the piobufavail registers, | |
741 | * which we compare against the chip registers for now, and | |
742 | * the in memory DMA'ed copies of the registers. This has to | |
743 | * be done early, before we calculate lastport, etc. | |
744 | */ | |
0ed3c594 | 745 | piobufs = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k; |
097709fe BS |
746 | /* |
747 | * calc number of pioavail registers, and save it; we have 2 | |
748 | * bits per buffer. | |
749 | */ | |
0ed3c594 | 750 | dd->ipath_pioavregs = ALIGN(piobufs, sizeof(u64) * BITS_PER_BYTE / 2) |
097709fe | 751 | / (sizeof(u64) * BITS_PER_BYTE / 2); |
0ed3c594 | 752 | uports = dd->ipath_cfgports ? dd->ipath_cfgports - 1 : 0; |
52e7fad8 | 753 | if (ipath_kpiobufs == 0) { |
ba11203a | 754 | /* not set by user (this is default) */ |
37a7e9b7 | 755 | if (piobufs > 144) |
52e7fad8 BS |
756 | kpiobufs = 32; |
757 | else | |
758 | kpiobufs = 16; | |
759 | } | |
760 | else | |
097709fe BS |
761 | kpiobufs = ipath_kpiobufs; |
762 | ||
0ed3c594 | 763 | if (kpiobufs + (uports * IPATH_MIN_USER_PORT_BUFCNT) > piobufs) { |
c59a80ac | 764 | int i = (int) piobufs - |
0ed3c594 | 765 | (int) (uports * IPATH_MIN_USER_PORT_BUFCNT); |
9355fb6a RC |
766 | if (i < 1) |
767 | i = 1; | |
0ed3c594 BS |
768 | dev_info(&dd->pcidev->dev, "Allocating %d PIO bufs of " |
769 | "%d for kernel leaves too few for %d user ports " | |
097709fe | 770 | "(%d each); using %u\n", kpiobufs, |
0ed3c594 | 771 | piobufs, uports, IPATH_MIN_USER_PORT_BUFCNT, i); |
097709fe BS |
772 | /* |
773 | * shouldn't change ipath_kpiobufs, because could be | |
774 | * different for different devices... | |
775 | */ | |
776 | kpiobufs = i; | |
777 | } | |
0ed3c594 BS |
778 | dd->ipath_lastport_piobuf = piobufs - kpiobufs; |
779 | dd->ipath_pbufsport = | |
780 | uports ? dd->ipath_lastport_piobuf / uports : 0; | |
781 | val32 = dd->ipath_lastport_piobuf - (dd->ipath_pbufsport * uports); | |
097709fe BS |
782 | if (val32 > 0) { |
783 | ipath_dbg("allocating %u pbufs/port leaves %u unused, " | |
784 | "add to kernel\n", dd->ipath_pbufsport, val32); | |
785 | dd->ipath_lastport_piobuf -= val32; | |
9355fb6a | 786 | kpiobufs += val32; |
097709fe BS |
787 | ipath_dbg("%u pbufs/port leaves %u unused, add to kernel\n", |
788 | dd->ipath_pbufsport, val32); | |
789 | } | |
c4b4d16e RC |
790 | dd->ipath_lastpioindex = 0; |
791 | dd->ipath_lastpioindexl = dd->ipath_piobcnt2k; | |
792 | ipath_chg_pioavailkernel(dd, 0, piobufs, 1); | |
097709fe BS |
793 | ipath_cdbg(VERBOSE, "%d PIO bufs for kernel out of %d total %u " |
794 | "each for %u user ports\n", kpiobufs, | |
0ed3c594 | 795 | piobufs, dd->ipath_pbufsport, uports); |
1d7c2e52 DO |
796 | if (dd->ipath_pioupd_thresh) { |
797 | if (dd->ipath_pbufsport < dd->ipath_pioupd_thresh) | |
798 | dd->ipath_pioupd_thresh = dd->ipath_pbufsport; | |
799 | if (kpiobufs < dd->ipath_pioupd_thresh) | |
800 | dd->ipath_pioupd_thresh = kpiobufs; | |
801 | } | |
097709fe BS |
802 | |
803 | dd->ipath_f_early_init(dd); | |
9380068f | 804 | /* |
2ba3f56e | 805 | * Cancel any possible active sends from early driver load. |
9380068f DO |
806 | * Follows early_init because some chips have to initialize |
807 | * PIO buffers in early_init to avoid false parity errors. | |
808 | */ | |
3810f2a8 | 809 | ipath_cancel_sends(dd, 0); |
097709fe | 810 | |
9355fb6a RC |
811 | /* |
812 | * Early_init sets rcvhdrentsize and rcvhdrsize, so this must be | |
813 | * done after early_init. | |
814 | */ | |
097709fe BS |
815 | dd->ipath_hdrqlast = |
816 | dd->ipath_rcvhdrentsize * (dd->ipath_rcvhdrcnt - 1); | |
817 | ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrentsize, | |
818 | dd->ipath_rcvhdrentsize); | |
819 | ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrsize, | |
820 | dd->ipath_rcvhdrsize); | |
821 | ||
822 | if (!reinit) { | |
823 | ret = init_pioavailregs(dd); | |
824 | init_shadow_tids(dd); | |
825 | if (ret) | |
826 | goto done; | |
827 | } | |
828 | ||
8c641d4b RC |
829 | ipath_write_kreg(dd, dd->ipath_kregs->kr_sendpioavailaddr, |
830 | dd->ipath_pioavailregs_phys); | |
097709fe BS |
831 | /* |
832 | * this is to detect s/w errors, which the h/w works around by | |
833 | * ignoring the low 6 bits of address, if it wasn't aligned. | |
834 | */ | |
835 | val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpioavailaddr); | |
836 | if (val != dd->ipath_pioavailregs_phys) { | |
837 | ipath_dev_err(dd, "Catastrophic software error, " | |
838 | "SendPIOAvailAddr written as %lx, " | |
839 | "read back as %llx\n", | |
840 | (unsigned long) dd->ipath_pioavailregs_phys, | |
841 | (unsigned long long) val); | |
842 | ret = -EINVAL; | |
843 | goto done; | |
844 | } | |
845 | ||
097709fe BS |
846 | ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvbthqp, IPATH_KD_QP); |
847 | ||
848 | /* | |
849 | * make sure we are not in freeze, and PIO send enabled, so | |
850 | * writes to pbc happen | |
851 | */ | |
852 | ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask, 0ULL); | |
853 | ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear, | |
854 | ~0ULL&~INFINIPATH_HWE_MEMBISTFAILED); | |
855 | ipath_write_kreg(dd, dd->ipath_kregs->kr_control, 0ULL); | |
e342c119 JG |
856 | |
857 | spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags); | |
858 | dd->ipath_sendctrl = INFINIPATH_S_PIOENABLE; | |
859 | ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl); | |
860 | ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch); | |
861 | spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags); | |
097709fe BS |
862 | |
863 | /* | |
864 | * before error clears, since we expect serdes pll errors during | |
865 | * this, the first time after reset | |
866 | */ | |
867 | if (bringup_link(dd)) { | |
868 | dev_info(&dd->pcidev->dev, "Failed to bringup IB link\n"); | |
869 | ret = -ENETDOWN; | |
870 | goto done; | |
871 | } | |
872 | ||
873 | /* | |
874 | * clear any "expected" hwerrs from reset and/or initialization | |
875 | * clear any that aren't enabled (at least this once), and then | |
876 | * set the enable mask | |
877 | */ | |
878 | dd->ipath_f_init_hwerrors(dd); | |
879 | ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear, | |
880 | ~0ULL&~INFINIPATH_HWE_MEMBISTFAILED); | |
881 | ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask, | |
882 | dd->ipath_hwerrmask); | |
883 | ||
097709fe BS |
884 | /* clear all */ |
885 | ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, -1LL); | |
886 | /* enable errors that are masked, at least this first time. */ | |
887 | ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask, | |
888 | ~dd->ipath_maskederrs); | |
9355fb6a RC |
889 | dd->ipath_maskederrs = 0; /* don't re-enable ignored in timer */ |
890 | dd->ipath_errormask = | |
891 | ipath_read_kreg64(dd, dd->ipath_kregs->kr_errormask); | |
78d1e02f | 892 | /* clear any interrupts up to this point (ints still not enabled) */ |
097709fe BS |
893 | ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, -1LL); |
894 | ||
9355fb6a RC |
895 | dd->ipath_f_tidtemplate(dd); |
896 | ||
097709fe BS |
897 | /* |
898 | * Set up the port 0 (kernel) rcvhdr q and egr TIDs. If doing | |
899 | * re-init, the simplest way to handle this is to free | |
900 | * existing, and re-allocate. | |
27b044a8 | 901 | * Need to re-create rest of port 0 portdata as well. |
097709fe | 902 | */ |
9355fb6a | 903 | pd = dd->ipath_pd[0]; |
f37bda92 | 904 | if (reinit) { |
9355fb6a RC |
905 | struct ipath_portdata *npd; |
906 | ||
907 | /* | |
908 | * Alloc and init new ipath_portdata for port0, | |
27b044a8 MA |
909 | * Then free old pd. Could lead to fragmentation, but also |
910 | * makes later support for hot-swap easier. | |
911 | */ | |
27b044a8 MA |
912 | npd = create_portdata0(dd); |
913 | if (npd) { | |
914 | ipath_free_pddata(dd, pd); | |
9355fb6a RC |
915 | dd->ipath_pd[0] = npd; |
916 | pd = npd; | |
27b044a8 | 917 | } else { |
9355fb6a RC |
918 | ipath_dev_err(dd, "Unable to allocate portdata" |
919 | " for port 0, failing\n"); | |
27b044a8 MA |
920 | ret = -ENOMEM; |
921 | goto done; | |
922 | } | |
f37bda92 | 923 | } |
097709fe | 924 | ret = ipath_create_rcvhdrq(dd, pd); |
9355fb6a | 925 | if (!ret) |
097709fe | 926 | ret = create_port0_egr(dd); |
9355fb6a RC |
927 | if (ret) { |
928 | ipath_dev_err(dd, "failed to allocate kernel port's " | |
097709fe | 929 | "rcvhdrq and/or egr bufs\n"); |
9355fb6a RC |
930 | goto done; |
931 | } | |
097709fe | 932 | else |
9355fb6a | 933 | enable_chip(dd, reinit); |
097709fe | 934 | |
9355fb6a RC |
935 | if (!reinit) { |
936 | /* | |
937 | * Used when we close a port, for DMA already in flight | |
938 | * at close. | |
939 | */ | |
35783ec0 | 940 | dd->ipath_dummy_hdrq = dma_alloc_coherent( |
9355fb6a | 941 | &dd->pcidev->dev, dd->ipath_pd[0]->port_rcvhdrq_size, |
35783ec0 BS |
942 | &dd->ipath_dummy_hdrq_phys, |
943 | gfp_flags); | |
2ba3f56e | 944 | if (!dd->ipath_dummy_hdrq) { |
35783ec0 BS |
945 | dev_info(&dd->pcidev->dev, |
946 | "Couldn't allocate 0x%lx bytes for dummy hdrq\n", | |
9355fb6a | 947 | dd->ipath_pd[0]->port_rcvhdrq_size); |
35783ec0 BS |
948 | /* fallback to just 0'ing */ |
949 | dd->ipath_dummy_hdrq_phys = 0UL; | |
950 | } | |
951 | } | |
952 | ||
097709fe BS |
953 | /* |
954 | * cause retrigger of pending interrupts ignored during init, | |
955 | * even if we had errors | |
956 | */ | |
957 | ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, 0ULL); | |
958 | ||
2ba3f56e | 959 | if (!dd->ipath_stats_timer_active) { |
097709fe BS |
960 | /* |
961 | * first init, or after an admin disable/enable | |
962 | * set up stats retrieval timer, even if we had errors | |
963 | * in last portion of setup | |
964 | */ | |
965 | init_timer(&dd->ipath_stats_timer); | |
966 | dd->ipath_stats_timer.function = ipath_get_faststats; | |
967 | dd->ipath_stats_timer.data = (unsigned long) dd; | |
968 | /* every 5 seconds; */ | |
969 | dd->ipath_stats_timer.expires = jiffies + 5 * HZ; | |
970 | /* takes ~16 seconds to overflow at full IB 4x bandwdith */ | |
971 | add_timer(&dd->ipath_stats_timer); | |
972 | dd->ipath_stats_timer_active = 1; | |
973 | } | |
974 | ||
58411d1c JG |
975 | /* Set up HoL state */ |
976 | init_timer(&dd->ipath_hol_timer); | |
977 | dd->ipath_hol_timer.function = ipath_hol_event; | |
978 | dd->ipath_hol_timer.data = (unsigned long)dd; | |
979 | dd->ipath_hol_state = IPATH_HOL_UP; | |
980 | ||
097709fe BS |
981 | done: |
982 | if (!ret) { | |
097709fe BS |
983 | *dd->ipath_statusp |= IPATH_STATUS_CHIP_PRESENT; |
984 | if (!dd->ipath_f_intrsetup(dd)) { | |
985 | /* now we can enable all interrupts from the chip */ | |
986 | ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, | |
987 | -1LL); | |
988 | /* force re-interrupt of any pending interrupts. */ | |
989 | ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, | |
990 | 0ULL); | |
991 | /* chip is usable; mark it as initialized */ | |
992 | *dd->ipath_statusp |= IPATH_STATUS_INITTED; | |
9b436eb4 DO |
993 | |
994 | /* | |
995 | * setup to verify we get an interrupt, and fallback | |
996 | * to an alternate if necessary and possible | |
997 | */ | |
998 | if (!reinit) { | |
999 | init_timer(&dd->ipath_intrchk_timer); | |
1000 | dd->ipath_intrchk_timer.function = | |
1001 | verify_interrupt; | |
1002 | dd->ipath_intrchk_timer.data = | |
1003 | (unsigned long) dd; | |
1004 | } | |
1005 | dd->ipath_intrchk_timer.expires = jiffies + HZ/2; | |
1006 | add_timer(&dd->ipath_intrchk_timer); | |
097709fe BS |
1007 | } else |
1008 | ipath_dev_err(dd, "No interrupts enabled, couldn't " | |
1009 | "setup interrupt address\n"); | |
1010 | ||
1011 | if (dd->ipath_cfgports > ipath_stats.sps_nports) | |
1012 | /* | |
1013 | * sps_nports is a global, so, we set it to | |
1014 | * the highest number of ports of any of the | |
1015 | * chips we find; we never decrement it, at | |
1016 | * least for now. Since this might have changed | |
1017 | * over disable/enable or prior to reset, always | |
1018 | * do the check and potentially adjust. | |
1019 | */ | |
1020 | ipath_stats.sps_nports = dd->ipath_cfgports; | |
1021 | } else | |
1022 | ipath_dbg("Failed (%d) to initialize chip\n", ret); | |
1023 | ||
1024 | /* if ret is non-zero, we probably should do some cleanup | |
1025 | here... */ | |
1026 | return ret; | |
1027 | } | |
1028 | ||
1029 | static int ipath_set_kpiobufs(const char *str, struct kernel_param *kp) | |
1030 | { | |
1031 | struct ipath_devdata *dd; | |
1032 | unsigned long flags; | |
1033 | unsigned short val; | |
1034 | int ret; | |
1035 | ||
1036 | ret = ipath_parse_ushort(str, &val); | |
1037 | ||
1038 | spin_lock_irqsave(&ipath_devs_lock, flags); | |
1039 | ||
1040 | if (ret < 0) | |
1041 | goto bail; | |
1042 | ||
1043 | if (val == 0) { | |
1044 | ret = -EINVAL; | |
1045 | goto bail; | |
1046 | } | |
1047 | ||
1048 | list_for_each_entry(dd, &ipath_dev_list, ipath_list) { | |
1049 | if (dd->ipath_kregbase) | |
1050 | continue; | |
1051 | if (val > (dd->ipath_piobcnt2k + dd->ipath_piobcnt4k - | |
1052 | (dd->ipath_cfgports * | |
1053 | IPATH_MIN_USER_PORT_BUFCNT))) | |
1054 | { | |
1055 | ipath_dev_err( | |
1056 | dd, | |
1057 | "Allocating %d PIO bufs for kernel leaves " | |
1058 | "too few for %d user ports (%d each)\n", | |
1059 | val, dd->ipath_cfgports - 1, | |
1060 | IPATH_MIN_USER_PORT_BUFCNT); | |
1061 | ret = -EINVAL; | |
1062 | goto bail; | |
1063 | } | |
1064 | dd->ipath_lastport_piobuf = | |
1065 | dd->ipath_piobcnt2k + dd->ipath_piobcnt4k - val; | |
1066 | } | |
1067 | ||
ba11203a | 1068 | ipath_kpiobufs = val; |
097709fe BS |
1069 | ret = 0; |
1070 | bail: | |
1071 | spin_unlock_irqrestore(&ipath_devs_lock, flags); | |
1072 | ||
1073 | return ret; | |
1074 | } |