Commit | Line | Data |
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097709fe | 1 | /* |
87427da5 | 2 | * Copyright (c) 2006, 2007 QLogic Corporation. All rights reserved. |
097709fe BS |
3 | * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved. |
4 | * | |
5 | * This software is available to you under a choice of one of two | |
6 | * licenses. You may choose to be licensed under the terms of the GNU | |
7 | * General Public License (GPL) Version 2, available from the file | |
8 | * COPYING in the main directory of this source tree, or the | |
9 | * OpenIB.org BSD license below: | |
10 | * | |
11 | * Redistribution and use in source and binary forms, with or | |
12 | * without modification, are permitted provided that the following | |
13 | * conditions are met: | |
14 | * | |
15 | * - Redistributions of source code must retain the above | |
16 | * copyright notice, this list of conditions and the following | |
17 | * disclaimer. | |
18 | * | |
19 | * - Redistributions in binary form must reproduce the above | |
20 | * copyright notice, this list of conditions and the following | |
21 | * disclaimer in the documentation and/or other materials | |
22 | * provided with the distribution. | |
23 | * | |
24 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
25 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
26 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
27 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
28 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
29 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
30 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
31 | * SOFTWARE. | |
32 | */ | |
33 | ||
34 | #include <linux/pci.h> | |
35 | #include <linux/netdevice.h> | |
36 | #include <linux/vmalloc.h> | |
37 | ||
38 | #include "ipath_kernel.h" | |
27b678dd | 39 | #include "ipath_common.h" |
097709fe BS |
40 | |
41 | /* | |
42 | * min buffers we want to have per port, after driver | |
43 | */ | |
44 | #define IPATH_MIN_USER_PORT_BUFCNT 8 | |
45 | ||
46 | /* | |
47 | * Number of ports we are configured to use (to allow for more pio | |
48 | * buffers per port, etc.) Zero means use chip value. | |
49 | */ | |
50 | static ushort ipath_cfgports; | |
51 | ||
52 | module_param_named(cfgports, ipath_cfgports, ushort, S_IRUGO); | |
53 | MODULE_PARM_DESC(cfgports, "Set max number of ports to use"); | |
54 | ||
55 | /* | |
0fd41363 BS |
56 | * Number of buffers reserved for driver (verbs and layered drivers.) |
57 | * Reserved at end of buffer list. Initialized based on | |
52e7fad8 BS |
58 | * number of PIO buffers if not set via module interface. |
59 | * The problem with this is that it's global, but we'll use different | |
60 | * numbers for different chip types. So the default value is not | |
61 | * very useful. I've redefined it for the 1.3 release so that it's | |
62 | * zero unless set by the user to something else, in which case we | |
63 | * try to respect it. | |
097709fe | 64 | */ |
52e7fad8 | 65 | static ushort ipath_kpiobufs; |
097709fe BS |
66 | |
67 | static int ipath_set_kpiobufs(const char *val, struct kernel_param *kp); | |
68 | ||
52e7fad8 | 69 | module_param_call(kpiobufs, ipath_set_kpiobufs, param_get_ushort, |
097709fe BS |
70 | &ipath_kpiobufs, S_IWUSR | S_IRUGO); |
71 | MODULE_PARM_DESC(kpiobufs, "Set number of PIO buffers for driver"); | |
72 | ||
73 | /** | |
74 | * create_port0_egr - allocate the eager TID buffers | |
75 | * @dd: the infinipath device | |
76 | * | |
77 | * This code is now quite different for user and kernel, because | |
78 | * the kernel uses skb's, for the accelerated network performance. | |
79 | * This is the kernel (port0) version. | |
80 | * | |
81 | * Allocate the eager TID buffers and program them into infinipath. | |
82 | * We use the network layer alloc_skb() allocator to allocate the | |
0fd41363 | 83 | * memory, and either use the buffers as is for things like verbs |
097709fe BS |
84 | * packets, or pass the buffers up to the ipath layered driver and |
85 | * thence the network layer, replacing them as we do so (see | |
86 | * ipath_rcv_layer()). | |
87 | */ | |
88 | static int create_port0_egr(struct ipath_devdata *dd) | |
89 | { | |
90 | unsigned e, egrcnt; | |
1fd3b40f | 91 | struct ipath_skbinfo *skbinfo; |
097709fe BS |
92 | int ret; |
93 | ||
60948a41 | 94 | egrcnt = dd->ipath_p0_rcvegrcnt; |
097709fe | 95 | |
1fd3b40f BS |
96 | skbinfo = vmalloc(sizeof(*dd->ipath_port0_skbinfo) * egrcnt); |
97 | if (skbinfo == NULL) { | |
097709fe BS |
98 | ipath_dev_err(dd, "allocation error for eager TID " |
99 | "skb array\n"); | |
100 | ret = -ENOMEM; | |
101 | goto bail; | |
102 | } | |
103 | for (e = 0; e < egrcnt; e++) { | |
104 | /* | |
105 | * This is a bit tricky in that we allocate extra | |
106 | * space for 2 bytes of the 14 byte ethernet header. | |
107 | * These two bytes are passed in the ipath header so | |
108 | * the rest of the data is word aligned. We allocate | |
109 | * 4 bytes so that the data buffer stays word aligned. | |
110 | * See ipath_kreceive() for more details. | |
111 | */ | |
1fd3b40f BS |
112 | skbinfo[e].skb = ipath_alloc_skb(dd, GFP_KERNEL); |
113 | if (!skbinfo[e].skb) { | |
097709fe BS |
114 | ipath_dev_err(dd, "SKB allocation error for " |
115 | "eager TID %u\n", e); | |
116 | while (e != 0) | |
1fd3b40f BS |
117 | dev_kfree_skb(skbinfo[--e].skb); |
118 | vfree(skbinfo); | |
097709fe BS |
119 | ret = -ENOMEM; |
120 | goto bail; | |
121 | } | |
122 | } | |
123 | /* | |
124 | * After loop above, so we can test non-NULL to see if ready | |
125 | * to use at receive, etc. | |
126 | */ | |
1fd3b40f | 127 | dd->ipath_port0_skbinfo = skbinfo; |
097709fe BS |
128 | |
129 | for (e = 0; e < egrcnt; e++) { | |
1fd3b40f BS |
130 | dd->ipath_port0_skbinfo[e].phys = |
131 | ipath_map_single(dd->pcidev, | |
132 | dd->ipath_port0_skbinfo[e].skb->data, | |
133 | dd->ipath_ibmaxlen, PCI_DMA_FROMDEVICE); | |
097709fe BS |
134 | dd->ipath_f_put_tid(dd, e + (u64 __iomem *) |
135 | ((char __iomem *) dd->ipath_kregbase + | |
f716cdfe JE |
136 | dd->ipath_rcvegrbase), |
137 | RCVHQ_RCV_TYPE_EAGER, | |
1fd3b40f | 138 | dd->ipath_port0_skbinfo[e].phys); |
097709fe BS |
139 | } |
140 | ||
141 | ret = 0; | |
142 | ||
143 | bail: | |
144 | return ret; | |
145 | } | |
146 | ||
147 | static int bringup_link(struct ipath_devdata *dd) | |
148 | { | |
149 | u64 val, ibc; | |
150 | int ret = 0; | |
151 | ||
152 | /* hold IBC in reset */ | |
153 | dd->ipath_control &= ~INFINIPATH_C_LINKENABLE; | |
154 | ipath_write_kreg(dd, dd->ipath_kregs->kr_control, | |
155 | dd->ipath_control); | |
156 | ||
157 | /* | |
158 | * Note that prior to try 14 or 15 of IB, the credit scaling | |
159 | * wasn't working, because it was swapped for writes with the | |
160 | * 1 bit default linkstate field | |
161 | */ | |
162 | ||
163 | /* ignore pbc and align word */ | |
164 | val = dd->ipath_piosize2k - 2 * sizeof(u32); | |
165 | /* | |
166 | * for ICRC, which we only send in diag test pkt mode, and we | |
167 | * don't need to worry about that for mtu | |
168 | */ | |
169 | val += 1; | |
170 | /* | |
171 | * Set the IBC maxpktlength to the size of our pio buffers the | |
172 | * maxpktlength is in words. This is *not* the IB data MTU. | |
173 | */ | |
174 | ibc = (val / sizeof(u32)) << INFINIPATH_IBCC_MAXPKTLEN_SHIFT; | |
175 | /* in KB */ | |
176 | ibc |= 0x5ULL << INFINIPATH_IBCC_FLOWCTRLWATERMARK_SHIFT; | |
177 | /* | |
178 | * How often flowctrl sent. More or less in usecs; balance against | |
179 | * watermark value, so that in theory senders always get a flow | |
180 | * control update in time to not let the IB link go idle. | |
181 | */ | |
182 | ibc |= 0x3ULL << INFINIPATH_IBCC_FLOWCTRLPERIOD_SHIFT; | |
183 | /* max error tolerance */ | |
184 | ibc |= 0xfULL << INFINIPATH_IBCC_PHYERRTHRESHOLD_SHIFT; | |
185 | /* use "real" buffer space for */ | |
186 | ibc |= 4ULL << INFINIPATH_IBCC_CREDITSCALE_SHIFT; | |
187 | /* IB credit flow control. */ | |
188 | ibc |= 0xfULL << INFINIPATH_IBCC_OVERRUNTHRESHOLD_SHIFT; | |
189 | /* initially come up waiting for TS1, without sending anything. */ | |
190 | dd->ipath_ibcctrl = ibc; | |
191 | /* | |
192 | * Want to start out with both LINKCMD and LINKINITCMD in NOP | |
193 | * (0 and 0). Don't put linkinitcmd in ipath_ibcctrl, want that | |
194 | * to stay a NOP | |
195 | */ | |
196 | ibc |= INFINIPATH_IBCC_LINKINITCMD_DISABLE << | |
197 | INFINIPATH_IBCC_LINKINITCMD_SHIFT; | |
198 | ipath_cdbg(VERBOSE, "Writing 0x%llx to ibcctrl\n", | |
199 | (unsigned long long) ibc); | |
200 | ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl, ibc); | |
201 | ||
202 | // be sure chip saw it | |
203 | val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch); | |
204 | ||
205 | ret = dd->ipath_f_bringup_serdes(dd); | |
206 | ||
207 | if (ret) | |
208 | dev_info(&dd->pcidev->dev, "Could not initialize SerDes, " | |
209 | "not usable\n"); | |
210 | else { | |
211 | /* enable IBC */ | |
212 | dd->ipath_control |= INFINIPATH_C_LINKENABLE; | |
213 | ipath_write_kreg(dd, dd->ipath_kregs->kr_control, | |
214 | dd->ipath_control); | |
215 | } | |
216 | ||
217 | return ret; | |
218 | } | |
219 | ||
27b044a8 MA |
220 | static struct ipath_portdata *create_portdata0(struct ipath_devdata *dd) |
221 | { | |
222 | struct ipath_portdata *pd = NULL; | |
223 | ||
224 | pd = kzalloc(sizeof(*pd), GFP_KERNEL); | |
225 | if (pd) { | |
226 | pd->port_dd = dd; | |
227 | pd->port_cnt = 1; | |
228 | /* The port 0 pkey table is used by the layer interface. */ | |
229 | pd->port_pkeys[0] = IPATH_DEFAULT_P_KEY; | |
230 | } | |
231 | return pd; | |
232 | } | |
233 | ||
097709fe BS |
234 | static int init_chip_first(struct ipath_devdata *dd, |
235 | struct ipath_portdata **pdp) | |
236 | { | |
237 | struct ipath_portdata *pd = NULL; | |
238 | int ret = 0; | |
239 | u64 val; | |
240 | ||
241 | /* | |
242 | * skip cfgports stuff because we are not allocating memory, | |
243 | * and we don't want problems if the portcnt changed due to | |
244 | * cfgports. We do still check and report a difference, if | |
245 | * not same (should be impossible). | |
246 | */ | |
60948a41 | 247 | dd->ipath_f_config_ports(dd, ipath_cfgports); |
097709fe BS |
248 | if (!ipath_cfgports) |
249 | dd->ipath_cfgports = dd->ipath_portcnt; | |
250 | else if (ipath_cfgports <= dd->ipath_portcnt) { | |
251 | dd->ipath_cfgports = ipath_cfgports; | |
252 | ipath_dbg("Configured to use %u ports out of %u in chip\n", | |
253 | dd->ipath_cfgports, dd->ipath_portcnt); | |
254 | } else { | |
255 | dd->ipath_cfgports = dd->ipath_portcnt; | |
256 | ipath_dbg("Tried to configured to use %u ports; chip " | |
257 | "only supports %u\n", ipath_cfgports, | |
258 | dd->ipath_portcnt); | |
259 | } | |
8e280d94 BS |
260 | /* |
261 | * Allocate full portcnt array, rather than just cfgports, because | |
262 | * cleanup iterates across all possible ports. | |
263 | */ | |
264 | dd->ipath_pd = kzalloc(sizeof(*dd->ipath_pd) * dd->ipath_portcnt, | |
097709fe BS |
265 | GFP_KERNEL); |
266 | ||
267 | if (!dd->ipath_pd) { | |
268 | ipath_dev_err(dd, "Unable to allocate portdata array, " | |
269 | "failing\n"); | |
270 | ret = -ENOMEM; | |
271 | goto done; | |
272 | } | |
273 | ||
27b044a8 | 274 | pd = create_portdata0(dd); |
27b044a8 | 275 | if (!pd) { |
097709fe BS |
276 | ipath_dev_err(dd, "Unable to allocate portdata for port " |
277 | "0, failing\n"); | |
278 | ret = -ENOMEM; | |
279 | goto done; | |
280 | } | |
27b044a8 MA |
281 | dd->ipath_pd[0] = pd; |
282 | ||
097709fe BS |
283 | dd->ipath_rcvtidcnt = |
284 | ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidcnt); | |
285 | dd->ipath_rcvtidbase = | |
286 | ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidbase); | |
287 | dd->ipath_rcvegrcnt = | |
288 | ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt); | |
289 | dd->ipath_rcvegrbase = | |
290 | ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrbase); | |
291 | dd->ipath_palign = | |
292 | ipath_read_kreg32(dd, dd->ipath_kregs->kr_pagealign); | |
293 | dd->ipath_piobufbase = | |
294 | ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiobufbase); | |
295 | val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiosize); | |
296 | dd->ipath_piosize2k = val & ~0U; | |
297 | dd->ipath_piosize4k = val >> 32; | |
e7340f04 RW |
298 | /* |
299 | * Note: the chips support a maximum MTU of 4096, but the driver | |
300 | * hasn't implemented this feature yet, so set the initial value | |
301 | * to 2048. | |
302 | */ | |
303 | dd->ipath_ibmtu = 2048; | |
097709fe BS |
304 | val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiobufcnt); |
305 | dd->ipath_piobcnt2k = val & ~0U; | |
306 | dd->ipath_piobcnt4k = val >> 32; | |
307 | dd->ipath_pio2kbase = | |
308 | (u32 __iomem *) (((char __iomem *) dd->ipath_kregbase) + | |
309 | (dd->ipath_piobufbase & 0xffffffff)); | |
310 | if (dd->ipath_piobcnt4k) { | |
311 | dd->ipath_pio4kbase = (u32 __iomem *) | |
312 | (((char __iomem *) dd->ipath_kregbase) + | |
313 | (dd->ipath_piobufbase >> 32)); | |
314 | /* | |
315 | * 4K buffers take 2 pages; we use roundup just to be | |
316 | * paranoid; we calculate it once here, rather than on | |
317 | * ever buf allocate | |
318 | */ | |
319 | dd->ipath_4kalign = ALIGN(dd->ipath_piosize4k, | |
320 | dd->ipath_palign); | |
321 | ipath_dbg("%u 2k(%x) piobufs @ %p, %u 4k(%x) @ %p " | |
322 | "(%x aligned)\n", | |
323 | dd->ipath_piobcnt2k, dd->ipath_piosize2k, | |
324 | dd->ipath_pio2kbase, dd->ipath_piobcnt4k, | |
325 | dd->ipath_piosize4k, dd->ipath_pio4kbase, | |
326 | dd->ipath_4kalign); | |
327 | } | |
328 | else ipath_dbg("%u 2k piobufs @ %p\n", | |
329 | dd->ipath_piobcnt2k, dd->ipath_pio2kbase); | |
330 | ||
331 | spin_lock_init(&dd->ipath_tid_lock); | |
e342c119 | 332 | spin_lock_init(&dd->ipath_sendctrl_lock); |
17b2eb9f | 333 | spin_lock_init(&dd->ipath_gpio_lock); |
aecd3b5a | 334 | spin_lock_init(&dd->ipath_eep_st_lock); |
2c45688f | 335 | mutex_init(&dd->ipath_eep_lock); |
17b2eb9f | 336 | |
097709fe BS |
337 | done: |
338 | *pdp = pd; | |
339 | return ret; | |
340 | } | |
341 | ||
342 | /** | |
343 | * init_chip_reset - re-initialize after a reset, or enable | |
344 | * @dd: the infinipath device | |
345 | * @pdp: output for port data | |
346 | * | |
347 | * sanity check at least some of the values after reset, and | |
348 | * ensure no receive or transmit (explictly, in case reset | |
349 | * failed | |
350 | */ | |
351 | static int init_chip_reset(struct ipath_devdata *dd, | |
352 | struct ipath_portdata **pdp) | |
353 | { | |
097709fe BS |
354 | u32 rtmp; |
355 | ||
44f8e3f3 | 356 | *pdp = dd->ipath_pd[0]; |
097709fe BS |
357 | /* ensure chip does no sends or receives while we re-initialize */ |
358 | dd->ipath_control = dd->ipath_sendctrl = dd->ipath_rcvctrl = 0U; | |
e342c119 JG |
359 | ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl, dd->ipath_rcvctrl); |
360 | ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl); | |
361 | ipath_write_kreg(dd, dd->ipath_kregs->kr_control, dd->ipath_control); | |
097709fe BS |
362 | |
363 | rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_portcnt); | |
364 | if (dd->ipath_portcnt != rtmp) | |
365 | dev_info(&dd->pcidev->dev, "portcnt was %u before " | |
366 | "reset, now %u, using original\n", | |
367 | dd->ipath_portcnt, rtmp); | |
368 | rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidcnt); | |
369 | if (rtmp != dd->ipath_rcvtidcnt) | |
370 | dev_info(&dd->pcidev->dev, "tidcnt was %u before " | |
371 | "reset, now %u, using original\n", | |
372 | dd->ipath_rcvtidcnt, rtmp); | |
373 | rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidbase); | |
374 | if (rtmp != dd->ipath_rcvtidbase) | |
375 | dev_info(&dd->pcidev->dev, "tidbase was %u before " | |
376 | "reset, now %u, using original\n", | |
377 | dd->ipath_rcvtidbase, rtmp); | |
378 | rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt); | |
379 | if (rtmp != dd->ipath_rcvegrcnt) | |
380 | dev_info(&dd->pcidev->dev, "egrcnt was %u before " | |
381 | "reset, now %u, using original\n", | |
382 | dd->ipath_rcvegrcnt, rtmp); | |
383 | rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrbase); | |
384 | if (rtmp != dd->ipath_rcvegrbase) | |
385 | dev_info(&dd->pcidev->dev, "egrbase was %u before " | |
386 | "reset, now %u, using original\n", | |
387 | dd->ipath_rcvegrbase, rtmp); | |
388 | ||
389 | return 0; | |
390 | } | |
391 | ||
392 | static int init_pioavailregs(struct ipath_devdata *dd) | |
393 | { | |
394 | int ret; | |
395 | ||
396 | dd->ipath_pioavailregs_dma = dma_alloc_coherent( | |
397 | &dd->pcidev->dev, PAGE_SIZE, &dd->ipath_pioavailregs_phys, | |
398 | GFP_KERNEL); | |
399 | if (!dd->ipath_pioavailregs_dma) { | |
400 | ipath_dev_err(dd, "failed to allocate PIOavail reg area " | |
401 | "in memory\n"); | |
402 | ret = -ENOMEM; | |
403 | goto done; | |
404 | } | |
405 | ||
406 | /* | |
407 | * we really want L2 cache aligned, but for current CPUs of | |
408 | * interest, they are the same. | |
409 | */ | |
410 | dd->ipath_statusp = (u64 *) | |
411 | ((char *)dd->ipath_pioavailregs_dma + | |
412 | ((2 * L1_CACHE_BYTES + | |
413 | dd->ipath_pioavregs * sizeof(u64)) & ~L1_CACHE_BYTES)); | |
414 | /* copy the current value now that it's really allocated */ | |
415 | *dd->ipath_statusp = dd->_ipath_status; | |
416 | /* | |
417 | * setup buffer to hold freeze msg, accessible to apps, | |
418 | * following statusp | |
419 | */ | |
420 | dd->ipath_freezemsg = (char *)&dd->ipath_statusp[1]; | |
421 | /* and its length */ | |
422 | dd->ipath_freezelen = L1_CACHE_BYTES - sizeof(dd->ipath_statusp[0]); | |
423 | ||
f37bda92 | 424 | ret = 0; |
097709fe | 425 | |
097709fe BS |
426 | done: |
427 | return ret; | |
428 | } | |
429 | ||
430 | /** | |
431 | * init_shadow_tids - allocate the shadow TID array | |
432 | * @dd: the infinipath device | |
433 | * | |
434 | * allocate the shadow TID array, so we can ipath_munlock previous | |
435 | * entries. It may make more sense to move the pageshadow to the | |
436 | * port data structure, so we only allocate memory for ports actually | |
437 | * in use, since we at 8k per port, now. | |
438 | */ | |
439 | static void init_shadow_tids(struct ipath_devdata *dd) | |
440 | { | |
1fd3b40f BS |
441 | struct page **pages; |
442 | dma_addr_t *addrs; | |
443 | ||
444 | pages = vmalloc(dd->ipath_cfgports * dd->ipath_rcvtidcnt * | |
097709fe | 445 | sizeof(struct page *)); |
1fd3b40f | 446 | if (!pages) { |
097709fe BS |
447 | ipath_dev_err(dd, "failed to allocate shadow page * " |
448 | "array, no expected sends!\n"); | |
1fd3b40f BS |
449 | dd->ipath_pageshadow = NULL; |
450 | return; | |
451 | } | |
452 | ||
453 | addrs = vmalloc(dd->ipath_cfgports * dd->ipath_rcvtidcnt * | |
454 | sizeof(dma_addr_t)); | |
455 | if (!addrs) { | |
456 | ipath_dev_err(dd, "failed to allocate shadow dma handle " | |
457 | "array, no expected sends!\n"); | |
458 | vfree(dd->ipath_pageshadow); | |
459 | dd->ipath_pageshadow = NULL; | |
460 | return; | |
461 | } | |
462 | ||
463 | memset(pages, 0, dd->ipath_cfgports * dd->ipath_rcvtidcnt * | |
464 | sizeof(struct page *)); | |
465 | ||
466 | dd->ipath_pageshadow = pages; | |
467 | dd->ipath_physshadow = addrs; | |
097709fe BS |
468 | } |
469 | ||
470 | static void enable_chip(struct ipath_devdata *dd, | |
471 | struct ipath_portdata *pd, int reinit) | |
472 | { | |
473 | u32 val; | |
e342c119 | 474 | unsigned long flags; |
097709fe BS |
475 | int i; |
476 | ||
0fd41363 BS |
477 | if (!reinit) |
478 | init_waitqueue_head(&ipath_state_wait); | |
479 | ||
097709fe BS |
480 | ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl, |
481 | dd->ipath_rcvctrl); | |
482 | ||
e342c119 | 483 | spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags); |
097709fe BS |
484 | /* Enable PIO send, and update of PIOavail regs to memory. */ |
485 | dd->ipath_sendctrl = INFINIPATH_S_PIOENABLE | | |
486 | INFINIPATH_S_PIOBUFAVAILUPD; | |
e342c119 JG |
487 | ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl); |
488 | ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch); | |
489 | spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags); | |
097709fe BS |
490 | |
491 | /* | |
492 | * enable port 0 receive, and receive interrupt. other ports | |
493 | * done as user opens and inits them. | |
494 | */ | |
d8274869 DO |
495 | dd->ipath_rcvctrl = (1ULL << dd->ipath_r_tailupd_shift) | |
496 | (1ULL << dd->ipath_r_portenable_shift) | | |
497 | (1ULL << dd->ipath_r_intravail_shift); | |
097709fe BS |
498 | ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl, |
499 | dd->ipath_rcvctrl); | |
500 | ||
501 | /* | |
502 | * now ready for use. this should be cleared whenever we | |
503 | * detect a reset, or initiate one. | |
504 | */ | |
505 | dd->ipath_flags |= IPATH_INITTED; | |
506 | ||
507 | /* | |
508 | * init our shadow copies of head from tail values, and write | |
509 | * head values to match. | |
510 | */ | |
511 | val = ipath_read_ureg32(dd, ur_rcvegrindextail, 0); | |
512 | (void)ipath_write_ureg(dd, ur_rcvegrindexhead, val, 0); | |
097709fe BS |
513 | |
514 | /* Initialize so we interrupt on next packet received */ | |
515 | (void)ipath_write_ureg(dd, ur_rcvhdrhead, | |
516 | dd->ipath_rhdrhead_intr_off | | |
c59a80ac | 517 | dd->ipath_pd[0]->port_head, 0); |
097709fe BS |
518 | |
519 | /* | |
520 | * by now pioavail updates to memory should have occurred, so | |
521 | * copy them into our working/shadow registers; this is in | |
522 | * case something went wrong with abort, but mostly to get the | |
523 | * initial values of the generation bit correct. | |
524 | */ | |
525 | for (i = 0; i < dd->ipath_pioavregs; i++) { | |
6358ae25 | 526 | __le64 pioavail; |
097709fe BS |
527 | |
528 | /* | |
529 | * Chip Errata bug 6641; even and odd qwords>3 are swapped. | |
530 | */ | |
4ea61b54 | 531 | if (i > 3 && (dd->ipath_flags & IPATH_SWAP_PIOBUFS)) |
6358ae25 | 532 | pioavail = dd->ipath_pioavailregs_dma[i ^ 1]; |
097709fe | 533 | else |
6358ae25 RD |
534 | pioavail = dd->ipath_pioavailregs_dma[i]; |
535 | dd->ipath_pioavailshadow[i] = le64_to_cpu(pioavail); | |
097709fe BS |
536 | } |
537 | /* can get counters, stats, etc. */ | |
538 | dd->ipath_flags |= IPATH_PRESENT; | |
539 | } | |
540 | ||
541 | static int init_housekeeping(struct ipath_devdata *dd, | |
542 | struct ipath_portdata **pdp, int reinit) | |
543 | { | |
544 | char boardn[32]; | |
545 | int ret = 0; | |
546 | ||
547 | /* | |
548 | * have to clear shadow copies of registers at init that are | |
549 | * not otherwise set here, or all kinds of bizarre things | |
550 | * happen with driver on chip reset | |
551 | */ | |
552 | dd->ipath_rcvhdrsize = 0; | |
553 | ||
554 | /* | |
555 | * Don't clear ipath_flags as 8bit mode was set before | |
556 | * entering this func. However, we do set the linkstate to | |
557 | * unknown, so we can watch for a transition. | |
52e7fad8 BS |
558 | * PRESENT is set because we want register reads to work, |
559 | * and the kernel infrastructure saw it in config space; | |
560 | * We clear it if we have failures. | |
097709fe | 561 | */ |
52e7fad8 | 562 | dd->ipath_flags |= IPATH_LINKUNK | IPATH_PRESENT; |
097709fe BS |
563 | dd->ipath_flags &= ~(IPATH_LINKACTIVE | IPATH_LINKARMED | |
564 | IPATH_LINKDOWN | IPATH_LINKINIT); | |
565 | ||
566 | ipath_cdbg(VERBOSE, "Try to read spc chip revision\n"); | |
567 | dd->ipath_revision = | |
568 | ipath_read_kreg64(dd, dd->ipath_kregs->kr_revision); | |
569 | ||
570 | /* | |
571 | * set up fundamental info we need to use the chip; we assume | |
572 | * if the revision reg and these regs are OK, we don't need to | |
573 | * special case the rest | |
574 | */ | |
575 | dd->ipath_sregbase = | |
576 | ipath_read_kreg32(dd, dd->ipath_kregs->kr_sendregbase); | |
577 | dd->ipath_cregbase = | |
578 | ipath_read_kreg32(dd, dd->ipath_kregs->kr_counterregbase); | |
579 | dd->ipath_uregbase = | |
580 | ipath_read_kreg32(dd, dd->ipath_kregs->kr_userregbase); | |
581 | ipath_cdbg(VERBOSE, "ipath_kregbase %p, sendbase %x usrbase %x, " | |
582 | "cntrbase %x\n", dd->ipath_kregbase, dd->ipath_sregbase, | |
583 | dd->ipath_uregbase, dd->ipath_cregbase); | |
584 | if ((dd->ipath_revision & 0xffffffff) == 0xffffffff | |
585 | || (dd->ipath_sregbase & 0xffffffff) == 0xffffffff | |
586 | || (dd->ipath_cregbase & 0xffffffff) == 0xffffffff | |
587 | || (dd->ipath_uregbase & 0xffffffff) == 0xffffffff) { | |
588 | ipath_dev_err(dd, "Register read failures from chip, " | |
589 | "giving up initialization\n"); | |
52e7fad8 | 590 | dd->ipath_flags &= ~IPATH_PRESENT; |
097709fe BS |
591 | ret = -ENODEV; |
592 | goto done; | |
593 | } | |
594 | ||
9783ab40 BS |
595 | |
596 | /* clear diagctrl register, in case diags were running and crashed */ | |
597 | ipath_write_kreg (dd, dd->ipath_kregs->kr_hwdiagctrl, 0); | |
598 | ||
097709fe BS |
599 | /* clear the initial reset flag, in case first driver load */ |
600 | ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, | |
601 | INFINIPATH_E_RESET); | |
602 | ||
603 | if (reinit) | |
604 | ret = init_chip_reset(dd, pdp); | |
605 | else | |
606 | ret = init_chip_first(dd, pdp); | |
607 | ||
608 | if (ret) | |
609 | goto done; | |
610 | ||
611 | ipath_cdbg(VERBOSE, "Revision %llx (PCI %x), %u ports, %u tids, " | |
612 | "%u egrtids\n", (unsigned long long) dd->ipath_revision, | |
613 | dd->ipath_pcirev, dd->ipath_portcnt, dd->ipath_rcvtidcnt, | |
614 | dd->ipath_rcvegrcnt); | |
615 | ||
616 | if (((dd->ipath_revision >> INFINIPATH_R_SOFTWARE_SHIFT) & | |
617 | INFINIPATH_R_SOFTWARE_MASK) != IPATH_CHIP_SWVERSION) { | |
618 | ipath_dev_err(dd, "Driver only handles version %d, " | |
619 | "chip swversion is %d (%llx), failng\n", | |
620 | IPATH_CHIP_SWVERSION, | |
621 | (int)(dd->ipath_revision >> | |
622 | INFINIPATH_R_SOFTWARE_SHIFT) & | |
623 | INFINIPATH_R_SOFTWARE_MASK, | |
624 | (unsigned long long) dd->ipath_revision); | |
625 | ret = -ENOSYS; | |
626 | goto done; | |
627 | } | |
628 | dd->ipath_majrev = (u8) ((dd->ipath_revision >> | |
629 | INFINIPATH_R_CHIPREVMAJOR_SHIFT) & | |
630 | INFINIPATH_R_CHIPREVMAJOR_MASK); | |
631 | dd->ipath_minrev = (u8) ((dd->ipath_revision >> | |
632 | INFINIPATH_R_CHIPREVMINOR_SHIFT) & | |
633 | INFINIPATH_R_CHIPREVMINOR_MASK); | |
634 | dd->ipath_boardrev = (u8) ((dd->ipath_revision >> | |
635 | INFINIPATH_R_BOARDID_SHIFT) & | |
636 | INFINIPATH_R_BOARDID_MASK); | |
637 | ||
638 | ret = dd->ipath_f_get_boardname(dd, boardn, sizeof boardn); | |
639 | ||
640 | snprintf(dd->ipath_boardversion, sizeof(dd->ipath_boardversion), | |
12f9a49e | 641 | "ChipABI %u.%u, %s, InfiniPath%u %u.%u, PCI %u, " |
097709fe BS |
642 | "SW Compat %u\n", |
643 | IPATH_CHIP_VERS_MAJ, IPATH_CHIP_VERS_MIN, boardn, | |
644 | (unsigned)(dd->ipath_revision >> INFINIPATH_R_ARCH_SHIFT) & | |
645 | INFINIPATH_R_ARCH_MASK, | |
646 | dd->ipath_majrev, dd->ipath_minrev, dd->ipath_pcirev, | |
647 | (unsigned)(dd->ipath_revision >> | |
648 | INFINIPATH_R_SOFTWARE_SHIFT) & | |
649 | INFINIPATH_R_SOFTWARE_MASK); | |
650 | ||
651 | ipath_dbg("%s", dd->ipath_boardversion); | |
652 | ||
653 | done: | |
654 | return ret; | |
655 | } | |
656 | ||
657 | ||
658 | /** | |
659 | * ipath_init_chip - do the actual initialization sequence on the chip | |
660 | * @dd: the infinipath device | |
661 | * @reinit: reinitializing, so don't allocate new memory | |
662 | * | |
663 | * Do the actual initialization sequence on the chip. This is done | |
664 | * both from the init routine called from the PCI infrastructure, and | |
665 | * when we reset the chip, or detect that it was reset internally, | |
666 | * or it's administratively re-enabled. | |
667 | * | |
668 | * Memory allocation here and in called routines is only done in | |
669 | * the first case (reinit == 0). We have to be careful, because even | |
670 | * without memory allocation, we need to re-write all the chip registers | |
671 | * TIDs, etc. after the reset or enable has completed. | |
672 | */ | |
673 | int ipath_init_chip(struct ipath_devdata *dd, int reinit) | |
674 | { | |
c59a80ac | 675 | int ret = 0; |
097709fe | 676 | u32 val32, kpiobufs; |
0ed3c594 | 677 | u32 piobufs, uports; |
f37bda92 | 678 | u64 val; |
097709fe | 679 | struct ipath_portdata *pd = NULL; /* keep gcc4 happy */ |
35783ec0 | 680 | gfp_t gfp_flags = GFP_USER | __GFP_COMP; |
e342c119 | 681 | unsigned long flags; |
097709fe BS |
682 | |
683 | ret = init_housekeeping(dd, &pd, reinit); | |
684 | if (ret) | |
685 | goto done; | |
686 | ||
687 | /* | |
688 | * we ignore most issues after reporting them, but have to specially | |
689 | * handle hardware-disabled chips. | |
690 | */ | |
691 | if (ret == 2) { | |
692 | /* unique error, known to ipath_init_one */ | |
693 | ret = -EPERM; | |
694 | goto done; | |
695 | } | |
696 | ||
697 | /* | |
698 | * We could bump this to allow for full rcvegrcnt + rcvtidcnt, | |
699 | * but then it no longer nicely fits power of two, and since | |
700 | * we now use routines that backend onto __get_free_pages, the | |
701 | * rest would be wasted. | |
702 | */ | |
703 | dd->ipath_rcvhdrcnt = dd->ipath_rcvegrcnt; | |
704 | ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrcnt, | |
705 | dd->ipath_rcvhdrcnt); | |
706 | ||
707 | /* | |
708 | * Set up the shadow copies of the piobufavail registers, | |
709 | * which we compare against the chip registers for now, and | |
710 | * the in memory DMA'ed copies of the registers. This has to | |
711 | * be done early, before we calculate lastport, etc. | |
712 | */ | |
0ed3c594 | 713 | piobufs = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k; |
097709fe BS |
714 | /* |
715 | * calc number of pioavail registers, and save it; we have 2 | |
716 | * bits per buffer. | |
717 | */ | |
0ed3c594 | 718 | dd->ipath_pioavregs = ALIGN(piobufs, sizeof(u64) * BITS_PER_BYTE / 2) |
097709fe | 719 | / (sizeof(u64) * BITS_PER_BYTE / 2); |
0ed3c594 | 720 | uports = dd->ipath_cfgports ? dd->ipath_cfgports - 1 : 0; |
52e7fad8 | 721 | if (ipath_kpiobufs == 0) { |
ba11203a | 722 | /* not set by user (this is default) */ |
37a7e9b7 | 723 | if (piobufs > 144) |
52e7fad8 BS |
724 | kpiobufs = 32; |
725 | else | |
726 | kpiobufs = 16; | |
727 | } | |
728 | else | |
097709fe BS |
729 | kpiobufs = ipath_kpiobufs; |
730 | ||
0ed3c594 | 731 | if (kpiobufs + (uports * IPATH_MIN_USER_PORT_BUFCNT) > piobufs) { |
c59a80ac | 732 | int i = (int) piobufs - |
0ed3c594 | 733 | (int) (uports * IPATH_MIN_USER_PORT_BUFCNT); |
097709fe BS |
734 | if (i < 0) |
735 | i = 0; | |
0ed3c594 BS |
736 | dev_info(&dd->pcidev->dev, "Allocating %d PIO bufs of " |
737 | "%d for kernel leaves too few for %d user ports " | |
097709fe | 738 | "(%d each); using %u\n", kpiobufs, |
0ed3c594 | 739 | piobufs, uports, IPATH_MIN_USER_PORT_BUFCNT, i); |
097709fe BS |
740 | /* |
741 | * shouldn't change ipath_kpiobufs, because could be | |
742 | * different for different devices... | |
743 | */ | |
744 | kpiobufs = i; | |
745 | } | |
0ed3c594 BS |
746 | dd->ipath_lastport_piobuf = piobufs - kpiobufs; |
747 | dd->ipath_pbufsport = | |
748 | uports ? dd->ipath_lastport_piobuf / uports : 0; | |
749 | val32 = dd->ipath_lastport_piobuf - (dd->ipath_pbufsport * uports); | |
097709fe BS |
750 | if (val32 > 0) { |
751 | ipath_dbg("allocating %u pbufs/port leaves %u unused, " | |
752 | "add to kernel\n", dd->ipath_pbufsport, val32); | |
753 | dd->ipath_lastport_piobuf -= val32; | |
754 | ipath_dbg("%u pbufs/port leaves %u unused, add to kernel\n", | |
755 | dd->ipath_pbufsport, val32); | |
756 | } | |
757 | dd->ipath_lastpioindex = dd->ipath_lastport_piobuf; | |
758 | ipath_cdbg(VERBOSE, "%d PIO bufs for kernel out of %d total %u " | |
759 | "each for %u user ports\n", kpiobufs, | |
0ed3c594 | 760 | piobufs, dd->ipath_pbufsport, uports); |
097709fe BS |
761 | |
762 | dd->ipath_f_early_init(dd); | |
9380068f DO |
763 | /* |
764 | * cancel any possible active sends from early driver load. | |
765 | * Follows early_init because some chips have to initialize | |
766 | * PIO buffers in early_init to avoid false parity errors. | |
767 | */ | |
3810f2a8 | 768 | ipath_cancel_sends(dd, 0); |
097709fe BS |
769 | |
770 | /* early_init sets rcvhdrentsize and rcvhdrsize, so this must be | |
771 | * done after early_init */ | |
772 | dd->ipath_hdrqlast = | |
773 | dd->ipath_rcvhdrentsize * (dd->ipath_rcvhdrcnt - 1); | |
774 | ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrentsize, | |
775 | dd->ipath_rcvhdrentsize); | |
776 | ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrsize, | |
777 | dd->ipath_rcvhdrsize); | |
778 | ||
779 | if (!reinit) { | |
780 | ret = init_pioavailregs(dd); | |
781 | init_shadow_tids(dd); | |
782 | if (ret) | |
783 | goto done; | |
784 | } | |
785 | ||
786 | (void)ipath_write_kreg(dd, dd->ipath_kregs->kr_sendpioavailaddr, | |
787 | dd->ipath_pioavailregs_phys); | |
788 | /* | |
789 | * this is to detect s/w errors, which the h/w works around by | |
790 | * ignoring the low 6 bits of address, if it wasn't aligned. | |
791 | */ | |
792 | val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpioavailaddr); | |
793 | if (val != dd->ipath_pioavailregs_phys) { | |
794 | ipath_dev_err(dd, "Catastrophic software error, " | |
795 | "SendPIOAvailAddr written as %lx, " | |
796 | "read back as %llx\n", | |
797 | (unsigned long) dd->ipath_pioavailregs_phys, | |
798 | (unsigned long long) val); | |
799 | ret = -EINVAL; | |
800 | goto done; | |
801 | } | |
802 | ||
097709fe BS |
803 | ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvbthqp, IPATH_KD_QP); |
804 | ||
805 | /* | |
806 | * make sure we are not in freeze, and PIO send enabled, so | |
807 | * writes to pbc happen | |
808 | */ | |
809 | ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask, 0ULL); | |
810 | ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear, | |
811 | ~0ULL&~INFINIPATH_HWE_MEMBISTFAILED); | |
812 | ipath_write_kreg(dd, dd->ipath_kregs->kr_control, 0ULL); | |
e342c119 JG |
813 | |
814 | spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags); | |
815 | dd->ipath_sendctrl = INFINIPATH_S_PIOENABLE; | |
816 | ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl); | |
817 | ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch); | |
818 | spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags); | |
097709fe BS |
819 | |
820 | /* | |
821 | * before error clears, since we expect serdes pll errors during | |
822 | * this, the first time after reset | |
823 | */ | |
824 | if (bringup_link(dd)) { | |
825 | dev_info(&dd->pcidev->dev, "Failed to bringup IB link\n"); | |
826 | ret = -ENETDOWN; | |
827 | goto done; | |
828 | } | |
829 | ||
830 | /* | |
831 | * clear any "expected" hwerrs from reset and/or initialization | |
832 | * clear any that aren't enabled (at least this once), and then | |
833 | * set the enable mask | |
834 | */ | |
835 | dd->ipath_f_init_hwerrors(dd); | |
836 | ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear, | |
837 | ~0ULL&~INFINIPATH_HWE_MEMBISTFAILED); | |
838 | ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask, | |
839 | dd->ipath_hwerrmask); | |
840 | ||
097709fe BS |
841 | /* clear all */ |
842 | ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, -1LL); | |
843 | /* enable errors that are masked, at least this first time. */ | |
844 | ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask, | |
845 | ~dd->ipath_maskederrs); | |
78d1e02f DO |
846 | dd->ipath_errormask = ipath_read_kreg64(dd, |
847 | dd->ipath_kregs->kr_errormask); | |
848 | /* clear any interrupts up to this point (ints still not enabled) */ | |
097709fe BS |
849 | ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, -1LL); |
850 | ||
097709fe BS |
851 | /* |
852 | * Set up the port 0 (kernel) rcvhdr q and egr TIDs. If doing | |
853 | * re-init, the simplest way to handle this is to free | |
854 | * existing, and re-allocate. | |
27b044a8 | 855 | * Need to re-create rest of port 0 portdata as well. |
097709fe | 856 | */ |
f37bda92 | 857 | if (reinit) { |
27b044a8 MA |
858 | /* Alloc and init new ipath_portdata for port0, |
859 | * Then free old pd. Could lead to fragmentation, but also | |
860 | * makes later support for hot-swap easier. | |
861 | */ | |
862 | struct ipath_portdata *npd; | |
863 | npd = create_portdata0(dd); | |
864 | if (npd) { | |
865 | ipath_free_pddata(dd, pd); | |
866 | dd->ipath_pd[0] = pd = npd; | |
867 | } else { | |
868 | ipath_dev_err(dd, "Unable to allocate portdata for" | |
869 | " port 0, failing\n"); | |
870 | ret = -ENOMEM; | |
871 | goto done; | |
872 | } | |
f37bda92 | 873 | } |
097709fe BS |
874 | dd->ipath_f_tidtemplate(dd); |
875 | ret = ipath_create_rcvhdrq(dd, pd); | |
f37bda92 BS |
876 | if (!ret) { |
877 | dd->ipath_hdrqtailptr = | |
878 | (volatile __le64 *)pd->port_rcvhdrtail_kvaddr; | |
097709fe | 879 | ret = create_port0_egr(dd); |
f37bda92 | 880 | } |
097709fe BS |
881 | if (ret) |
882 | ipath_dev_err(dd, "failed to allocate port 0 (kernel) " | |
883 | "rcvhdrq and/or egr bufs\n"); | |
884 | else | |
885 | enable_chip(dd, pd, reinit); | |
886 | ||
35783ec0 BS |
887 | |
888 | if (!ret && !reinit) { | |
889 | /* used when we close a port, for DMA already in flight at close */ | |
890 | dd->ipath_dummy_hdrq = dma_alloc_coherent( | |
891 | &dd->pcidev->dev, pd->port_rcvhdrq_size, | |
892 | &dd->ipath_dummy_hdrq_phys, | |
893 | gfp_flags); | |
894 | if (!dd->ipath_dummy_hdrq ) { | |
895 | dev_info(&dd->pcidev->dev, | |
896 | "Couldn't allocate 0x%lx bytes for dummy hdrq\n", | |
897 | pd->port_rcvhdrq_size); | |
898 | /* fallback to just 0'ing */ | |
899 | dd->ipath_dummy_hdrq_phys = 0UL; | |
900 | } | |
901 | } | |
902 | ||
097709fe BS |
903 | /* |
904 | * cause retrigger of pending interrupts ignored during init, | |
905 | * even if we had errors | |
906 | */ | |
907 | ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, 0ULL); | |
908 | ||
909 | if(!dd->ipath_stats_timer_active) { | |
910 | /* | |
911 | * first init, or after an admin disable/enable | |
912 | * set up stats retrieval timer, even if we had errors | |
913 | * in last portion of setup | |
914 | */ | |
915 | init_timer(&dd->ipath_stats_timer); | |
916 | dd->ipath_stats_timer.function = ipath_get_faststats; | |
917 | dd->ipath_stats_timer.data = (unsigned long) dd; | |
918 | /* every 5 seconds; */ | |
919 | dd->ipath_stats_timer.expires = jiffies + 5 * HZ; | |
920 | /* takes ~16 seconds to overflow at full IB 4x bandwdith */ | |
921 | add_timer(&dd->ipath_stats_timer); | |
922 | dd->ipath_stats_timer_active = 1; | |
923 | } | |
924 | ||
925 | done: | |
926 | if (!ret) { | |
097709fe BS |
927 | *dd->ipath_statusp |= IPATH_STATUS_CHIP_PRESENT; |
928 | if (!dd->ipath_f_intrsetup(dd)) { | |
929 | /* now we can enable all interrupts from the chip */ | |
930 | ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, | |
931 | -1LL); | |
932 | /* force re-interrupt of any pending interrupts. */ | |
933 | ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, | |
934 | 0ULL); | |
935 | /* chip is usable; mark it as initialized */ | |
936 | *dd->ipath_statusp |= IPATH_STATUS_INITTED; | |
937 | } else | |
938 | ipath_dev_err(dd, "No interrupts enabled, couldn't " | |
939 | "setup interrupt address\n"); | |
940 | ||
941 | if (dd->ipath_cfgports > ipath_stats.sps_nports) | |
942 | /* | |
943 | * sps_nports is a global, so, we set it to | |
944 | * the highest number of ports of any of the | |
945 | * chips we find; we never decrement it, at | |
946 | * least for now. Since this might have changed | |
947 | * over disable/enable or prior to reset, always | |
948 | * do the check and potentially adjust. | |
949 | */ | |
950 | ipath_stats.sps_nports = dd->ipath_cfgports; | |
951 | } else | |
952 | ipath_dbg("Failed (%d) to initialize chip\n", ret); | |
953 | ||
954 | /* if ret is non-zero, we probably should do some cleanup | |
955 | here... */ | |
956 | return ret; | |
957 | } | |
958 | ||
959 | static int ipath_set_kpiobufs(const char *str, struct kernel_param *kp) | |
960 | { | |
961 | struct ipath_devdata *dd; | |
962 | unsigned long flags; | |
963 | unsigned short val; | |
964 | int ret; | |
965 | ||
966 | ret = ipath_parse_ushort(str, &val); | |
967 | ||
968 | spin_lock_irqsave(&ipath_devs_lock, flags); | |
969 | ||
970 | if (ret < 0) | |
971 | goto bail; | |
972 | ||
973 | if (val == 0) { | |
974 | ret = -EINVAL; | |
975 | goto bail; | |
976 | } | |
977 | ||
978 | list_for_each_entry(dd, &ipath_dev_list, ipath_list) { | |
979 | if (dd->ipath_kregbase) | |
980 | continue; | |
981 | if (val > (dd->ipath_piobcnt2k + dd->ipath_piobcnt4k - | |
982 | (dd->ipath_cfgports * | |
983 | IPATH_MIN_USER_PORT_BUFCNT))) | |
984 | { | |
985 | ipath_dev_err( | |
986 | dd, | |
987 | "Allocating %d PIO bufs for kernel leaves " | |
988 | "too few for %d user ports (%d each)\n", | |
989 | val, dd->ipath_cfgports - 1, | |
990 | IPATH_MIN_USER_PORT_BUFCNT); | |
991 | ret = -EINVAL; | |
992 | goto bail; | |
993 | } | |
994 | dd->ipath_lastport_piobuf = | |
995 | dd->ipath_piobcnt2k + dd->ipath_piobcnt4k - val; | |
996 | } | |
997 | ||
ba11203a | 998 | ipath_kpiobufs = val; |
097709fe BS |
999 | ret = 0; |
1000 | bail: | |
1001 | spin_unlock_irqrestore(&ipath_devs_lock, flags); | |
1002 | ||
1003 | return ret; | |
1004 | } |