Commit | Line | Data |
---|---|---|
22d199a5 SS |
1 | /* |
2 | * Industrial I/O driver for Microchip digital potentiometers | |
3 | * | |
4 | * Copyright (c) 2016 Slawomir Stepien | |
5 | * Based on: Peter Rosin's code from mcp4531.c | |
6 | * | |
7 | * Datasheet: http://ww1.microchip.com/downloads/en/DeviceDoc/22060b.pdf | |
8 | * | |
9 | * DEVID #Wipers #Positions Resistor Opts (kOhm) | |
10 | * mcp4131 1 129 5, 10, 50, 100 | |
11 | * mcp4132 1 129 5, 10, 50, 100 | |
12 | * mcp4141 1 129 5, 10, 50, 100 | |
13 | * mcp4142 1 129 5, 10, 50, 100 | |
14 | * mcp4151 1 257 5, 10, 50, 100 | |
15 | * mcp4152 1 257 5, 10, 50, 100 | |
16 | * mcp4161 1 257 5, 10, 50, 100 | |
17 | * mcp4162 1 257 5, 10, 50, 100 | |
18 | * mcp4231 2 129 5, 10, 50, 100 | |
19 | * mcp4232 2 129 5, 10, 50, 100 | |
20 | * mcp4241 2 129 5, 10, 50, 100 | |
21 | * mcp4242 2 129 5, 10, 50, 100 | |
22 | * mcp4251 2 257 5, 10, 50, 100 | |
23 | * mcp4252 2 257 5, 10, 50, 100 | |
24 | * mcp4261 2 257 5, 10, 50, 100 | |
25 | * mcp4262 2 257 5, 10, 50, 100 | |
26 | * | |
27 | * This program is free software; you can redistribute it and/or modify it | |
28 | * under the terms of the GNU General Public License version 2 as published by | |
29 | * the Free Software Foundation. | |
30 | */ | |
31 | ||
32 | /* | |
33 | * TODO: | |
34 | * 1. Write wiper setting to EEPROM for EEPROM capable models. | |
35 | */ | |
36 | ||
37 | #include <linux/cache.h> | |
38 | #include <linux/err.h> | |
39 | #include <linux/export.h> | |
40 | #include <linux/iio/iio.h> | |
41 | #include <linux/iio/types.h> | |
42 | #include <linux/module.h> | |
43 | #include <linux/mutex.h> | |
44 | #include <linux/of.h> | |
45 | #include <linux/spi/spi.h> | |
46 | ||
47 | #define MCP4131_WRITE (0x00 << 2) | |
48 | #define MCP4131_READ (0x03 << 2) | |
49 | ||
50 | #define MCP4131_WIPER_SHIFT 4 | |
51 | #define MCP4131_CMDERR(r) ((r[0]) & 0x02) | |
52 | #define MCP4131_RAW(r) ((r[0]) == 0xff ? 0x100 : (r[1])) | |
53 | ||
54 | struct mcp4131_cfg { | |
55 | int wipers; | |
56 | int max_pos; | |
57 | int kohms; | |
58 | }; | |
59 | ||
60 | enum mcp4131_type { | |
61 | MCP413x_502 = 0, | |
62 | MCP413x_103, | |
63 | MCP413x_503, | |
64 | MCP413x_104, | |
65 | MCP414x_502, | |
66 | MCP414x_103, | |
67 | MCP414x_503, | |
68 | MCP414x_104, | |
69 | MCP415x_502, | |
70 | MCP415x_103, | |
71 | MCP415x_503, | |
72 | MCP415x_104, | |
73 | MCP416x_502, | |
74 | MCP416x_103, | |
75 | MCP416x_503, | |
76 | MCP416x_104, | |
77 | MCP423x_502, | |
78 | MCP423x_103, | |
79 | MCP423x_503, | |
80 | MCP423x_104, | |
81 | MCP424x_502, | |
82 | MCP424x_103, | |
83 | MCP424x_503, | |
84 | MCP424x_104, | |
85 | MCP425x_502, | |
86 | MCP425x_103, | |
87 | MCP425x_503, | |
88 | MCP425x_104, | |
89 | MCP426x_502, | |
90 | MCP426x_103, | |
91 | MCP426x_503, | |
92 | MCP426x_104, | |
93 | }; | |
94 | ||
95 | static const struct mcp4131_cfg mcp4131_cfg[] = { | |
96 | [MCP413x_502] = { .wipers = 1, .max_pos = 128, .kohms = 5, }, | |
97 | [MCP413x_103] = { .wipers = 1, .max_pos = 128, .kohms = 10, }, | |
98 | [MCP413x_503] = { .wipers = 1, .max_pos = 128, .kohms = 50, }, | |
99 | [MCP413x_104] = { .wipers = 1, .max_pos = 128, .kohms = 100, }, | |
100 | [MCP414x_502] = { .wipers = 1, .max_pos = 128, .kohms = 5, }, | |
101 | [MCP414x_103] = { .wipers = 1, .max_pos = 128, .kohms = 10, }, | |
102 | [MCP414x_503] = { .wipers = 1, .max_pos = 128, .kohms = 50, }, | |
103 | [MCP414x_104] = { .wipers = 1, .max_pos = 128, .kohms = 100, }, | |
104 | [MCP415x_502] = { .wipers = 1, .max_pos = 256, .kohms = 5, }, | |
105 | [MCP415x_103] = { .wipers = 1, .max_pos = 256, .kohms = 10, }, | |
106 | [MCP415x_503] = { .wipers = 1, .max_pos = 256, .kohms = 50, }, | |
107 | [MCP415x_104] = { .wipers = 1, .max_pos = 256, .kohms = 100, }, | |
108 | [MCP416x_502] = { .wipers = 1, .max_pos = 256, .kohms = 5, }, | |
109 | [MCP416x_103] = { .wipers = 1, .max_pos = 256, .kohms = 10, }, | |
110 | [MCP416x_503] = { .wipers = 1, .max_pos = 256, .kohms = 50, }, | |
111 | [MCP416x_104] = { .wipers = 1, .max_pos = 256, .kohms = 100, }, | |
112 | [MCP423x_502] = { .wipers = 2, .max_pos = 128, .kohms = 5, }, | |
113 | [MCP423x_103] = { .wipers = 2, .max_pos = 128, .kohms = 10, }, | |
114 | [MCP423x_503] = { .wipers = 2, .max_pos = 128, .kohms = 50, }, | |
115 | [MCP423x_104] = { .wipers = 2, .max_pos = 128, .kohms = 100, }, | |
116 | [MCP424x_502] = { .wipers = 2, .max_pos = 128, .kohms = 5, }, | |
117 | [MCP424x_103] = { .wipers = 2, .max_pos = 128, .kohms = 10, }, | |
118 | [MCP424x_503] = { .wipers = 2, .max_pos = 128, .kohms = 50, }, | |
119 | [MCP424x_104] = { .wipers = 2, .max_pos = 128, .kohms = 100, }, | |
120 | [MCP425x_502] = { .wipers = 2, .max_pos = 256, .kohms = 5, }, | |
121 | [MCP425x_103] = { .wipers = 2, .max_pos = 256, .kohms = 10, }, | |
122 | [MCP425x_503] = { .wipers = 2, .max_pos = 256, .kohms = 50, }, | |
123 | [MCP425x_104] = { .wipers = 2, .max_pos = 256, .kohms = 100, }, | |
124 | [MCP426x_502] = { .wipers = 2, .max_pos = 256, .kohms = 5, }, | |
125 | [MCP426x_103] = { .wipers = 2, .max_pos = 256, .kohms = 10, }, | |
126 | [MCP426x_503] = { .wipers = 2, .max_pos = 256, .kohms = 50, }, | |
127 | [MCP426x_104] = { .wipers = 2, .max_pos = 256, .kohms = 100, }, | |
128 | }; | |
129 | ||
130 | struct mcp4131_data { | |
131 | struct spi_device *spi; | |
132 | const struct mcp4131_cfg *cfg; | |
133 | struct mutex lock; | |
134 | u8 buf[2] ____cacheline_aligned; | |
135 | }; | |
136 | ||
137 | #define MCP4131_CHANNEL(ch) { \ | |
138 | .type = IIO_RESISTANCE, \ | |
139 | .indexed = 1, \ | |
140 | .output = 1, \ | |
141 | .channel = (ch), \ | |
142 | .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ | |
143 | .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ | |
144 | } | |
145 | ||
146 | static const struct iio_chan_spec mcp4131_channels[] = { | |
147 | MCP4131_CHANNEL(0), | |
148 | MCP4131_CHANNEL(1), | |
149 | }; | |
150 | ||
151 | static int mcp4131_read(struct spi_device *spi, void *buf, size_t len) | |
152 | { | |
153 | struct spi_transfer t = { | |
154 | .tx_buf = buf, /* We need to send addr, cmd and 12 bits */ | |
155 | .rx_buf = buf, | |
156 | .len = len, | |
157 | }; | |
158 | struct spi_message m; | |
159 | ||
160 | spi_message_init(&m); | |
161 | spi_message_add_tail(&t, &m); | |
162 | ||
163 | return spi_sync(spi, &m); | |
164 | } | |
165 | ||
166 | static int mcp4131_read_raw(struct iio_dev *indio_dev, | |
167 | struct iio_chan_spec const *chan, | |
168 | int *val, int *val2, long mask) | |
169 | { | |
170 | int err; | |
171 | struct mcp4131_data *data = iio_priv(indio_dev); | |
172 | int address = chan->channel; | |
173 | ||
174 | switch (mask) { | |
175 | case IIO_CHAN_INFO_RAW: | |
176 | mutex_lock(&data->lock); | |
177 | ||
178 | data->buf[0] = (address << MCP4131_WIPER_SHIFT) | MCP4131_READ; | |
179 | data->buf[1] = 0; | |
180 | ||
181 | err = mcp4131_read(data->spi, data->buf, 2); | |
182 | if (err) { | |
183 | mutex_unlock(&data->lock); | |
184 | return err; | |
185 | } | |
186 | ||
187 | /* Error, bad address/command combination */ | |
188 | if (!MCP4131_CMDERR(data->buf)) { | |
189 | mutex_unlock(&data->lock); | |
190 | return -EIO; | |
191 | } | |
192 | ||
193 | *val = MCP4131_RAW(data->buf); | |
194 | mutex_unlock(&data->lock); | |
195 | ||
196 | return IIO_VAL_INT; | |
197 | ||
198 | case IIO_CHAN_INFO_SCALE: | |
199 | *val = 1000 * data->cfg->kohms; | |
200 | *val2 = data->cfg->max_pos; | |
201 | return IIO_VAL_FRACTIONAL; | |
202 | } | |
203 | ||
204 | return -EINVAL; | |
205 | } | |
206 | ||
207 | static int mcp4131_write_raw(struct iio_dev *indio_dev, | |
208 | struct iio_chan_spec const *chan, | |
209 | int val, int val2, long mask) | |
210 | { | |
211 | int err; | |
212 | struct mcp4131_data *data = iio_priv(indio_dev); | |
213 | int address = chan->channel << MCP4131_WIPER_SHIFT; | |
214 | ||
215 | switch (mask) { | |
216 | case IIO_CHAN_INFO_RAW: | |
217 | if (val > data->cfg->max_pos || val < 0) | |
218 | return -EINVAL; | |
219 | break; | |
220 | ||
221 | default: | |
222 | return -EINVAL; | |
223 | } | |
224 | ||
225 | mutex_lock(&data->lock); | |
226 | ||
227 | data->buf[0] = address << MCP4131_WIPER_SHIFT; | |
228 | data->buf[0] |= MCP4131_WRITE | (val >> 8); | |
229 | data->buf[1] = val & 0xFF; /* 8 bits here */ | |
230 | ||
231 | err = spi_write(data->spi, data->buf, 2); | |
232 | mutex_unlock(&data->lock); | |
233 | ||
234 | return err; | |
235 | } | |
236 | ||
237 | static const struct iio_info mcp4131_info = { | |
238 | .read_raw = mcp4131_read_raw, | |
239 | .write_raw = mcp4131_write_raw, | |
240 | .driver_module = THIS_MODULE, | |
241 | }; | |
242 | ||
243 | static int mcp4131_probe(struct spi_device *spi) | |
244 | { | |
245 | int err; | |
246 | struct device *dev = &spi->dev; | |
247 | unsigned long devid = spi_get_device_id(spi)->driver_data; | |
248 | struct mcp4131_data *data; | |
249 | struct iio_dev *indio_dev; | |
250 | ||
251 | indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); | |
252 | if (!indio_dev) | |
253 | return -ENOMEM; | |
254 | ||
255 | data = iio_priv(indio_dev); | |
256 | spi_set_drvdata(spi, indio_dev); | |
257 | data->spi = spi; | |
258 | data->cfg = &mcp4131_cfg[devid]; | |
259 | ||
260 | mutex_init(&data->lock); | |
261 | ||
262 | indio_dev->dev.parent = dev; | |
263 | indio_dev->info = &mcp4131_info; | |
264 | indio_dev->channels = mcp4131_channels; | |
265 | indio_dev->num_channels = data->cfg->wipers; | |
266 | indio_dev->name = spi_get_device_id(spi)->name; | |
267 | ||
268 | err = devm_iio_device_register(dev, indio_dev); | |
269 | if (err) { | |
270 | dev_info(&spi->dev, "Unable to register %s\n", indio_dev->name); | |
271 | return err; | |
272 | } | |
273 | ||
274 | return 0; | |
275 | } | |
276 | ||
277 | #if defined(CONFIG_OF) | |
278 | static const struct of_device_id mcp4131_dt_ids[] = { | |
279 | { .compatible = "microchip,mcp4131-502", | |
280 | .data = &mcp4131_cfg[MCP413x_502] }, | |
281 | { .compatible = "microchip,mcp4131-103", | |
282 | .data = &mcp4131_cfg[MCP413x_103] }, | |
283 | { .compatible = "microchip,mcp4131-503", | |
284 | .data = &mcp4131_cfg[MCP413x_503] }, | |
285 | { .compatible = "microchip,mcp4131-104", | |
286 | .data = &mcp4131_cfg[MCP413x_104] }, | |
287 | { .compatible = "microchip,mcp4132-502", | |
288 | .data = &mcp4131_cfg[MCP413x_502] }, | |
289 | { .compatible = "microchip,mcp4132-103", | |
290 | .data = &mcp4131_cfg[MCP413x_103] }, | |
291 | { .compatible = "microchip,mcp4132-503", | |
292 | .data = &mcp4131_cfg[MCP413x_503] }, | |
293 | { .compatible = "microchip,mcp4132-104", | |
294 | .data = &mcp4131_cfg[MCP413x_104] }, | |
295 | { .compatible = "microchip,mcp4141-502", | |
296 | .data = &mcp4131_cfg[MCP414x_502] }, | |
297 | { .compatible = "microchip,mcp4141-103", | |
298 | .data = &mcp4131_cfg[MCP414x_103] }, | |
299 | { .compatible = "microchip,mcp4141-503", | |
300 | .data = &mcp4131_cfg[MCP414x_503] }, | |
301 | { .compatible = "microchip,mcp4141-104", | |
302 | .data = &mcp4131_cfg[MCP414x_104] }, | |
303 | { .compatible = "microchip,mcp4142-502", | |
304 | .data = &mcp4131_cfg[MCP414x_502] }, | |
305 | { .compatible = "microchip,mcp4142-103", | |
306 | .data = &mcp4131_cfg[MCP414x_103] }, | |
307 | { .compatible = "microchip,mcp4142-503", | |
308 | .data = &mcp4131_cfg[MCP414x_503] }, | |
309 | { .compatible = "microchip,mcp4142-104", | |
310 | .data = &mcp4131_cfg[MCP414x_104] }, | |
311 | { .compatible = "microchip,mcp4151-502", | |
312 | .data = &mcp4131_cfg[MCP415x_502] }, | |
313 | { .compatible = "microchip,mcp4151-103", | |
314 | .data = &mcp4131_cfg[MCP415x_103] }, | |
315 | { .compatible = "microchip,mcp4151-503", | |
316 | .data = &mcp4131_cfg[MCP415x_503] }, | |
317 | { .compatible = "microchip,mcp4151-104", | |
318 | .data = &mcp4131_cfg[MCP415x_104] }, | |
319 | { .compatible = "microchip,mcp4152-502", | |
320 | .data = &mcp4131_cfg[MCP415x_502] }, | |
321 | { .compatible = "microchip,mcp4152-103", | |
322 | .data = &mcp4131_cfg[MCP415x_103] }, | |
323 | { .compatible = "microchip,mcp4152-503", | |
324 | .data = &mcp4131_cfg[MCP415x_503] }, | |
325 | { .compatible = "microchip,mcp4152-104", | |
326 | .data = &mcp4131_cfg[MCP415x_104] }, | |
327 | { .compatible = "microchip,mcp4161-502", | |
328 | .data = &mcp4131_cfg[MCP416x_502] }, | |
329 | { .compatible = "microchip,mcp4161-103", | |
330 | .data = &mcp4131_cfg[MCP416x_103] }, | |
331 | { .compatible = "microchip,mcp4161-503", | |
332 | .data = &mcp4131_cfg[MCP416x_503] }, | |
333 | { .compatible = "microchip,mcp4161-104", | |
334 | .data = &mcp4131_cfg[MCP416x_104] }, | |
335 | { .compatible = "microchip,mcp4162-502", | |
336 | .data = &mcp4131_cfg[MCP416x_502] }, | |
337 | { .compatible = "microchip,mcp4162-103", | |
338 | .data = &mcp4131_cfg[MCP416x_103] }, | |
339 | { .compatible = "microchip,mcp4162-503", | |
340 | .data = &mcp4131_cfg[MCP416x_503] }, | |
341 | { .compatible = "microchip,mcp4162-104", | |
342 | .data = &mcp4131_cfg[MCP416x_104] }, | |
343 | { .compatible = "microchip,mcp4231-502", | |
344 | .data = &mcp4131_cfg[MCP423x_502] }, | |
345 | { .compatible = "microchip,mcp4231-103", | |
346 | .data = &mcp4131_cfg[MCP423x_103] }, | |
347 | { .compatible = "microchip,mcp4231-503", | |
348 | .data = &mcp4131_cfg[MCP423x_503] }, | |
349 | { .compatible = "microchip,mcp4231-104", | |
350 | .data = &mcp4131_cfg[MCP423x_104] }, | |
351 | { .compatible = "microchip,mcp4232-502", | |
352 | .data = &mcp4131_cfg[MCP423x_502] }, | |
353 | { .compatible = "microchip,mcp4232-103", | |
354 | .data = &mcp4131_cfg[MCP423x_103] }, | |
355 | { .compatible = "microchip,mcp4232-503", | |
356 | .data = &mcp4131_cfg[MCP423x_503] }, | |
357 | { .compatible = "microchip,mcp4232-104", | |
358 | .data = &mcp4131_cfg[MCP423x_104] }, | |
359 | { .compatible = "microchip,mcp4241-502", | |
360 | .data = &mcp4131_cfg[MCP424x_502] }, | |
361 | { .compatible = "microchip,mcp4241-103", | |
362 | .data = &mcp4131_cfg[MCP424x_103] }, | |
363 | { .compatible = "microchip,mcp4241-503", | |
364 | .data = &mcp4131_cfg[MCP424x_503] }, | |
365 | { .compatible = "microchip,mcp4241-104", | |
366 | .data = &mcp4131_cfg[MCP424x_104] }, | |
367 | { .compatible = "microchip,mcp4242-502", | |
368 | .data = &mcp4131_cfg[MCP424x_502] }, | |
369 | { .compatible = "microchip,mcp4242-103", | |
370 | .data = &mcp4131_cfg[MCP424x_103] }, | |
371 | { .compatible = "microchip,mcp4242-503", | |
372 | .data = &mcp4131_cfg[MCP424x_503] }, | |
373 | { .compatible = "microchip,mcp4242-104", | |
374 | .data = &mcp4131_cfg[MCP424x_104] }, | |
375 | { .compatible = "microchip,mcp4251-502", | |
376 | .data = &mcp4131_cfg[MCP425x_502] }, | |
377 | { .compatible = "microchip,mcp4251-103", | |
378 | .data = &mcp4131_cfg[MCP425x_103] }, | |
379 | { .compatible = "microchip,mcp4251-503", | |
380 | .data = &mcp4131_cfg[MCP425x_503] }, | |
381 | { .compatible = "microchip,mcp4251-104", | |
382 | .data = &mcp4131_cfg[MCP425x_104] }, | |
383 | { .compatible = "microchip,mcp4252-502", | |
384 | .data = &mcp4131_cfg[MCP425x_502] }, | |
385 | { .compatible = "microchip,mcp4252-103", | |
386 | .data = &mcp4131_cfg[MCP425x_103] }, | |
387 | { .compatible = "microchip,mcp4252-503", | |
388 | .data = &mcp4131_cfg[MCP425x_503] }, | |
389 | { .compatible = "microchip,mcp4252-104", | |
390 | .data = &mcp4131_cfg[MCP425x_104] }, | |
391 | { .compatible = "microchip,mcp4261-502", | |
392 | .data = &mcp4131_cfg[MCP426x_502] }, | |
393 | { .compatible = "microchip,mcp4261-103", | |
394 | .data = &mcp4131_cfg[MCP426x_103] }, | |
395 | { .compatible = "microchip,mcp4261-503", | |
396 | .data = &mcp4131_cfg[MCP426x_503] }, | |
397 | { .compatible = "microchip,mcp4261-104", | |
398 | .data = &mcp4131_cfg[MCP426x_104] }, | |
399 | { .compatible = "microchip,mcp4262-502", | |
400 | .data = &mcp4131_cfg[MCP426x_502] }, | |
401 | { .compatible = "microchip,mcp4262-103", | |
402 | .data = &mcp4131_cfg[MCP426x_103] }, | |
403 | { .compatible = "microchip,mcp4262-503", | |
404 | .data = &mcp4131_cfg[MCP426x_503] }, | |
405 | { .compatible = "microchip,mcp4262-104", | |
406 | .data = &mcp4131_cfg[MCP426x_104] }, | |
407 | {} | |
408 | }; | |
409 | MODULE_DEVICE_TABLE(of, mcp4131_dt_ids); | |
410 | #endif /* CONFIG_OF */ | |
411 | ||
412 | static const struct spi_device_id mcp4131_id[] = { | |
413 | { "mcp4131-502", MCP413x_502 }, | |
414 | { "mcp4131-103", MCP413x_103 }, | |
415 | { "mcp4131-503", MCP413x_503 }, | |
416 | { "mcp4131-104", MCP413x_104 }, | |
417 | { "mcp4132-502", MCP413x_502 }, | |
418 | { "mcp4132-103", MCP413x_103 }, | |
419 | { "mcp4132-503", MCP413x_503 }, | |
420 | { "mcp4132-104", MCP413x_104 }, | |
421 | { "mcp4141-502", MCP414x_502 }, | |
422 | { "mcp4141-103", MCP414x_103 }, | |
423 | { "mcp4141-503", MCP414x_503 }, | |
424 | { "mcp4141-104", MCP414x_104 }, | |
425 | { "mcp4142-502", MCP414x_502 }, | |
426 | { "mcp4142-103", MCP414x_103 }, | |
427 | { "mcp4142-503", MCP414x_503 }, | |
428 | { "mcp4142-104", MCP414x_104 }, | |
429 | { "mcp4151-502", MCP415x_502 }, | |
430 | { "mcp4151-103", MCP415x_103 }, | |
431 | { "mcp4151-503", MCP415x_503 }, | |
432 | { "mcp4151-104", MCP415x_104 }, | |
433 | { "mcp4152-502", MCP415x_502 }, | |
434 | { "mcp4152-103", MCP415x_103 }, | |
435 | { "mcp4152-503", MCP415x_503 }, | |
436 | { "mcp4152-104", MCP415x_104 }, | |
437 | { "mcp4161-502", MCP416x_502 }, | |
438 | { "mcp4161-103", MCP416x_103 }, | |
439 | { "mcp4161-503", MCP416x_503 }, | |
440 | { "mcp4161-104", MCP416x_104 }, | |
441 | { "mcp4162-502", MCP416x_502 }, | |
442 | { "mcp4162-103", MCP416x_103 }, | |
443 | { "mcp4162-503", MCP416x_503 }, | |
444 | { "mcp4162-104", MCP416x_104 }, | |
445 | { "mcp4231-502", MCP423x_502 }, | |
446 | { "mcp4231-103", MCP423x_103 }, | |
447 | { "mcp4231-503", MCP423x_503 }, | |
448 | { "mcp4231-104", MCP423x_104 }, | |
449 | { "mcp4232-502", MCP423x_502 }, | |
450 | { "mcp4232-103", MCP423x_103 }, | |
451 | { "mcp4232-503", MCP423x_503 }, | |
452 | { "mcp4232-104", MCP423x_104 }, | |
453 | { "mcp4241-502", MCP424x_502 }, | |
454 | { "mcp4241-103", MCP424x_103 }, | |
455 | { "mcp4241-503", MCP424x_503 }, | |
456 | { "mcp4241-104", MCP424x_104 }, | |
457 | { "mcp4242-502", MCP424x_502 }, | |
458 | { "mcp4242-103", MCP424x_103 }, | |
459 | { "mcp4242-503", MCP424x_503 }, | |
460 | { "mcp4242-104", MCP424x_104 }, | |
461 | { "mcp4251-502", MCP425x_502 }, | |
462 | { "mcp4251-103", MCP425x_103 }, | |
463 | { "mcp4251-503", MCP425x_503 }, | |
464 | { "mcp4251-104", MCP425x_104 }, | |
465 | { "mcp4252-502", MCP425x_502 }, | |
466 | { "mcp4252-103", MCP425x_103 }, | |
467 | { "mcp4252-503", MCP425x_503 }, | |
468 | { "mcp4252-104", MCP425x_104 }, | |
469 | { "mcp4261-502", MCP426x_502 }, | |
470 | { "mcp4261-103", MCP426x_103 }, | |
471 | { "mcp4261-503", MCP426x_503 }, | |
472 | { "mcp4261-104", MCP426x_104 }, | |
473 | { "mcp4262-502", MCP426x_502 }, | |
474 | { "mcp4262-103", MCP426x_103 }, | |
475 | { "mcp4262-503", MCP426x_503 }, | |
476 | { "mcp4262-104", MCP426x_104 }, | |
477 | {} | |
478 | }; | |
479 | MODULE_DEVICE_TABLE(spi, mcp4131_id); | |
480 | ||
481 | static struct spi_driver mcp4131_driver = { | |
482 | .driver = { | |
483 | .name = "mcp4131", | |
484 | .of_match_table = of_match_ptr(mcp4131_dt_ids), | |
485 | }, | |
486 | .probe = mcp4131_probe, | |
487 | .id_table = mcp4131_id, | |
488 | }; | |
489 | ||
490 | module_spi_driver(mcp4131_driver); | |
491 | ||
492 | MODULE_AUTHOR("Slawomir Stepien <sst@poczta.fm>"); | |
493 | MODULE_DESCRIPTION("MCP4131 digital potentiometer"); | |
494 | MODULE_LICENSE("GPL v2"); |