[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / iio / dac / ad5686.c

/*
 * AD5686R, AD5685R, AD5684R Digital to analog converters  driver
 *
 * Copyright 2011 Analog Devices Inc.
 *
 * Licensed under the GPL-2.
 */

#include <linux/interrupt.h>
#include <linux/fs.h>
#include <linux/device.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/spi/spi.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/regulator/consumer.h>

#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>

#define AD5686_DAC_CHANNELS			4

#define AD5686_ADDR(x)				((x) << 16)
#define AD5686_CMD(x)				((x) << 20)

#define AD5686_ADDR_DAC(chan)		(0x1 << (chan))
#define AD5686_ADDR_ALL_DAC			0xF

#define AD5686_CMD_NOOP				0x0
#define AD5686_CMD_WRITE_INPUT_N		0x1
#define AD5686_CMD_UPDATE_DAC_N			0x2
#define AD5686_CMD_WRITE_INPUT_N_UPDATE_N	0x3
#define AD5686_CMD_POWERDOWN_DAC		0x4
#define AD5686_CMD_LDAC_MASK			0x5
#define AD5686_CMD_RESET			0x6
#define AD5686_CMD_INTERNAL_REFER_SETUP		0x7
#define AD5686_CMD_DAISY_CHAIN_ENABLE		0x8
#define AD5686_CMD_READBACK_ENABLE		0x9

#define AD5686_LDAC_PWRDN_NONE			0x0
#define AD5686_LDAC_PWRDN_1K			0x1
#define AD5686_LDAC_PWRDN_100K			0x2
#define AD5686_LDAC_PWRDN_3STATE		0x3

/**
 * struct ad5686_chip_info - chip specific information
 * @int_vref_mv:	AD5620/40/60: the internal reference voltage
 * @channel:		channel specification
*/

struct ad5686_chip_info {
	u16				int_vref_mv;
	struct iio_chan_spec		channel[AD5686_DAC_CHANNELS];
};

/**
 * struct ad5446_state - driver instance specific data
 * @spi:		spi_device
 * @chip_info:		chip model specific constants, available modes etc
 * @reg:		supply regulator
 * @vref_mv:		actual reference voltage used
 * @pwr_down_mask:	power down mask
 * @pwr_down_mode:	current power down mode
 * @data:		spi transfer buffers
 */

struct ad5686_state {
	struct spi_device		*spi;
	const struct ad5686_chip_info	*chip_info;
	struct regulator		*reg;
	unsigned short			vref_mv;
	unsigned			pwr_down_mask;
	unsigned			pwr_down_mode;
	/*
	 * DMA (thus cache coherency maintenance) requires the
	 * transfer buffers to live in their own cache lines.
	 */

	union {
		u32 d32;
		u8 d8[4];
	} data[3] ____cacheline_aligned;
};

/**
 * ad5686_supported_device_ids:
 */

enum ad5686_supported_device_ids {
	ID_AD5684,
	ID_AD5685,
	ID_AD5686,
};
static int ad5686_spi_write(struct ad5686_state *st,
			     u8 cmd, u8 addr, u16 val, u8 shift)
{
	val <<= shift;

	st->data[0].d32 = cpu_to_be32(AD5686_CMD(cmd) |
			      AD5686_ADDR(addr) |
			      val);

	return spi_write(st->spi, &st->data[0].d8[1], 3);
}

static int ad5686_spi_read(struct ad5686_state *st, u8 addr)
{
	struct spi_transfer t[] = {
		{
			.tx_buf = &st->data[0].d8[1],
			.len = 3,
			.cs_change = 1,
		}, {
			.tx_buf = &st->data[1].d8[1],
			.rx_buf = &st->data[2].d8[1],
			.len = 3,
		},
	};
	struct spi_message m;
	int ret;

	spi_message_init(&m);
	spi_message_add_tail(&t[0], &m);
	spi_message_add_tail(&t[1], &m);

	st->data[0].d32 = cpu_to_be32(AD5686_CMD(AD5686_CMD_READBACK_ENABLE) |
			      AD5686_ADDR(addr));
	st->data[1].d32 = cpu_to_be32(AD5686_CMD(AD5686_CMD_NOOP));

	ret = spi_sync(st->spi, &m);
	if (ret < 0)
		return ret;

	return be32_to_cpu(st->data[2].d32);
}

static const char * const ad5686_powerdown_modes[] = {
	"1kohm_to_gnd",
	"100kohm_to_gnd",
	"three_state"
};

static int ad5686_get_powerdown_mode(struct iio_dev *indio_dev,
	const struct iio_chan_spec *chan)
{
	struct ad5686_state *st = iio_priv(indio_dev);

	return ((st->pwr_down_mode >> (chan->channel * 2)) & 0x3) - 1;
}

static int ad5686_set_powerdown_mode(struct iio_dev *indio_dev,
	const struct iio_chan_spec *chan, unsigned int mode)
{
	struct ad5686_state *st = iio_priv(indio_dev);

	st->pwr_down_mode &= ~(0x3 << (chan->channel * 2));
	st->pwr_down_mode |= ((mode + 1) << (chan->channel * 2));

	return 0;
}

static const struct iio_enum ad5686_powerdown_mode_enum = {
	.items = ad5686_powerdown_modes,
	.num_items = ARRAY_SIZE(ad5686_powerdown_modes),
	.get = ad5686_get_powerdown_mode,
	.set = ad5686_set_powerdown_mode,
};

static ssize_t ad5686_read_dac_powerdown(struct iio_dev *indio_dev,
	uintptr_t private, const struct iio_chan_spec *chan, char *buf)
{
	struct ad5686_state *st = iio_priv(indio_dev);

	return sprintf(buf, "%d\n", !!(st->pwr_down_mask &
			(0x3 << (chan->channel * 2))));
}

static ssize_t ad5686_write_dac_powerdown(struct iio_dev *indio_dev,
	 uintptr_t private, const struct iio_chan_spec *chan, const char *buf,
	 size_t len)
{
	bool readin;
	int ret;
	struct ad5686_state *st = iio_priv(indio_dev);

	ret = strtobool(buf, &readin);
	if (ret)
		return ret;

	if (readin)
		st->pwr_down_mask |= (0x3 << (chan->channel * 2));
	else
		st->pwr_down_mask &= ~(0x3 << (chan->channel * 2));

	ret = ad5686_spi_write(st, AD5686_CMD_POWERDOWN_DAC, 0,
			       st->pwr_down_mask & st->pwr_down_mode, 0);

	return ret ? ret : len;
}

static int ad5686_read_raw(struct iio_dev *indio_dev,
			   struct iio_chan_spec const *chan,
			   int *val,
			   int *val2,
			   long m)
{
	struct ad5686_state *st = iio_priv(indio_dev);
	unsigned long scale_uv;
	int ret;

	switch (m) {
	case IIO_CHAN_INFO_RAW:
		mutex_lock(&indio_dev->mlock);
		ret = ad5686_spi_read(st, chan->address);
		mutex_unlock(&indio_dev->mlock);
		if (ret < 0)
			return ret;
		*val = ret;
		return IIO_VAL_INT;
		break;
	case IIO_CHAN_INFO_SCALE:
		scale_uv = (st->vref_mv * 100000)
			>> (chan->scan_type.realbits);
		*val =  scale_uv / 100000;
		*val2 = (scale_uv % 100000) * 10;
		return IIO_VAL_INT_PLUS_MICRO;

	}
	return -EINVAL;
}

static int ad5686_write_raw(struct iio_dev *indio_dev,
			       struct iio_chan_spec const *chan,
			       int val,
			       int val2,
			       long mask)
{
	struct ad5686_state *st = iio_priv(indio_dev);
	int ret;

	switch (mask) {
	case IIO_CHAN_INFO_RAW:
		if (val > (1 << chan->scan_type.realbits) || val < 0)
			return -EINVAL;

		mutex_lock(&indio_dev->mlock);
		ret = ad5686_spi_write(st,
				 AD5686_CMD_WRITE_INPUT_N_UPDATE_N,
				 chan->address,
				 val,
				 chan->scan_type.shift);
		mutex_unlock(&indio_dev->mlock);
		break;
	default:
		ret = -EINVAL;
	}

	return ret;
}

static const struct iio_info ad5686_info = {
	.read_raw = ad5686_read_raw,
	.write_raw = ad5686_write_raw,
	.driver_module = THIS_MODULE,
};

static const struct iio_chan_spec_ext_info ad5686_ext_info[] = {
	{
		.name = "powerdown",
		.read = ad5686_read_dac_powerdown,
		.write = ad5686_write_dac_powerdown,
	},
	IIO_ENUM("powerdown_mode", false, &ad5686_powerdown_mode_enum),
	IIO_ENUM_AVAILABLE("powerdown_mode", &ad5686_powerdown_mode_enum),
	{ },
};

#define AD5868_CHANNEL(chan, bits, shift) {			\
		.type = IIO_VOLTAGE,				\
		.indexed = 1,					\
		.output = 1,					\
		.channel = chan,				\
		.info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |	\
		IIO_CHAN_INFO_SCALE_SHARED_BIT,			\
		.address = AD5686_ADDR_DAC(chan),			\
		.scan_type = IIO_ST('u', bits, 16, shift),	\
		.ext_info = ad5686_ext_info,			\
}

static const struct ad5686_chip_info ad5686_chip_info_tbl[] = {
	[ID_AD5684] = {
		.channel[0] = AD5868_CHANNEL(0, 12, 4),
		.channel[1] = AD5868_CHANNEL(1, 12, 4),
		.channel[2] = AD5868_CHANNEL(2, 12, 4),
		.channel[3] = AD5868_CHANNEL(3, 12, 4),
		.int_vref_mv = 2500,
	},
	[ID_AD5685] = {
		.channel[0] = AD5868_CHANNEL(0, 14, 2),
		.channel[1] = AD5868_CHANNEL(1, 14, 2),
		.channel[2] = AD5868_CHANNEL(2, 14, 2),
		.channel[3] = AD5868_CHANNEL(3, 14, 2),
		.int_vref_mv = 2500,
	},
	[ID_AD5686] = {
		.channel[0] = AD5868_CHANNEL(0, 16, 0),
		.channel[1] = AD5868_CHANNEL(1, 16, 0),
		.channel[2] = AD5868_CHANNEL(2, 16, 0),
		.channel[3] = AD5868_CHANNEL(3, 16, 0),
		.int_vref_mv = 2500,
	},
};


static int ad5686_probe(struct spi_device *spi)
{
	struct ad5686_state *st;
	struct iio_dev *indio_dev;
	int ret, regdone = 0, voltage_uv = 0;

	indio_dev = iio_device_alloc(sizeof(*st));
	if (indio_dev == NULL)
		return  -ENOMEM;

	st = iio_priv(indio_dev);
	spi_set_drvdata(spi, indio_dev);

	st->reg = regulator_get(&spi->dev, "vcc");
	if (!IS_ERR(st->reg)) {
		ret = regulator_enable(st->reg);
		if (ret)
			goto error_put_reg;

		ret = regulator_get_voltage(st->reg);
		if (ret < 0)
			goto error_disable_reg;

		voltage_uv = ret;
	}

	st->chip_info =
		&ad5686_chip_info_tbl[spi_get_device_id(spi)->driver_data];

	if (voltage_uv)
		st->vref_mv = voltage_uv / 1000;
	else
		st->vref_mv = st->chip_info->int_vref_mv;

	st->spi = spi;

	/* Set all the power down mode for all channels to 1K pulldown */
	st->pwr_down_mode = 0x55;

	indio_dev->dev.parent = &spi->dev;
	indio_dev->name = spi_get_device_id(spi)->name;
	indio_dev->info = &ad5686_info;
	indio_dev->modes = INDIO_DIRECT_MODE;
	indio_dev->channels = st->chip_info->channel;
	indio_dev->num_channels = AD5686_DAC_CHANNELS;

	regdone = 1;
	ret = ad5686_spi_write(st, AD5686_CMD_INTERNAL_REFER_SETUP, 0,
				!!voltage_uv, 0);
	if (ret)
		goto error_disable_reg;

	ret = iio_device_register(indio_dev);
	if (ret)
		goto error_disable_reg;

	return 0;

error_disable_reg:
	if (!IS_ERR(st->reg))
		regulator_disable(st->reg);
error_put_reg:
	if (!IS_ERR(st->reg))
		regulator_put(st->reg);

	iio_device_free(indio_dev);

	return ret;
}

static int ad5686_remove(struct spi_device *spi)
{
	struct iio_dev *indio_dev = spi_get_drvdata(spi);
	struct ad5686_state *st = iio_priv(indio_dev);

	iio_device_unregister(indio_dev);
	if (!IS_ERR(st->reg)) {
		regulator_disable(st->reg);
		regulator_put(st->reg);
	}
	iio_device_free(indio_dev);

	return 0;
}

static const struct spi_device_id ad5686_id[] = {
	{"ad5684", ID_AD5684},
	{"ad5685", ID_AD5685},
	{"ad5686", ID_AD5686},
	{}
};
MODULE_DEVICE_TABLE(spi, ad5686_id);

static struct spi_driver ad5686_driver = {
	.driver = {
		   .name = "ad5686",
		   .owner = THIS_MODULE,
		   },
	.probe = ad5686_probe,
	.remove = ad5686_remove,
	.id_table = ad5686_id,
};
module_spi_driver(ad5686_driver);

MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
MODULE_DESCRIPTION("Analog Devices AD5686/85/84 DAC");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
c2f37c8d MH	1	/*
	2	* AD5686R, AD5685R, AD5684R Digital to analog converters driver
	3	*
	4	* Copyright 2011 Analog Devices Inc.
	5	*
	6	* Licensed under the GPL-2.
	7	*/
	8
	9	#include <linux/interrupt.h>
c2f37c8d MH	10	#include <linux/fs.h>
c2f37c8d MH	11	#include <linux/device.h>
99c97852	12	#include <linux/module.h>
c2f37c8d MH	13	#include <linux/kernel.h>
	14	#include <linux/spi/spi.h>
	15	#include <linux/slab.h>
	16	#include <linux/sysfs.h>
	17	#include <linux/regulator/consumer.h>
	18
06458e27 JC	19	#include <linux/iio/iio.h>
06458e27 JC	20	#include <linux/iio/sysfs.h>
c2f37c8d MH	21
	22	#define AD5686_DAC_CHANNELS 4
	23
	24	#define AD5686_ADDR(x) ((x) << 16)
	25	#define AD5686_CMD(x) ((x) << 20)
	26
a45186c0	27	#define AD5686_ADDR_DAC(chan) (0x1 << (chan))
c2f37c8d MH	28	#define AD5686_ADDR_ALL_DAC 0xF
	29
	30	#define AD5686_CMD_NOOP 0x0
	31	#define AD5686_CMD_WRITE_INPUT_N 0x1
	32	#define AD5686_CMD_UPDATE_DAC_N 0x2
	33	#define AD5686_CMD_WRITE_INPUT_N_UPDATE_N 0x3
	34	#define AD5686_CMD_POWERDOWN_DAC 0x4
	35	#define AD5686_CMD_LDAC_MASK 0x5
	36	#define AD5686_CMD_RESET 0x6
	37	#define AD5686_CMD_INTERNAL_REFER_SETUP 0x7
	38	#define AD5686_CMD_DAISY_CHAIN_ENABLE 0x8
	39	#define AD5686_CMD_READBACK_ENABLE 0x9
	40
	41	#define AD5686_LDAC_PWRDN_NONE 0x0
	42	#define AD5686_LDAC_PWRDN_1K 0x1
	43	#define AD5686_LDAC_PWRDN_100K 0x2
	44	#define AD5686_LDAC_PWRDN_3STATE 0x3
	45
	46	/**
	47	* struct ad5686_chip_info - chip specific information
	48	* @int_vref_mv: AD5620/40/60: the internal reference voltage
	49	* @channel: channel specification
	50	*/
	51
	52	struct ad5686_chip_info {
	53	u16 int_vref_mv;
	54	struct iio_chan_spec channel[AD5686_DAC_CHANNELS];
	55	};
	56
	57	/**
	58	* struct ad5446_state - driver instance specific data
	59	* @spi: spi_device
	60	* @chip_info: chip model specific constants, available modes etc
	61	* @reg: supply regulator
	62	* @vref_mv: actual reference voltage used
	63	* @pwr_down_mask: power down mask
	64	* @pwr_down_mode: current power down mode
	65	* @data: spi transfer buffers
	66	*/
	67
	68	struct ad5686_state {
	69	struct spi_device *spi;
	70	const struct ad5686_chip_info *chip_info;
	71	struct regulator *reg;
	72	unsigned short vref_mv;
	73	unsigned pwr_down_mask;
	74	unsigned pwr_down_mode;
	75	/*
	76	* DMA (thus cache coherency maintenance) requires the
	77	* transfer buffers to live in their own cache lines.
	78	*/
	79
	80	union {
	81	u32 d32;
	82	u8 d8[4];
	83	} data[3] ____cacheline_aligned;
	84	};
	85
	86	/**
	87	* ad5686_supported_device_ids:
	88	*/
	89
	90	enum ad5686_supported_device_ids {
	91	ID_AD5684,
92	ID_AD5685,
93	ID_AD5686,
94	};
c2f37c8d MH	95	static int ad5686_spi_write(struct ad5686_state *st,
	96	u8 cmd, u8 addr, u16 val, u8 shift)
	97	{
	98	val <<= shift;
	99
	100	st->data[0].d32 = cpu_to_be32(AD5686_CMD(cmd) \|
	101	AD5686_ADDR(addr) \|
	102	val);
	103
	104	return spi_write(st->spi, &st->data[0].d8[1], 3);
	105	}
	106
	107	static int ad5686_spi_read(struct ad5686_state *st, u8 addr)
	108	{
	109	struct spi_transfer t[] = {
	110	{
	111	.tx_buf = &st->data[0].d8[1],
	112	.len = 3,
	113	.cs_change = 1,
	114	}, {
	115	.tx_buf = &st->data[1].d8[1],
	116	.rx_buf = &st->data[2].d8[1],
	117	.len = 3,
	118	},
	119	};
	120	struct spi_message m;
	121	int ret;
	122
	123	spi_message_init(&m);
	124	spi_message_add_tail(&t[0], &m);
	125	spi_message_add_tail(&t[1], &m);
	126
	127	st->data[0].d32 = cpu_to_be32(AD5686_CMD(AD5686_CMD_READBACK_ENABLE) \|
	128	AD5686_ADDR(addr));
	129	st->data[1].d32 = cpu_to_be32(AD5686_CMD(AD5686_CMD_NOOP));
	130
	131	ret = spi_sync(st->spi, &m);
	132	if (ret < 0)
	133	return ret;
	134
	135	return be32_to_cpu(st->data[2].d32);
	136	}
	137
fe4586a8 LPC	138	static const char * const ad5686_powerdown_modes[] = {
	139	"1kohm_to_gnd",
	140	"100kohm_to_gnd",
	141	"three_state"
	142	};
	143
	144	static int ad5686_get_powerdown_mode(struct iio_dev *indio_dev,
	145	const struct iio_chan_spec *chan)
c2f37c8d	146	{
c2f37c8d	147	struct ad5686_state *st = iio_priv(indio_dev);
c2f37c8d	148
fe4586a8	149	return ((st->pwr_down_mode >> (chan->channel * 2)) & 0x3) - 1;
c2f37c8d MH	150	}
c2f37c8d MH	151
fe4586a8 LPC	152	static int ad5686_set_powerdown_mode(struct iio_dev *indio_dev,
fe4586a8 LPC	153	const struct iio_chan_spec *chan, unsigned int mode)
c2f37c8d	154	{
c2f37c8d	155	struct ad5686_state *st = iio_priv(indio_dev);
c2f37c8d	156
fe4586a8 LPC	157	st->pwr_down_mode &= ~(0x3 << (chan->channel * 2));
fe4586a8 LPC	158	st->pwr_down_mode \|= ((mode + 1) << (chan->channel * 2));
c2f37c8d	159
fe4586a8	160	return 0;
c2f37c8d MH	161	}
c2f37c8d MH	162
fe4586a8 LPC	163	static const struct iio_enum ad5686_powerdown_mode_enum = {
	164	.items = ad5686_powerdown_modes,
	165	.num_items = ARRAY_SIZE(ad5686_powerdown_modes),
	166	.get = ad5686_get_powerdown_mode,
	167	.set = ad5686_set_powerdown_mode,
	168	};
	169
	170	static ssize_t ad5686_read_dac_powerdown(struct iio_dev *indio_dev,
	171	uintptr_t private, const struct iio_chan_spec chan, char buf)
c2f37c8d	172	{
c2f37c8d	173	struct ad5686_state *st = iio_priv(indio_dev);
c2f37c8d MH	174
c2f37c8d MH	175	return sprintf(buf, "%d\n", !!(st->pwr_down_mask &
fe4586a8	176	(0x3 << (chan->channel * 2))));
c2f37c8d MH	177	}
c2f37c8d MH	178
fe4586a8 LPC	179	static ssize_t ad5686_write_dac_powerdown(struct iio_dev *indio_dev,
	180	uintptr_t private, const struct iio_chan_spec chan, const char buf,
	181	size_t len)
c2f37c8d MH	182	{
	183	bool readin;
	184	int ret;
c2f37c8d	185	struct ad5686_state *st = iio_priv(indio_dev);
c2f37c8d MH	186
	187	ret = strtobool(buf, &readin);
	188	if (ret)
	189	return ret;
	190
7737fa6d	191	if (readin)
fe4586a8	192	st->pwr_down_mask \|= (0x3 << (chan->channel * 2));
c2f37c8d	193	else
fe4586a8	194	st->pwr_down_mask &= ~(0x3 << (chan->channel * 2));
c2f37c8d MH	195
	196	ret = ad5686_spi_write(st, AD5686_CMD_POWERDOWN_DAC, 0,
	197	st->pwr_down_mask & st->pwr_down_mode, 0);
	198
	199	return ret ? ret : len;
	200	}
	201
c2f37c8d MH	202	static int ad5686_read_raw(struct iio_dev *indio_dev,
	203	struct iio_chan_spec const *chan,
	204	int *val,
	205	int *val2,
	206	long m)
	207	{
	208	struct ad5686_state *st = iio_priv(indio_dev);
	209	unsigned long scale_uv;
	210	int ret;
	211
	212	switch (m) {
09f4eb40	213	case IIO_CHAN_INFO_RAW:
c2f37c8d MH	214	mutex_lock(&indio_dev->mlock);
	215	ret = ad5686_spi_read(st, chan->address);
	216	mutex_unlock(&indio_dev->mlock);
	217	if (ret < 0)
	218	return ret;
	219	*val = ret;
	220	return IIO_VAL_INT;
	221	break;
c8a9f805	222	case IIO_CHAN_INFO_SCALE:
c2f37c8d MH	223	scale_uv = (st->vref_mv * 100000)
	224	>> (chan->scan_type.realbits);
	225	*val = scale_uv / 100000;
	226	val2 = (scale_uv % 100000) 10;
	227	return IIO_VAL_INT_PLUS_MICRO;
	228
	229	}
	230	return -EINVAL;
	231	}
	232
	233	static int ad5686_write_raw(struct iio_dev *indio_dev,
	234	struct iio_chan_spec const *chan,
	235	int val,
	236	int val2,
	237	long mask)
	238	{
	239	struct ad5686_state *st = iio_priv(indio_dev);
	240	int ret;
	241
	242	switch (mask) {
09f4eb40	243	case IIO_CHAN_INFO_RAW:
cd8eca6f	244	if (val > (1 << chan->scan_type.realbits) \|\| val < 0)
c2f37c8d MH	245	return -EINVAL;
	246
	247	mutex_lock(&indio_dev->mlock);
	248	ret = ad5686_spi_write(st,
	249	AD5686_CMD_WRITE_INPUT_N_UPDATE_N,
	250	chan->address,
	251	val,
	252	chan->scan_type.shift);
	253	mutex_unlock(&indio_dev->mlock);
	254	break;
	255	default:
	256	ret = -EINVAL;
	257	}
	258
	259	return ret;
	260	}
	261
	262	static const struct iio_info ad5686_info = {
	263	.read_raw = ad5686_read_raw,
	264	.write_raw = ad5686_write_raw,
c2f37c8d MH	265	.driver_module = THIS_MODULE,
	266	};
	267
fe4586a8 LPC	268	static const struct iio_chan_spec_ext_info ad5686_ext_info[] = {
	269	{
	270	.name = "powerdown",
	271	.read = ad5686_read_dac_powerdown,
	272	.write = ad5686_write_dac_powerdown,
	273	},
	274	IIO_ENUM("powerdown_mode", false, &ad5686_powerdown_mode_enum),
	275	IIO_ENUM_AVAILABLE("powerdown_mode", &ad5686_powerdown_mode_enum),
	276	{ },
	277	};
	278
	279	#define AD5868_CHANNEL(chan, bits, shift) { \
	280	.type = IIO_VOLTAGE, \
	281	.indexed = 1, \
	282	.output = 1, \
	283	.channel = chan, \
	284	.info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT \| \
	285	IIO_CHAN_INFO_SCALE_SHARED_BIT, \
	286	.address = AD5686_ADDR_DAC(chan), \
	287	.scan_type = IIO_ST('u', bits, 16, shift), \
	288	.ext_info = ad5686_ext_info, \
	289	}
	290
	291	static const struct ad5686_chip_info ad5686_chip_info_tbl[] = {
	292	[ID_AD5684] = {
	293	.channel[0] = AD5868_CHANNEL(0, 12, 4),
	294	.channel[1] = AD5868_CHANNEL(1, 12, 4),
	295	.channel[2] = AD5868_CHANNEL(2, 12, 4),
	296	.channel[3] = AD5868_CHANNEL(3, 12, 4),
	297	.int_vref_mv = 2500,
	298	},
	299	[ID_AD5685] = {
	300	.channel[0] = AD5868_CHANNEL(0, 14, 2),
	301	.channel[1] = AD5868_CHANNEL(1, 14, 2),
	302	.channel[2] = AD5868_CHANNEL(2, 14, 2),
	303	.channel[3] = AD5868_CHANNEL(3, 14, 2),
	304	.int_vref_mv = 2500,
	305	},
	306	[ID_AD5686] = {
	307	.channel[0] = AD5868_CHANNEL(0, 16, 0),
	308	.channel[1] = AD5868_CHANNEL(1, 16, 0),
	309	.channel[2] = AD5868_CHANNEL(2, 16, 0),
	310	.channel[3] = AD5868_CHANNEL(3, 16, 0),
	311	.int_vref_mv = 2500,
	312	},
	313	};
	314
	315
fc52692c	316	static int ad5686_probe(struct spi_device *spi)
c2f37c8d MH	317	{
	318	struct ad5686_state *st;
	319	struct iio_dev *indio_dev;
	320	int ret, regdone = 0, voltage_uv = 0;
	321
7cbb7537	322	indio_dev = iio_device_alloc(sizeof(*st));
c2f37c8d MH	323	if (indio_dev == NULL)
	324	return -ENOMEM;
	325
	326	st = iio_priv(indio_dev);
	327	spi_set_drvdata(spi, indio_dev);
	328
	329	st->reg = regulator_get(&spi->dev, "vcc");
	330	if (!IS_ERR(st->reg)) {
	331	ret = regulator_enable(st->reg);
	332	if (ret)
	333	goto error_put_reg;
	334
359570ad AL	335	ret = regulator_get_voltage(st->reg);
	336	if (ret < 0)
	337	goto error_disable_reg;
	338
	339	voltage_uv = ret;
c2f37c8d MH	340	}
	341
	342	st->chip_info =
	343	&ad5686_chip_info_tbl[spi_get_device_id(spi)->driver_data];
	344
	345	if (voltage_uv)
	346	st->vref_mv = voltage_uv / 1000;
	347	else
	348	st->vref_mv = st->chip_info->int_vref_mv;
	349
	350	st->spi = spi;
	351
fe4586a8 LPC	352	/* Set all the power down mode for all channels to 1K pulldown */
	353	st->pwr_down_mode = 0x55;
	354
c2f37c8d MH	355	indio_dev->dev.parent = &spi->dev;
	356	indio_dev->name = spi_get_device_id(spi)->name;
	357	indio_dev->info = &ad5686_info;
	358	indio_dev->modes = INDIO_DIRECT_MODE;
	359	indio_dev->channels = st->chip_info->channel;
	360	indio_dev->num_channels = AD5686_DAC_CHANNELS;
	361
c2f37c8d MH	362	regdone = 1;
	363	ret = ad5686_spi_write(st, AD5686_CMD_INTERNAL_REFER_SETUP, 0,
	364	!!voltage_uv, 0);
	365	if (ret)
	366	goto error_disable_reg;
	367
26d25ae3 JC	368	ret = iio_device_register(indio_dev);
	369	if (ret)
	370	goto error_disable_reg;
	371
c2f37c8d MH	372	return 0;
	373
	374	error_disable_reg:
	375	if (!IS_ERR(st->reg))
	376	regulator_disable(st->reg);
	377	error_put_reg:
	378	if (!IS_ERR(st->reg))
	379	regulator_put(st->reg);
	380
7cbb7537	381	iio_device_free(indio_dev);
c2f37c8d MH	382
	383	return ret;
	384	}
	385
fc52692c	386	static int ad5686_remove(struct spi_device *spi)
c2f37c8d MH	387	{
	388	struct iio_dev *indio_dev = spi_get_drvdata(spi);
	389	struct ad5686_state *st = iio_priv(indio_dev);
c2f37c8d	390
d2fffd6c	391	iio_device_unregister(indio_dev);
26a54797 JC	392	if (!IS_ERR(st->reg)) {
	393	regulator_disable(st->reg);
	394	regulator_put(st->reg);
c2f37c8d	395	}
7cbb7537	396	iio_device_free(indio_dev);
c2f37c8d MH	397
	398	return 0;
	399	}
	400
	401	static const struct spi_device_id ad5686_id[] = {
	402	{"ad5684", ID_AD5684},
	403	{"ad5685", ID_AD5685},
	404	{"ad5686", ID_AD5686},
	405	{}
	406	};
55e4390c	407	MODULE_DEVICE_TABLE(spi, ad5686_id);
c2f37c8d MH	408
	409	static struct spi_driver ad5686_driver = {
	410	.driver = {
	411	.name = "ad5686",
	412	.owner = THIS_MODULE,
	413	},
	414	.probe = ad5686_probe,
fc52692c	415	.remove = ad5686_remove,
c2f37c8d MH	416	.id_table = ad5686_id,
c2f37c8d MH	417	};
ae6ae6fe	418	module_spi_driver(ad5686_driver);
c2f37c8d MH	419
	420	MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
	421	MODULE_DESCRIPTION("Analog Devices AD5686/85/84 DAC");
	422	MODULE_LICENSE("GPL v2");